Integrated Circuit and Data Storage Method

Abstract

To improve management of secure access to multiple memory dies stacked in a common package.SOLUTION: An integrated circuit includes a primary memory die and a secondary memory die. The primary memory die is coupled to a bus providing a primary chip select signal via a primary chip select line. The secondary memory die is coupled to the bus, excluding the primary chip select line, and coupled to a secondary chip select line provided by the primary memory die. The primary memory die is configured to: receive a command while the primary chip select signal is active; in response to identifying that the command is destined for the primary memory die, execute the command within the primary memory die; and, in response to identifying that the command is destined for the secondary memory die, cause the secondary memory die to execute the command by transferring the primary chip select signal on the secondary chip select line.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to secure data storage, and more particularly, to a secure storage method and system for use in a multi-die package.

Background Art

[0002] Various systems store data in a storage device that includes multiple memory dies stacked in a common package.

[0003] Using multiple memory dies stacked in a common package is a known technique. For example, U.S. Patent No. 9,245,590 describes stacking and packaging any number of Serial Peripheral Interface (“SPI”) flash memory dies to achieve any one or combination of various functions such as low bit cost, high density storage, code shadowing to RAM, and fast random access to “in-place execution” applications while maintaining the advantages of the SPI interface. When manufacturing the device, each stacked die is assigned a unique identification symbol or “die ID” relative to the other stacked dies in the package. During normal operation, the unique die ID is used by a die select command to enable any one of the stacked dies to respond to subsequent commands on the SPI interface and prevent the other stacked dies in the package from responding to subsequent commands, except for some “universal” commands that include the die select command, and support parallel operation by the stacked dies.

[0004] As another example, U.S. Patent No. 11,194,726 describes a method, system, and apparatus for a combination of stacking memory dies and access operations. The apparatus may include a plurality of memory dies. One die can be configured as a master device and the other die can be configured as a slave device. The master device can communicate with a host device. The slave device can be coupled to the master device. The apparatus may include a first die (e.g., the master device) and a second die (e.g., the slave device). The first die may be coupled to the host device and may be configured to output a data set in response to a read command. The first die can provide a first subset of the data and can obtain a second subset of the data from the second die. Summary of the Invention Problems to be Solved by the Invention

[0005] Embodiments of the present invention provide improvements for the management of secure access to a plurality of memory dies stacked in a common package. Means for Solving the Problems

[0006] Embodiments described herein provide an integrated circuit (IC) including a primary memory die and a secondary memory die. The primary memory die is coupled to a bus that provides a primary CS signal via a primary chip select (CS) line that connects to the primary memory die. The secondary memory die is coupled to a bus that does not include the primary CS line and is coupled to a secondary CS line that carries a secondary CS signal provided by the primary memory die. The primary memory die is configured to receive a command via the bus when the primary CS signal is active, execute the command within the primary memory die in response to identifying that the command is addressed to the primary memory die, and cause the secondary memory die to execute the command by transmitting the primary CS signal as a secondary CS signal on the secondary CS line in response to identifying that the command is addressed to the secondary memory die.

[0007] In some embodiments, the primary memory die includes local memory selectable by a local valid signal transmitted on a local valid line, and the primary memory die is configured to execute a command by: (i) transmitting a primary CS signal as the local valid signal on the local valid line; (ii) deactivating a secondary CS signal provided to a secondary memory die. In other embodiments, the IC includes another secondary die coupled to a bus that does not include a primary CS line and coupled to another secondary CS line that carries another secondary CS signal provided by the primary memory die, and the primary die is configured to cause the other secondary die to execute a command by: (i) transmitting the primary CS signal as another secondary CS signal on the other secondary CS line; (ii) deactivating the secondary CS signal provided to the secondary die; (iii) deactivating the local valid signal of the local memory provided to the primary die. In other embodiments, the primary memory die and the secondary memory die have corresponding first and second different memory types, and each memory type is selected from a list including at least (i) a NAND flash memory type; (ii) or a NOR flash memory type.

[0008] In one embodiment, the primary memory die and the secondary memory die support corresponding first and second different access protocols, and the primary memory die is configured to present the second access protocol for the secondary memory die to a host coupled to the bus. In another embodiment, the primary memory die is configured to cause a selected memory die, selected in response to receiving a die selection command that designates the memory die selected between the primary memory die and the secondary memory die, to execute one or more commands received after the die selection command. In yet another embodiment, the primary memory die and the secondary memory die are mapped to corresponding different address sub-ranges of a common address space, and the primary memory die is configured to identify an address parameter in a received command and execute the received command through the primary memory die or the secondary memory die according to the address range to which the address parameter belongs.

[0009] In some embodiments, the primary memory die is configured to operate according to an access mode in which the primary memory die controls a second CS signal to block access to the secondary memory die for all received commands. In other embodiments, the primary memory die is configured to operate according to an access mode in which the primary memory die controls a second CS signal to permit access to the secondary memory die for a partial subset of commands supported by the secondary memory die. Also, in another embodiment, the primary memory die is configured to operate according to an access mode in which the primary memory die controls a second CS signal to enable full access to the secondary memory die for all commands supported by the secondary memory die while selectively executing commands that modify the access mode.

[0010] In one embodiment, the primary memory die is configured to locally store the host's boot code coupled to the bus and manage secure access to the stored boot code. In another embodiment, the primary memory die is arranged to function as a Root of Trust (RoT) of the base system including the IC to secure the storage operation for the secondary memory die.

[0011] According to the embodiments described herein, a data storage method is further provided. The method is in an integrated circuit (IC), the integrated circuit including a primary memory die coupled to a bus that provides a primary chip select (CS) signal via a primary CS line connected to the primary memory die, and a secondary memory die coupled to a bus that does not include the primary CS line and is coupled to a secondary CS line that carries a secondary CS signal provided by the primary memory die. When the primary CS signal is active, the primary memory die receives a command via the bus. In response to identifying that the command is addressed to the primary memory die, the primary memory die executes the command within itself, and in response to identifying that the command is addressed to the secondary memory die, the primary memory die transmits the primary CS signal as a secondary CS signal on the secondary CS line to cause the secondary memory die to execute the command.

Advantages of the Invention

[0012] Embodiments of the present invention can improve the management of secure access to a plurality of memory dies stacked in a common package.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

[0014] Embodiments of this specification provide methods and systems for improving the management of secure access to a plurality of memory dies stacked in a common package. In the disclosed embodiments, one memory die controls access to other memory dies by controlling its corresponding chip select (CS) input. The disclosed embodiments can be applied to different types of memory dies having different corresponding command sets and / or supporting different access protocols.

[0015] In various systems, a host is coupled to a storage device including a plurality of memory dies via a bus. The bus typically includes one or more input / output (IO) lines for transmitting an opcode, an address, and data, and a CS signal that becomes active during a command.

[0016] Each memory die has a CS input for selecting the memory die to be used for command execution when active. A memory die can complete the execution of a supported command if its CS input is active throughout the command, and typically abandons the command execution if the CS input becomes inactive before the execution is completed. A memory die typically ignores an unsupported command even if its CS input is active throughout the command.

[0017] Various structures can be used to access individual memory dies within a package. For example, the entire bus signal including the bus CS signal may be coupled in parallel to all memory dies. This type of technology is provided under the name SpiStack (registered trademark) by Winbond Electronics Corp and is implemented within the company's W25M product series. When sending commands via the bus, all memory dies first receive the command, and each memory die independently determines whether to execute the command or discard it. In this parallel bus approach, since the memory dies are usually of the same memory type and need to share common rules for determining command execution or discard, it is not suitable for mixing different types of memory dies within a package.

[0018] In another approach, the host bus can be terminated and the host bus can be coupled to an intermediary controller that generates individual bus signals including the corresponding CS signals to different memory dies. The host can communicate with each memory die only indirectly through the controller. This approach is usually highly complex and expensive because the controller processes multiple full buses for each memory die.

[0019] In the disclosed embodiment, the bus is coupled in parallel to a plurality of memory dies except for the CS signal that is connected to only one of the memory dies (referred to herein as the "primary memory die" in this specification). The primary memory die controls access to the other memory dies (also referred to herein as "secondary dies") by providing an individual CS signal to each secondary die.

[0020] Consider an integrated circuit (IC) that includes one primary memory die and one or more secondary memory dies. The primary memory die is coupled to a bus that provides a primary chip select (CS) signal via a primary CS line that connects only to the primary memory die. The secondary memory die is coupled to a bus that does not include the primary CS line and is coupled to a corresponding secondary CS line that transmits a corresponding secondary CS signal provided by the primary memory die. When the primary CS signal is active, the primary memory die receives a command via the bus and, in response to an identification that the command is addressed to the primary memory die, executes the command within the primary memory die. Otherwise, in response to an identification that the command is addressed to a secondary memory die, the primary memory die causes the secondary memory die to execute the command by transmitting the primary CS signal as a secondary CS signal on the secondary CS line of a given secondary memory die.

[0021] In the following description, for clarity, some of the embodiments described refer to a package that includes a primary memory die and a single secondary die. However, the disclosed technology is equally applicable to packages that include multiple secondary memory dies.

[0022] In some embodiments, the primary memory die includes local memory that is selectable by a local “valid signal” transmitted on a local “valid line,” and the primary memory die (i) transmits the primary CS signal as a local valid signal on the local valid line; and (ii) executes the command by deactivating the secondary CS signal provided to the secondary memory die.

[0023] In other embodiments, the IC includes a secondary die coupled to a bus that does not include a primary CS line and coupled to another secondary CS line that carries another secondary CS signal provided by the primary memory die. In these embodiments, the primary die causes the secondary die to execute commands via operations of (i) transmitting the primary CS signal as another secondary CS signal on another secondary CS line; (ii) deactivating the secondary CS signal provided to the secondary die; and (iii) deactivating the local valid signal of the local memory provided to the primary die.

[0024] In the disclosed structure, at least a portion of the primary memory die and the secondary memory die may be different corresponding memory types, and each memory type is selected from a list including at least (i) a NAND flash memory type; and (ii) a NOR flash memory type.

[0025] In one embodiment, the primary memory die and the secondary memory die support corresponding first and second different access protocols, and the primary memory die presents the second access protocol for the secondary memory die to a host coupled to the bus.

[0026] The primary memory die can select a target memory die for executing the received command (or one or more subsequent commands) using any suitable method (e.g., based on a dedicated die selection command or based on address information included in the command).

[0027] In some embodiments, the primary die can operate in one of three access modes: "Standalone" mode, "Restricted-Access" mode, and "Full-Access" mode. In Standalone mode, the primary memory die controls the second CS signal to block access to the secondary memory die for all received commands. In Restricted-Access mode, the primary memory die controls the second CS signal to enable access to the secondary memory die for a corresponding partial subset of commands supported by the secondary memory die. In Full-Access mode, the primary memory die controls the second CS signal to enable full access to the secondary memory die for all commands supported by the secondary memory die, and at the same time, selectively executes (by the primary memory die) commands that modify the access mode.

[0028] The disclosed structure can be used, for example, for secure boot. In such an exemplary embodiment, the primary memory die locally stores the boot code of the host coupled to the bus and manages secure access to the stored boot code, such as during storage, update, upload, etc. of the boot code.

[0029] In one embodiment, the primary memory die functions as the root of trust (RoT) of the base layer system including the IC to secure the storage operations for the secondary memory die. For example, the primary memory die can provide the secondary memory die with write protection and various encryption services such as encryption and data authentication.

[0030] In the disclosed technology, the primary memory die controls access to the secondary memory die by controlling the corresponding CS input. With the disclosed structure and related embodiments, complexity is reduced, power consumption is decreased, and fast access to the secondary memory die is achieved. Also, it supports memory dies of various storage technologies, such as mixing flash NOR dies and flash NAND dies within the same package. Since the primary die manages the selection of each command die, the memory dies do not need to follow common rules and / or do not need to cooperate with each other in other ways to select the target die, and as a result, implementation is simplified and becomes more flexible.

[0031] Referring to FIG. 1, computer system 20 includes a host 24 coupled to an integrated circuit (IC) 28 that implements a storage device in this embodiment via a bus 32 (also referred to as a link or interface). It includes a plurality of (e.g., 'n') input / output (IO) lines, a clock line indicated by "CLK", and a chip select (CS) line indicated by "CS-0". The bus 32 may include, for example, a Serial Peripheral Interface (SPI). Alternatively, other suitable bus types may be used, such as, for example, an extended SPI, an extended SPI (xSPI), or an Inter-Integrated Circuit (I2C) bus.

[0032] In computer system 20, host 24 typically transmits commands via bus 32 and storage device 28. The communication may include transmission of an opcode, transmission of an address, transmission of data, and / or reception of data.

[0033] Computer system 20 can be used in various applications such as a single Internet of Thing (IoT) device, automotive applications, a PC / server Basic Input-Output System (BIOS), and industrial controllers.

[0034] The memory device 28 includes a memory die 40 denoted as "die-0" that includes a local memory 42 and CS logic 46. The memory die 40 is referred to herein as the "primary memory die" or simply the "primary die". The memory device 28 further includes one or more memory dies 50, each of which includes a memory 54. The memory dies 50 are denoted as "die-m", where'm' represents an integer greater than 0. The memory dies 50 are referred to herein as the "secondary memory dies" or simply the "secondary dies".

[0035] Both the primary die and each secondary die have a CS input, and when the CS input is active, it selects the corresponding memory die. Note that the selection of a memory die means obtaining access to the internal memory of the memory die. In FIG. 1, the memory device 28 includes two secondary dies denoted as die-1 and die-2, but in alternative embodiments, the memory device 28 may include a single secondary die or more than two secondary dies.

[0036] In the structure of FIG. 1, the CLK line and the IO line of the bus 32 are connected in parallel between the host 24 and each primary die and secondary die. In comparison, the CS-0 line of the bus 32 (also referred to herein as the "primary CS line") is connected between the host and the CS input of the primary die, but not to the CS input of the secondary die. The memory selection line (also referred to herein as the "enable line") is connected between the CS logic and the local memory 42. The CS lines denoted as "CS-1" and "CS-2" (also referred to herein as the "secondary CS lines") are connected between the CS logic and the CS input of the corresponding secondary die. With the above-described structure, the CS logic 46 can control access to its local memory (42), as well as the secondary dies (50) and their memories (54).

[0037] In the following description, the CS signal transmitted on the primary CS line is also referred to as the "primary CS signal" in this specification, the CS signal transmitted on the secondary CS line is also referred to as the "secondary CS signal" in this specification, and the memory selection signal transmitted on the active line is also referred to as the "active signal" in this specification. In the following description, the CS logic controls the active signal for accessing the local memory 42 of the primary die and controls the secondary CS signal for accessing the secondary die.

[0038] The local memory 42 of the primary die 40 and the memory 54 of the secondary die 50 may include any suitable type of memory. In one embodiment, the local memory 42 of die-0 includes a NOR flash device, and the memories 54 of die-1 and die-2 include NAND flash devices. However, in other embodiments, any other suitable combination of memory types may be used. For example, the local memory 42 of the primary die and the memories 54 of all secondary dies may be of the same memory type. As another example, the memories 54 of two (or more) secondary dies may be of different corresponding memory types. In the description of the present invention, the main memory types used are NOR dies and NAND dies, but this is not essential, and any other suitable memory types (volatile or non-volatile) may be used.

[0039] When the host 24 transmits a command via the bus, the primary die controls the active signal and the secondary signal so that the command is first received by the primary die and all secondary dies while the primary CS signal (transmitted on the CS-0 line) is active. As the command progresses (e.g., after receiving the opcode parameter), the CS logic determines the target die to which the command is to be transmitted and controls the active signal and the secondary CS signal so that the command is executed by the target die and discarded by all other memory dies.

[0040] The method for determining the target die will be described in detail below.

[0041] Execution of Commands in a Multi-Die Memory Device

[0042] Referring to FIG. 2, this method is described as being executed by the primary die (die-0) of the memory device 28 in FIG. 1. For example, if all memory dies of the memory device support the same command set and command format, the method of FIG. 2 can be applied.

[0043] This method starts with a command reception step 100. Here, die-0 receives a command from host 24 via bus 32. The command is transmitted on the bus IO lines using the bus CLK signal. Also, it is assumed that the primary CS signal transmitted on the primary CS line (CS-0) is active during the command.

[0044] In response to the primary CS signal, the CS logic 46 of die-0 first selects the local memory 42 and all secondary dies 50 (die-1 and die-2 in this embodiment). To achieve this, the CS logic transmits the primary CS signal as a valid signal on the internal enable line and transmits the primary CS signal as a secondary CS signal on the secondary CS lines of the secondary dies. Thus, the local memory 42 of die-0 and the memories 54 of the secondary dies receive at least the opcode parameter of the command. Thus, each of the primary die and the secondary dies is ready to execute the command when selected as the target die.

[0045] In the die selection step 104, the CS logic of die-0 determines the target die to which the command is to be transmitted. Die-0 can determine the target die based on, for example, the opcode parameter and / or address parameter (if available) in the current or previous command.

[0046] In step 104, if die-0 is selected as the target die, the method proceeds to the primary die execution step 108. Further, if die-1 or die-2 is selected as the target die, the method proceeds to the secondary die execution step 112.

[0047] In step 108, die-0 executes a command by CS logic by: (i) transmitting an (active) primary CS signal as a valid signal on the local active line of the local memory 42; and (ii) deactivating the secondary CS signals of all secondary dies (die-1 and die-2 in this embodiment). Since the selection of the selected secondary die is canceled, the secondary die abandons the execution of the command.

[0048] In step 112, die-0 causes the target die (die-1 or die-2 in this embodiment) to execute a command by CS logic by: (i) transmitting the primary CS signal as a secondary CS signal on the secondary CS line of the target die; (ii) deactivating the secondary CS signals of the other secondary dies; and (iii) deactivating the local active signal of die-0.

[0049] The deactivation of the valid signal or the secondary CS signal can be performed by any suitable method, such as using a logical OR gate (ORgate) when the signal is low-active or using a logical AND gate (ANDgate) when the signal is high-active. After steps 108 and 112, the method loops back to step 100 to receive subsequent commands.

[0050] The method of FIG. 2 is shown as an example, and other suitable methods can also be used. For example, if the command includes only an opcode command (e.g., an arrangement command), the primary die can control the valid signal and the secondary CS signal to cause a plurality of memory dies to execute the command in parallel with each other.

[0051] Referring to FIG. 3, this timing diagram describes a system (e.g., system 20) in which host 24 executes a read command using, for example, the method of FIG. 2.

[0052] In one embodiment, bus 32 includes SPI, and the SPI has an IO0 line for transmitting commands to storage device 28 and an IO1 line for receiving data from the storage device. As shown, the command has an 8-bit opcode parameter 150 to be transmitted that starts with the Most Significant bit (MSb) and ends with the Least Significant bit (LSb). Following the opcode parameter is a 32-bit address parameter 154 to be transmitted that starts with the most significant address bit (A31) and ends with the least significant address bit (A0). In response to the read command, the storage device sends back bytes - 0... byte - m of the data read from the target die to the host via the IO1 line.

[0053] The primary CS signal 158 transmitted from the host via the primary CS line (CS - 0) of the bus becomes active during the command. In the embodiment of FIG. 3, the primary CS signal becomes active immediately before the start of the MSb of the opcode (e.g., in this embodiment, it changes from high level to low level and is maintained until the memory device completes the transmission of the m - th data byte via the IO1 line).

[0054] In the embodiment of FIG. 3, assume that die - 0 determines the target die at time instance 162 based on some of the upper address bits of the address parameter. The timing diagram shows the active signals and the secondary CS signals when (i) the target die is the primary die - 0 (170) and (ii) the target die is the secondary die - 2 (174).

[0055] When the primary CS158 signal becomes active, the CS logic first transmits the primary CS signal as a valid signal on the active line of die-0, and then transmits it as a secondary signal on the secondary CS lines of both die-1 and die-2. As a result, all memory dies can receive at least part of the opcode parameter and the address parameter.

[0056] When die-0 is the target die, the CS logic continues to transmit the primary CS signal as a valid signal on the active line. Also, by deactivating the secondary CS signals of the secondary dies by the CS logic, die-1 and die-2 discard the command. When die-2 (for example) is the target die, die-2 executes the command by transmitting the primary CS signal as a secondary signal on the secondary CS line of die-2 by the CS logic. Further, by deactivating the secondary CS signal of die-1 and the valid signal of die-0 by the CS logic respectively, die-1 and die-0 discard the command.

[0057] The timing diagram shown in FIG. 3 and described above is cited as an example. In alternative embodiments, other suitable timing diagrams may be used. For example, in some embodiments, the operation mode of the bus width can be quad or octal, and separate IO lines can be added accordingly. In this case, multiple bits of the command are transmitted every clock cycle. Although FIG. 3 shows a 32-bit address parameter, other address lengths such as a 24-bit address may be used. As another example, although the low-active CS signal is illustrated in the timing diagram of FIG. 3, a high-active CS signal may be used in alternative embodiments.

[0058] After receiving a command from the memory device 28, the primary die determines (e.g., using the CS logic 46) which memory die within the memory device will execute the command. The memory die selected to execute a given command is referred to herein as the "target die" of the given command. The target die can be one of the primary die or the secondary die. In general, a command sequence can include commands sent to the same memory die or two or more different memory dies. In the disclosed embodiments, the primary die 40 (die-0) processes the selection of a single target die for each command.

[0059] The primary die can determine the target die of a given command in various ways, as described below. In one embodiment, each memory die is pre-assigned a corresponding die identifier, and the primary die selects the target die in response to a dedicated die selection command that specifies the identifier of the target die. The dedicated command can specify the die identifier, for example, within the opcode parameter or in a separate parameter after the opcode parameter. The die selection command is processed by the primary die but is ignored by the secondary die because it is not part of the command set supported by the secondary die.

[0060] In one embodiment, in response to the die selection command, the primary die controls the valid signal and the secondary CS signal so that subsequent commands are executed by the target die (usually not by other dies). The primary die continues to monitor the commands received thereafter, even if the target die is a secondary die, and re-selects the target die in response to receiving another die selection command.

[0061] Some commands, such as read, programming, and erase commands, include an address parameter. In the case of such commands, the primary die can determine the target die based on the address parameter. In this method, the primary die and the secondary die are mapped to a common address space divided into a plurality of address sub-ranges. Here, each memory die is mapped to a corresponding address sub-range of the address space. In some embodiments, after receiving a command having an address parameter, the primary die determines the target die based on at least a part of the address parameter (e.g., the most significant (MS) byte of the address) by identifying the address sub-range to which the address parameter belongs. The selection of the target die based on the address described above can be applied to a storage device in which all memory dies share a command set and a command format, but is not limited thereto.

[0062] As described above with reference to FIG. 1, the storage device may include memory dies of various memory types that follow different command sets, different command formats, and / or different access protocols, such as when mixing NOR and NAND flash memory devices within the same storage device. In such an embodiment, the host accessing the target die needs to use a command from the command set supported by the corresponding target die. Alternatively or additionally, the primary die can present to the host the access protocol used by the secondary die having a different memory type than the primary die. Thereby, the host can communicate with all memory dies using a common access protocol.

[0063] For example, consider a case where a read operation is performed in a memory device 28 in which the primary die is a NOR flash device and the secondary die is a NAND flash device. The read (or write) command of the NOR flash device usually transmits a full address parameter for direct access (e.g., a 24-bit or 32-bit memory address). In contrast, the read operation applied to the NAND flash device is usually indirect and includes a "page load" command followed by one or more "page read" commands. In the target NAND device, the page load command loads a page from the memory into a local read buffer (not shown) of the target NAND device. The page may contain thousands of bytes of data (e.g., 4 kilobytes or other appropriate size). The page read command reads the data loaded by the previous page load command from the read buffer. The page load command usually transmits only the upper 16 bits (e.g., A31... A16) of the address parameter, and the page read command usually transmits only the lower 16 bits (e.g., A15... A0) of the address parameter. In the present embodiment, when the portion of the address transmitted by the page load command is within the sub-range assigned to a given target die, the primary die selects the given target die.

[0064] The page load command is usually executed by all secondary NAND dies. After determining the NAND target die, the primary die controls the valid signal and the secondary CS signal so that the subsequent page read command is executed only by the target NAND die and discarded by the primary die and other secondary dies. Also, the primary die monitors the subsequent commands received via the bus, and after detecting a subsequent page load command, reselects the target die based on the address parameter transmitted by the subsequent page load command described above.

[0065] If the corresponding storage sizes of two or more memory dies are different, various address mappings can be used. For example, consider a storage device including a 128-megabit primary NOR die and one or more 1-gigabit secondary NAND dies. This structure is suitable, for example, when storing relatively small boot code in the NOR device and using the secondary NAND die to expand the entire storage space.

[0066] In such an embodiment, the primary die can be mapped to an address sub-range that exceeds the address sub-range assigned to the secondary NAND die. For example, in the case of a single 1-gigabit secondary NAND die, the NAND die is mapped to the address sub-range 0000_0000h - 07FF_FFFFh, and the 128-megabit primary NOR is mapped to the address range 0800_0000h - 08FF_FFFFh.

[0067] In another embodiment, the address sub-range assigned to the primary NOR die and the address range assigned to the secondary NAND die overlap. For example, a 128-megabit primary NOR die is mapped to the address sub-range specified by 0000_0000h - 00FF_FFFFh, and a single 1-gigabit secondary NAND die is mapped to the address sub-range specified by 0100_0000h - 07FF_FFFFh. In this case, the lower 128-megabit address of the secondary die cannot be accessed.

[0068] In some embodiments, the primary die NOR presents the access protocol of the secondary die NAND to the host. To achieve this purpose, the primary die NOR implements the page load and page read commands of the NAND die so that the host of the controller with the NAND flash can use the same command set and format (at least when used for read operations) to access the primary die NOR and the secondary die NAND. In these embodiments, since the local memory of the primary die NOR appears to the host as a NAND device, the software executed by the host can access the memory in the storage device when accessing the memory in the monolithic (single die) NAND flash memory device. In some embodiments, before accessing either the primary die in the NAND format or the secondary NAND die, the host needs to load a suitable driver designed to access the NAND memory, for example, from the storage device.

[0069] Some commands are so short that the primary die may not have enough time to determine the target die based on the address parameter. For example, the block erase command for a NAND device issued in the xSPI octal dual transfer rate (DTR) bus mode (also referred to as the “8d-8d-8d” mode, meaning that commands, addresses, and data are transmitted as 8-bit-wide DTRs) requires one clock cycle for the opcode, followed by additional clock cycles for the address. In this case, the secondary die may undesirably execute the erase command in response to the opcode and address parameter before the primary die has determined the target die based on the address parameter. In some embodiments, to avoid such incorrect command execution, the primary die restricts the use of the address-based target selection method to selected commands (e.g., read operations only) and blocks commands that may cause incorrect execution (such as erase operations and programming operations).

[0070] Note that, unlike erase commands and program commands, in a read command, the die continues to process the command after receiving the address, prepares a response, and begins transmitting the response to the host. This provides sufficient time for the command to complete by a die other than the target die.

[0071] In some embodiments, a write-enable command is performed before a command (such as a programming command or an erase command) that modifies the content stored in the memory device. The primary die monitors the commands received via the bus and, when it detects a write-enable command (or other condition) when the target die is one of the secondary dies, the primary die blocks further access to the secondary die until, for example, the next system reset or according to a predefined implementation within the primary die. Thus, the primary die blocks a command sequence that begins with a write-enable command followed by a programming or erase command. This means that the secondary die is essentially write-protected. Thus, the primary die manages the write protection of the secondary die even if the secondary die itself does not support a proprietary write protection mechanism.

[0072] In some embodiments, the primary die supports a security function for providing write protection (and other security features) to the secondary die even if the secondary die does not support a proprietary security function. For example, the primary die can obtain access to the secondary die by executing security commands protected by, for example, a signature, a password, and / or other user authentication mechanisms.

[0073] In some embodiments, the primary die supports an access mode selected from a plurality of predefined modes. In an exemplary embodiment, the primary die supports three access modes including (i) a "standalone mode", (ii) a "restricted access" mode, and (iii) a "full access" mode. In one embodiment, the primary die 40 switches the access mode under the control of the host 24.

[0074] In stand-alone mode, the primary die permits access only to local memory and blocks access to the secondary die. This mode is useful, for example, in a system where the host boots from the primary die (e.g., a NOR flash device). In stand-alone mode, the primary die selects itself as the target die for all received commands. Thus, there is no need to determine the target die during operation.

[0075] After the boot process is complete, the primary die may be switched to restricted access mode. In restricted access mode, the primary die (e.g., NOR) permits access (e.g., read access) to the secondary die (e.g., NAND) for some commands that include an address parameter. In restricted access mode, as described above, the primary die can present the access protocol of the secondary die to the host.

[0076] In full access mode, the primary die permits access to the secondary die for all supported commands. This mode can be used for programming, erasing, and / or configuring the secondary die. In full access mode, the primary die monitors the received commands and responds only to memory commands that modify the access mode to restricted access mode or stand-alone mode.

[0077] In some embodiments, the stand-alone mode functions as the default access mode after reset. In such embodiments, in response to a reset event, the primary die automatically starts operating in the stand-alone mode, enabling the host to boot from the primary die (e.g., NOR). At an appropriate later time, e.g., after boot completion, the host loads firmware (FW) code including a driver for accessing the NAND die from the storage device and switches to the restricted access or full access mode. In other embodiments, the restricted access mode or full access mode may function as the default mode after reset. In this case, after reset, the primary die starts operating in the restricted access mode or full access mode. For example, this embodiment is useful when the host boots from the secondary die instead of the primary die.

[0078] In an exemplary embodiment, the primary die includes a security device stacked within the same package as one or more secondary dies. In such an embodiment, the primary die functions as the root of trust (RoT) of the system. The storage device can store, protect, and update the boot code stored in the primary die, depending on the security function of the primary die.

[0079] The above embodiments are provided as examples, and other suitable embodiments can also be used. For example, in some of the above embodiments, a storage device including a NOR primary die and one or more NAND secondary dies is mentioned, but this structure is not essential, and in other embodiments, other suitable combinations of NOR, NAND, and / or other types of memory may be used.

[0080] The configuration of the computer system 20 (including the host 24, the storage device 28, and its components such as the primary die 40, the local memory 42, the CS logic 46, and the secondary die 50 and its memory 54) is only a configuration example shown solely for the purpose of conceptually clarifying. In alternative embodiments, any other suitable computer, host, and memory die configurations can be used.

[0081] The different sub-units of the storage device 28 can be implemented using appropriate hardware such as one or more Application-Specific Integrated Circuits (ASICs) or Field-Programmable Gate Arrays (FPGAs), using software, or using a combination of hardware elements and software elements.

[0082] The storage device 28 may include one or more general-purpose processors programmed with software to perform the functions described herein. The software may be, for example, in electronic form downloaded to the processor via a network or a host, or alternatively or additionally, provided and / or stored on a non-transitory tangible medium (such as, for example, magnetic, optical, or electronic memory).

Industrial Applicability

[0083] The secure storage method and system in the multi-die package of the present invention can be applied to memory devices.

Explanation of Reference Numerals

[0084] 20: Computer system 24: Host 28: Integrated circuit / Storage device 32: Bus 40: Primary memory die 42: Local memory 46: CS logic 50: Secondary memory die 54: Memory 100, 104, 108, 112: Step 150: Opcode parameter 154: Address parameter 158: Primary CS signal 162: Time instance A0: Lowest address bit A31: Highest address bit LSb: Least significant bit MSb: Most significant bit

Claims

1. A primary memory die coupled to a bus that provides a primary chip select signal via a primary chip select line connected to the primary memory die; A secondary memory die coupled to a secondary chip select line that transmits a secondary chip select signal provided by the primary memory die and is coupled to the bus excluding the primary chip select line; comprising wherein the primary memory die receives a command via the bus when the primary chip select signal is active, executes the command within the primary memory die in response to an identification that the command is addressed to the primary memory die, and causes the secondary memory die to execute the command by transmitting the primary chip select signal as the secondary chip select signal on the secondary chip select line in response to an identification that the command is addressed to the secondary memory die; is arranged as wherein the primary memory die includes a local memory selectable by a local valid signal transmitted on a local valid line, and the primary memory die is configured to: (i) transmit the primary chip select signal as the local valid signal on the local valid line; and (ii) execute the command through an operation of deactivating the secondary chip select signal provided to the secondary memory die; an integrated circuit.

2. The integrated circuit includes another secondary die coupled to another secondary chip select line that transmits another secondary chip select signal provided by the primary memory die and is coupled to the bus excluding the primary chip select line, and the primary die is configured to: (i) transmit the primary chip select signal as the another secondary chip select signal on the another secondary chip select line; (ii) deactivate the secondary chip select signal provided to the secondary die; and (iii) cause the another secondary die to execute the command through an operation of deactivating the local valid signal of the local memory provided to the primary die; The integrated circuit according to claim 1.

3. The primary memory die and the secondary memory die have corresponding first and second different memory types, each memory type being selected from a list including at least: i. a NAND flash memory type; and ii. a NOR flash memory type. The integrated circuit according to claim 1.

4. The primary memory die and the secondary memory die support corresponding first and second different access protocols, and the primary memory die is configured to present the second access protocol for the secondary memory die to a host coupled to the bus. The integrated circuit according to claim 1.

5. The primary memory die is configured to cause the selected memory die to execute one or more commands received after the die selection command that specifies the memory die selected between the primary memory die and the secondary memory die in response to receiving the die selection command. The integrated circuit according to claim 1.

6. The primary memory die and the secondary memory die are mapped to different corresponding address sub-ranges of a common address space, and the primary memory die is configured to identify an address parameter in the received command and execute the received command through the primary memory die or the secondary memory die according to the address range to which the address parameter belongs. The integrated circuit according to claim 1.

7. When the primary memory die is switched to the stand-alone mode, the primary memory die is configured such that the primary memory die controls a second chip select signal to block access to the secondary memory die for all received commands. The integrated circuit according to claim 1.

8. When the primary memory die is switched to the restricted access mode, the primary memory die is configured such that the primary memory die controls a second chip select signal to permit access to the secondary memory die for a partial subset of the commands supported by the secondary memory die. The integrated circuit according to claim 1.

9. When the primary memory die is switched to the full access mode, the primary memory die controls the second chip select signal such that the primary memory die permits full access to all commands supported by the secondary memory die by the secondary memory die, and at the same time, is configured to selectively execute a command that modifies the access mode. The integrated circuit according to claim 1.

10. The primary memory die locally stores the host boot code coupled to the bus and manages secure access to the stored boot code. The integrated circuit according to claim 1.

11. The primary memory die is arranged to function as a root of trust of the base layer system including the integrated circuit to secure the memory operation for the secondary memory die. The integrated circuit according to claim 1.

12. In an integrated circuit, the integrated circuit includes a primary memory die coupled to a bus that provides a primary chip select signal via a primary chip select line connected to the primary memory die, and a secondary memory die coupled to a secondary chip select line that does not include the primary chip select line and transmits a secondary chip select signal provided by the primary memory die. When the primary chip select signal is active, the primary memory die receives a command via the bus. In response to identifying that the command is addressed to the primary memory die, the command is executed within the primary memory die. In response to identifying that the command is addressed to the secondary memory die, the primary memory die transmits the command to the secondary memory die by transmitting the primary chip select signal as the secondary chip select signal on the secondary chip select line. The primary memory die includes a local memory selectable by a local valid signal transmitted on a local valid line, and executing the command within the primary memory die includes: i. transmitting the primary chip select signal as the local valid signal on the local valid line; and ii. executing the command through an operation of deactivating the secondary chip select signal provided to the secondary memory die. Data storage method.

13. The integrated circuit includes another secondary die coupled to the bus excluding the primary chip select line and coupled to another secondary chip select line for transmitting another secondary chip select signal provided by the primary memory die, and the method includes: i. transmitting the primary chip select signal as the another secondary chip select signal on the another secondary chip select line; ii. deactivating the secondary chip select signal provided to the secondary die; and iii. causing the another secondary die to execute the command through an operation of deactivating the local valid signal of the local memory provided to the primary die. The data storage method according to claim 12.

14. The primary memory die and the secondary memory die have corresponding first and second different memory types, and each memory type is selected from a list including at least: i. NAND flash memory type; and ii. NOR flash memory type. The data storage method according to claim 12.

15. The primary memory die and the secondary memory die support corresponding first and second different access protocols, and the method includes presenting, via the primary die, the second access protocol for the secondary memory die to a host coupled to the bus. The data storage method according to claim 12.

16. In response to receiving a die selection command that designates a selected memory die between the primary memory die and the secondary memory die, causing the selected memory die to execute one or more commands received after the die selection command. The data storage method according to claim 12.

17. The primary memory die and the secondary memory die are mapped to different corresponding address sub - ranges of a common address space, and the method includes identifying an address parameter in the received command and executing the received command through the primary memory die or the secondary memory die according to the address range to which the address parameter belongs. The data storage method according to claim 12.

18. When the primary memory die is switched to the stand - alone mode, the primary memory die includes controlling a second chip - select signal to block access to the secondary memory die for all received commands. The data storage method according to claim 12.

19. When the primary memory die is switched to the restricted - access mode, the primary memory die includes controlling a second chip - select signal to permit access to the secondary memory die for a partial subset of the commands supported by the secondary memory die. The data storage method according to claim 12.

20. When the primary memory die is switched to the full - access mode, the primary memory die includes controlling a second chip - select signal to permit full access to the secondary memory die for all commands supported by the secondary memory die and, at the same time, selectively executing commands that modify the access mode. The data storage method according to claim 12.

21. Further including locally storing the boot code of the host coupled to the bus and managing secure access to the stored boot code. The data storage method according to claim 12.

22. Further including functioning as a root of trust for the base - layer system including the integrated circuit to secure the memory operation for the secondary memory die. The data storage method according to claim 12.

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