Resistivity measurement method

Abstract

To provide a resistivity measurement method having a novel resistivity conversion performing when tracing an international standard of a C-V method by using a PW wafer.SOLUTION: A resistivity measurement method for measuring a resistivity of an EP layer formed in an EPW manufactured by using a resistivity substrate with a C-V method, is a resistivity measurement method for obtaining a four-probe resistivity of the EP layer of a measurement object by performing: a conversion by a first conversion formula obtained by comparing a C-V resistivity obtained by measuring a reference PW to which the with a four-probe reference resistivity with the C-V method and the four-probe reference resistivity to the resistivity to which a SEMI conversion resistivity obtained by measuring the resistivity of the EP layer of the measurement object with the C-V method or the resistivity obtained by executing a predetermined conversion thereto; and a conversion by a second conversion formula calculated by comparing a high resistivity substrate EPW manufactured by using the high resistivity substrate with the resistivity which can be measured by the C-V method and a C-V resistivity of the EP layer of a low resistivity substrate EPW manufactured by using the low resistivity substrate.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a resistivity measurement method, and more particularly, to a resistivity measurement method for converting the resistivity of a silicon epitaxial layer measured by the C-V method into a four-probe resistivity traceable to an international standard such as NIST.

Background Art

[0002] Conventionally, as a method for measuring the resistivity of a polished wafer (PW) in which the main surface of a silicon single crystal wafer is polished (hereinafter sometimes simply referred to as PW), or a silicon epitaxial wafer (hereinafter sometimes simply referred to as EPW) in which a silicon epitaxial layer (hereinafter sometimes simply referred to as an epi layer) is vapor-phase grown on the main surface of the PW wafer, the C-V (Capacitance-Voltage) method is known.

[0003] For example, as described in Patent Document 1, in order to measure the C-V characteristics of a silicon single crystal wafer, a Schottky junction is formed on the main surface (first main surface) of the silicon single crystal wafer serving as a sample using a metal electrode, the sample is fixed to the wafer stage of a C-V measurement device, and a reverse bias voltage is continuously applied while varying it with respect to the electrode, thereby expanding the depletion layer inside the silicon single crystal wafer and changing its capacitance.

[0004] Then, from the relationship between the bias voltage and the capacitance of the depletion layer, the impurity concentration and resistivity at a predetermined depth from the main surface of the silicon single crystal wafer are calculated.

[0005] In order to obtain highly accurate C-V characteristics, it is necessary to keep the contact resistance between the main back surface (second main surface) of the sample and the wafer stage small.

[0006] Patent Document 1 discloses a method for measuring C-V characteristics by placing a conductive cushion on the wafer stage and closely attaching a silicon single crystal wafer having a conductive paste applied to the main back surface on the conductive cushion.

[0007] As the conductive cushion, it is preferably to use silicone rubber kneaded with silver or carbon, having a resistivity of 0.01 Ω·cm or less and a thickness of 0.2 mm or more and 0.75 mm or less.

[0008] For the conversion from C-V characteristics to resistivity, SEMI MF723-0307 or the Irvin curve is used. The resistivity measurement value by the four-probe method can be corrected using a standard wafer having traceability to international standards such as the 7-level resistivity standard materials (SRM: Standard Reference Material) of SRM2541 (0.01 Ω·cm) to SRM2547 (200 Ω·cm) provided by NIST (National Institute of Standards and Technology).

[0009] It is also desirable that the resistivity measurement value by the C-V method has traceability to international standards such as NIST. Therefore, for example, it has been proposed to ensure traceability by measuring a standard wafer having traceability to the resistivity standard material SRM by the C-V method.

[0010] For example, in Patent Document 2, using a measurement device of the four-probe method calibrated with the resistivity standard materials of SRM2541 to SRM2547 as the primary standard sample, the epitaxial layer resistivity of a silicon epitaxial wafer having a P / N junction is valued to obtain a secondary standard sample, and by measuring the epitaxial layer with a C-V method measurement device for surface electrodes, the C-V method measurement device for the surface electrodes is calibrated.

[0011] Then, using the C-V method measurement device for surface electrodes calibrated with the secondary standard sample, the epitaxial layer resistivity of a P / P type or N / N type silicon epitaxial wafer is measured to obtain a tertiary standard sample, and it has been proposed to calibrate the C-V method measurement device for back electrodes using the tertiary standard sample.

Prior Art Documents

Patent Document

[0012]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0013] When using the method proposed in Patent Document 2, it is necessary to calibrate the resistivity using a silicon epitaxial wafer (EPW) having a P / N junction. Also, both a C - V method measuring device for the surface electrode and a C - V method measuring device for the back electrode are required.

[0014] The present invention has been made in view of the above problems, and an object thereof is to provide a resistivity measurement method having a new resistivity conversion performed when tracing the C - V method to an international standard such as NIST using a PW wafer.

Means for Solving the Problems

[0015] In order to solve the above problems, in the present invention, a resistivity measurement method for measuring the resistivity of a silicon epitaxial layer to be measured formed on a silicon epitaxial wafer manufactured using a low - resistivity substrate having a resistivity of 0.02 Ω·cm or less by the C - V method, for the SEMI - converted resistivity obtained by measuring the resistivity of the silicon epitaxial layer to be measured by the C - V method, or the resistivity obtained by performing a predetermined conversion on the SEMI - converted resistivity, conversion by a first conversion formula obtained by comparing the C - V resistivity obtained by measuring a standard polished wafer with a four - probe standard resistivity assigned to a four - probe standard resistivity by the C - V method, and For the silicon epitaxial layer of a high-resistivity substrate silicon epitaxial wafer fabricated using a high-resistivity substrate having a resistivity measurable by the C-V method and the silicon epitaxial layer of a low-resistivity substrate silicon epitaxial wafer fabricated using a low-resistivity substrate having a resistivity of 0.02 Ω·cm or less, conversion by a second conversion formula obtained by comparing the C-V resistivity is performed, and a resistivity measurement method is provided, characterized by obtaining the four-probe resistivity of the silicon epitaxial layer to be measured. Here, the resistivity of the high-resistivity substrate having a resistivity measurable by the C-V method is, for example, 0.1 Ω·cm or more and 1000 Ω·cm or less.

[0016] In addition to the conversion by the first conversion formula obtained by comparing the C-V resistivity and the four-probe standard resistivity of a standard polished wafer using the present invention, by performing the conversion by the second conversion formula obtained by comparing the C-V resistivity of the silicon epitaxial layer formed on the high-resistivity substrate silicon epitaxial wafer and the C-V resistivity of the silicon epitaxial layer formed on the low-resistivity substrate silicon epitaxial wafer, it becomes possible to convert the C-V resistivity of the silicon epitaxial layer formed on the low-resistivity substrate into a four-probe resistivity traceable to an international standard such as NIST.

[0017] That is, according to the present invention, it is possible to provide a resistivity measurement method having a new resistivity conversion performed when tracing the C-V method to an international standard such as NIST using a PW wafer.

[0018] The assignment of the four-probe standard resistivity value to the standard polished wafer is a four-probe resistivity measurement device calibration step of calibrating a four-probe resistivity measurement device using a standard wafer traceable to an international standard, and a polished wafer standard resistivity assignment step of assigning the four-probe standard resistivity value to a polished wafer using the four-probe resistivity measurement device calibrated in the four-probe resistivity measurement device calibration step, and It is desirable to have

[0019] Using the standard polished wafer thus obtained, the first conversion formula is obtained, and by performing the conversion according to this first conversion formula, the C-V resistivity of the silicon epitaxial layer formed on the high-resistivity substrate can be converted into the four-probe resistivity that can be traced to international standards such as NIST with higher accuracy.

[0020] In this case, in the process of attaching the standard resistivity value to the polished wafer, the main surface of the polished wafer may be measured with the four-probe resistivity measuring device.

[0021] Alternatively, the polished wafer may be ground to form a ground surface, and the ground surface may be measured with the four-probe resistivity measuring device. It is desirable to perform surface grinding as the grinding.

[0022] Thus, the measurement using the four-probe resistivity measuring device may be performed on the main surface (PW surface) of the polished wafer or on the ground surface. When the ground surface is measured using the four-probe resistivity measuring device, the measurement accuracy of the four-probe resistivity is improved compared to the case of measuring the PW surface.

[0023] It is desirable to use, as the polished wafer, one that has been subjected to a heat treatment for eliminating oxygen donors.

[0024] By doing so, the attachment of the four-probe standard resistivity can be performed more accurately.

[0025] Alternatively, as the standard polished wafer with the four-probe standard resistivity attached, a four-probe resistivity measuring device calibration step of calibrating the four-probe resistivity measuring device using a standard wafer traceable to international standards, and a step of measuring the resistivity of a silicon single crystal wafer that has been previously subjected to a heat treatment for eliminating oxygen donors using the four-probe resistivity measuring device calibrated in the four-probe resistivity measuring device calibration step, and attaching a four-probe standard resistivity. A processing step of processing at least a first main surface of the silicon single crystal wafer with a value assigned thereto to form a polished wafer, A cleaning step of cleaning the polished wafer, It is desirable to use a material that has been subjected to the above. As the silicon single crystal wafer, for example, a wafer whose main surface is a lapped surface, a ground surface, or a chemically etched surface is used.

[0026] By using such a standard polished wafer, the C-V resistivity of the silicon epitaxial layer to be measured can be converted into a four-probe resistivity that can be traced to international standards such as NIST with higher accuracy.

[0027] For the second conversion formula, A substrate polished wafer preparation step of preparing a high-resistivity polished wafer having a resistivity measurable by the C-V method and a low-resistivity polished wafer having a resistivity of 0.02 Ωcm or less, An epitaxial wafer preparation step of epitaxially growing a silicon epitaxial layer having the same resistivity and the same conductivity type as the high-resistivity polished wafer on each of the high-resistivity polished wafer and the low-resistivity polished wafer under the growth conditions of the same dopant concentration to prepare the high-resistivity substrate silicon epitaxial wafer and the low-resistivity substrate silicon epitaxial wafer, A C-V measurement step of the comparative epitaxial wafer for C-V measurement of the silicon epitaxial layer of the low-resistivity substrate silicon epitaxial wafer and the silicon epitaxial layer of the high-resistivity substrate silicon epitaxial wafer, A comparison step of comparing the C-V resistivity of the silicon epitaxial layer of the low-resistivity substrate silicon epitaxial wafer and the silicon epitaxial layer of the high-resistivity substrate silicon epitaxial wafer is obtained through, It is desirable to perform a second conversion step of converting the C-V resistivity measurement result of the silicon epitaxial layer formed on the low resistivity substrate into the C-V resistivity of the silicon epitaxial layer formed on the silicon epitaxial wafer including the high resistivity substrate by the second conversion formula.

[0028] In addition to the conversion by the first conversion formula, by performing the second conversion step in this way, the C-V resistivity of the silicon epitaxial layer formed on the low resistivity substrate can be converted into a four-probe resistivity that can be traced to international standards such as NIST with higher accuracy.

[0029] When obtaining the first conversion formula, it is desirable to heat-treat the standard polished wafer in a hydrogen atmosphere at 250 °C or higher and 1150 °C or lower before measuring the resistivity of the standard polished wafer by the C-V method.

[0030] By subjecting the standard polished wafer heat-treated in this way to C-V measurement, it is possible to prevent a high resistance region from appearing in the surface layer portion of the impurity concentration profile or resistivity profile.

[0031] When obtaining the first conversion formula, while disposing a conductive cushion between the second main surface of the standard polished wafer and the measurement stage of the measurement device using the C-V method, a high-frequency voltage is applied to the first main surface of the standard polished wafer, and it is desirable to measure the resistivity of the standard polished wafer by the C-V method.

[0032] When obtaining the first conversion formula, by measuring the C-V resistivity of the standard polished wafer with the conductive cushion disposed in this way, even for high resistivity wafers with different resistivities, the contact resistance to the wafer stage is kept constant, so an improvement in the accuracy of the first conversion formula and the second conversion formula can be expected.

Advantages of the Invention

[0033] As described above, in the present invention, in addition to the conversion by the first conversion formula obtained by comparing the C-V resistivity of a standard polished wafer with the four-probe standard resistivity, by comparing the C-V resistivity of a silicon epitaxial layer formed on a high-resistivity substrate silicon epitaxial wafer with the C-V resistivity of a silicon epitaxial layer formed on a low-resistivity substrate silicon epitaxial wafer, and performing conversion using the second conversion formula obtained thereby, it becomes possible to convert the C-V resistivity of a silicon epitaxial layer formed on a low-resistivity substrate into a four-probe resistivity traceable to an international standard such as NIST.

Brief Description of the Drawings

[0034]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Modes for Carrying Out the Invention

[0035] As described above, when tracing the C-V method to international standards such as NIST using a polished wafer (hereinafter sometimes simply referred to as "PW wafer"), there has been a demand for the development of a resistivity measurement method having a new resistivity conversion.

[0036] As a result of intensive studies on the above problems, the present inventors, in addition to the conversion by the first conversion formula obtained by comparing the C-V resistivity of a standard polished wafer with the four-probe standard resistivity, for the epitaxial layer of a high-resistivity substrate silicon epitaxial wafer and the epitaxial layer of a low-resistivity substrate silicon epitaxial wafer, by performing conversion using the second conversion formula obtained by comparing the C-V resistivity, it has been found that the C-V resistivity of the silicon epitaxial layer to be measured can be converted into a four-probe resistivity traceable to international standards such as NIST, and the present invention has been completed.

[0037] That is, the present invention is a resistivity measurement method for measuring the resistivity of a silicon epitaxial layer to be measured formed on a silicon epitaxial wafer manufactured using a low-resistivity substrate having a resistivity of 0.02 Ω·cm or less by the C-V method, with respect to the SEMI-converted resistivity obtained by measuring the resistivity of the silicon epitaxial layer to be measured by the C-V method or the resistivity obtained by subjecting the SEMI-converted resistivity to a predetermined conversion, conversion by the first conversion formula obtained by comparing the C-V resistivity obtained by measuring a standard polished wafer with a four-probe standard resistivity value attached by the C-V method with the four-probe standard resistivity, and conversion by the second conversion formula obtained by comparing the C-V resistivity for the silicon epitaxial layer of a high-resistivity substrate silicon epitaxial wafer manufactured using a high-resistivity substrate having a resistivity measurable by the C-V method and the silicon epitaxial layer of a low-resistivity substrate silicon epitaxial wafer manufactured using a low-resistivity substrate having a resistivity of 0.02 Ω·cm or less, A resistivity measurement method, characterized by performing the following steps to obtain the four-probe resistivity of the silicon epitaxial layer to be measured.

[0038] Hereinafter, the present invention will be described in detail with reference to the drawings, but the present invention is not limited thereto.

[0039] [First Embodiment] Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

[0040] FIG. 1 is a schematic process diagram showing a schematic process for obtaining a first conversion formula in the resistivity measurement method according to the first embodiment of the present invention.

[0041] First, a four-probe resistivity measurement device is calibrated using a standard wafer traceable to an international standard, for example, NIST (FIG. 1(a) Four-probe resistivity measurement device calibration process).

[0042] For example, for the resistivity measurement value obtained by the four-probe method, a standard wafer having traceability to 7 levels of resistivity standard materials (SRM: Standard Reference Material) such as SRM2541 (0.01 Ω·cm) to SRM2547 (200 Ω·cm) provided by NIST (National Institute of Standards and Technology) can be used to calibrate and correct the four-probe resistivity measurement device.

[0043] In this example, to calibrate the four-probe resistivity measurement device, the resistivity standard materials such as SRM2541 to SRM2547 are measured with the four-probe resistivity measurement device, and it is confirmed that the measurement results are within the management standards. To correct, the resistivity standard material is measured with the four-probe resistivity measurement device, the ratio between the measurement result and the standard value assigned to the resistivity standard material is obtained, and the measurement value obtained by the four-probe resistivity measurement device is multiplied by that ratio.

[0044] Next, using the four-probe resistivity measurement device calibrated in the four-probe resistivity measurement device calibration process, measure the resistivity of the PW wafer and assign a four-probe standard resistivity (Figure 1(b) standard resistivity assignment process).

[0045] As the PW wafer, it is desirable to use one that has a resistivity measurable by the C-V method and has been subjected to a heat treatment for eliminating oxygen donors. When measuring the PW surface of the PW wafer with the four-probe resistivity measurement device, in order to ensure the accuracy of the four-probe standard resistivity, it is desirable to measure the resistivity multiple times and use the average value as the standard value. When the PW wafer is ground (e.g., surface grinding) to form a ground surface and the ground surface is measured with the four-probe resistivity measurement device, the measurement accuracy of the four-probe standard resistivity is improved compared to the case of measuring the PW surface. Hereinafter, the PW wafer with the four-probe standard resistivity assigned may be referred to as a standard PW.

[0046] Subsequently, perform C-V measurement on the standard PW (Figure 1(c) C-V measurement process of the standard PW). When the surface is ground in the PW standard resistivity assignment process (Figure 1(b)), perform C-V measurement on another PW wafer having the same resistivity. When a high-resistance region appears in the surface layer portion of the impurity concentration profile or resistivity profile during C-V measurement, it is desirable to perform heat treatment in a hydrogen atmosphere at 250°C or higher and 1150°C or lower for 10 minutes to 60 minutes before performing C-V measurement on the standard PW.

[0047] Then, by comparing the C-V resistivity obtained by measuring the standard PW by the C-V method with the four-probe standard resistivity (Figure 1(d) comparison process between the C-V measurement value of the standard PW and the four-probe standard resistivity), obtain a first conversion formula for converting the C-V measurement value of the PW wafer into a four-probe resistivity traceable to the international standard (Figure 1(e)).

[0048] The first conversion formula obtained in this way is for using a high-resistivity substrate, for example, P - -type PW, N - -type PW, P / P - -type silicon epitaxial wafer (hereinafter, may be simply referred to as "EPW"), N / N- It can be applied to the EPW of type + EPW or N / N of type + It cannot be applied to the EPW of type. This is because the contact resistance between the wafer stage for fixing the wafer during C-V measurement and the back surface of the EPW is different depending on whether the back surface of the EPW is a high-resistivity substrate or a low-resistivity substrate, and this difference affects the measurement result of the C-V resistivity.

[0049] Therefore, a high-resistivity substrate EPW and a low-resistivity substrate EPW with the same dopant concentration in the silicon epitaxial layer (hereinafter sometimes simply referred to as "epi layer") are prepared, and by comparing the C-V resistivity of the epi layers of these EPWs, a second conversion formula for converting from the epi layer C-V resistivity of the low-resistivity substrate EPW to the epi layer C-V resistivity of the high-resistivity substrate EPW is obtained (Fig. 2). That is, Fig. 2 is a schematic process diagram showing the schematic process for obtaining the second conversion formula in the resistivity measurement method of the present invention.

[0050] In Fig. 2, first, a high-resistivity PW wafer having a resistivity measurable by the C-V method and a low-resistivity PW wafer having a resistivity of 0.02 Ω·cm or less are prepared (substrate PW wafer preparation step in Fig. 2(a)). Here, the resistivity of the high-resistivity substrate having a resistivity measurable by the C-V method is, for example, 0.1 Ω·cm or more and 1000 Ω·cm or less.

[0051] Next, on each of the high-resistivity PW wafer and the low-resistivity PW wafer, a silicon epitaxial layer having substantially the same resistivity and the same conductivity type as the high-resistivity PW wafer is epitaxially grown under the growth conditions of the same dopant concentration. Thereby, a high-resistivity substrate EPW and a low-resistivity substrate EPW are prepared (comparison EPW preparation step in Fig. 2(b)).

[0052] Subsequently, a C-V measurement is performed on the epi-layer of the low-resistivity substrate EPW and the epi-layer of the high-resistivity substrate EPW (C-V measurement step of the comparison EPW in Fig. 2(c)). Further, the C-V resistivity is compared between the epi-layer of the low-resistivity substrate EPW and the epi-layer of the high-resistivity substrate EPW (comparison step of the C-V resistivity between the EP layer of the low-resistivity substrate EPW and the EP layer of the high-resistivity substrate EPW in Fig. 2(d)).

[0053] Then, a second conversion formula for converting from the C-V resistivity of the epi-layer of the low-resistivity substrate EPW to the C-V resistivity of the epi-layer of the high-resistivity substrate EPW is obtained (Fig. 2(e)). The high-resistivity substrate EPW with the same resistivity as the epi-layer and the substrate is substantially the same as PW. Therefore, the second conversion formula can also be used for converting from the C-V resistivity of the epi-layer of the low-resistivity substrate EPW to the C-V resistivity of PW.

[0054] As described above, the contact resistance between the wafer stage on which the EPW is fixed during the C-V measurement and the back surface of the EPW is different between the case where the back surface of the EPW is a high-resistivity substrate and the case where it is a low-resistivity substrate, and this difference affects the measurement result of the C-V resistivity. Further, even for the same high-resistivity substrate or high-resistivity PW, for example, between 1 Ω·cm and 100 Ω·cm, the contact resistance with respect to the wafer stage is different.

[0055] Therefore, when performing a C-V measurement by fixing a high-resistivity substrate EPW or a high-resistivity PW (hereinafter, may be referred to as a high-resistivity wafer) to a wafer stage, it is desirable to perform the C-V measurement while sandwiching a conductive cushion between the high-resistivity wafer and the wafer stage. Then, even for high-resistivity wafers with different resistivities, the contact resistance with respect to the wafer stage can be kept constant, so an improvement in the accuracy of the first conversion formula and the second conversion formula can be expected.

[0056] Fig. 3 shows a schematic diagram of a C-V measurement device 10 (hereinafter, may be simply referred to as device 10) used when performing a C-V measurement while sandwiching a conductive cushion 7 between a high-resistivity wafer 3 and a wafer stage 6.

[0057] The high-resistivity wafer 3 is formed by vapor-phase growing a silicon epitaxial layer 2 on the high-resistivity substrate 1, and is applicable to either P / P - or N / N - However, for the sake of convenience of explanation, the case of P / P - is illustrated. Furthermore, although the electrode of the device 10 is a back electrode, it is also applicable to a front electrode.

[0058] As a pretreatment for C-V measurement, the high-resistivity wafer 3 is treated with, for example, hydrofluoric acid (HF) to remove the oxide film formed on the surface. Next, a metal electrode 4 is formed at a desired position on the surface of the silicon epitaxial layer 2. The metal of the metal electrode 4 is preferably samarium (Sm) when the silicon epitaxial layer 2 is P-type, and preferably gold (Au) when the silicon epitaxial layer 2 is N-type. When using mercury (Hg) as the metal electrode 4, it can be applied to both P-type and N-type.

[0059] Next, while sandwiching a conductive cushion 7 between the second major surface (main back surface) of the HF-treated high-resistivity wafer 3 and the measurement stage 6 of the C-V measurement device 10, a high-frequency voltage is applied to the metal electrode 4 in contact with the first major surface of the high-resistivity wafer 3 to perform C-V measurement.

[0060] As the conductive cushion 7, silicone rubber with a resistivity of 1 Ωcm or less kneaded with silver or carbon is desirable. The reason for using the conductive cushion 7 is to maintain a good ohmic contact with a constant resistivity between the second major surface of the high-resistivity wafer 1 and the measurement stage 6 of the C-V measurement device 10.

[0061] When the conductive cushion 7 is not used, the magnitude of the resistance formed between the second major surface of the high-resistivity wafer 3 and the measurement stage 6 varies depending on the resistivity of the high-resistivity substrate 1. It also varies depending on the strength of the adsorption between the back surface of the high-resistivity wafer 3 and the measurement stage 6. The magnitude of the resistance formed between the second major surface of the high-resistivity wafer 3 and the measurement stage 6 becomes smaller if the adsorption force is strong, and larger if the adsorption force is weak.

[0062] When a reverse bias voltage is applied to the metal electrode 4 in contact with the first main surface of the high resistivity wafer 3, the depletion layer formed near the surface of the EP layer 2 in contact with the metal electrode 4 expands.

[0063] The depletion layer width W can be obtained from the following equation. (Equation 1) W = Aε0ε Si / C Here, A is the area of the metal electrode 4, ε0 is the permittivity of free space, ε Si is the relative permittivity of silicon, and C is the capacitance formed by the depletion layer of the epi layer 2.

[0064] And the dopant concentration N(W) at the depletion layer width W can be obtained from the following equation. (Equation 2) N(W) = 2 / (qε0ε Si A 2 )*{d(C -2 ) / dV} -1 Here, q is the charge of an electron.

[0065] When a correspondence list between the dopant concentration N(W) and the depletion layer width W (depth) is created, it can be output as a dopant concentration profile. Also, when the dopant concentration N(w) is converted to resistivity (SEMI-converted resistivity) using SEMI MF723-0307 and a correspondence list with the depletion layer width (depth) is created, it can also be output as a resistivity profile.

[0066] By performing the conversion of the first conversion formula on the SEMI-converted resistivity or the resistivity obtained by subjecting the SEMI-converted resistivity to a predetermined conversion, the measurement result of the C-V resistivity of the high resistivity wafer 3 can be converted to a four-probe resistivity traceable to NIST.

[0067] When the object of C-V measurement does not include the high resistivity substrate 1, that is, P / P + type EPW or N / N +In the case of a low-resistivity substrate EPW such as type EPW, it is not necessary to use the conductive cushion 7. The C-V resistivity of the epi-layer (hereinafter sometimes referred to as "EP layer") formed on the low-resistivity substrate EPW can also be measured as shown in FIG. 3, except that the conductive cushion 7 is not used. Then, for the SEMI-converted resistivity or the measurement result of the C-V resistivity of the EP layer formed on the low-resistivity substrate EPW (FIG. 4(a)) obtained by applying a predetermined conversion to the SEMI-converted resistivity, by performing the conversion using the second conversion formula (FIG. 4(b)) and the conversion using the first conversion formula (FIG. 4(c)), the measurement result of the C-V resistivity of the silicon epitaxial layer to be measured can be converted into a four-probe resistivity traceable to NIST (FIG. 4(d)).

[0068] The predetermined conversion applied to the SEMI-converted resistivity includes, for example, conversion for adapting to other C-V method resistivity measurement devices, conversion for adapting to the customer's measured value (customer conversion), conversion for correcting the bias from the standard value, and the like.

[0069] [Second Embodiment] Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In the first embodiment, the resistivity of the PW wafer is measured using a calibrated four-probe resistivity measurement device, and a four-probe standard resistivity is assigned. In contrast, in the second embodiment, the assignment of the four-probe standard resistivity is performed on a silicon single-crystal wafer (hereinafter sometimes simply referred to as "LW") having a main surface that has been lapped (hereinafter sometimes simply referred to as "LW surface"), a silicon single-crystal wafer having a main surface that has been ground (hereinafter sometimes simply referred to as "ground surface"), or a silicon single-crystal wafer (hereinafter sometimes simply referred to as "CW") having a main surface that has been chemically etched (hereinafter sometimes simply referred to as "CW surface").

[0070] FIG. 5 is a schematic process diagram showing the schematic process of the resistivity measurement method according to the second embodiment of the present invention. First, a four-probe resistivity measurement device is calibrated using a standard wafer traceable to NIST (FIG. 5(a) four-probe resistivity measurement device calibration step).

[0071] Next, the four-probe standard resistivity is determined for a silicon single crystal wafer whose main surface is the LW plane, the ground surface, or the CW plane (standard resistivity determination step in Fig. 5(b)). Then, the variation in repeated measurements becomes smaller compared to the case of measuring a PW wafer whose main surface is the PW plane by the four-probe method. The CW plane includes a high-luminance surface ground plane.

[0072] When oxygen in a silicon single crystal undergoes heat treatment at around 450°C, several atoms gather and release one electron to generate donors. Therefore, it is desirable to use a crystal with a low oxygen concentration for the silicon single crystal wafer used for determining the four-probe standard resistivity. Also, it is desirable to perform heat treatment (donor killer heat treatment) for the purpose of eliminating oxygen donors before determining the four-probe standard resistivity.

[0073] Subsequently, at least the first main surface of the resistivity-determined silicon single crystal wafer is processed to form a PW wafer (processing step in Fig. 5(c)). When the main surface of the wafer is the LW plane, etching, chemical mechanical polishing (polishing), etc. are performed to form a PW wafer. Further, in order to clean the PW plane, the PW wafer is washed. For washing, for example, a combination of ammonia-hydrogen peroxide water, hydrochloric acid-hydrogen peroxide water, ozone water, and hydrofluoric acid is used.

[0074] When the PW wafer is washed, hydrogen is introduced into the PW wafer, and as a result, the resistivity of the surface layer portion of the PW wafer increases. As a countermeasure, the washed PW wafer is heat-treated at a temperature of 250°C or higher and 1150°C or lower. The heat-treated standard PW prepared in this way is used for C-V measurement.

[0075] After this C-V measurement step of the standard PW (Fig. 5(d)), it is the same as after the C-V measurement step of the standard PW described in the first embodiment (C-V measurement step of the standard PW in Fig. 1(c)).

[0076] By performing the value assignment of the four-probe standard resistivity on a silicon single crystal wafer whose main surface is the LW surface, the ground surface, or the CW surface, the variation in repeated measurements becomes smaller compared to the case of measuring a PW wafer whose main surface is the PW surface. As a result, since the first conversion formula and the second conversion formula with higher accuracy can be obtained, the C-V resistivity measurement result of the EP layer formed on the low resistivity substrate EPW can be converted to the four-probe resistivity with higher accuracy.

Example

[0077] Hereinafter, the present invention will be specifically described using examples and comparative examples, but the present invention is not limited thereto. Note that the reference numerals in the following description of the examples correspond to the reference numerals shown in FIG. 3.

[0078] [Example 1] First, as a PW wafer for a substrate for obtaining the second conversion formula, five high resistivity PW wafers having a resistivity of 1 to 100 Ω·cm measurable by the C-V method and five low resistivity PW wafers having a resistivity of 0.015 Ω·cm, which are P-type, <100> and have a diameter of 300 mm, were prepared.

[0079] Next, silicon epitaxial layers 2 having substantially the same resistivity and the same conductivity type as the high resistivity PW wafer were epitaxially grown on each of the high resistivity PW wafer 1 and the low resistivity PW wafer 1 under the growth conditions of the same dopant concentration. For example, a P-type silicon epitaxial layer 2 having a resistivity of approximately 1 Ω·cm was epitaxially grown on each of a high resistivity P-type PW wafer 1 having a resistivity of 1 Ω·cm and a low resistivity P-type PW wafer 1 having a resistivity of 0.015 Ω·cm under the growth conditions of the same dopant concentration to obtain EPW3 (low resistivity substrate EPW and high resistivity substrate EPW).

[0080] Subsequently, an electrode 4 was formed on the main surface of EPW3, and C-V measurements were performed on the epi-layers 2 of EPW3 having the epitaxially grown high-resistivity PW1 and EPW3 having the low-resistivity PW1, respectively. When performing C-V measurement on the epi-layer 2 of the high-resistivity substrate EPW3, the high-resistivity substrate EPW3 was adsorbed and held on the wafer stage 6 with a conductive cushion 7 having a resistivity of 0.9 Ω·cm sandwiched between the high-resistivity substrate EPW3 and the wafer stage 6 for measurement.

[0081] Then, the C-V resistivity of the epi-layer 2 of the low-resistivity substrate EPW3 and the C-V resistivity of the epi-layer 2 of the high-resistivity substrate EPW3 were compared, and a second conversion formula for converting from the C-V resistivity of the epi-layer of the low-resistivity substrate EPW to the C-V resistivity of the epi-layer of the high-resistivity substrate EPW was obtained.

[0082] FIG. 6 shows, in percentage, the ratio of the C-V resistivity of the epi-layer of the high-resistivity substrate EPW to the epi-layer of the low-resistivity substrate EPW, that is, the bias amount (measured value - standard value) of the resistivity when not using the second conversion formula with respect to the resistivity converted using the second conversion formula. When not using the second conversion formula, it can be seen that at a resistivity level of 10 Ω·cm, it is about 1%, and at a resistivity level of 100 Ω·cm, it is about 6%, and the resistivity is measured on the high side.

[0083] The definition of "Bias (%)" on the vertical axis of FIG. 6 is as follows. Bias (%) = (Measured value - Standard value) / Standard value × 100 (%)

[0084] Furthermore, by comparing the C-V resistivity obtained by measuring a standard PW with a four-probe standard resistivity previously obtained by the four-probe method and the C-V resistivity, a first conversion formula for converting the C-V measurement value of the high-resistivity PW wafer to a four-probe resistivity traceable to the international standard was obtained.

[0085] On the one hand, as the measurement object, a silicon epitaxial wafer (EPW) manufactured using a low-resistivity substrate having a resistivity of 0.015 Ω·cm was prepared. The resistivity of the silicon epitaxial layer formed on this EPW was measured by C-V measurement, and the SEMI-converted resistivity of the silicon epitaxial layer (EP layer) to be measured, which was formed on the low-resistivity substrate, was obtained.

[0086] Finally, by performing the conversion using the second conversion formula and the conversion using the first conversion formula on the SEMI-converted resistivity of the silicon epitaxial layer to be measured, the measurement result of the C-V resistivity of the EP layer to be measured formed on the low-resistivity substrate EPW was converted into a four-probe resistivity traceable to NIST.

[0087] Fig. 7 shows a graph comparing the four-probe standard resistivity obtained in advance by measuring with the four-probe method and the measurement result (after conversion) of the C-V resistivity of the EP layer to be measured, which was converted into a four-probe resistivity traceable to NIST. As shown in Fig. 7, according to the present invention, the four-probe resistivity and the measurement result of the C-V resistivity of the EP layer to be measured are substantially the same value.

[0088] That is, according to the present invention, it becomes possible to convert the C-V resistivity of the silicon epitaxial layer to be measured formed on a silicon epitaxial wafer manufactured using a low-resistivity substrate into a four-probe resistivity traceable to an international standard such as NIST. In other words, it is possible to provide a resistivity measurement method having a new resistivity conversion performed when tracing the C-V method to an international standard such as NIST using a PW wafer.

Industrial Applicability

[0089] In addition to the conversion using the first conversion formula for comparing the C-V resistivity of the standard PW with the four-probe standard resistivity, by using the present invention and performing conversion by the second conversion formula obtained by comparing the C-V resistivity of the EP layer for the high-resistivity substrate EPW and the low-resistivity substrate EPW, it becomes possible to convert the C-V resistivity of the EP layer formed on the EPW manufactured using the low-resistivity substrate into a four-probe resistivity traceable to an international standard such as NIST.

[0090] Note that the present invention is not limited to the above-described embodiments. The above-described embodiments are examples, and any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and exhibits the same operational effects is included in the technical scope of the present invention.

Description of Reference Numerals

[0091] 1... High-resistivity substrate, 2... Silicon epitaxial layer, 3... Epitaxial wafer, 4... Metal electrode, 6... Wafer stage, 7... Conductive cushion, 10... C-V measurement device.

Claims

1. A resistivity measurement method for measuring the resistivity of a silicon epitaxial layer to be measured formed on a silicon epitaxial wafer manufactured using a low-resistivity substrate having a resistivity of 0.02 Ω·cm or less by the C-V method, comprising: For the SEMI-converted resistivity obtained by measuring the resistivity of the silicon epitaxial layer to be measured by the C-V method, or the resistivity obtained by applying a predetermined conversion to the SEMI-converted resistivity, Performing conversion by a first conversion formula obtained by comparing the C-V resistivity obtained by measuring a standard polished wafer with a four-probe standard resistivity assigned thereto by the C-V method and the four-probe standard resistivity; For the silicon epitaxial layer of a high-resistivity substrate silicon epitaxial wafer manufactured using a high-resistivity substrate having a resistivity measurable by the C-V method and the silicon epitaxial layer of a low-resistivity substrate silicon epitaxial wafer manufactured using a low-resistivity substrate having a resistivity of 0.02 Ω·cm or less, performing conversion by a second conversion formula obtained by comparing the C-V resistivity; And obtaining the four-probe resistivity of the silicon epitaxial layer to be measured.

2. The assignment of the four-probe standard resistivity to the standard polished wafer includes: A four-probe resistivity measurement device calibration step of calibrating a four-probe resistivity measurement device using a standard wafer traceable to an international standard; and A polished wafer standard resistivity assignment step of assigning the four-probe standard resistivity to a polished wafer using the four-probe resistivity measurement device calibrated in the four-probe resistivity measurement device calibration step. The resistivity measurement method according to claim 1, characterized by comprising the above steps.

3. The resistivity measurement method according to claim 2, characterized in that, in the polished wafer standard resistivity assignment step, the main surface of the polished wafer is measured by the four-probe resistivity measurement device.

4. The resistivity measurement method according to claim 2, characterized in that, in the polished wafer standard resistivity assignment step, the polished wafer is ground to form a ground surface, and the ground surface is measured by the four-probe resistivity measurement device.

5. The resistivity measurement method according to claim 4, characterized in that surface grinding is performed as the grinding.

6. The resistivity measurement method according to any one of claims 2 to 4, characterized in that a polished wafer that has been heat-treated to eliminate an oxygen donor is used.

7. As the standard polished wafer with the four-probe standard resistivity assigned, a four-probe resistivity measurement device calibration step of calibrating a four-probe resistivity measurement device using a standard wafer traceable to an international standard, using the four-probe resistivity measurement device calibrated in the four-probe resistivity measurement device calibration step, measuring the resistivity of a silicon single crystal wafer that has been previously heat-treated to eliminate an oxygen donor, and a value-assigning step of assigning a four-probe standard resistivity, a processing step of processing at least a first main surface of the silicon single crystal wafer with the assigned value into a polished wafer, a cleaning step of cleaning the polished wafer, The resistivity measurement method according to claim 1, characterized in that one in which the above steps are performed is used.

8. The resistivity measurement method according to claim 7, characterized in that as the silicon single crystal wafer, one having a main surface that is a lapped surface, a ground surface, or a chemically etched surface is used.

9. Regarding the second conversion formula, a substrate polished wafer preparation step of preparing a high-resistivity polished wafer having a resistivity measurable by the C-V method and a low-resistivity polished wafer having a resistivity of 0.02 Ωcm or less, an epitaxial wafer preparation step of epitaxially growing a silicon epitaxial layer having the same resistivity and the same conductivity type as the high-resistivity polished wafer on each of the high-resistivity polished wafer and the low-resistivity polished wafer under the growth conditions of the same dopant concentration to prepare the high-resistivity substrate silicon epitaxial wafer and the low-resistivity substrate silicon epitaxial wafer, a C-V measurement step of a comparative epitaxial wafer of performing C-V measurement on the silicon epitaxial layer of the low-resistivity substrate silicon epitaxial wafer and the silicon epitaxial layer of the high-resistivity substrate silicon epitaxial wafer, a comparison step of comparing the C-V resistivity for the silicon epitaxial layer of the low-resistivity substrate silicon epitaxial wafer and the silicon epitaxial layer of the high-resistivity substrate silicon epitaxial wafer is obtained through The second conversion step of converting the C-V resistivity measurement result of the silicon epitaxial layer formed on the low-resistivity substrate into the C-V resistivity of the silicon epitaxial layer formed on the silicon epitaxial wafer including the high-resistivity substrate by the second conversion formula is performed. The resistivity measurement method according to claim 1, characterized in that.

10. When obtaining the first conversion formula, before measuring the resistivity of the standard polished wafer by the C-V method, the standard polished wafer is heat-treated in a hydrogen atmosphere at 250 ° C or higher and 1150 ° C or lower. The resistivity measurement method according to claim 1, characterized in that.

11. When obtaining the first conversion formula, while arranging a conductive cushion between the second main surface of the standard polished wafer and the measurement stage of the measuring device using the C-V method, a high-frequency voltage is applied to the first main surface of the standard polished wafer. The resistivity measurement method according to claim 1, characterized in that the resistivity of the standard polished wafer is measured by the C-V method.

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