Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of achieving further microfabrication, and the manufacturing method thereof.SOLUTION: A semiconductor device includes: a first semiconductor layer 161; a first and a second semiconductor region arranged across the first semiconductor layer; a second semiconductor layer 163 arranged above the first semiconductor layer; a third and a fourth semiconductor region arranged across the second semiconductor layer; a third semiconductor layer 261 arranged side by side with the first semiconductor layer; a fifth and a sixth semiconductor region arranged across the third semiconductor layer; a fourth semiconductor layer 263 arranged side by side with the second semiconductor layer; a seventh and an eighth semiconductor region arranged across the fourth semiconductor layer; an insulating wall 50 including a first side surface 51 in contact with the first and second semiconductor layers and a second side wall 52 in contact with the fourth semiconductor layer; a buffer including a first gate electrode arranged on the first and second semiconductor layers via a first gate insulation film and a second gate electrode arranged on the third and fourth semiconductor layers via a second gate insulation film; and power lines 910 and 920.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] An element called a complementary field effect transistor (CFET) is known. In a CFET, an n-channel FET and a p-channel FET are stacked on a substrate. The CFET is suitable for miniaturization of semiconductor devices.

[0003] An element called a forksheet transistor is also known. In a forksheet transistor, a channel of a nanowire or a nanosheet is arranged with a wall-shaped insulating film sandwiched therebetween. The forksheet transistor is also suitable for miniaturization of semiconductor devices.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Non-Patent Documents

[0005]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] So far, no detailed examination has been made on a specific configuration that allows for further miniaturization.

[0007] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that allow for further miniaturization.

Means for Solving the Problems

[0008] A semiconductor device according to the disclosed technology includes a substrate, a first semiconductor layer disposed on the substrate, a first semiconductor region and a second semiconductor region disposed on the substrate and sandwiching the first semiconductor layer in a first direction in plan view, a second semiconductor layer disposed above the first semiconductor layer, a third semiconductor region and a fourth semiconductor region disposed above the first semiconductor region and the second semiconductor region, respectively, and sandwiching the second semiconductor layer in the first direction, A first insulating film disposed between the first semiconductor region and the third semiconductor region, and a second insulating film disposed between the second semiconductor region and the fourth semiconductor region, a third semiconductor layer disposed on the substrate and arranged side by side with the first semiconductor layer in a second direction different from the first direction in plan view, a fifth semiconductor region and a sixth semiconductor region disposed on the substrate and sandwiching the third semiconductor layer in the first direction in plan view, a fourth semiconductor layer disposed above the third semiconductor layer and arranged side by side with the second semiconductor layer in the second direction in plan view, a seventh semiconductor region and an eighth semiconductor region disposed above the fifth semiconductor region and the sixth semiconductor region, respectively, and sandwiching the fourth semiconductor layer in the first direction, A third insulating film disposed between the fifth semiconductor region and the seventh semiconductor region, and a fourth insulating film disposed between the sixth semiconductor region and the eighth semiconductor region, an insulating wall disposed on the substrate, extending in the first direction, and having a first side surface and a second side surface opposite to the first side surface, a first gate electrode disposed on the first semiconductor layer and the second semiconductor layer via a first gate insulating film, and a second gate electrode disposed on the third semiconductor layer and the fourth semiconductor layer via a second gate insulating film, wherein the first side surface is the first semiconductor layer 、 the second semiconductor layer , the first insulating film and the second insulating filmis in contact with, and the second side surface is in contact with the third semiconductor layer and the fourth semiconductor layer , the third insulating film and the fourth insulating film therewith.

Advantages of the Invention

[0009] According to the disclosed technology, a semiconductor device capable of further miniaturization and a method for manufacturing the same can be provided.

Brief Description of the Drawings

[0010]

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Embodiments for Carrying Out the Invention

[0011] Hereinafter, embodiments will be specifically described with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configuration may be denoted by the same reference numerals, and redundant descriptions may be omitted. In the following description, two directions parallel to the surface of the substrate and perpendicular to each other are defined as the X direction and the Y direction, and the direction perpendicular to the surface of the substrate is defined as the Z direction. An n-channel field-effect transistor may be referred to as an nFET, and a p-channel field-effect transistor may be referred to as a pFET. Also, the coincidence of the arrangements in the present disclosure does not strictly exclude those that become non-coincident due to manufacturing variations. Even when there is a displacement in the arrangement due to manufacturing variations, the arrangements can be regarded as coincident.

[0012] (Circuits included in the semiconductor device) The circuits included in the semiconductor device according to the embodiment will be described. FIG. 1 is a diagram showing the configuration of the circuits included in the semiconductor device according to the embodiment.

[0013] As shown in FIG. 1, the semiconductor device 100 according to the embodiment includes a buffer BU, a VDD wiring to which a power supply potential of VDD is supplied, and a VSS wiring to which a power supply potential of VSS is supplied. The VDD wiring may sometimes be referred to as a power supply wiring. The power supply potential of VSS is, for example, a ground potential, and the VSS wiring may sometimes be referred to as a ground wiring. The buffer BU includes an inverter 1 and an inverter 2. An input signal IN is input to the inverter 1, the output of the inverter 1 is input to the inverter 2, and an output signal OUT is output from the inverter 2. The inverter 1 includes a p-channel field effect transistor (pFET) 1P and an n-channel field effect transistor (nFET) 1N, and the inverter 2 includes a pFET 2P and an nFET 2N.

[0014] (Configuration of Buffer) Next, the configuration of the buffer BU will be described. FIGS. 2 and 3 are schematic diagrams showing the planar configuration of the buffer BU. FIG. 2 mainly shows the layouts of the nFET 1N and the pFET 2P. FIG. 3 mainly shows the layouts of the pFET 1P and the nFET 2N. Except for the structures shown in both FIGS. 2 and 3, the structures shown in FIG. 3 are located above the structures shown in FIG. 2. FIGS. 4, 5, 6, 7, and 8 are cross-sectional views showing the buffer BU. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIGS. 2 and 3. FIG. 5 corresponds to a cross-sectional view taken along line V-V in FIGS. 2 and 3. FIG. 6 corresponds to a cross-sectional view taken along line VI-VI in FIGS. 2 and 3. FIG. 7 corresponds to a cross-sectional view taken along line VII-VII in FIGS. 2 and 3. FIG. 8 corresponds to a cross-sectional view taken along line VIII-VIII in FIGS. 2 and 3.

[0015] As shown in FIGS. 2 to 8, an element isolation film 102 is formed on the surface of a substrate 101. The element isolation film 102 is formed, for example, by the STI (Shallow Trench Isolation) method. A plurality of grooves extending in the X direction are formed in the substrate 101 and the element isolation film 102, and power lines 910 and 920 are formed in these grooves via an insulating film 104. For example, the surfaces of the power lines 910 and 920 are covered by an insulating film 103. For example, the surface of the element isolation film 102 and the surface of the insulating film 103 may or may not be flush with the surface of the substrate 101. The power lines 910 and 920 are embedded in the substrate 101. The power lines 910 and 920 having such a structure are sometimes referred to as BPR (Buried Power Rail). For example, the power line 910 corresponds to a VDD wiring, and the power line 920 corresponds to a VSS wiring.

[0016] The element isolation film 102 defines, for example, two regions 10 and 20 arranged in the X direction. Generally, an inverter 1 is formed in the region 10, and an inverter 2 is formed in the region 20.

[0017] In the region 10, a stacked transistor structure 11 is formed on the substrate 101. The stacked transistor structure 11 includes a gate electrode 110, nanosheets 121 and 122, a gate insulating film 130, and a spacer 140. The gate electrode 110 extends in the Y direction and rises in the Z direction. The nanosheets 121 and 122 penetrate the gate electrode 110 in the X direction and are arranged in the Y and Z directions. The gate insulating film 130 is formed between the gate electrode 110 and the nanosheets 121 and 122. In the X direction, the gate electrode 110 and the gate insulating film 130 are formed so as to recede from both ends of the nanosheets 121 and 122, and a spacer 140 is formed in this receded portion. In other words, in the X direction, a spacer 140 is formed between the n-type semiconductor layer 161 and the p-type semiconductor layer 163, which will be described later, and the gate electrode 110.

[0018] For example, the number of nanosheets 121 and 122 arranged in the Z direction is 2 each, and two nanosheets 122 are arranged above two nanosheets 121. The thickness of the nanosheets 121 and 122 is, for example, about 5 nm. Note that the number of nanosheets 121 and 122 may be 1 each, or may be 3 or more. Also, the number of nanosheets 121 and 122 may be the same or different.

[0019] In region 10, two n-type semiconductor layers 161 in contact with the ends of the nanosheets 121 are formed so as to sandwich the gate electrode 110 in the X direction. Two local wirings 162 in contact with the n-type semiconductor layers 161 are formed so as to sandwich the gate electrode 110 in the X direction. Two p-type semiconductor layers 163 in contact with the ends of the nanosheets 122 are formed so as to sandwich the gate electrode 110 in the X direction. Two local wirings 164 in contact with the p-type semiconductor layers 163 are formed so as to sandwich the gate electrode 110 in the X direction. An insulating film 31 is formed between the local wiring 162 and the local wiring 164. For example, the n-type semiconductor layer 161 is an n-type Si layer, and the p-type semiconductor layer 163 is a p-type SiGe layer. For example, silicon oxide or silicon nitride or the like can be used for the insulating film 31. A contact hole 312 is formed in the insulating film 31 between the local wiring 162 and the local wiring 164. The local wiring 164 is electrically connected to the local wiring 162 through a conductor in the contact hole 312.

[0020] A part of the gate electrode 110, the nanosheet 121, a part of the gate insulating film 130, and the n-type semiconductor layer 161 are included in the nFET1N. In the nFET1N, one n-type semiconductor layer 161 functions as a source region, the other n-type semiconductor layer 161 functions as a drain region, and the nanosheet 121 functions as a channel. A part of the gate electrode 110, the nanosheet 122, a part of the gate insulating film 130, and the p-type semiconductor layer 163 are included in the pFET1P. In the pFET1P, one p-type semiconductor layer 163 functions as a source region, the other p-type semiconductor layer 163 functions as a drain region, and the nanosheet 122 functions as a channel. The n-type semiconductor layer 161 and the substrate 101 may be electrically connected, or may be electrically separated by an insulating film formed therebetween.

[0021] In the region 20, a stacked transistor structure 21 is formed on the substrate 101. The stacked transistor structure 21 includes a gate electrode 210, nanosheets 221 and 222, a gate insulating film 230, and spacers 240. The gate electrode 210 extends in the Y direction and rises in the Z direction. The nanosheets 221 and 222 penetrate the gate electrode 210 in the X direction and are arranged in the Y and Z directions. The gate insulating film 230 is formed between the gate electrode 210 and the nanosheets 221 and 222. In the X direction, the gate electrode 210 and the gate insulating film 230 are formed so as to recede from both ends of the nanosheets 221 and 222, and spacers 240 are formed in the receded portions. In other words, in the X direction, spacers 240 are formed between the p-type semiconductor layer 261 and the n-type semiconductor layer 263, which will be described later, and the gate electrode 210.

[0022] For example, the number of the nanosheets 221 and 222 arranged in the Z direction is 2 each, and the two nanosheets 222 are arranged above the two nanosheets 221. The thicknesses of the nanosheets 221 and 222 are, for example, 10 nm or less, preferably 5 nm or less. Note that the number of the nanosheets 221 and 222 may be 1 each, or may be 3 or more. Also, the number of the nanosheets 221 and 222 may be the same or different.

[0023] In region 20, two p-type semiconductor layers 261 in contact with the ends of the nanosheet 221 are formed so as to sandwich the gate electrode 210 in the X direction. Two local wirings 262 in contact with the p-type semiconductor layer 261 are formed so as to sandwich the gate electrode 210 in the X direction. Two n-type semiconductor layers 263 in contact with the ends of the nanosheet 222 are formed so as to sandwich the gate electrode 210 in the X direction. Two local wirings 264 in contact with the n-type semiconductor layer 263 are formed so as to sandwich the gate electrode 210 in the X direction. An insulating film 32 is formed between the local wiring 262 and the local wiring 264. For example, the p-type semiconductor layer 261 is a p-type SiGe layer, and the n-type semiconductor layer 263 is an n-type Si layer. For example, silicon oxide, silicon nitride, or the like can be used for the insulating film 32. A contact hole 322 is formed in the insulating film 32 between the local wiring 262 and the local wiring 264. The local wiring 264 is electrically connected to the local wiring 262 through the conductor in the contact hole 322. The p-type semiconductor layer 261 and the substrate 101 may be electrically connected, or may be electrically separated by an insulating film formed therebetween.

[0024] A part of the gate electrode 210, the nanosheet 221, a part of the gate insulating film 230, and the p-type semiconductor layer 261 are included in the pFET2P. In the pFET2P, one p-type semiconductor layer 261 functions as a source region, the other p-type semiconductor layer 261 functions as a drain region, and the nanosheet 221 functions as a channel. A part of the gate electrode 210, the nanosheet 222, a part of the gate insulating film 230, and the n-type semiconductor layer 263 are included in the nFET2N. In the nFET2N, one n-type semiconductor layer 263 functions as a source region, the other n-type semiconductor layer 263 functions as a drain region, and the nanosheet 222 functions as a channel.

[0025] Although illustration is omitted, the gate electrodes 110 and 210 and the substrate 101 are electrically separated by an insulating film formed therebetween.

[0026] The local wiring 162 extends in the Y direction. The local wiring 162 extends above the power line 910. A contact hole 311 is formed in the insulating film 103 between the local wiring 162 and the power line 910. The local wiring 162 is connected to the power line 910 through the conductor in the contact hole 311.

[0027] The local wiring 262 extends in the Y direction. The local wiring 262 extends above the power line 920. A contact hole 321 is formed in the insulating film 103 between the local wiring 262 and the power line 920. The local wiring 262 is connected to the power line 920 through the conductor in the contact hole 321.

[0028] On the substrate 101, an insulating wall 50 is provided between the region 10 and the region 20. The wall 50 extends in the X direction and rises in the Z direction. The wall 50 includes a side surface 51 and a side surface 52 opposite to the side surface 51. The side surface 51 is in contact with the nanosheets 121 and 122, and the side surface 52 is in contact with the nanosheets 221 and 222. The width of the wall 50, that is, the distance between the side surface 51 and the side surface 52, is, for example, 15 nm or less, preferably 8 nm or less.

[0029] As shown in FIG. 4, sidewalls 55 are formed so as to sandwich the gate electrodes 110 and 210 together with the wall 50 in the Y direction. An insulating film 61 is formed on the side of the sidewalls 55. As shown in FIG. 5, an insulating film 63 is formed between the insulating film 61 and the local wirings 164 and 264, and as shown in FIG. 6, an insulating film 62 is formed between the insulating film 61 and the local wiring 262.

[0030] An insulating film 64 is formed on the wall 50, the gate electrodes 110 and 210, the spacers 140 and 240, the local wirings 164 and 264, the sidewalls 55, and the insulating films 61 and 63, and an insulating film 65 is formed on the insulating film 64.

[0031] Contact holes 313 reaching the local wiring 162 are formed in the insulating films 64, 63, and 31, and contact holes 323 reaching the local wiring 262 are formed in the insulating films 64, 63, and 32. For example, the contact hole 313 is formed above the contact hole 311, and the contact hole 323 is formed above the contact hole 321.

[0032] Signal lines 411 and 421 are formed in the insulating film 64. The signal line 411 is connected to the local wiring 162 through the conductor in the contact hole 313. The signal line 421 is connected to the local wiring 262 through the conductor in the contact hole 323.

[0033] A contact hole 314 reaching the gate electrode 110, a contact hole 315 reaching one of the local wirings 164, and a contact hole 316 reaching the other local wiring 164 are formed in the insulating film 64. A contact hole 324 reaching the gate electrode 210, a contact hole 325 reaching one of the local wirings 264, and a contact hole 326 reaching the other local wiring 264 are formed in the insulating film 64.

[0034] Signal lines 412, 413, 414, 422, 423, and 424 are formed in the insulating film 64. The signal line 412 is connected to the gate electrode 110 through the conductor in the contact hole 314. The signal line 413 is connected to one of the local wirings 164 through the conductor in the contact hole 315. The signal line 414 is connected to the other local wiring 164 through the conductor in the contact hole 316. The signal line 423 is connected to the gate electrode 210 through the conductor in the contact hole 324. The signal line 424 is connected to one of the local wirings 264 through the conductor in the contact hole 325. The signal line 422 is connected to the other local wiring 264 through the conductor in the contact hole 326.

[0035] In the insulating film 65, a contact hole 317 reaching the signal line 414, a contact hole 318 reaching the signal line 413, and a contact hole 319 reaching the signal line 411 are formed. In the insulating film 65, a contact hole 327 reaching the signal line 423, a contact hole 328 reaching the signal line 421, and a contact hole 329 reaching the signal line 424 are formed.

[0036] Signal lines 431, 432, and 433 are formed in the insulating film 65. The signal line 431 is connected to the signal line 413 through the conductor in the contact hole 318 and is connected to the signal line 421 through the conductor in the contact hole 328. The signal line 432 is connected to the signal line 414 through the conductor in the contact hole 317 and is connected to the signal line 423 through the conductor in the contact hole 327. The signal line 433 is connected to the signal line 411 through the conductor in the contact hole 319 and is connected to the signal line 424 through the conductor in the contact hole 329.

[0037] In the buffer BU, an input signal IN is input to the signal line 412, and an output signal OUT is output from the signal line 422.

[0038] For example, materials for the power supply lines 910 and 920 include ruthenium (Ru), molybdenum (Mo), cobalt (Co), tungsten (W), etc. For example, materials for the signal lines 411 - 414, 421 - 424, and 431 - 433 include copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co), etc. When using copper, cobalt, or tungsten, it is preferable to form a conductive underlayer film (barrier metal film), such as a tantalum (Ta) film or a tantalum nitride (TaN) film. However, when using ruthenium, it is not necessary to form an underlayer film.

[0039] For example, materials for the local wirings 162, 164, 262, and 264 include copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co), tungsten (W), or the like. When using copper, cobalt, or tungsten, it is preferable to form a conductive underlayer film (barrier metal film), for example, a titanium (Ti) film or a titanium nitride (TiN) film. However, when using molybdenum or ruthenium, it may not be necessary to form an underlayer film. For example, for the conductor (via) in the contact hole, a material similar to that of the local wiring can be used, for example.

[0040] For example, a semiconductor such as silicon (Si) can be used for the substrate 101. For example, a semiconductor such as silicon (Si) can be used for the nanosheets 121, 122, 221, and 222. For the p-type semiconductor layers 163 and 261, semiconductors such as silicon, silicon carbide (SiC), silicon germanium (SiGe), etc., containing boron (B) as a p-type impurity can be used. For the n-type semiconductor layers 161 and 263, semiconductors such as silicon, silicon carbide, silicon germanium, etc., containing phosphorus (P) as an n-type impurity can be used.

[0041] For example, conductive materials such as titanium (Ti), titanium nitride (TiN), polycrystalline silicon (poly-Si), etc. can be used for the gate electrodes 110 and 210. For example, high-k dielectric materials such as hafnium oxide, aluminum oxide, oxides of hafnium and aluminum, etc. can be used for the gate insulating films 130 and 230. The gate insulating film 130 formed on the nanosheet 121 and the gate insulating film 130 formed on the nanosheet 122 may contain different materials respectively. Also, the gate insulating film 230 formed on the nanosheet 221 and the gate insulating film 230 formed on the nanosheet 222 may contain different materials respectively.

[0042] For example, local wiring and signal lines are formed by a dual damascene process together with contact holes disposed thereunder. Further, local wiring and signal lines may be formed by a single damascene process separately from the contact holes disposed thereunder.

[0043] For example, silicon oxide, silicon nitride, or the like can be used as the material for sidewall 55, spacers 140 and 240, and insulating wall 50.

[0044] (Method of manufacturing semiconductor device) Next, a method of manufacturing the semiconductor device 100 according to the embodiment will be described. FIGS. 9 to 24 are plan views showing the method of manufacturing the semiconductor device according to the embodiment. FIGS. 25 to 37 are cross-sectional views showing the method of manufacturing the semiconductor device according to the embodiment. FIGS. 25 to 37 show changes in the cross-section along line IV-IV in FIGS. 2 and 3. FIGS. 38 to 44 are cross-sectional views showing the method of manufacturing the semiconductor device according to the embodiment. FIGS. 38 to 44 show changes in the cross-section along line V-V in FIGS. 2 and 3. FIGS. 45 to 48 are cross-sectional views showing the method of manufacturing the semiconductor device according to the embodiment. FIGS. 45 to 48 show changes in the cross-section along line VI-VI in FIGS. 2 and 3. FIGS. 49 to 63 are cross-sectional views showing the method of manufacturing the semiconductor device according to the embodiment. FIGS. 49 to 63 show changes in the cross-section along line VII-VII in FIGS. 2 and 3. In FIGS. 12 to 24, insulating films other than the gate insulating film are omitted.

[0045] First, as shown in FIGS. 9, 25, and 49, an SiGe film 71, an Si film 81, an SiGe film 72, an Si film 82, an SiGe film 73, an Si film 83, an SiGe film 74, an Si film 84, and an SiGe film 75 are formed on a substrate 101. The Si films 81 and 82 become nanosheets 121 and 221, and the Si films 83 and 84 become nanosheets 122 and 222. The thicknesses of the Si films 81 to 84 are, for example, about 5 nm. The thicknesses of the SiGe films 71 to 75 are, for example, about 5 nm to 8 nm. The SiGe film 73 may be thicker than the SiGe films 71, 72, 74, and 75. The SiGe films 71 to 75 and the Si films 81 to 84 are formed, for example, by an epitaxial growth method.

[0046] Next, as shown in FIGS. 10 and 26, subsequently, the stack of the SiGe films 71 to 75 and the Si films 81 to 84 is etched and patterned into a plate shape protruding from the substrate 101. By this patterning, fins 91 and 92 extending in the Y direction are formed so as to correspond to regions 10 and 20, respectively. The fins 91 and 92 are arranged in the X direction. Also, in a plan view, grooves 105 for an element isolation film 102 are formed on the surface of the substrate 101 on the sides of the fins 91 and 92.

[0047] Thereafter, as shown in FIG. 27, an element isolation film 102 is formed in the grooves 105. The element isolation film 102 defines, for example, two regions 10 and 20 arranged in the X direction.

[0048] Subsequently, as shown in FIG. 28, an insulating film 106 that covers the upper surfaces and side surfaces of the fins 91 and 92 and covers the upper surface of the element isolation film 102 is formed. The insulating film 106 is formed so as to fill the gap between the fins 91 and 92.

[0049] Next, as shown in FIGS. 11 and 29, an insulating wall 50 is formed by etching the insulating film 106 so as to remain in the gap between the fins 91 and 92. The wall 50 has a side surface 51 in contact with the fin 91 and a side surface 52 in contact with the fin 92. Note that the insulating film 106 may be formed before the element isolation film 102 is formed, the insulating film 106 may be etched so as to remain in the gap between the fins 91 and 92, and then the element isolation film 102 may be formed. In this case, the wall 50 is formed in the groove 105 between the fins 91 and 92 instead of the element isolation film 102. Further, the element isolation film 102 and the insulating film 106 may be formed together, and then the insulating film 106 may be etched so as to remain in the gap between the fins 91 and 92.

[0050] Thereafter, as shown in FIGS. 12 and 30, a plurality of grooves extending in the X direction for the power supply lines 910 and 920 are formed in the element isolation film 102 and the substrate 101, and the insulating film 104 is formed along the bottom surface and the side surfaces of these grooves. Then, the power supply lines 910 and 920 are formed on the insulating film 104, and the insulating film 103 is formed on the power supply lines 910 and 920. The formation of the grooves, the formation of the insulating film 104, the formation of the power supply lines 910 and 920, and the formation of the insulating film 103 may be performed before the formation of the wall 50.

[0051] Subsequently, as shown in FIGS. 13, 31, and 50, a sacrificial gate 107 and sidewalls 55 are formed. The sacrificial gate 107 is, for example, a polycrystalline silicon film. The sidewalls 55 can be formed, for example, by forming an insulating film and performing etch back.

[0052] Next, as shown in FIGS. 14, 32, 38, and 51, an insulating film 61 is formed. In the formation of the insulating film 61, for example, a silicon oxide film is formed, and the upper surface of the silicon oxide film is polished by chemical mechanical polishing (CMP) until the sacrificial gate 107 and the sidewalls 55 are exposed.

[0053] Subsequently, as shown in FIGS. 15, 39, and 52, in the planned formation regions of the gate electrode and the local wiring, the insulating film 61 is selectively removed, and the portions exposed from the sacrificial gates 107 and the sidewalls 55 of the fins 91 and 92 are removed.

[0054] Subsequently, as shown in FIG. 53, both ends of the SiGe films 71 to 75 are retracted in the X direction by isotropic etching. The portions of the Si films 81 and 82 within the fin 91 become the nanosheets 121, the portions of the Si films 81 and 82 within the fin 92 become the nanosheets 221, the portions of the Si films 83 and 84 within the fin 91 become the nanosheets 122, and the portions of the Si films 83 and 84 within the fin 92 become the nanosheets 222.

[0055] Next, as shown in FIG. 54, spacers 140 are formed in the portions where the SiGe films 71 to 75 have retracted.

[0056] Thereafter, as shown in FIGS. 16 and 55, a cover film 108 is formed so as to cover both end faces in the X direction of the nanosheets 122 and 222.

[0057] Subsequently, as shown in FIGS. 17, 40, and 56, an n-type semiconductor layer 161 is epitaxially grown on the side surface of the nanosheet 121, and a p-type semiconductor layer 261 is epitaxially grown on the side surface of the nanosheet 221. For example, phosphorus (P) is introduced as an n-type impurity into the n-type semiconductor layer 161 using phosphine (PH3), and boron (B) is introduced as a p-type impurity into the p-type semiconductor layer 261 using diborane (B2H6). The n-type semiconductor layer 161 and the p-type semiconductor layer 261 may be formed in either order. The cover film 108 is also formed on the side surface of the nanosheet 121 or 221 that grows the semiconductor layer to be formed later among the n-type semiconductor layer 161 and the p-type semiconductor layer 261, and it is preferably removed from the portion where the semiconductor layer to be formed later is grown after the growth of the semiconductor layer to be formed first.

[0058] Next, as shown in FIGS. 18, 41, 45, and 57, an insulating film 62 is formed, and two local wirings 162 in contact with the n-type semiconductor layer 161 and two local wirings 262 in contact with the p-type semiconductor layer 261 are formed. The local wirings 162 and 262 can be formed simultaneously. The local wirings 162 and 262 can be formed, for example, by forming a conductive film and etch-back. Further, an insulating film 31 is formed on the local wiring 162, and an insulating film 32 is formed on the local wiring 262. The insulating films 31 and 32 can be formed simultaneously. Before forming the local wirings 162 and 262, contact holes 311 and 321 are formed in the insulating film 103, and one of the local wirings 162 may be formed to be in contact with the power line 910, and one of the local wirings 262 may be formed to be in contact with the power line 920.

[0059] Thereafter, as shown in FIGS. 19, 42, 46, and 58, the cover film 108 is removed, a p-type semiconductor layer 163 is epitaxially grown on the side surface of the nanosheet 122, and an n-type semiconductor layer 263 is epitaxially grown on the side surface of the nanosheet 222. For example, boron (B) is introduced as a p-type impurity into the p-type semiconductor layer 163 using diborane (B2H6), and phosphorus (P) is introduced as an n-type impurity into the n-type semiconductor layer 263 using phosphine (PH3). The p-type semiconductor layer 163 and the n-type semiconductor layer 263 may be formed in either order. The cover film 108 is preferably left on the side surface of the nanosheet 122 or 222 that grows the semiconductor layer to be formed later among the p-type semiconductor layer 163 and the n-type semiconductor layer 263 to grow the semiconductor layer to be formed first, and then removed entirely.

[0060] Subsequently, an insulating film 63 is formed, and a local wiring 164 in contact with the p-type semiconductor layer 163 and a local wiring 264 in contact with the n-type semiconductor layer 263 are formed. The local wirings 164 and 264 can be formed simultaneously. The local wirings 164 and 264 can be formed, for example, by forming a conductive film and etch-back. Before forming the local wirings 164 and 264, contact holes 312 and 322 are respectively formed in the insulating films 31 and 32, and one of the local wirings 164 may be formed to be in contact with the local wiring 162, and one of the local wirings 264 may be formed to be in contact with the local wiring 262.

[0061] Next, as shown in FIGS. 20, 33, and 59, the sacrificial gate 107 is removed.

[0062] Thereafter, as shown in FIGS. 21, 34, and 60, the SiGe films 71 to 75 are removed. As a result, spaces are formed around the nanosheets 121, 122, 221, and 222.

[0063] Subsequently, as shown in FIGS. 22, 35, and 61, gate insulating films 130 and 230 are formed around the nanosheets 121, 122, 221, and 222. The gate insulating films 130 and 230 can be formed by a deposition method such as a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. The gate insulating films 130 and 230 are also formed on the surface of the substrate 101 and the like, but the illustration is omitted.

[0064] Next, as shown in FIGS. 23, 36, 43, 47, and 62, gate electrodes 110 and 210 are formed, and for example, the insulating film 61 and the like are polished until the upper surface of the wall 50 is exposed, and the upper surfaces of the gate electrodes 110 and 210 are flattened. In this way, a stacked transistor structure 11 is formed in the region 10, and a stacked transistor structure 21 is formed in the region 20.

[0065] Thereafter, as shown in FIGS. 24, 37, 44, 48, and 63, an insulating film 64 is formed, contact holes 313 to 316 and 323 to 326 are formed, and signal lines 411 to 414 and 421 to 424 are formed. Subsequently, an insulating film 65 is formed, contact holes 317 to 319 and 327 to 329 are formed, and signal lines 431 to 433 are formed.

[0066] Thereafter, upper-layer wirings and the like are appropriately formed to complete the semiconductor device 100.

[0067] The circuit included in the semiconductor device of the present disclosure is not limited to a buffer in which two inverters are connected in series. The connection relationship of the local wiring and the signal lines is different from that of the above-described embodiment. For example, a circuit in which two inverters are connected in parallel may be included in the semiconductor device of the present disclosure, and two independent inverters may be included in the semiconductor device of the present disclosure.

[0068] Also, the first to fourth semiconductor regions may have the same conductivity type as each other, and the fifth to eighth semiconductor regions may have the same conductivity type as each other. For example, the conductivity types of all the semiconductor regions connected to the semiconductor layer (nanosheet) in contact with the side surface 51 may be all N-type, and the conductivity types of all the semiconductor regions connected to the semiconductor layer (nanosheet) in contact with the side surface 52 may be all P-type. Also, the first to eighth semiconductor regions may have the same conductivity type as each other.

[0069] The power supply lines 910 and 920 do not have to be embedded in the substrate 101, and for example, may be provided above the insulating film 61.

[0070] As described above, the present invention has been described based on each embodiment, but the present invention is not limited to the requirements shown in the above embodiments. In these respects, it can be changed without departing from the gist of the present invention, and can be appropriately determined according to the application form.

Description of Reference Numerals

[0071] 1, 2: Inverter 11, 21: Stacked transistor structure 50: Wall 51, 52: Side surface 91, 92: Fin 100: Semiconductor device 110, 210: Gate electrode 121, 122, 221, 222: Nanoscale sheet 130, 230: Gate insulating film 161, 263: n-type semiconductor layer 163, 261: p-type semiconductor layer 162, 164, 262, 264: Local wiring 910, 920: Power supply line

Claims

1. A substrate, a first semiconductor layer disposed on the substrate, a first semiconductor region and a second semiconductor region disposed on the substrate and sandwiching the first semiconductor layer in a first direction in a plan view, a second semiconductor layer disposed above the first semiconductor layer, a third semiconductor region and a fourth semiconductor region disposed above the first semiconductor region and the second semiconductor region respectively and sandwiching the second semiconductor layer in the first direction, a first insulating film disposed between the first semiconductor region and the third semiconductor region, a second insulating film disposed between the second semiconductor region and the fourth semiconductor region, a third semiconductor layer disposed on the substrate and arranged side by side with the first semiconductor layer in a second direction different from the first direction in a plan view, a fifth semiconductor region and a sixth semiconductor region disposed on the substrate and sandwiching the third semiconductor layer in the first direction in a plan view, a fourth semiconductor layer disposed above the third semiconductor layer and arranged side by side with the second semiconductor layer in the second direction in a plan view, a seventh semiconductor region and an eighth semiconductor region disposed above the fifth semiconductor region and the sixth semiconductor region respectively and sandwiching the fourth semiconductor layer in the first direction, a third insulating film disposed between the fifth semiconductor region and the seventh semiconductor region, a fourth insulating film disposed between the sixth semiconductor region and the eighth semiconductor region, an insulating wall disposed on the substrate, extending in the first direction, and having a first side surface and a second side surface opposite to the first side surface, a first gate electrode disposed on the first semiconductor layer and the second semiconductor layer via a first gate insulating film, a second gate electrode disposed on the third semiconductor layer and the fourth semiconductor layer via a second gate insulating film, characterized by having, the first side surface being in contact with the first semiconductor layer, the second semiconductor layer, the first insulating film, and the second insulating film, the second side surface being in contact with the third semiconductor layer, the fourth semiconductor layer, the third insulating film, and the fourth insulating film. A semiconductor device.

2. A first wiring connected to the first semiconductor region and disposed under the first insulating film, a second wiring connected to the second semiconductor region and disposed under the second insulating film, a third wiring connected to the third semiconductor region and disposed on the first insulating film, A fourth wiring connected to the fourth semiconductor region and disposed on the second insulating film, A fifth wiring connected to the fifth semiconductor region and disposed under the third insulating film, A sixth wiring connected to the sixth semiconductor region and disposed under the fourth insulating film, A seventh wiring connected to the seventh semiconductor region and disposed on the third insulating film, An eighth wiring connected to the eighth semiconductor region and disposed on the fourth insulating film, The semiconductor device according to claim 1, characterized by having the above.

3. A first power line electrically connected to the first semiconductor region via the first wiring, A second power line electrically connected to the fifth semiconductor region via the fifth wiring, The semiconductor device according to claim 2, characterized by having the above.

4. The semiconductor device according to claim 3, characterized in that the first power line and the second power line are embedded in the substrate.

5. The conductivity types of the first semiconductor region and the second semiconductor region are of a first conductivity type, The semiconductor device according to any one of claims 1 to 4, characterized in that the conductivity types of the third semiconductor region and the fourth semiconductor region are of a second conductivity type different from the first conductivity type.

6. The semiconductor device according to claim 5, characterized in that the second semiconductor region and the fourth semiconductor region are electrically connected.

7. The semiconductor device according to claim 6, characterized in that the second semiconductor region and the fourth semiconductor region are electrically connected to the second gate electrode.

8. The conductivity types of the fifth semiconductor region and the sixth semiconductor region are of the second conductivity type, The semiconductor device according to any one of claims 5 to 7, characterized in that the conductivity types of the seventh semiconductor region and the eighth semiconductor region are of the first conductivity type.

9. The semiconductor device according to claim 8, characterized in that the sixth semiconductor region and the eighth semiconductor region are electrically connected.

10. A step of forming a first semiconductor material layer above the substrate, A step of forming a second semiconductor material layer above the first semiconductor material layer, Etching a stack including the first semiconductor material layer and the second semiconductor material layer to form a first fin and a second fin extending in a first direction in a plan view and arranged in a second direction different from the first direction, wherein the first fin includes a first semiconductor layer obtained from the first semiconductor material layer and a second semiconductor layer obtained from the second semiconductor material layer, and the second fin includes a third semiconductor layer obtained from the first semiconductor material layer and a fourth semiconductor layer obtained from the second semiconductor material layer; Forming an insulating wall having a first side surface in contact with the first semiconductor layer and the second semiconductor layer and a second side surface in contact with the third semiconductor layer and the fourth semiconductor layer between the first fin and the second fin; Forming a first semiconductor region and a second semiconductor region sandwiching the first semiconductor layer in the first direction; Forming a first insulating film on the first semiconductor region and a second insulating film on the second semiconductor region; Forming a third semiconductor region on the first insulating film and a fourth semiconductor region on the second insulating film, sandwiching the second semiconductor layer in the first direction; Forming a fifth semiconductor region and a sixth semiconductor region sandwiching the third semiconductor layer in the first direction; Forming a third insulating film on the fifth semiconductor region and a fourth insulating film on the sixth semiconductor region; Forming a seventh semiconductor region on the third insulating film and an eighth semiconductor region on the fourth insulating film, sandwiching the fourth semiconductor layer in the first direction; Forming a first gate electrode via a first gate insulating film on the first semiconductor layer and the second semiconductor layer; Forming a second gate electrode via a second gate insulating film on the third semiconductor layer and the fourth semiconductor layer; A method for manufacturing a semiconductor device, characterized by comprising the above steps.

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