Level shifter

Abstract

To provide a level shifter capable of shortening the transition time of a level of an output signal without enlarging a circuit scale.SOLUTION: A speed-up circuit 17 includes a capacitor C1 and while a MOS transistor MDn1 is on, a voltage VL is connected with a minus side of the capacitor C1 and a voltage VH is connected with a plus side thereof to charge the capacitor C1. When the MOS transistor MDn1 is off, the voltage VH is connected with the minus side of the capacitor C1 and an input of an inverter INV1 is connected with the minus side.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a level shifter.

Background Art

[0002] Conventionally, as a level shifter, the one described in Patent Document 1 has been proposed. The level shifter described in Patent Document 1 converts an input voltage having an amplitude between an H level (= VDD3) and an L level (= 0 V) into an output voltage having an amplitude between an H level (= VDD1) and an L level (= VDD1 - VDD2).

[0003] Also, the level shifter described in Patent Document 1 includes a first current limiter circuit that shortens the transition time from the L level to the H level of the output signal, a second current limiter circuit that shortens the transition time from the H level to the L level of the output signal, a logic level determination circuit, and a level conversion assist circuit. The above-described level conversion assist circuit is composed of a logic circuit. Therefore, the conventional level shifter has a problem that the circuit scale is large.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide a level shifter that can shorten the transition time of the level of an output signal without increasing the circuit scale.

Means for Solving the Problems

[0006] In order to achieve the above object, the level shifter according to the present invention is characterized by the following [1] to [3]. [1] A level shifter that converts an input signal having an amplitude of a first low voltage and a first high voltage into an output signal having an amplitude of a second low voltage and a second high voltage, an output unit that compares a voltage supplied to an input with a threshold value and outputs the output signal; a constant current circuit provided between a positive electrode of a high-side voltage source that supplies the second high voltage and an input of the output unit, and that supplies a constant current to the input of the output unit to raise the input voltage of the output unit to the second high voltage; a clamp circuit having a Zener diode and clamping the input voltage of the output unit to a value obtained by subtracting the Zener voltage of the Zener diode from the second high voltage; a MOS transistor that turns on and off according to the voltage of the input signal, and that turns on and off the clamping function of the clamp circuit by turning on and off; a speed-up circuit having a capacitor, connecting a negative electrode of a high-side voltage source that supplies the second low voltage to one end of the capacitor while the MOS transistor is on, connecting a positive electrode of the high-side voltage source to the other end to charge the capacitor, and Ta when the MOS transistor turns off, connecting the positive electrode of the high-side voltage source to one end of the capacitor and connecting the input of the output unit to the other end. It is a level shifter. [2] The level shifter according to [1], comprising a diode having an anode connected to the other end of the capacitor and a cathode connected to the positive electrode of the high-side voltage source. It is a level shifter. [3] The level shifter according to [1] or [2], wherein the speed-up circuit a first PMOS transistor having a gate connected to the input of the output unit and a source connected to the positive electrode of the high-side voltage source; A first NMOS transistor having a gate connected to an input of the output section, a source connected to a negative electrode of the high-side voltage source, and a drain connected to the first PMOS transistor, A second PMOS transistor having a gate connected to drains of the first PMOS transistor and the first NMOS transistor, and a source connected to a positive electrode of the high-side voltage source, A second NMOS transistor having a gate connected to drains of the first PMOS transistor and the first NMOS transistor, a source connected to a negative electrode of the high-side voltage source, and a drain connected to a drain of the second PMOS transistor, A third PMOS transistor having a gate connected to drains of the first PMOS transistor and the first NMOS transistor, and a source connected to a positive electrode of the high-side voltage source, A third NMOS transistor having a gate connected to drains of the first PMOS transistor and the first NMOS transistor, a source connected to a negative electrode of the high-side voltage source, and a drain connected to a drain of the third PMOS transistor, A fourth PMOS transistor having a source connected to a positive electrode of the high-side voltage source, and a gate connected to drains of the third PMOS transistor and the third NMOS transistor, A fifth PMOS transistor having a gate connected to drains of the first PMOS transistor and the first NMOS transistor, a source connected to a drain of the fourth PMOS transistor, and a drain connected to an input of the output section, and having One end of the capacitor is connected to drains of the second PMOS transistor and the second NMOS transistor, and drains of the fourth PMOS transistor and a source of the fifth PMOS transistor are connected to the other end of the capacitor A level shifter.

Advantages of the Invention

[0007] According to the present invention, it is possible to provide a level shifter that can shorten the transition time of the level of the output signal without increasing the circuit scale.

[0008] As described above, the present invention has been briefly explained. Further, the details of the present invention will be further clarified by reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments") with reference to the accompanying drawings.

Brief Explanation of Drawings

[0009]

Figure 1

Figure 2

Figure 3

Embodiments for Carrying out the Invention

[0010] Specific embodiments of the present invention will be described below with reference to the respective drawings.

[0011] The level shifter of the present invention is used in the DC / DC converter 1 shown in FIG. 1. The DC / DC converter 1 steps down the DC input voltage V PWH , M PWL supplied from the input voltage source by turning on and off the power MOS transistors M IN and outputs it as the output voltage V OUT from the output terminal OUT. The DC / DC converter 1 includes power MOS transistors M PWH , M PWL , a coil L OUT1 , a capacitor C OUT1 , voltage detection resistors R B1 , R B2 , and power MOS transistors M PWH , MPWL and includes a control IC2 for controlling the on / off thereof.

[0012] The power MOS transistor M as the high-side MOS transistor PWH is composed of a P-channel field-effect transistor. The power MOS transistor M PWH has its source connected to the positive electrode of the input voltage source, and its drain connected to one end of a coil L OUT1 described later and to the drain of the power MOS transistor M PWL and its gate is connected to a control IC2 described later via a resistor R H .

[0013] The power MOS transistor M PWL is composed of an N-channel field-effect transistor. The power MOS transistor M PWL has its drain connected to the drain of the power MOS transistor M PWH and one end of the coil L OUT1 and its source is connected to the ground, and its gate is connected to a control IC2 described later via a resistor R L .

[0014] The coil L OUT1 has one end connected to the drain of the power MOS transistors M PWH and M PWL and the other end connected to the positive electrode side of the output terminal OUT. The capacitor C OUT1 and the voltage detection resistors R B1 and R B2 are connected in parallel to each other between a pair of output terminals OUT. Specifically, the capacitor C OUT1 has one end connected to the other end of the coil L OUT1 and the positive electrode side of the output terminal OUT, and the other end connected to the ground.

[0015] The voltage detection resistors R B1 and R B2 are connected in series to each other. The voltage detection resistor R B1 has one end connected to the coil L OUT1The other end is connected to the positive side of the output terminal OUT, and the other end is connected to the voltage detection resistor R B2 Connected to the voltage detection resistor R B2 One end of the resistor R B1 and the other end is connected to ground. Output voltage V OUT Voltage detection resistor R B1 , R B2 The detection voltage V divided by OUTS is supplied to control IC2.

[0016] The above-mentioned power MOS transistor M PWH Turn on the power MOS transistor M PWL When the power is turned off, coil L OUT1 to the input voltage V IN Energy from the power MOS transistor M PWH Turn off the power MOS transistor M PWL When the coil L is turned on OUT1 A current corresponding to the energy stored in flows from ground to coil L OUT1 is sent to the capacitor C OUT1 The output voltage V smoothed by OUT will be output.

[0017] The control IC2 detects the voltage V OUTS is the reference value of the power MOS transistor M PWH , M PWL The control IC 2 has a PWM control unit 3, an oscillator 4, a dead time control unit 5, a high side drive unit 6, a low side drive unit 7, and a regulator 8.

[0018] The PWM control unit 3 detects the voltage V OUTS and a reference value, and outputs a PWM signal having a duty corresponding to a comparison between the error signal and a slope signal synchronized with the clock output from the oscillator 4 to the dead time control unit 5. The dead time control unit 5 includes a power MOS transistor M PWH , M PWLOutputs PWM signals with dead time provided so that they are not turned on simultaneously to the high-side drive unit 6 and the low-side drive unit 7, respectively.

[0019] The high-side drive unit 6 outputs a drive voltage to the gate of the high-side power MOS transistor M PWH in response to the PWM signal output from the dead-time control unit 5.

[0020] The high-side drive unit 6 includes the transistors M 1H , M 2H , the high-side regulator 9, the level shifter 10, and the pre-driver 11. The transistor M 1H is composed of a P-channel field-effect transistor. The transistor M 1H has its source connected to the positive electrode of the input voltage source, its drain connected to the gate of the power MOS transistor M H via the resistor R PWH , and its gate connected to the pre-driver 11 described later. The transistor M 2H is composed of an N-channel field-effect transistor. The transistor M 2H has its source connected to the output terminal of the high-side regulator 9, its drain connected to the gate of the power MOS transistor M H via the resistor R PWH , and its gate connected to the pre-driver 11 described later.

[0021] The high-side regulator 9 generates the output voltage (V IN -V HREG ). The level shifter 10 converts a PWM signal (input signal) with an amplitude where the L level output from the dead-time control unit 5 is 0 V (the first low voltage) and the H level is the voltage V REG (the first high voltage) into a signal where the H level is the voltage VH (=V IN : the second high voltage) and the L level is the voltage VL (=V IN -V HREG: It converts it into an output signal having an amplitude of the second low voltage) and supplies it to the pre-driver 11. The level shifter 10 will be described later. The pre-driver 11 outputs the level-shifted PWM signal to the gates of the transistors M 1H , M 2H .

[0022] Thus, when a PWM signal of L level is output, the transistor M 1H turns on, the transistor M 2H turns off, and the input voltage V PWH is supplied to the gate of the power MOS transistor M IN , and the power MOS transistor M PWH turns off. On the other hand, when a PWM signal of H level is output, the transistor M 1H turns off, the transistor M 2H turns on, and the output voltage of the high-side regulator 9 (V PWH - V IN - V HREG ) is supplied to the gate of the power MOS transistor M PWH , and the power MOS transistor M

[0023] The low-side drive unit 7 outputs a drive voltage to the gate of the low-side power MOS transistor M PWL according to the PWM signal output from the dead-time control unit 5.

[0024] The low-side drive unit 7 includes the transistors M 1L , M 2L , the low-side regulator 12, the level shifter 13, and the pre-driver 14. The transistor M 1L is composed of a P-channel field-effect transistor. The transistor M 1L has its source connected to the output terminal of the low-side regulator 12, its drain connected to the gate of the power MOS transistor M PWL via a resistor R L , and its gate connected to the pre-driver 14 described later. The transistor M 2Lis composed of N-channel field-effect transistors. Transistor M 2L has its source connected to ground, its drain connected to the gate of power MOS transistor M PWL through resistor R L , and its gate is connected to a pre-driver 14 described later.

[0025] The low-side regulator 12 generates an output voltage V LREG . The level shifter 13 level-shifts the PWM signal output from the dead-time control unit 5 so that the H level becomes V LREG , and the L level becomes ground (0V), and supplies it to the pre-driver 14. The pre-driver 14 outputs the level-shifted PWM signal to the gates of transistors M 1L , M 2L .

[0026] Thus, when a PWM signal of L level is output, transistor M 1L turns on, transistor M 2L turns off, and the output voltage V of the low-side regulator 12 is supplied to the gate of power MOS transistor M PWL , and power MOS transistor M LREG turns on. On the other hand, when a PWM signal of H level is output, transistor M PWL turns off, transistor M 1L turns on, 0V is supplied to the gate of power MOS transistor M 2L , and power MOS transistor M PWL turns off. PWL

[0027] The regulator 8 generates an output voltage V REG to supply to the PWM control unit 3, oscillator 4, dead-time control unit 5, level shifter 10, and level shifter 13 described above.

[0028] Next, the details of the high-side level shifter 10 described above will be described with reference to FIG. 2. The level shifter 10 includes an inverter INV1 (output section), a current mirror circuit 15 (constant current circuit), a clamp circuit 16, an MOS transistor MDn1, a buffer BUF1, and a speed-up circuit 17.

[0029] The inverter INV1 operates by the voltage V supplied from the high-side voltage source 9. HREG When the voltage supplied to the input is lower than the first threshold value VTH1 (threshold value), the inverter INV1 outputs an H level (VH = V). IN When the input voltage exceeds the second threshold value VTH2 (threshold value) that is greater than the first threshold value VTH1, the inverter INV1 outputs an L level (VL = V). IN -V. HREG ) is output. The output of this inverter INV1 becomes the output terminal OUT of the level shifter 10. Note that the first threshold value VTH1 and the second threshold value VTH2 are set between the voltage VH and the voltage VL. Also, the high-side voltage source 9 represents the high-side regulator 9 shown in FIG. 1, and the negative electrode of the high-side voltage source 9 is the output terminal of the high-side regulator 9.

[0030] The current mirror circuit 15 is a circuit that raises the voltage supplied to the input of the inverter INV1 to the voltage VH when the clamp circuit 16 described later is not functioning. The current mirror circuit 15 includes MOS transistors Mp6 and Mp7 and a current source 151. The MOS transistors Mp6 and Mp7 are composed of P-channel field effect transistors. The source of the MOS transistor Mp6 is connected to the positive electrode of the high-side voltage source 9, the drain is connected to the current source 151, and the gate is connected to the drain.

[0031] The source of MOS transistor Mp7 is connected to the positive electrode of the high-side voltage source 9, the drain is connected to the input of the inverter INV1, and the gate is connected to the gate of MOS transistor Mp6. The current source 151 is connected between the drain of MOS transistor Mp6 and the negative electrode of the high-side voltage source 9, and allows a drain current of current Iref1 to flow through MOS transistor Mp6. This current Iref1 is copied by MOS transistor Mp7, and the input voltage of inverter INV1 becomes voltage VH.

[0032] The clamp circuit 16 is a circuit that clamps the input voltage of the inverter INV1 to voltage VL. The clamp circuit 16 includes a Zener diode ZD1, MOS transistors MDp1 and MDp2, and a current source 161. The cathode of the Zener diode ZD1 is connected to the positive electrode of the high-side voltage source 9, and the anode is connected to the source of MOS transistor MDp1 described later.

[0033] MOS transistors MDp1 and MDp2 are composed of P-channel field-effect transistors. The source of MOS transistor MDp1 is connected to the anode of the Zener diode ZD1, the drain is connected to the current source 161, and the gate is connected to the drain. The source of MOS transistor MDp2 is connected to the input of the inverter INV, the drain is connected to the drain of MOS transistor MDn1 described later, and the gate is connected to the gate of MOS transistor MDp1.

[0034] The current source 161 is connected between the drain of MOS transistor MDp1 and the ground, and allows a drain current of current Iref2 to flow through MOS transistor MDp1. With the above configuration, when the clamp circuit 16 allows current Iref2 to flow through the Zener diode ZD1, the sources of MOS transistors MDp1 and MDp2 are clamped to a voltage (VH - VZD) obtained by subtracting the Zener voltage VZD of the Zener diode ZD1 from voltage VH. The Zener voltage VZD of the Zener diode ZD1 is voltage V HREGIf it is made equal to, the input voltage of the inverter INV1 connected to the source of the MOS transistor MDp2 can be clamped to the voltage VL.

[0035] The MOS transistor MDn1 turns on and off the clamping function of the clamping circuit 16. The MOS transistor MDn1 is composed of an N-channel field effect transistor. The drain of the MOS transistor MDn1 is connected to the drain of the MOS transistor MDp2. When the MOS transistor MDn1 is turned on, the current Iref2 is copied to the transistor MDp2, the clamping circuit 16 functions, and the input voltage of the inverter INV1 becomes the voltage VL. On the other hand, when the MOS transistor MDn1 is turned off, the drain current of the MOS transistor MDp2 is cut off, the clamping circuit 16 does not function, and the input voltage of the inverter INV1 becomes the voltage VH by the current mirror circuit 15.

[0036] The gate of the above-described MOS transistor MDn1 is connected to the output of the buffer BUF1. The buffer BUF1 operates receiving the supply of the output voltage V REG and has an input that is the input terminal IN of the level shifter 10. A PWM signal is input to this input terminal IN.

[0037] Specifically, when a PWM signal of the H level (V REG ) is input to the buffer BUF1, the H level (V REG) The output signal of is input to the gate of MOS transistor MDn1. Due to this input, MOS transistor MDn1 turns on, the clamp circuit 16 functions, the input voltage of inverter INV1 becomes voltage VL, and inverter INV1 outputs a high-level voltage (VH). On the other hand, when a low-level (0V) PWM signal is input to buffer BUF1, buffer BUF1 inputs an output signal of low level (0V) to the gate of MOS transistor MDn1. Due to this input, MOS transistor MDn1 turns off, the clamp circuit 16 does not function, and the input voltage of inverter INV1 is pulled up to voltage VH by current mirror circuit 15, and inverter INV1 outputs a low-level voltage (VL). Thus, level shifter 10 can shift the high level (V REG ) of the PWM signal to high level (VH = V IN ) and shift the low level (0V) to low level (VL = V IN - V HREG ).

[0038] When the PWM signal switches from low level to high level and MOS transistor MDn1 turns off to on, since the drive ability of MOS transistor MDn1 is large, the input voltage of inverter INV1 immediately drops from voltage VH to voltage VL. As a result, the output voltage of inverter INV1 also immediately switches from low level to high level. However, when the PWM signal switches from high level to low level and MOS transistor MDn1 turns on to off, in order to supply current Iref1 from MOS transistor Mp7 of current mirror circuit 15 to the parasitic capacitance of the input of inverter INV1 and pull up the input voltage of inverter INV1 to voltage VH, the output voltage of inverter INV cannot immediately switch from high level to low level.

[0039] Therefore, in this embodiment, a speed-up circuit 17 is provided to immediately pull up the input voltage of inverter INV1 to voltage VH when the PWM signal switches from high level to low level.

[0040] The speed-up circuit 17 includes a capacitor C1, MOS transistors Mp1 and Mn1, MOS transistors Mp2 and Mn2, MOS transistors Mp3 and Mn3, MOS transistors Mp4 and Mp5, and a diode D2.

[0041] During the period when the PWM signal is at the H level (MOS transistor MDn1 is on), the MOS transistors Mp1, Mn1, Mp2, Mn2, Mp3, Mn3, Mp4, and Mp5 charge the capacitor C1 with the voltage V HREG Further, when the PWM signal becomes the L level (MOS transistor MDn1 is off), the MOS transistors Mp1, Mn1, Mp2, Mn2, Mp3, Mn3, Mp4, and Mp5 connect the + side of the capacitor C1 charged with the voltage V HREG to the input of the inverter INV1 and connect the - side of the capacitor C1 to the positive electrode of the high-side voltage source 9. As a result, when the PWM signal changes from the H level to the L level, the current from the capacitor C1 can also be supplied to the parasitic capacitance at the input of the inverter INV1, so that the input voltage of the inverter INV1 rapidly rises to VH + V HREG and the output voltage of the inverter INV1 can be immediately switched from the H level to the L level.

[0042] Next, the details of MOS transistors Mp1, Mn1, Mp2, Mn2, Mp3, Mn3, Mp4, and Mp5 will be described. MOS transistors Mp1, Mp2, Mp3, Mp4, and Mp5 are composed of P-channel field-effect transistors. MOS transistors Mn1, Mn2, and Mn3 are composed of N-channel field-effect transistors. MOS transistor Mp1 (the first PMOS transistor) has its source connected to the positive electrode of the high-side voltage source 9, its gate connected to the input of inverter INV1, and its drain connected to the drain of MOS transistor Mn1 described later. MOS transistor Mn1 (the second NMOS transistor) has its source connected to the negative electrode of the high-side voltage source 9, its gate connected to the input of inverter INV1, and its drain connected to the drain of MOS transistor Mp1. Note that MOS transistor Mp1 is set to have a low gate threshold voltage for transitioning from on to off, and MOS transistor Mn1 is set to have a low gate threshold voltage for transitioning from off to on.

[0043] MOS transistor Mp2 (the second PMOS transistor) has its source connected to the positive electrode of the high-side voltage source 9, its drain connected to the drain of MOS transistor Mn2 described later, and its gate connected to the drains of MOS transistors Mp1 and Mn1. MOS transistor Mn2 (the second NMOS transistor) is composed of an N-channel field-effect transistor. MOS transistor Mn2 has its source connected to the negative electrode of the high-side voltage source 9, its drain connected to the drain of MOS transistor Mp2, and its gate connected to the drains of MOS transistors Mp1 and Mn1. One end (the - side) of capacitor C1 is connected to the drains of these MOS transistors Mp2 and Mn2.

[0044] The MOS transistor Mp3 (the third PMOS transistor) has its source connected to the positive electrode of the high-side voltage source 9, its drain connected to the drain of the MOS transistor Mn3 described later, and its gate connected to the drains of the transistors Mp1 and Mn1. The MOS transistor Mn3 (the third NMOS transistor) has its source connected to the negative electrode of the high-side voltage source 9, its drain connected to the drain of the MOS transistor Mp3, and its gate connected to the drains of the transistors Mp1 and Mn1.

[0045] The MOS transistor Mp4 (the fourth PMOS transistor) has its source connected to the positive electrode of the voltage VH high-side voltage source 9, its drain connected to the source of the MOS transistor Mp5 described later, and its gate connected to the drains of the transistors Mp3 and Mn3. The MOS transistor Mp5 (the fifth PMOS transistor) has its source connected to the drain of the MOS transistor Mp4, its drain connected to the input of the inverter INV1, and its gate connected to the drains of the transistors Mp1 and Mn1.

[0046] Also, the drain of the MOS transistor Mp4 and the source of the MOS transistor Mp5 are connected to the + side (the other end) of the capacitor C1. The cathode of the diode D2 is connected to the positive electrode of the high-side voltage source 9, and its anode is connected to the + side of the capacitor C1, the drain of the MOS transistor Mp4, and the source of the MOS transistor Mp5.

[0047] Next, the operation of the level shifter 10 with the above-described configuration will be described below with reference to the time chart of FIG. 3. First, the case where the PWM signal input to the input terminal IN switches from the L level to the H level will be described. When the PWM signal input to the buffer BUF1 switches from the L level to the H level, the output signal of the buffer BUF1 switches from the L level to the H level. As a result, the MOS transistor MDn1 whose output of the buffer BUF1 is connected to the gate switches from off to on. For this reason, the clamp circuit 16 functions, and the input voltage of the inverter INV1 is lowered from the voltage VH to the voltage VL. At this time, since the driving ability of the MOS transistor MDn1 is high, the input voltage of the inverter INV1 is immediately lowered from the voltage VH to the voltage VL.

[0048] When the input voltage of the inverter INV1 is lowered, the input of the inverter INV1 falls below the first threshold value VTH1, and the output voltage of the output terminal OUT of the inverter INV1 switches from the voltage VL to the voltage VH.

[0049] Note that when the input voltage of the inverter INV1 is the voltage VL, the MOS transistor Mp1 is on, the MOS transistor Mn1 is off, and the voltage at the drains of the MOS transistors Mp1 and Mn1 becomes the voltage VH. When the voltage at the drains of the MOS transistors Mp1 and Mn1 becomes the voltage VH, the MOS transistor Mp2 is off, the MOS transistor Mn2 is on, and the voltage at the drains of the MOS transistors Mp2 and Mn2 becomes the voltage VL. Therefore, the voltage VL is applied to the negative side of the capacitor C1 connected to the drains of the MOS transistors Mp2 and Mn2.

[0050] Also, when the drain voltages of MOS transistors Mp1 and Mn1 are at voltage VH, MOS transistor Mp3 turns off, MOS transistor Mn3 turns on, and the drain voltages of MOS transistors Mp3 and Mn3 become voltage VL. When the drain voltages of MOS transistors Mp3 and Mn3 become voltage VL, MOS transistor Mp4 turns on. On the other hand, when the drain voltages of MOS transistors Mp1 and Mn1 are at voltage VH, MOS transistor Mp5 turns off. Therefore, the drain voltages of MOS transistors Mp4 and Mp5 become voltage VH. Thus, voltage VH is applied to the + side of capacitor C1 connected to MOS transistors Mp4 and Mp5, and capacitor C1 is charged so that the + side is positive and the - side is negative with voltage V HREG is charged.

[0051] Next, the case where the PWM signal switches from the H level to the L level will be described. When the PWM signal input to buffer BUF1 switches from the H level to the L level, the output signal of buffer BUF1 switches from the H level to the L level. As a result, MOS transistor MDn1, whose output of buffer BUF1 is connected to the gate, switches from on to off. Therefore, clamp circuit 16 stops functioning, and the input of inverter INV1 gradually rises from voltage VL towards voltage VH with the current Iref1 of MOS transistor Mp7 that constitutes current mirror circuit 15 (part A in FIG. 3).

[0052] When the input voltage of inverter INV1 rises, before the input voltage of inverter INV1 exceeds the second threshold value VTH2, MOS transistor Mp1 with a low gate threshold voltage set turns off, MOS transistor Mn1 turns on, and the drain voltages of MOS transistors Mp1 and Mn1 become voltage VL.

[0053] When the drains of MOS transistors Mp1 and Mn1 reach voltage VL, MOS transistor Mp2 turns on and MOS transistor Mn2 turns off. As shown in part B of Figure 3, the voltage at the drains of MOS transistors Mp2 and Mn2 switches from voltage VL to voltage VH, and the negative side of capacitor C1 is connected to the positive electrode of high-side voltage source 9. Also, when the voltage at the drains of MOS transistors Mp1 and Mn1 reaches voltage VL, MOS transistor Mp3 turns on and MOS transistor Mn3 turns off, and the voltage at the drains of MOS transistors Mp3 and Mn3 becomes voltage VH.

[0054] When the drains of MOS transistors Mp3 and Mn3 reach voltage VH, MOS transistor Mp4 turns off. Also, when the voltage at the drains of MOS transistors Mp1 and Mn1 reaches voltage VL, MOS transistor Mp5 turns on. That is, since MOS transistor Mp4 turns off and MOS transistor Mp5 turns on, the positive side of capacitor C1 is connected to the input of inverter INV1.

[0055] As a result, the input voltage of inverter INV1 rapidly rises toward voltage (VH + V HREG ) as shown in part C of Figure 3. Therefore, after the PWM signal switches from the H level to the L level, the input voltage of inverter INV1 immediately exceeds the second threshold value VTH2. As shown in part D of Figure 3, the output signal at the output terminal OUT of level shifter 10, which is the output of inverter INV1, can immediately switch from the H level to the L level. Note that capacitor C1 is discharged by diode D2, and the input voltage of inverter INV1 immediately returns to voltage VH as shown in part E of Figure 3.

[0056] According to the above-described embodiment, due to the operation of the speed-up circuit 17, when the PWM signal input to the input terminal IN switches from the H level to the L level, the transition time for the output signal at the output terminal OUT to transition from the H level to the L level can be shortened. In the case where there is no speed-up circuit 17, the input voltage of the inverter INV1 gradually rises toward the voltage VH due to the drain current Iref1 of the MOS transistor Mp7, as shown by the broken line (portion F) in FIG. 3. For this reason, as shown by the broken line (portion G) in FIG. 3, the transition time for the output signal at the output terminal OUT to transition from the H level to the L level becomes long. In contrast, in this embodiment, when the PWM signal input to the input terminal IN switches from the H level to the L level, the input voltage of the inverter INV1 rapidly increases due to the capacitor C1. Therefore, as shown in portion D of FIG. 3, the transition time for the output signal to transition from the H level to the L level can be shortened. Thereby, without increasing the circuit scale, the transition time of the level of the output signal can be shortened.

[0057] Note that the present invention is not limited to the above-described embodiment, and modifications, improvements, etc. can be made as appropriate. In addition, the material, shape, dimensions, number, location of arrangement, etc. of each component in the above-described embodiment are arbitrary as long as the present invention can be achieved, and are not limited.

[0058] According to the above-described embodiment, the diode D2 is provided, but the diode D2 is not essential and may be omitted.

[0059] According to the above-described embodiment, the speed-up circuit 17 is composed of MOS transistors Mp1 to Mp5 and Mn1 to Mn3, but it is not limited to this. As the speed-up circuit 17, while the MOS transistor MDn1 is on, the negative electrode of the high-side voltage source 9 is connected to the - side of the capacitor C1, and the positive electrode of the high-side voltage source 9 is connected to the + side of the capacitor C1, and the capacitor C1 is charged to the voltage V HREGWhen charging with the voltage of (=VH - VL) and the MOS transistor MDn1 turns off, it is sufficient that the positive electrode of the high-side voltage source 9 is connected to the - side of the capacitor C1 and the input of the inverter INV1 is connected to the + side.

[0060] Also, according to the above-described embodiment, the level shifter 10 is used in the DC / DC converter 1, but it is not limited to this. The level shifter 10 may be used in another device.

[0061] Also, according to the above-described embodiment, the inverter INV1 is used as the output unit, but it is not limited to this. A buffer may be used as the output unit.

Explanation of Reference Numerals

[0062] 10 Level shifter 15 Constant current circuit 16 Clamp circuit 17 Speed-up circuit C1 Capacitor D2 Diode INV1 Inverter (output unit) MDn1 MOS transistor Mp1 MOS transistor (first PMOS transistor) Mp2 MOS transistor (second PMOS transistor) Mp3 MOS transistor (third PMOS transistor) Mp4 MOS transistor (fourth PMOS transistor) Mp5 MOS transistor (fifth PMOS transistor) Mn1 MOS transistor (first NMOS transistor) Mn2 MOS transistor (second NMOS transistor) Mn3 MOS transistor (third NMOS transistor) V REG Voltage (first high voltage) VH Voltage (second high voltage) VL Voltage (second low voltage) VTH1 First threshold value (threshold value) VTH2 Second threshold value (threshold value) VZD Zener voltage ZD1 Zener diode

Claims

1. A level shifter that converts an input signal having an amplitude of a first low voltage and a first high voltage into an output signal having an amplitude of a second low voltage and a second high voltage, comprising: an output unit that compares a voltage supplied to an input with a threshold value and outputs the output signal; a constant current circuit provided between a positive electrode of a high-side voltage source that supplies the second high voltage and an input of the output unit, and supplies a constant current to the input of the output unit to raise the input voltage of the output unit to the second high voltage; a clamp circuit having a Zener diode and clamping the input voltage of the output unit to a value obtained by subtracting the Zener voltage of the Zener diode from the second high voltage; a MOS transistor that turns on and off according to the voltage of the input signal, and turns on and off the clamping function of the clamp circuit by turning on and off; a speed-up circuit having a capacitor, connecting a negative electrode of a high-side voltage source that supplies the second low voltage to one end of the capacitor while the MOS transistor is on, connecting a positive electrode of the high-side voltage source to the other end, charging the capacitor, and when the MOS transistor turns off, connecting the positive electrode of the high-side voltage source to one end of the capacitor and connecting the input of the output unit to the other end. Level shifter.

2. The level shifter according to claim 1, comprising: a diode having an anode connected to the other end of the capacitor and a cathode connected to the positive electrode of the high-side voltage source. Level shifter.

3. The level shifter according to claim 1 or 2, wherein the speed-up circuit includes a first PMOS transistor having a gate connected to the input of the output unit and a source connected to the positive electrode of the high-side voltage source; a first NMOS transistor having a gate connected to the input of the output unit, a source connected to the negative electrode of the high-side voltage source, and a drain connected to the first PMOS transistor; a second PMOS transistor having a gate connected to the drains of the first PMOS transistor and the first NMOS transistor and a source connected to the positive electrode of the high-side voltage source; a second NMOS transistor having a gate connected to the drains of the first PMOS transistor and the first NMOS transistor, a source connected to the negative electrode of the high-side voltage source, and a drain connected to the drain of the second PMOS transistor. A third PMOS transistor having a gate connected to the drains of the first PMOS transistor and the first NMOS transistor and a source connected to the positive electrode of the high-side voltage source, A third NMOS transistor having a gate connected to the drains of the first PMOS transistor and the first NMOS transistor, a source connected to the negative electrode of the high-side voltage source, and a drain connected to the drain of the third PMOS transistor, A fourth PMOS transistor having a source connected to the positive electrode of the high-side voltage source and a gate connected to the drains of the third PMOS transistor and the third NMOS transistor, A fifth PMOS transistor having a gate connected to the drains of the first PMOS transistor and the first NMOS transistor, a source connected to the drain of the fourth PMOS transistor, and a drain connected to the input of the output section, and One end of the capacitor is connected to the drains of the second PMOS transistor and the second NMOS transistor, and the drain of the fourth PMOS transistor and the source of the fifth PMOS transistor are connected to the other end of the capacitor Level shifter.

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