Display device, electronic device

Abstract

To provide a display that has a small circuit area and low power consumption.SOLUTION: A display has an image signal line, an image data holding unit, a correction data holding unit, and a display element. The correction data holding unit is electrically connected to the image signal line. The image signal line is electrically connected to the image data holding unit. The image data holding unit is electrically connected to the display element. The image signal line has a function to hold first image data by a parasitic capacitance. The image data holding unit has a function to hold the first image data. The correction data holding unit has a function to hold the correction data, and a function to, after the image data holding unit holds the first image data, hold the correction data in the correction data holding unit to generate second image data having a larger number of gradations than the first image data according to the first image data and the correction data.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] One aspect of the present invention relates to a display device and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The invention disclosed in this specification etc. The technical field relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, one aspect of the present invention disclosed in this specification Examples of the technical field include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods.

Background Art

[0003] In recent years, display devices included in mobile phones such as smartphones, tablet-type information terminals, notebook personal computers, portable game machines, etc. have been improved in various aspects. For example, developments of display devices such as increasing the resolution, improving the color reproducibility, reducing the size of the driving circuit, reducing the power consumption, etc. have been carried out. Also, for example, in order to display multi-tone images, an invention of a source driver IC of a display device having a liquid crystal element using a multi-tone linear digital-to-analog conversion circuit is disclosed in Patent Document 1.

[0004] In addition, as a switching element included in a pixel circuit of a display device, a technique of applying a transistor using an oxide semiconductor as a semiconductor thin film can be mentioned.

[0005] ​​​As a semiconductor thin film applicable to a transistor, silicon-based semiconductor materials are widely known However, oxide semiconductors are attracting attention as other materials. Examples of oxide semiconductors include not only oxides of monovalent metals such as indium oxide and zinc oxide, but also oxides of multivalent metals Among the oxides of multivalent metals, in particular, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.

[0006] According to research on IGZO, in oxide semiconductors, a C AAC (c-axis aligned crystalline) structure and an nc (n anocrystalline) structure that are neither single crystal nor amorphous have been found (see Non-Patent Documents 1 to 3 . In Non-Patent Documents 1 and 2, techniques for fabricating transistors using oxide semiconductors having a CAAC structure are also disclosed. Furthermore, even oxide semiconductors with lower crystallinity than the CAAC structure and the nc structure have been shown to have minute crystals in Non-Patent Documents 4 and 5.

[0007] Furthermore, a transistor using IGZO as an active layer has an extremely low off-current (see Non-Patent Document 6 .), and LSIs and display devices utilizing its characteristics have been reported (see Non-Patent Documents 7 and 8 .). In addition, Patent Document 2 discloses an invention in which a transistor containing IGZO in an active layer is used in a pixel circuit of a display device.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

[0009] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD’13 Digest of Technical Papers”, 2013, p.151-154 [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 [Summary of the Invention] [Problems to be Solved by the Invention]

[0010] As conditions for a display device to display high-quality images, the display device is required to have, for example, high resolution, multi-tone adjustment, a wide color gamut, etc. For example, in a display device including a light-emitting element such as an organic EL (Electro Lumi nescence) element, or a liquid crystal element such as a transmissive liquid crystal element or a reflective liquid crystal element, to realize a multi-tone image, it is necessary to appropriately design the source driver circuit.

[0011] To handle multi-tone image data, it is necessary to increase the resolution of the digital-to-analog conversion circuit included in the source driver circuit. The digital-to-analog conversion circuit can output an analog value (voltage) more finely by increasing its resolution. However, when designing a digital-to-analog conversion circuit with high resolution, the circuit area of the digital-to-analog conversion circuit increases.

[0012] One aspect of the present invention is to provide a display device capable of generating multi-tone image data as one of the problems. Another aspect of the present invention is to provide a novel display device as one of the problems. ​​​​​​Another aspect of the present invention is to provide a novel electronic device having the display device as an issue. This is the first one.

[0013] Another aspect of the present invention is to provide a display device having a source driver circuit with a small circuit area as one of the issues. Another aspect of the present invention is to provide a display device having a source driver circuit with low power consumption as one of the issues.

[0014] Note that the issues of one aspect of the present invention are not limited to the above-listed issues. The above-listed issues do not prevent the existence of other issues. Other issues are the issues not mentioned in this item described below. The issues not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification or drawings, etc., and can be appropriately extracted from these descriptions. That is, those skilled in the art can derive them from the descriptions in the specification or drawings, etc., and can appropriately extract them from these descriptions. Note that one aspect of the present invention solves at least one of the above-listed issues and other issues. Note that one aspect of the present invention does not necessarily need to solve all of the above-listed issues and other issues.

Means for Solving the Issues

[0015] (1) One aspect of the present invention has a first circuit, a second circuit, and an image signal line. The first circuit has an image data holding unit and a display element. The second circuit has a correction data holding unit. The second circuit is electrically connected to the image signal line. The image signal line is electrically connected to the first circuit. The image data holding unit is electrically connected to the display element. The first circuit has a function of holding first image data in the image data holding unit. The second circuit has a function of holding correction data in the correction data holding unit and a function of correcting the first image data held in the image signal line and the image data holding unit with the correction data. ​​​​​​​​​​​ A function of correcting the second image data according to data, and the display element has the second image data A display device having a function of displaying an image corresponding thereto.

[0016] (2) Alternatively, in one aspect of the present invention, in the configuration of (1) above, the second circuit has the first to third switches And a first capacitive element, and the first circuit has a fourth switch and a second capacitive element The first terminal of the first switch is electrically connected to the first terminal of the first capacitive element and the image signal line The second terminal of the first switch is electrically connected to the first terminal of the second switch, and the correction The data holding unit is electrically connected to the second terminal of the second switch, the second terminal of the first capacitive element, and the first terminal of the third switch The first terminal of the fourth switch is electrically connected to the image signal line The image data holding unit is a display device electrically connected to the second terminal of the fourth switch and the second capacitive element Connected thereto.

[0017] (3) Alternatively, in one aspect of the present invention, in the configuration of (2) above, at least one of the first to fourth switches Is a transistor, and the transistor has either metal oxide or silicon in the channel formation region. A display device. One of silicon.

[0018] (4) Alternatively, in one aspect of the present invention, in the configuration of (2) or (3) above, the first to fourth functions The first function is to turn off the second switch, turn on the third switch, and write the first potential to the correction Data holding unit, turn off the second switch, turn on each of the first switch and the fourth switch, and the image signal line and the image data holding Each of them is turned on, and the image signal line and the image data holding a section, and a function of writing a second potential corresponding to the first image data, and the second function is the first turns off the first switch, turns on the fourth switch, and electrically floats the image signal line and the image data holding section, and the third function is to turn off each of the first switch and the third switch, turn on the second switch, and write a third potential corresponding to the correction data to the correction data holding section; when the potential of the second terminal of the first capacitive element changes from the first potential to the third potential, the second potential held by the image signal line and the image data holding section changes to a fourth potential corresponding to the second image data, and the fourth function is a display device having a function of turning off the fourth switch and driving the display element according to the fourth potential. section, and the third function is to turn off each of the first switch and the third switch, turn on the second switch, and write a third potential corresponding to the correction data to the correction data holding section; when the potential of the second terminal of the first capacitive element changes from the first potential to the third potential, the second potential held by the image signal line and the image data holding section changes to a fourth potential corresponding to the second image data, and the fourth function is a display device having a function of turning off the fourth switch and driving the display element according to the fourth potential. section, and the third function is to turn off each of the first switch and the third switch, turn on the second switch, and write a third potential corresponding to the correction data to the correction data holding section; when the potential of the second terminal of the first capacitive element changes from the first potential to the third potential, the second potential held by the image signal line and the image data holding section changes to a fourth potential corresponding to the second image data, and the fourth function is a display device having a function of turning off the fourth switch and driving the display element according to the fourth potential. potential to the third potential, the second potential held by the image signal line and the image data holding section changes to a fourth potential corresponding to the second image data, and the fourth function is a display device having a function of turning off the fourth switch and driving the display element according to the fourth potential. section, and the third function is to turn off each of the first switch and the third switch, turn on the second switch, and write a third potential corresponding to the correction data to the correction data holding section; when the potential of the second terminal of the first capacitive element changes from the first potential to the third potential, the second potential held by the image signal line and the image data holding section changes to a fourth potential corresponding to the second image data, and the fourth function is a display device having a function of turning off the fourth switch and driving the display element according to the fourth potential. section, and the third function is to turn off each of the first switch and the third switch, turn on the second switch, and write a third potential corresponding to the correction data to the correction data holding section; when the potential of the second terminal of the first capacitive element changes from the first potential to the third potential, the second potential held by the image signal line and the image data holding section changes to a fourth potential corresponding to the second image data, and the fourth function is a display device having a function of turning off the fourth switch and driving the display element according to the fourth potential. section, and the third function is to turn off each of the first switch and the third switch, turn on the second switch, and write a third potential corresponding to the correction data to the correction data holding section; when the potential of the second terminal of the first capacitive element changes from the first potential to the third potential, the second potential held by the image signal line and the image data holding section changes to a fourth potential corresponding to the second image data, and the fourth function is a display device having a function of turning off the fourth switch and driving the display element according to the fourth potential.

[0019] (5) Alternatively, in one aspect of the present invention, in the configuration of (4) above, the second potential is a potential corresponding to the upper bits of the second image data, and the third potential is a potential corresponding to the lower bits of the second image data. is a display device. is a display device.

[0020] (6) Alternatively, in one aspect of the present invention, in any one of the configurations of (2) to (5) above, the display element is a liquid crystal element, and the first terminal of the liquid crystal element is electrically connected to the image data holding section. is a display device. is a display device.

[0021] (7) Alternatively, in one aspect of the present invention, in any one of the configurations of (2) to (5) above, the display element is a light-emitting element, has a drive circuit section, the drive circuit section has a drive transistor, the gate of the drive transistor is electrically connected to the image data holding section, and the first section, and the third function is to turn off each of the first switch and the third switch, turn on the second switch, and write a third potential corresponding to the correction data to the correction data holding section; when the potential of the second terminal of the first capacitive element changes from the first potential to the third potential, the second potential held by the image signal line and the image data holding section changes to a fourth potential corresponding to the second image data, and the fourth function is a display device having a function of turning off the fourth switch and driving the display element according to the fourth potential. section, and the third function is to turn off each of the first switch and the third switch, turn on the second switch, and write a third potential corresponding to the correction data to the correction data holding section; when the potential of the second terminal of the first capacitive element changes from the first potential to the third potential, the second potential held by the image signal line and the image data holding section changes to a fourth potential corresponding to the second image data, and the fourth function is a display device having a function of turning off the fourth switch and driving the display element according to the fourth potential. The terminal is electrically connected to the second terminal of the second capacitor element and the input terminal of the light-emitting element. It is a display device.

[0022] (8) Alternatively, one aspect of the present invention is an electronic device having a display device configured as any one of (1) to (7) above and a housing.

Advantages of the Invention

[0023] According to one aspect of the present invention, a display device capable of generating multi-tone image data can be provided. Further, according to one aspect of the present invention, a novel display device can be provided. Also, according to one aspect of the present invention, an electronic device having the display device can be provided.

[0024] Also, according to one aspect of the present invention, a display device having a source driver circuit with a small circuit area can be provided. Further, according to one aspect of the present invention, a display device having a source driver circuit with low power consumption can be provided.

[0025] Note that the effects of one aspect of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects are those effects not mentioned in this item described below. Effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification or drawings, etc., and can be appropriately extracted from these descriptions. That is, effects not mentioned in this item can be derived by those skilled in the art from the descriptions in the specification or drawings, etc., and can be appropriately extracted from these descriptions. Note that one aspect of the present invention has at least one of the effects listed above and other effects. Therefore, one aspect of the present invention may not have the effects listed above in some cases.

Brief Description of the Drawings

[0026]

Figure 1

Figure 2

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Figure 10

Figure 11

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Figure 13

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Figure 15

Figure 16

Figure 17

Mode for Carrying Out the Invention

[0027] In this specification and the like, metal oxide refers to a metal oxide in a broad sense. is an oxide of a metal. Metal oxides include oxide insulators, oxide conductors (including transparent oxide conductors). ) and oxide semiconductors (also referred to as Oxide Semiconductor or simply OS). For example, when a metal oxide is used in the active layer of a transistor, the metal Oxides are sometimes called oxide semiconductors. In other words, metal oxides have amplifying and rectifying properties. and forming a channel forming region of a transistor having at least one switching function. When the metal oxide can be formed, the metal oxide is called a metal oxide semiconductor. It can also be called OS FET or O In the case of the term "S transistor," a transistor having a metal oxide or oxide semiconductor is used. This can be rephrased as transistor.

[0028] In the present specification and the like, metal oxides having nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are also called metal oxynitrides (MEs). It may also be called tal oxynitride.

[0029] (Embodiment 1) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0030] <Display device configuration example 1> First, a configuration example of a display device will be described. FIG. 1 shows a configuration example of a display device having a display element. The display device DD includes a display unit PA and a source driver circuit SD and a gate driver circuit GD.

[0031] The display unit PA has a plurality of pixels PIX. In FIG. Only one of the pixels PIX is shown, and the other pixels PIX are omitted. In addition, the plurality of pixels PIX of the display unit PA are arranged in a matrix. preferable.

[0032] In FIG. 1, the pixel PIX is electrically connected to the source driver circuit SD via a wiring SL that functions as an image signal line. In addition, the pixel PIX is electrically connected to the gate driver circuit GD via a wiring GL that functions as a selection signal line. Note that since the display unit PA has a plurality of pixels PIX, a plurality of pixels PIX electrically connected to the wiring SL may be provided. Similarly, a plurality of pixels PIX electrically connected to the wiring GL may be provided. In addition, each of the wiring SL and the wiring GL may be provided in a plurality according to the number of pixels PIX included in the display unit PA. Furthermore, depending on the circuit configuration of the pixel PIX, a configuration may be adopted in which a plurality of wiring SL or a plurality of wiring GL are electrically connected to one pixel PIX.

[0033] The pixel PIX can be configured to have one or more sub-pixels. For example, the pixel PIX may have a configuration with one sub-pixel (any one of red (R), green (G), blue (B), white (W)), a configuration with three sub-pixels (three colors of red (R), green (G), and blue (B)), or a configuration with four sub-pixels (four colors of red (R), green (G), blue (B), white (W), or four colors of red (R), green (G), blue (B), yellow (Y)). Note that the color elements applied to the sub-pixels are not limited to the above combinations, and cyan (C) and magenta (M) may be combined as necessary.

[0034] The source driver circuit SD has a function of generating image data for input to the pixels PIX included in the display unit PA and a function of transmitting the image data to the pixels PIX. ​​​​​​​​​​​​​​​​

[0035] The source driver circuit SD includes, for example, a shift register SR, a latch circuit LAT, and A bell shift circuit LVS, a digital-to-analog conversion circuit DAC, an amplifier circuit AMP, and In FIG. 1, the output terminal of the shift register SR is is electrically connected to the clock input terminal of the latch circuit LAT, and the input terminal of the latch circuit LAT The terminal of the latch circuit LAT is electrically connected to the data bus wiring DB, and the output terminal of the latch circuit LAT is The output terminal of the level shift circuit LVS is electrically connected to the input terminal of the digital The digital-to-analog conversion circuit DAC is electrically connected to the input terminal of the digital-to-analog conversion circuit DAC. The output terminal of the DAC is electrically connected to the input terminal of the amplifier circuit AMP. The output terminal of the display unit PA is electrically connected to the display unit PA.

[0036] The latch circuit LAT, the level shift circuit LVS, and the digital The analog conversion circuit DAC and the amplifier circuit AMP are provided for one wiring SL. That is, the latch circuit LAT and the level shift circuit LVS are arranged according to the number of lines SL. A plurality of digital-to-analog conversion circuits DAC and amplifier circuits AMP are provided. In this case, the shift register SR is required to receive the clocks of the multiple latch circuits LAT. The pulse signal may be transmitted sequentially to each of the clock input terminals.

[0037] The data bus wiring DB transmits digital signals including image data to be input to the display unit PA. The image data has gradations, and the higher the gradations, the For example, the color or brightness changes can be expressed more smoothly, and images closer to nature can be displayed on the display unit PA. This can be done. However, the larger the gradation, the larger the data volume of the image data , and it is necessary to use a digital-to-analog conversion circuit with high resolution.

[0038] A digital signal including image data is input from the data bus wiring DB to the input terminal of the latch circuit LAT. Then, the latch circuit LAT either holds the image data or outputs the held image data from the output terminal in response to a signal transmitted from the shift register SR.

[0039] The level shift circuit LVS has a function of converting an input signal into an output signal with a larger or smaller amplitude voltage. In FIG. 1, the digital-to-analog conversion circuit DAC has the role of converting the amplitude voltage of the digital signal including the image data sent from the latch circuit LAT into an amplitude voltage at which the digital-to-analog conversion circuit DAC operates properly.

[0040] The digital-to-analog conversion circuit DAC has a function of converting a digital signal including the input image data into an analog signal and a function of outputting the analog signal from the output terminal. . In particular, when displaying multi-gradation image data on the display unit PA, the digital-to-analog conversion circuit DAC needs to be a high-resolution digital-to-analog conversion circuit.

[0041] The amplifier circuit AMP has a function of amplifying an analog signal input to the input terminal and outputting it to the output terminal. By providing an amplifier circuit AMP between the digital-to-analog conversion circuit DAC and the display unit PA, the image data can be stably sent to the display unit PA. As the amplifier circuit AMP, a voltage follower circuit having an operational amplifier or the like can be applied. ​​​​​It is possible. When using a circuit having a differential input circuit as the amplifier circuit, the offset voltage of the differential input circuit is preferably a voltage that is as close to 0V as possible.

[0042] By performing the above-described operation, the source driver circuit SD can convert a digital signal including image data, which is sent from the data bus wiring DB, into an analog signal and transmit it to the display unit PA. to be able to.

[0043] The gate driver circuit GD has a function of selecting a pixel PIX that is the input destination of the image data among a plurality of pixels PIX included in the display unit PA.

[0044] As a method of inputting image data to the display unit PA, for example, the gate driver circuit GD sends a selection signal to a plurality of pixels PIX that are electrically connected to a certain single wiring GL, turns on the write switching elements of the image data included in the plurality of pixels PIX, and then, from the source driver circuit SD, via the wiring SL, transmits image data to the plurality of pixels PIX, and write the image data. Therefore, in this specification and the like, the wiring GL can be referred to as a gate line, a selection signal line, etc., and the wiring SL can be referred to as a source line, a data line, an image signal line, etc.

[0045] Note that one aspect of the present invention is not limited to the configuration of the display device DD shown in FIG. 1. One aspect of the present invention can be, for example, appropriately changing the components of the display device DD according to circumstances such as design specifications and purposes.

[0046] Incidentally, when displaying a multi-tone image on the display unit PA, the digital-to-analog conversion circuit DA ​​​It is only necessary to increase the resolution of C. However, in this case, the digital-to-analog conversion circuit DAC becomes large, and thus the circuit area of the source driver circuit SD may increase. In order to reduce the circuit area of the source driver circuit SD, if circuit elements such as transistors and capacitor elements included in the circuit of the source driver circuit SD are made small, the electrical characteristics of the circuit elements may be impaired due to the influence of parasitic resistance and the influence of variations in the structure caused during the fabrication of the circuit elements. There is a possibility.

[0047] <Configuration Example 2 of Display Device> The display device according to one aspect of the present invention is configured in view of the above, and the potential of the holding portion of the image data of the pixel PIX is varied by capacitive coupling to a potential having higher accuracy than the outputable potential of the digital-to-analog conversion circuit DAC. That is, the display device according to one aspect of the present invention can provide a potential with higher resolution than the digital-to-analog conversion circuit DAC to the holding portion of the image data of the pixel PIX. As a result, it is not necessary to increase the resolution of the digital-to-analog conversion circuit, and thus a digital-to-analog conversion circuit with low resolution can be used. Therefore, the circuit area of the source driver circuit SD including the digital-to-analog conversion circuit DAC can be reduced, and the power consumption of the source driver circuit SD can be reduced.

[0048] A configuration example of the display device according to one aspect of the present invention is shown in FIGS. 2(A) and 2(B).

[0049] The block diagram of FIG. 2(A) shows an example of a display device having a liquid crystal element, and the display device DD1 has a display portion PA and a circuit provided around the display portion PA.

[0050] Specifically, the display device DD1 shown in FIG. 2(A) includes, in addition to the display unit PA shown in FIG. 1, a gate driver circuit GD and a source driver circuit SD, and further has a correction data holding unit 104. Each pixel PIX included in the display unit PA has an image data holding unit 101 and a display element 103.

[0051] The input terminal of the correction data holding unit 104 is electrically connected to the output terminal of the source driver circuit SD, and the output terminal of the correction data holding unit 104 is electrically connected to the wiring SL.

[0052] Similar to the display unit PA shown in FIG. 1, the display unit PA shown in FIG. 2(A) has a plurality of pixels PIX. Note that FIG. 2(A) shows only one of the plurality of pixels PIX included in the display unit PA, and the other pixels PIX are omitted. In the pixel PIX included in the display unit PA, the image data holding unit 101 is electrically connected to the display element 103. Also, the image data holding unit 101 is electrically connected to the wiring SL.

[0053] The image data holding unit 101 has a function of holding the image data sent from the source driver circuit SD via the correction data holding unit 104 and the wiring SL. Also, the image data holding unit 101 can have a writing switching element, a capacitive element, etc. for holding the image data.

[0054] The display element 103 included in the pixel PIX shown in FIG. 2(A) has a function of controlling the light emitted from the pixel PIX. The intensity of the light (which can be described as brightness, height of gradation, etc.) is determined according to the image data held in the image data holding unit 101.

[0055] ​​​​​​​​ As the element 103, a liquid crystal element can be applied as described above. The liquid crystal element includes, for example, a transmissive liquid crystal element, a reflective liquid crystal element, and the like. In addition, elements other than the liquid crystal element include, for example, an electrophoretic element, a display element using electro-fluid (registered trademark), a display element using an electro-wetting method, and the like. Regarding the application of light-emitting elements such as an inorganic EL element and an organic EL element as the display element 103, it will be described later.

[0056] The wiring VA shown in FIG. 2(A) is electrically connected to the pixel PIX. The wiring VA can be, for example, a capacitance line for holding image data in the image data holding unit 101, a wiring for applying a potential to one terminal of the liquid crystal element of the display element 103, and the like. Therefore, the wiring VA can be one or a plurality of wirings.

[0057] In the description of the display device DD in FIG. 1, the wiring GL was described as having a function of transmitting a selection signal in advance when writing image data to the pixel PIX. However, the pixel PIX in FIG. 2(A) and the wiring VA may have a function of controlling an on state and an off state between them. Therefore, the wiring GL can be one or a plurality of wirings. Thereby, the application of the voltage and / or the supply of current from the wiring VA can be temporarily stopped.

[0058] The block diagram in FIG. 2(B) shows an example of a display device having a light-emitting element such as an organic EL element or an inorganic EL element.

[0059] Specifically, the display device DD2 shown in FIG. 2(B) has substantially the same configuration as the pixel PIX of the display device DD1, but the pixel PIX included in the display unit PA has a drive circuit unit 102. in this respect, it is different from the display device DD1. Therefore, for the display device DD2, only the parts different from the above-mentioned display device DD1 will be described, and the description of the same parts as the display device DD1 will be omitted.

[0060] The drive circuit unit 102 is electrically connected to the image data holding unit 101 and the display element 103.

[0061] The drive circuit unit 102 has a function of driving the display element 103 according to the image data held in the image data holding unit 101. For example, when a light-emitting element whose emission luminance is determined by current, such as an organic EL element, is applied as the display element 103, the drive circuit unit 102 can have a drive transistor that controls the current. Note that the drive transistor has a function of flowing a drive current to the display element 103.

[0062] As the display element 103 included in the pixel PIX shown in FIG. 2(B), for example, as described above, a light-emitting element can be applied. Examples of the light-emitting element include an inorganic EL element and an organic EL element. In addition, other examples include micro LEDs.

[0063] The wiring VA in FIG. 2(B) is electrically connected to the pixel PIX in the same manner as the wiring VA shown in FIG. 2(A). The wiring VA here can be a capacitance line for holding image data in the image data holding unit 101, a voltage supply line for driving the drive circuit unit 102, a wiring for supplying current to the light-emitting element, etc. Therefore, the wiring VA in FIG. 2(B) can be one or a plurality of wirings in the same manner as the wiring VA shown in FIG. 2(A).

[0064] ​​​​​​​​​​​​​Next, the correction data holding unit 104, the wiring SL that functions as an image signal line, and the pixel PIX FIG. 3 shows the parasitic capacitance and wiring resistance of the line SL and the circuit configuration of the pixel PIX. 3 is a circuit diagram showing an example of the circuit configuration of the correction data holding unit 104. In order to show the connection relationship with the correction data holding unit 104, the source driver circuit SD is illustrated. In addition, in the pixel PIX, only the circuit elements of the switch SWC and the capacitance element Cs are shown. In FIG. 3, the pixel PIX is shown with the following circuit elements. The wiring SL electrically connected to the pixel PIX is shown. 1 and 2, a wiring for connecting a specific node to a specific Wiring for applying a potential (wires corresponding to the wiring VA shown in FIG. 2) and the like are omitted.

[0065] As described above, the wiring SL shown in FIG. 3 has the parasitic capacitance and wiring resistance of the wiring SL. Specifically, the wiring SL has a wiring resistance of The display unit PA shown in FIG. There are N pixels PIX (N is an integer equal to or greater than 1) for each column, and the wiring SL is The resistor Rp is connected in series with N capacitance elements Cp. In addition, in FIG. 3, the first terminal of the capacitance element Cp and the first terminal of the resistance element Rp are It is assumed that one pixel PIX is electrically connected to the electrical connection point of the pixel PIX.

[0066] In the display unit PA shown in FIG. 3, a display unit 101 is provided in the i-th row (i is an integer of 1 to N). The pixel PIX that is being detected is illustrated as pixel PIX[i]. Unless otherwise specified, the description of the addresses of each of the pixels PIX[1] to PIX[N] is omitted. This may be the case. Also, in FIG. 3, pixels PIX[1], PIX[2], PIX N] are illustrated, and other pixels PIX are omitted.

[0067] The pixel PIX has a switch SWC and a capacitive element Cs. The first terminal of the switch SWC is electrically connected to the first terminal of the capacitive element Cs, and the second terminal of the switch SWC is electrically connected to the wiring SL. The second terminal of the capacitive element Cs is electrically connected to the wiring VC. The switching between the on state and the off state of the switch SWC is performed, for example, by a selection signal from the wiring GL or the like sent to the pixel PIX.

[0068] The capacitive element Cs can be, for example, a capacitive element for holding image data included in the image data holding unit 101 described in FIG. 2. Also, the wiring VC can be, for example, a wiring for applying an appropriate potential to the second terminal of the capacitive element Cs in order to hold the image data.

[0069] The second terminal of the capacitive element Cp that functions as a parasitic capacitance is electrically connected to the wiring VP. As the wiring VP, for example, the wiring GL, the wiring VC, or the like for transmitting a selection signal to the pixel PIX can be used.

[0070] The correction data holding unit 104 has switches SW1 to SW3 and a capacitive element Cd. The first terminal of the switch SW1 is electrically connected to the first terminal of the capacitive element Cd and the wiring SL, and the second terminal of the switch SW1 is electrically connected to the first terminal of the switch SW2 and the source The driver circuit SD is electrically connected thereto. The first terminal of the switch SW3 is electrically connected to the second terminal of the capacitor element Cd, and the second terminal of the switch SW2, and the second terminal of the switch SW3 is electrically connected to the wiring VG.

[0071] In this embodiment, the electrical connection point between the second terminal of the switch SW2, the second terminal of the capacitor element Cd, and the first terminal of the switch SW3 is referred to as the node ND3.

[0072] The correction data holding unit can write correction data to the second terminal of the capacitor element Cd (node ND3) by turning on the switch SW2.

[0073] The wiring VG is a wiring for resetting the correction data held in the correction data holding unit 104, and can be, for example, a wiring that provides a reference potential.

[0074] <Circuit configuration example of pixel> Next, a circuit configuration example applicable to the pixel PIX shown in FIGS. 1 to 3 will be described.

[0075] The pixel PIX shown in FIG. 4(A1) includes a transistor Tr1, a capacitor element C1, and a liquid crystal element LC. Further, the wiring DL, the wiring GL, and the wiring VCOM are electrically connected to the pixel PIX.

[0076] The transistor Tr1 functions as a switching element. In particular, the transistor Tr1 electrically connects or disconnects between the first terminal of the liquid crystal element LC and the wiring DL. That is, the transistor Tr1 can correspond to the switch SWC included in the pixel PIX of FIG. 3. Further, the transistor Tr1 is in Embodiment 3 ​​​The configuration described can be applied.

[0077] The wiring DL is a wiring for transmitting image data to the pixel PIX, and corresponds to the wiring SL shown in FIGS. 1 to 3. In addition, the wiring GL is a selection signal line for the pixel PIX, and corresponds to the wiring GL shown in FIGS. 1 and 2.

[0078] The wiring VCOM is a wiring for applying a predetermined potential to the second terminal of the liquid crystal element LC. As the predetermined potential, for example, a reference potential, a low-level potential, a potential lower than these, etc. can be used. In addition, the wiring VCOM can apply a common potential to the second terminals of the liquid crystal elements LC included in each of the plurality of pixels PIX of the display unit PA.

[0079] The first terminal of the transistor Tr1 is electrically connected to the first terminal of the capacitor element C1, the second terminal of the transistor Tr1 is electrically connected to the wiring DL, and the gate of the transistor Tr1 is electrically connected to the wiring GL.

[0080] In the present embodiment, the electrical connection point of the first terminal of the transistor Tr1, the first terminal of the capacitor element C1, and the first terminal of the liquid crystal element LC is referred to as the node ND1.

[0081] The second terminal of the liquid crystal element LC is electrically connected to the wiring VCOM. In addition, the second terminal of the capacitor element C1 is electrically connected to the wiring VCOM.

[0082] The capacitor element C1 has a function of holding the potential difference between the first terminal of the transistor Tr1 and the wiring VCOM. In addition, the capacitor element C1 is the capacitor element C included in the pixel PIX shown in FIG. 3. It can correspond to s. In this case, the wiring VC shown in FIG. 3 corresponds to the wiring VC in FIG. 4(A1). It can correspond to OM. Note that as long as the capacitor element C1 has the role of holding the potential of the first terminal of the capacitor element C1, the second terminal of the capacitor element C1 may be electrically connected to a wiring that provides a constant potential other than the wiring VCOM.

[0083] Also, in the pixel PIX shown in FIG. 4(A1), the transistor Tr1 and the capacitor element C1 can correspond to the circuit elements included in the image data holding unit 101 of the pixel PIX shown in FIG. 2(A). Further, in the pixel PIX shown in FIG. 4(A1), the liquid crystal element LC can correspond to the display element 103 of the pixel PIX shown in FIG. 2(A).

[0084] The pixel PIX shown in FIG. 4(A1) holds a potential corresponding to the image data at the node ND1, so that the liquid crystal molecules included in the liquid crystal element LC are arranged between the first terminal and the second terminal of the liquid crystal element LC according to the voltage. The arranged liquid crystal molecules transmit the light from the backlight unit included in the display device or reflect the light incident from outside the display device by the reflection electrode included in the display device, so that the pixel PIX can emit light corresponding to the image data.

[0085] In the pixel PIX of FIG. 4(A1), the transistor Tr1 is preferably an OS transistor. In particular, the OS transistor preferably has an oxide containing indium, element M (element M is aluminum, gallium, yttrium, or tin), and zinc in its channel formation region. ​​​​​​​​​​​By applying an OS transistor like this to transistor Tr1, the off current of the transistor can be made very low. When holding data at the first terminal (node ND1) of the capacitive element C1, by using transistor Tr1 as an OS transistor, destruction of the data held at node ND1 due to the off current can be prevented. Also, as transistor Tr1, for example, a transistor having silicon in the channel formation region can be applied (hereinafter referred to as an Si transistor). As the silicon, for example, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon etc. can be used. In addition, the transistor Tr1 shown in FIG. 4(A1) may be a transistor having a back gate. The pixel PIX shown in FIG. 4(A2) has a configuration in which a back gate is provided for the transistor Tr1 shown in FIG. 4(A1). In FIG. 4(A2), the gate and the back gate of transistor Tr1 are electrically connected. Since a transistor with the gate and the back gate electrically connected can increase the on current flowing through the transistor, by adopting the configuration of the pixel PIX shown in FIG. 4(A2), the pixel PIX can operate faster. Note that although the pixel PIX shown in FIG. 4(A2) is configured such that the gate and the back gate of transistor Tr1 are connected, the back gate of transistor Tr1 may be configured to have a potential applied by another wiring. Furthermore, an example of a circuit configuration different from FIGS. 4(A1) and 4(A2) that can be applied to the pixel PIX shown in FIGS. 1 to 3 will be described.

[0086] By applying an OS transistor like this to transistor Tr1, the off current of the transistor can be made very low. When holding data at the first terminal (node ND1) of the capacitive element C1, by using transistor Tr1 as an OS transistor, destruction of the data held at node ND1 due to the off current can be prevented. Also, as transistor Tr1, for example, a transistor having silicon in the channel formation region can be applied (hereinafter referred to as an Si transistor). As the silicon, for example, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon etc. can be used. In addition, the transistor Tr1 shown in FIG. 4(A1) may be a transistor having a back gate. The pixel PIX shown in FIG. 4(A2) has a configuration in which a back gate is provided for the transistor Tr1 shown in FIG. 4(A1). In FIG. 4(A2), the gate and the back gate of transistor Tr1 are electrically connected. Since a transistor with the gate and the back gate electrically connected can increase the on current flowing through the transistor, by adopting the configuration of the pixel PIX shown in FIG. 4(A2), the pixel PIX can operate faster. Note that although the pixel PIX shown in FIG. 4(A2) is configured such that the gate and the back gate of transistor Tr1 are connected, the back gate of transistor Tr1 may be configured to have a potential applied by another wiring. Furthermore, an example of a circuit configuration different from FIGS. 4(A1) and 4(A2) that can be applied to the pixel PIX shown in FIGS. 1 to 3 will be described.

[0087] In addition, the transistor Tr1 shown in FIG. 4(A1) may be a transistor having a back gate. The pixel PIX shown in FIG. 4(A2) has a configuration in which a back gate is provided for the transistor Tr1 shown in FIG. 4(A1). In FIG. 4(A2), the gate and the back gate of transistor Tr1 are electrically connected. Since a transistor with the gate and the back gate electrically connected can increase the on current flowing through the transistor, by adopting the configuration of the pixel PIX shown in FIG. 4(A2), the pixel PIX can operate faster. Note that although the pixel PIX shown in FIG. 4(A2) is configured such that the gate and the back gate of transistor Tr1 are connected, the back gate of transistor Tr1 may be configured to have a potential applied by another wiring. Also, as transistor Tr1, for example, a transistor having silicon in the channel formation region can be applied (hereinafter referred to as an Si transistor). As the silicon, for example, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon etc. can be used. Furthermore, an example of a circuit configuration different from FIGS. 4(A1) and 4(A2) that can be applied to the pixel PIX shown in FIGS. 1 to 3 will be described. By applying an OS transistor like this to transistor Tr1, the off current of the transistor can be made very low. When holding data at the first terminal (node ND1) of the capacitive element C1, by using transistor Tr1 as an OS transistor, destruction of the data held at node ND1 due to the off current can be prevented. In addition, the transistor Tr1 shown in FIG. 4(A1) may be a transistor having a back gate. The pixel PIX shown in FIG. 4(A2) has a configuration in which a back gate is provided for the transistor Tr1 shown in FIG. 4(A1). In FIG. 4(A2), the gate and the back gate of transistor Tr1 are electrically connected. Since a transistor with the gate and the back gate electrically connected can increase the on current flowing through the transistor, by adopting the configuration of the pixel PIX shown in FIG. 4(A2), the pixel PIX can operate faster. Note that although the pixel PIX shown in FIG. 4(A2) is configured such that the gate and the back gate of transistor Tr1 are connected, the back gate of transistor Tr1 may be configured to have a potential applied by another wiring. Furthermore, an example of a circuit configuration different from FIGS. 4(A1) and 4(A2) that can be applied to the pixel PIX shown in FIGS. 1 to 3 will be described. By applying an OS transistor like this to transistor Tr1, the off current of the transistor can be made very low. When holding data at the first terminal (node ND1) of the capacitive element C1, by using transistor Tr1 as an OS transistor, destruction of the data held at node ND1 due to the off current can be prevented. In addition, the transistor Tr1 shown in FIG. 4(A1) may be a transistor having a back gate. The pixel PIX shown in FIG. 4(A2) has a configuration in which a back gate is provided for the transistor Tr1 shown in FIG. 4(A1). In FIG. 4(A2), the gate and the back gate of transistor Tr1 are electrically connected. Since a transistor with the gate and the back gate electrically connected can increase the on current flowing through the transistor, by adopting the configuration of the pixel PIX shown in FIG. 4(A2), the pixel PIX can operate faster. Note that although the pixel PIX shown in FIG. 4(A2) is configured such that the gate and the back gate of transistor Tr1 are connected, the back gate of transistor Tr1 may be configured to have a potential applied by another wiring. Furthermore, an example of a circuit configuration different from FIGS. 4(A1) and 4(A2) that can be applied to the pixel PIX shown in FIGS. 1 to 3 will be described.

[0088] By applying an OS transistor like this to transistor Tr1, the off current of the transistor can be made very low. When holding data at the first terminal (node ND1) of the capacitive element C1, by using transistor Tr1 as an OS transistor, destruction of the data held at node ND1 due to the off current can be prevented. In addition, the transistor Tr1 shown in FIG. 4(A1) may be a transistor having a back gate. The pixel PIX shown in FIG. 4(A2) has a configuration in which a back gate is provided for the transistor Tr1 shown in FIG. 4(A1). In FIG. 4(A2), the gate and the back gate of transistor Tr1 are electrically connected. Since a transistor with the gate and the back gate electrically connected can increase the on current flowing through the transistor, by adopting the configuration of the pixel PIX shown in FIG. 4(A2), the pixel PIX can operate faster. Note that although the pixel PIX shown in FIG. 4(A2) is configured such that the gate and the back gate of transistor Tr1 are connected, the back gate of transistor Tr1 may be configured to have a potential applied by another wiring.

[0089] The pixel PIX shown in FIG. 4 (B1) includes transistors Tr2 to Tr4, a capacitor element C2, and a light-emitting element LD. Also, wiring DL, wiring GL1, wiring AL, wiring VL, and wiring CAT are electrically connected to the pixel PIX.

[0090] Each of the transistors Tr2 and Tr4 functions as a switching element. Writing of image data is performed by controlling the transistor Tr2, so the transistor Tr2 can correspond to the switch SWC included in the pixel PIX of FIG. 3. The transistor Tr3 functions as a driving transistor that controls the current flowing through the light-emitting element LD. Also, the transistors Tr2 to Tr4 can apply the configuration described in Embodiment 3.

[0091] The wiring DL is wiring for transmitting image data to the pixel PIX and can correspond to the wiring SL shown in FIGS. 1 to 3. In addition, the wiring GL1 is a selection signal line for the pixel PIX and can correspond to the wiring GL shown in FIGS. 1 and 2.

[0092] The wiring VL is wiring for applying a predetermined potential to a specific node within the pixel PIX. In addition, the wiring AL is wiring for supplying the current to be passed through the light-emitting element LD. The wiring VL and the wiring AL can correspond to the wiring VA shown in FIG. 2.

[0093] The wiring CAT is wiring for applying a predetermined potential to the output terminal of the light-emitting element LD. Examples of the predetermined potential include a reference potential, a low-level potential, and a potential lower than these. It is possible. Also, the wiring CAT can correspond to the wiring VA shown in FIG. 2. The wiring C AT is desirably used as a wiring for applying a common potential to a plurality of pixels PIX included in the display unit PA.

[0094] The first terminal of the transistor Tr2 is electrically connected to the first terminal of the capacitor element C2 and the gate of the transistor Tr3. The second terminal of the transistor Tr2 is electrically connected to the wiring DL. The gate of the transistor Tr2 is electrically connected to the wiring GL1. The first terminal of the transistor Tr3 is electrically connected to the wiring AL. The second terminal of the transistor Tr3 is electrically connected to the second terminal of the capacitor element C2, the first terminal of the transistor Tr4, and the input terminal of the light-emitting element LD. The second terminal of the transistor Tr4 is electrically connected to the wiring VL. The gate of the transistor Tr4 is electrically connected to the wiring GL1. The output terminal of the light-emitting element LD is electrically connected to the wiring CAT.

[0095] In this embodiment, the electrical connection point of the first terminal of the transistor Tr2, the first terminal of the capacitor element C2, and the gate of the transistor Tr3 is referred to as the node ND2.

[0096] The capacitor element C2 has a function of holding the potential difference between the second terminal and the gate of the transistor Tr3. Also, the capacitor element C2 can correspond to the capacitor element Cs included in the pixel PIX shown in FIG. 3.

[0097] Also, in the pixel PIX shown in FIG. 4(B1), the transistor Tr2 and the capacitor element C2 correspond to the circuit elements included in the image data holding unit 101 of the pixel PIX shown in FIG. 2(B). ​​​​​​​​​​​It is possible. Also, in the pixel PIX shown in FIG. 4(B1), the transistor Tr3 and the transistor Tr4 can correspond to the circuit elements included in the drive circuit section 102 of the pixel PIX shown in FIG. 2(B). Also, in the pixel PIX shown in FIG. 4(B1), the light-emitting element L D can correspond to the display element 103 of the pixel PIX shown in FIG. 2(B).

[0098] The pixel PIX shown in FIG. 4(B1) holds a potential corresponding to the image data at the node ND2, so that a current corresponding to the gate-source voltage of the transistor Tr3, which is the drive transistor, flows between the source and drain of the transistor Tr3. Since the current flows into the input terminal of the light-emitting element LD, the light-emitting element LD emits light. Therefore, the pixel PIX can emit light corresponding to the image data.

[0099] In the pixel PIX of FIG. 4(B1), at least one of the transistors Tr2 to Tr4 is preferably an OS transistor. In particular, the OS transistor preferably has an oxide containing at least one of indium, element M (element M is aluminum, gallium, yttrium, or tin), and zinc in the channel formation region. Also, the oxide will be described in detail in Embodiment 4. By applying such an OS transistor to at least one of the transistors Tr2 to Tr4, the off-current of the applied transistor can be made extremely low. When holding data at the first terminal (node ND2) of the capacitor element C2, by using the transistor Tr2 as the OS transistor, it is possible to prevent the data held at the node ND2 from being destroyed due to the off-current. Also, the transistor Tr By applying the OS transistor to all of transistors Tr2 to Tr4, each of these transistors can be formed simultaneously, which may shorten the manufacturing process of the display unit PA. That is, since the production time of the display unit PA can be reduced, the production quantity per unit time can be increased.

[0100] In addition, for at least one of transistors Tr2 to Tr4, for example, an Si transistor having silicon in the channel formation region can be applied. As the silicon, for example, hydrogenated amorphous silicon, microcrystalline silicon, or polycrystalline silicon can be used.

[0101] Also, the channel formation regions of transistors Tr2 to Tr4 are preferably made of the same material. Further, depending on the situation, some of the transistors among transistors Tr2 to Tr4 can be Si transistors and the remaining transistors can be OS transistors for the pixel PIX.

[0102] Note that for the pixel PIX shown in FIG. 4(B1), a switching element may be provided at the input terminal of the light emitting element LD. The pixel PIX shown in FIG. 4(B2) has a configuration in which a transistor Tr5 is provided as a switching element between the electrical connection point of the second terminal of the transistor Tr3, the second terminal of the capacitor element C2, and the first terminal of the transistor Tr4, and the light emitting element LD. That is, the first terminal of the transistor Tr5 is electrically connected to the second terminal of the transistor Tr3, the second terminal of the capacitor element C2, and the first terminal of the transistor Tr4. The second terminal of the transistor Tr5 is electrically connected to the input terminal of the light-emitting element LD. Also, the gate of the transistor Tr5 is electrically connected to the wiring GL2 which is one of the selection signal lines.

[0103] In the case of the pixel PIX shown in FIG. 4(B1), in order to stop the light emission of the light-emitting element LD, it is only necessary not to pass a current through the input terminal of the light-emitting element LD. Therefore, for example, the potential applied to the wiring AL may be lowered in accordance with that timing. In this case, since it is necessary to separately provide a driver circuit for controlling the wiring AL, the cost at the time of manufacturing the display device may increase. On the other hand, in the case of the pixel PIX shown in FIG. 4(B2), by applying a low-level potential to the wiring GL2 to turn off the transistor Tr5, the supply of current to the light-emitting element LD may be stopped. Also, by using the transistor Tr5 as the above-described OS transistor, it is possible to prevent the light-emitting element LD from emitting light due to the off-current.

[0104] Also, in the pixel PIX shown in FIG. 4(B2), the transistor Tr5 can correspond to the circuit elements included in the drive circuit unit 102 of the pixel PIX shown in FIG. 2(B).

[0105] <Circuit configuration example of correction data holding unit> Next, a circuit configuration example applicable to the correction data holding unit 104 shown in FIGS. 1 to 3 will be described.

[0106] The correction data holding unit 104 shown in FIG. 5(A) is a circuit configuration example in which transistors SWT1 to SWT3 are respectively applied as the switches SW1 to SW3 of the correction data holding unit 104 shown in FIG. 3. In FIG. 5(A), the correction data holding unit ​​​​​​​​​​​​To show the connection relationship with 104, a display unit PA and a source driver circuit SD are illustrated. are shown.

[0107] The first terminal of transistor SWT1 is electrically connected to the first terminal of capacitor element Cd and to wiring SL (wiring DL ), and the second terminal of transistor SWT1 is electrically connected to the first terminal of transistor SWT2 and to the source driver circuit SD. The gate of transistor SWT1 is electrically connected to wiring CRL1. The gate of transistor SWT2 is electrically connected to wiring CRL2. The first terminal of transistor SWT3 is electrically connected to the second terminal of capacitor element Cd and to the second terminal of transistor SWT2, and the second terminal of transistor SWT3 is electrically connected to wiring VG. The gate of transistor SWT3 is electrically connected to wiring CRL1.

[0108] Similar to FIG. 3, in FIG. 5, the electrical connection point of the second terminal of transistor SWT2, the second terminal of capacitor element Cd, and the first terminal of transistor SWT3 is defined as node ND3. is shown.

[0109] Wiring CRL1 and wiring CRL2 are for switching the on and off states of transistors SWT1 to SWT3. In particular, since the gates of transistor SWT1 and transistor SWT3 are each electrically connected to wiring CRL1, by applying a high-level potential or a low-level potential to wiring CRL1, the on and off states of transistor SWT1 and transistor SWT3 can be switched simultaneously. Note that the on states of transistor SWT1 and transistor SWT3 respectively. can be switched simultaneously. In addition, the on states of transistor SWT1 and transistor SWT3 respectively. , switching to the off state does not need to be done simultaneously, and the on and off states of transistor SWT1 and transistor SWT3 may be switched independently. In that case, the compensation data holding unit 104 may be configured such that the gates of transistor SWT1 and transistor SWT3 are electrically connected to different wirings.

[0110] At least one of transistors SWT1 to SWT3 is preferably an OS transistor. Since the OS transistor has the characteristic that the off-current is very low, for example, by applying the OS transistor as transistor SWT2 and / or transistor SWT3, the data held at node ND3 due to the off-current can be prevented from being destroyed. Also, by using all of transistors SWT1 to SWT3 as OS transistors, the respective transistors can be formed simultaneously, so the manufacturing process of the display unit PA may be shortened in some cases.

[0111] Also, at least one of transistors SWT1 to SWT3 shown in FIG. 5(A) may be a transistor having a back gate. FIG. 5(B) shows that all of transistors SWT1 to SWT3 are transistors having a back gate, and for each transistor, the gate and the back gate are electrically connected. Since a transistor in which the gate and the back gate are electrically connected can increase the on-current flowing through the transistor, by adopting the configuration of pixel PIX shown in FIG. 5(B), the pixel PIX can operate faster. Note that the pixel PIX shown in FIG. 5(B) In each of transistors SWT1 to SWT3, the gate is connected to the back gate. However, a potential may be applied to the back gate of each transistor by a separate wiring.

[0112] Also, at least one of transistors SWT1 to SWT3 may be a Si transistor. Also, among transistors SWT1 to SWT3, some transistors may be Si transistors and the remaining transistors may be OS transistors.

[0113] Also, FIGS. 5(A) and 5(B) show circuit configuration examples in which transistors SWT1 to SWT3 are applied as switches SW1 to SW3 of the correction data holding unit 104 shown in FIG. 3. However, switches SW1 to SW3 of the correction data holding unit 104 shown in FIG. 3 may be switches configured by a CMOS (Complementary MOS) circuit, for example, analog switches.

[0114] Furthermore, when the correction data holding unit 104 and the pixel PIX are formed on the same substrate, the channel formation regions of transistors SWT1 to SWT3 and the transistors included in the pixel PIX are preferably

[0115] formed of the same material. Also, when the channel formation regions of the respective transistors included in the correction data holding unit 104 and the source driver circuit The channel formation regions of the respective transistors included in the data holding unit 104 and the source driver circuit SD are formed of different materials. When this is the case, it is preferable to form the source driver circuit SD on a semiconductor substrate and form the correction data holding unit 104 above the source driver circuit SD in a stacked structure. In this case, the transistors SWT1 to SWT3 of the correction data holding unit 104 can be configured as OS transistors, and the source driver circuit SD can be configured with Si transistors. Further, the correction data holding unit 104 and the source driver circuit SD may be configured such that a substrate on which the correction data holding unit 104 is formed is mounted on the semiconductor substrate on which the source driver circuit SD is formed. Further, the correction data holding unit 104 may be included inside the source driver circuit SD. When forming the channel formation regions of the respective transistors included in the data holding unit 104 and the source driver circuit SD with different materials, the source driver circuit SD is formed on a semiconductor substrate, and it is preferable to form the correction data holding unit 104 above the source driver circuit SD in a stacked structure. In this case, the transistors SWT1 to SWT3 of the correction data holding unit 104 are configured as OS transistors, and the source driver circuit SD can be configured with Si transistors. Further, the correction data holding unit 104 and the source driver circuit SD may be configured such that a substrate on which the correction data holding unit 104 is formed is mounted on the semiconductor substrate on which the source driver circuit SD is formed. Further, the correction data holding unit 104 may be included inside the source driver circuit SD. Note that examples of the substrate on which the pixel PIX, the correction data holding unit 104, the source driver circuit SD, etc. are formed include insulator substrates such as glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Further, examples of the substrate include semiconductor substrates such as silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, examples of the substrate include SOI (Silicon On Insulator) substrates in which an insulating region is included in a semiconductor substrate.

[0116] Note that examples of the substrate on which the pixel PIX, the correction data holding unit 104, the source driver circuit SD, etc. are formed include insulator substrates such as glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Further, examples of the substrate include semiconductor substrates such as silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, examples of the substrate include SOI (Silicon On Insulator) substrates in which an insulating region is included in a semiconductor substrate. Further, examples of the substrate include conductor substrates such as graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Further, examples of the substrate include semiconductor substrates such as silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, examples of the substrate include SOI (Silicon On Insulator) substrates in which an insulating region is included in a semiconductor substrate. Further, examples of the substrate include conductor substrates such as graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. <<Operation Example>> Further, examples of the substrate include conductor substrates such as graphite substrates, metal substrates, alloy substrates, and conductive resin substrates.

[0117] <<Operation Example>> Next, an operation example of the display device of one embodiment of the present invention will be described. The display device is the display device DD3 shown in FIG. In this case, the pixel PIX is the pixel PIX shown in FIG. 4(A1), and the wiring SL is the wiring SL shown in FIG. SL, and the correction data storage unit 104 is the correction data storage unit 104 shown in FIG. In FIG. 6, the capacitance element Cpa is a capacitance of the wiring SL shown in FIG. The raw capacitance of the pixel PIX is the sum of the capacitance elements Cp, which are electrically connected to the wiring SL. When the number of wirings is N, Cpa=N×Cp. The resistor element Rp showing the wiring resistance of the source driver circuit S shown in FIG. In D, only the amplifier circuit AMP is shown, and the The circuits and elements that are not shown are omitted.

[0118] FIG. 7 is a timing chart showing an example of the operation of the display device DD3. The timing chart shows the wiring GL, wiring VCOM, wire CRL1, wire CRL2, wire VG, wire DL, amplifier circuit output voltage ( In FIG. 7, this is indicated as AMP_out. The potentials of the node ND1 and the node ND3 In addition, "high" in Figure 7 indicates a high-level potential, and "low" indicates a low-level potential. indicates the low-level potential. Also, V in Figure 7 GND refers to the reference potential.

[0119] In addition, the wiring VCOM and the wiring VG are connected at times T1 to T6 and around those times. And always V GND is applied.

[0120] In this operation example, the transistor Tr1 and the transistors SWT1 to SWT3 are, unless otherwise specified, in the on state and finally operate in the linear region including the case of operation. That is, the gate voltage, source voltage, and drain voltage of the transistor Tr1 and the transistors SWT1 to SWT3 are assumed to include the case where they are appropriately biased to voltages within the operating range in the linear region. When applying the pixel PIX described in FIGS. 4(B1) and 4(B2) as the pixel PIX of the display device DD1, it is preferable to operate the transistors Tr2 and Tr4 in the linear region and the transistor Tr3 in the saturation region. Before time T1 Before time T1, a low-level potential is applied to the wiring GL. When the potential of the wiring GL is at a low level, a low-level potential is applied to the gate of the transistor Tr1, so that the transistor Tr1 is turned off. That is, the wiring DL and the node ND1 are in a non-conductive state. Also, a low-level potential is applied to the wiring CRL1. When the potential of the wiring CRL1 is at a low level, a low-level potential is applied to the gates of the transistors SWT1 and SWT3 respectively, so that the transistors SWT1 and SWT3 are each turned off. That is, the source driver circuit SD and the display unit PA are in a non-conductive state, and the node ND3 and the wiring VG are also in a non-conductive state. By the way, a certain amount or more of voltage is applied between the first terminal (node ND1) and the second terminal of the liquid crystal element LC.

[0121] [Before time T1] Before time T1, a low-level potential is applied to the wiring GL. When the potential of the wiring GL is at a low level, a low-level potential is applied to the gate of the transistor Tr1, so that the transistor Tr1 is turned off. That is, the wiring DL and the node ND1 are in a non-conductive state. Also, a low-level potential is applied to the wiring CRL1. When the potential of the wiring CRL1 is at a low level, a low-level potential is applied to the gates of the transistors SWT1 and SWT3 respectively, so that the transistors SWT1 and SWT3 are each turned off. That is, the source driver circuit SD and the display unit PA are in a non-conductive state, and the node ND3 and the wiring VG are also in a non-conductive state. are in a non-conductive state.

[0122] Also, a low-level potential is applied to the wiring CRL1. When the potential of the wiring CRL1 is at a low level, a low-level potential is applied to the gates of the transistors SWT1 and SWT3 respectively, so that the transistors SWT1 and SWT3 are each turned off. That is, the source driver circuit SD and the display unit PA are in a non-conductive state, and the node ND3 and the wiring VG are also in a non-conductive state. are each turned off. That is, the source driver circuit SD and the display unit PA are in a non-conductive state, and the node ND3 and the wiring VG are also in a non-conductive state. are each turned off. That is, the source driver circuit SD and the display unit PA are in a non-conductive state, and the node ND3 and the wiring VG are also in a non-conductive state. are in a non-conductive state, and the node ND3 and the wiring VG are also in a non-conductive state.

[0123] By the way, a certain amount or more of voltage is applied between the first terminal (node ND1) and the second terminal of the liquid crystal element LC.​ When a potential difference occurs, the liquid crystal molecules contained in the liquid crystal element LC are aligned according to the potential difference. The aligned liquid crystal molecules pass through the light from the backlight unit included in the display device DD1, so that the light is emitted from the pixel PIX. The intensity of the light depends on the voltage applied between the first terminal (node ND1) and the second terminal of the liquid crystal element LC, that is, the potential of node ND1. Therefore, gradation display can be performed by adjusting the potential. Before the time T1 in the timing chart shown in FIG. 7, it is assumed that a potential difference occurs between the first terminal (node ND1) and the second terminal of the liquid crystal element LC such that no light is emitted from the pixel PIX. Such a potential is denoted as V In the timing chart shown in FIG. 7, the potential of node ND1 is described as V Note that V may be a potential lower than V or V. In this operation example, V is described as a potential greater than V and such that no light is emitted from the pixel PIX, and will be explained. Ini1 That is, in the timing chart shown in FIG. 7, the potential of node ND1 is V Note that V may be a potential lower than V or V. In this operation example, V Ini1 is described as a potential greater than V and such that no light is emitted from the pixel PIX, and will be explained. I ni1 is, or may be a potential lower than V or V. In this operation example, V GND is, or may be a potential lower than V or V. In this operation example, V GND is described as a potential greater than V and such that no light is emitted from the pixel PIX, and will be explained. I ni1 is described as a potential greater than V and such that no light is emitted from the pixel PIX, and will be explained. GND is described as a potential greater than V and such that no light is emitted from the pixel PIX, and will be explained. will be explained.

[0124] Before time T1, the potential of the wiring CRL2 changes from a high-level potential to a low-level potential. When the potential of the wiring CRL2 is at a high-level potential, a high-level potential is applied to the gate of the transistor SWT2, so that the transistor SWT2 is turned on. That is, a conductive state is established between the source driver circuit SD and the node ND3. At this time, the potential output from the output terminal of the amplifier circuit AMP of the source driver circuit SD is applied to the node ND3. a high-level potential is applied to the gate of the transistor SWT2, so that the transistor SWT2 is turned on. That is, a conductive state is established between the source driver circuit SD and the node ND3. At this time, the potential output from the output terminal of the amplifier circuit AMP of the source driver circuit SD is applied to the node ND3. a conductive state is established between the source driver circuit SD and the node ND3. At this time, the potential output from the output terminal of the amplifier circuit AMP of the source driver circuit SD is applied to the node ND3. It is printed. Also, when the potential of the wiring CRL2 becomes a low-level potential, the transistor SW T2 is turned off, so the source driver circuit SD and the node ND3 are non-conductive in a state.

[0125] Also, to simply explain this operation example, before time T1, the potential of the node ND3 is set to V Ini2 . Note that V Ini2 is a potential lower than V GND or V GND , but in this operation example, V is set to a potential higher than V Ini2 and V GND .

[0126] Before time T1, the wiring DL is assumed to have an appropriate potential. In FIG. 7 , the potential of the wiring DL is shown as a potential higher than V GND .

[0127] [Time T1] At time T1, a high-level potential is applied to the wiring GL. Therefore, between time T1 and time T2, a high-level potential is applied to the gate of the transistor Tr1 , so the transistor Tr1 is turned on. As a result, the wiring DL and the source driver circuit SD are in a conductive state.

[0128] Also, at time T1, a high-level potential is applied to the wiring CRL1. Therefore, between time T1 and time T2, a high-level potential is applied to the gates of the transistor SWT1 and the transistor SWT3 , so the transistor SWT1 and the transistor SWT3 are turned on. The node ND3 and the wiring VG are in a conductive state .

[0129] Here, at time T1, let a potential V be output as an analog signal from the output terminal of the amplifier circuit da ta1 . Let V data1 be the potential that can be output by the digital - to - analog conversion circuit DAC of the source driver circuit SD. At this time, since the transistor SWT1 is in the on state, the potential of the wiring DL is V . Also, since the transistor Tr1 is in the on state, the potential of the node ND1 of the pixel PIX is also V data1 . . dat a1

[0130] On the other hand, since the transistor SWT3 is in the on state, the potential of the node ND3 is V GND . Also, since the transistor SWT2 is in the off state, the potential V output from the output terminal of the amplifier circuit AMP is not applied to the node ND3 data1 .

[0131] At this time, the voltage between the first terminal and the second terminal of the capacitive element Cd is V data1 .

[0132] [Time T2] At time T2, a low - level potential is applied to the wiring CRL1. Therefore, between time T2 and time T3, a low - level potential is applied to the gates of the transistor SWT1 and the transistor SWT3 respectively, so that the transistor SWT1 and the transistor SWT 3 are each in the off state .

[0133] When the transistor SWT1 is in the off state, the wiring DL, the source driver circuit SD, and ​​The interval therebetween becomes a non-conductive state. Therefore, the wiring DL and the node ND1 become electrically floating states. Also, when the transistor SWT3 becomes an OFF state, the interval between the node ND3 and the wiring VG also becomes a non-conductive state, so that the node ND3 also becomes an electrically floating state.

[0134] Furthermore, between time T2 and time T3, it is assumed that a potential V is output as an analog signal from the output terminal of the amplifier circuit AMP. data2 data2 data Similar to V1, V is a potential that can be output by the digital-analog conversion circuit DAC included in the source driver circuit SD.

[0135] [Time T3] At time T3, a high-level potential is applied to the wiring CRL2. Therefore, between time T3 and time T4, a high-level potential is applied to the gate of the transistor SWT2, so that the transistor SWT2 becomes an ON state.

[0136] At this time, since the transistor SWT2 is in an ON state, the potential V output from the output terminal of the amplifier circuit AMP is applied to the node ND3. Also, since the transistor SWT3 is in an OFF state, no current flows from the source driver circuit SD to the wiring VG, and the potential of the node ND3 increases from V to V. data2 GND data2

[0137] Also, since the wiring DL and the node ND1 are in an electrically floating state, the potentials of the wiring DL and the node ND1 also change due to the capacitive coupling of the capacitor element Cd as the potential of the node ND3 changes. In the timing chart of FIG. 7, the wiring DL and the node ND1 ​​​​​​​​​​​​​​​ Let the amount of change in each potential be ΔV g as described, but let the value of the capacitance of the capacitor element Cd be C A and let the capacitor element Cpa that is the parasitic capacitance of the wiring SL and the capacitor element C1 of the pixel PIX When the combined capacitance value is C B ΔV g can be estimated by the following equation (E1). can be estimated by the following equation (E1).

[0138]

Equation

[0139] Therefore, when the potential of the node ND1 is V ND1 V ND1 is represented by the following equation (E2). is represented by the following equation (E2).

[0140]

Equation

[0141] Note that for equations (E1) and (E2), the parasitic capacitance generated between the first terminal and the second terminal of the liquid crystal element LC is ignored. However, since the first terminal of the liquid crystal element LC and the first terminal of the capacitor element C1 are electrically connected to each other, and each of the second terminal of the liquid crystal element LC and the second terminal of the capacitor element C1 is electrically connected to the wiring VCOM, the two can be regarded as being electrically connected in parallel. Therefore, the capacitance value C in equations (E1) and (E2) can be treated as a value considering the parasitic capacitance of the liquid crystal element. The first terminals of the liquid crystal element LC and the capacitor element C1 are electrically connected to each other, and each of the second terminals of the liquid crystal element LC and the capacitor element C1 is electrically connected to the wiring VCOM, so the two can be regarded as being electrically connected in parallel. Therefore, the capacitance value C in equations (E1) and (E2) B is the liquid can be treated as a value considering the parasitic capacitance of the crystal element.

[0142] [Time T4] At time T4, a low-level potential is applied to the wiring GL. Therefore, from time T4 Before time T5, a low-level potential is applied to the gate of transistor Tr1. Therefore, transistor Tr1 is turned off.

[0143] When transistor Tr1 is turned off, the wiring DL and the node ND1 become non-conductive. As a result, the potential V of node ND1 ND1 is held by the capacitor element C1. Thereby.

[0144] [Time T5] At time T5, a low-level potential is applied to the wiring CRL2. Therefore, between time T5 and time T6, a low-level potential is applied to the gate of transistor SWT2, so transistor SWT2 is turned off.

[0145] When transistor SWT2 is turned off, the source driver circuit SD and the node ND3 become non-conductive. Also, since transistor SWT3 is turned off, node ND3 is electrically floating. Therefore, the potential of node ND3 is held by the capacitor element Cd.

[0146] [Time T6] At time T6, a high-level potential is applied to the wiring CRL1. Therefore, after time T6 a high-level potential is applied to the gates of transistor SWT1 and transistor SWT3, respectively. As a result, transistor SWT1 and transistor SWT3 are turned on, respectively. Thereby.

[0147] Also, at time T6, it is assumed that a potential V is output as an analog signal from the output terminal of the amplifier circuit AMP. AN Let V be AN V is data1and V data2 Similarly, the potential that can be output by the digital - analog conversion circuit DAC included in the source driver circuit SD is assumed. Since the transistor SWT1 is in the on - state, the potential from the output terminal of the amplifier circuit AMP is applied to the wiring DL. As a result, the potential of the wiring DL becomes V.

[0148] Since the transistor SWT1 is in the on - state, the potential from the output terminal of the amplifier circuit AMP is applied to the wiring DL. This causes the potential of the wiring DL to be V. AN becomes.

[0149] Also, since the transistor SWT3 is in the on - state, the potential V from the wiring VG is applied to the node ND3. from the wiring VG is applied to the node ND3. GND is applied.

[0150] Here, focus on the liquid crystal element LC after time T4. Between the first terminal and the second terminal of the liquid crystal element LC, a voltage of V = V ND1 = V data1 + ΔV g is applied. Therefore, after time T4, the liquid crystal molecules included in the liquid crystal element LC are oriented according to the potential V ND1 and light is emitted from the pixel PIX. and light is emitted from the pixel PIX.

[0151] Note that the luminance of the light emitted from the pixel PIX is determined by the voltage applied between the first terminal - second terminal of the liquid crystal element LC. is determined by the voltage applied between the first terminal - second terminal of the liquid crystal element LC.

[0152] As described above, for the display device DD3 shown in FIG. 6, by performing the operations at times T1 to T6 and times in the vicinity thereof in the timing chart of FIG. 7, a potential with a resolution higher than that of the digital - analog conversion circuit DAC can be given to the image data holding part (node ND1 ) of the pixel PIX. ) of the pixel PIX. ) of the pixel PIX.

[0153] <<Specific Example>> Here, according to the above - described operation example, the image output from the digital - analog conversion circuit DAC An example of displaying image data with more gradations than image data on a display unit PA of a display device DD3 will be described. will be described.

[0154] In this example, as a digital-to-analog conversion circuit DAC of a source driver circuit SD, a 6-bit digital-to-analog conversion circuit is provided, and the capacitance value C of the capacitance element Cd included in the correction data holding unit 104 is provided, and the capacitance value C of the capacitance element Cd included in the correction data holding unit 104 and the combined capacitance value C of the capacitance element Cpa as the parasitic capacitance of the wiring SL and the capacitance element C1 of the pixel PIX A and the combined capacitance value C of the capacitance element Cpa as the parasitic capacitance of the wiring SL and the capacitance element C1 of the pixel PIX and the combined capacitance value C of the capacitance element Cpa as the parasitic capacitance of the wiring SL and the capacitance element C1 of the pixel PIX B and the ratio of the combined capacitance value C of the capacitance element Cpa as the parasitic capacitance of the wiring SL and the capacitance element C1 of the pixel PIX A :C B = 1:63 shall be assumed.

[0155] By using a 6-bit digital-to-analog conversion circuit DAC as the digital-to-analog conversion circuit DAC, the voltage V written to the wiring DL and the node ND1 can take values from "000000" to "111111" in binary notation. Here data1 , if the voltage value of "111111" is 6.3V, the voltage value that the digital-to-analog conversion circuit DAC can output can take values from 0V to 6.3V in 0.1V increments. , if the voltage value of "111111" is 6.3V, the voltage value that the digital-to-analog conversion circuit DAC can output V data1 is in the range from 0V to 6.3V in 0.1V increments. range.

[0156] Therefore, in the above operation example, during the period from time T1 to time T2, the wiring D L and the node ND1 can be written with V data1 in the range from 0V to 6.3V. can be written.

[0157] The capacitance value C of the capacitance element Cd A and the combined capacitance value C of the capacitance element Cpa as the parasitic capacitance of the wiring SL and the capacitance element C1 of the pixel PIX and the combined capacitance value C of the capacitance element Cpa as the parasitic capacitance of the wiring SL and the capacitance element C1 of the pixel PIX BThe ratio of to is C A :C B =1: 63, so Equation (E1) becomes the following Equation (E3).

[0158]

Equation

[0159] Here, the digital-to-analog conversion circuit that outputs V data2 , for example, when using the same digital-to-analog conversion circuit DAC that outputs V data1 , V data2 is V data1 can take values from "000000" to "111111" in binary notation, similar to . At this time, the possible voltage values of V data2 are also in 0.1V increments, ranging from 0V to 6.3V. That is, from Equation (E3), ΔV g is in 0.1 / 64V (= 0.0015625V) increments and can take values from 0V to 6.3 / 64V (=0.0984375V) .

[0160] Therefore, in the above operation example, between time T3 and time T4, the potential of the node ND1 of the pixel P IX can take values from 0V to 6.3 + 6.3 / 64V (=6.3984375V) in 0.1 / 64V (=0.00 15625V) increments according to Equations (E2) and (E3). .

[0161] That is, in the display devices DD1 to DD3 of one aspect of the present invention, by performing the above operation example , finer voltage values that cannot be output by a 6-bit digital-to-analog conversion circuit DAC can be applied to the node ND1 of the pixel PIX. In the above specific example, the de ​The digital-to-analog conversion circuit DAC outputs a potential in 0.1 V increments, but the node ND1 of the pixel PIX can write a potential in 0.1 / 64 V (= 0.0015625 V) increments. That is, a potential (image data) with a higher resolution than that of a 6-bit digital-to-analog conversion circuit DAC can be written to the pixel PIX. In other words, a potential (image data) with a higher resolution than that of a 6-bit digital-to-analog conversion circuit DAC can be written to the pixel PIX. In the above specific example, V given by the 6-bit digital-to-analog conversion circuit DAC corresponds to the upper 6 bits of the image data, and ΔV applied to the node ND1 by capacitive coupling by the capacitive element Cd of the correction data holding unit 104 corresponds to the lower 6 bits of the image data.

[0162] That is, by using the display devices DD1 to DD3 according to one aspect of the present invention, the lower 6-bit image data can be interpolated into the upper 6-bit image data given by the digital-to-analog conversion circuit DAC, and 12-bit equivalent image data can be displayed on the display unit PA. data1 In the above specific example, V given by the 6-bit digital-to-analog conversion circuit DAC corresponds to the upper 6 bits of the image data, and ΔV applied to the node ND1 by capacitive coupling by the capacitive element Cd of the correction data holding unit 104 corresponds to the lower 6 bits of the image data. In the above specific example, V given by the 6-bit digital-to-analog conversion circuit DAC corresponds to the upper 6 bits of the image data, and ΔV applied to the node ND1 by capacitive coupling by the capacitive element Cd of the correction data holding unit 104 corresponds to the lower 6 bits of the image data. g That is, by using the display devices DD1 to DD3 according to one aspect of the present invention, the lower 6-bit image data can be interpolated into the upper 6-bit image data given by the digital-to-analog conversion circuit DAC, and 12-bit equivalent image data can be displayed on the display unit PA. That is, by using the display devices DD1 to DD3 according to one aspect of the present invention, the lower 6-bit image data can be interpolated into the upper 6-bit image data given by the digital-to-analog conversion circuit DAC, and 12-bit equivalent image data can be displayed on the display unit PA. That is, by using the display devices DD1 to DD3 according to one aspect of the present invention, the lower 6-bit image data can be interpolated into the upper 6-bit image data given by the digital-to-analog conversion circuit DAC, and 12-bit equivalent image data can be displayed on the display unit PA. That is, by using the display devices DD1 to DD3 according to one aspect of the present invention, the lower 6-bit image data can be interpolated into the upper 6-bit image data given by the digital-to-analog conversion circuit DAC, and 12-bit equivalent image data can be displayed on the display unit PA. That is, by using the display devices DD1 to DD3 according to one aspect of the present invention, the lower 6-bit image data can be interpolated into the upper 6-bit image data given by the digital-to-analog conversion circuit DAC, and 12-bit equivalent image data can be displayed on the display unit PA.

[0163] Also, in the above operation example, a potential higher than V is applied to the node ND3 of the correction data holding unit 104 between time T3 and time T4, but a potential lower than V may be applied as the correction data. That is, ΔV applied to the node ND1 by capacitive coupling by the capacitive element Cd of the correction data holding unit 104 may be a negative potential. Also, in the above operation example, a potential higher than V is applied to the node ND3 of the correction data holding unit 104 between time T3 and time T4, but a potential lower than V may be applied as the correction data. That is, ΔV applied to the node ND1 by capacitive coupling by the capacitive element Cd of the correction data holding unit 104 may be a negative potential. GND Also, in the above operation example, a potential higher than V is applied to the node ND3 of the correction data holding unit 104 between time T3 and time T4, but a potential lower than V may be applied as the correction data. That is, ΔV applied to the node ND1 by capacitive coupling by the capacitive element Cd of the correction data holding unit 104 may be a negative potential. Also, in the above operation example, a potential higher than V is applied to the node ND3 of the correction data holding unit 104 between time T3 and time T4, but a potential lower than V may be applied as the correction data. That is, ΔV applied to the node ND1 by capacitive coupling by the capacitive element Cd of the correction data holding unit 104 may be a negative potential. GND Also, in the above operation example, a potential higher than V is applied to the node ND3 of the correction data holding unit 104 between time T3 and time T4, but a potential lower than V may be applied as the correction data. That is, ΔV applied to the node ND1 by capacitive coupling by the capacitive element Cd of the correction data holding unit 104 may be a negative potential. Also, in the above operation example, a potential higher than V is applied to the node ND3 of the correction data holding unit 104 between time T3 and time T4, but a potential lower than V may be applied as the correction data. That is, ΔV applied to the node ND1 by capacitive coupling by the capacitive element Cd of the correction data holding unit 104 may be a negative potential. g Also, in the above operation example, a potential higher than V is applied to the node ND3 of the correction data holding unit 104 between time T3 and time T4, but a potential lower than V may be applied as the correction data. That is, ΔV applied to the node ND1 by capacitive coupling by the capacitive element Cd of the correction data holding unit 104 may be a negative potential. Also, in the above operation example, a potential higher than V is applied to the node ND3 of the correction data holding unit 104 between time T3 and time T4, but a potential lower than V may be applied as the correction data. That is, ΔV applied to the node ND1 by capacitive coupling by the capacitive element Cd of the correction data holding unit 104 may be a negative potential.

[0164] Note that the configuration of the display device according to one aspect of the present invention is not limited to the configurations illustrated in FIGS. 1 to 3 and FIG. 6. One aspect of the present invention can be, for example, according to circumstances such as design specifications and purposes. Note that the configuration of the display device according to one aspect of the present invention is not limited to the configurations illustrated in FIGS. 1 to 3 and FIG. 6. One aspect of the present invention can be, for example, according to circumstances such as design specifications and purposes. The components of the display device may be modified as appropriate.

[0165] Moreover, one of the configuration examples described in this embodiment can be combined with another configuration example. For example, in the same pixel PIX as in FIG. 4(A2) where a back gate is provided on the transistor Tr1, Similarly, the pixel PIX shown in FIG. 4B1 and FIG. 4B2 includes transistors Tr2 to Tr4 may be provided with a back gate (not shown).

[0166] The operation method of the display device of one embodiment of the present invention is not limited to the above-described operation examples or specific examples. The operation method may be, for example, the order in which potentials are applied to elements, circuits, wiring, etc., or the potentials The value of can be appropriately changed. Since the above can be appropriately changed, the operation method of the display device may be changed according to the configuration. good.

[0167] This embodiment mode may be combined as appropriate with other embodiment modes or examples shown in this specification. It is possible.

[0168] (Embodiment 2) In this embodiment, a configuration example of a display device using a liquid crystal element will be described. In this embodiment, the signal output from the source driver circuit SD described in the first embodiment is A description of the operation and function of adding lower-bit image data to image data will be omitted.

[0169] The display device shown in FIG. 8A includes a first substrate 4001 and a second substrate 4006. In the display device, a display portion 215 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided on the second substrate 215. The display unit 215 is formed on the second substrate 215 by the sealant 4005. It is sealed by the plate 4006.

[0170] The display unit 215 is provided with a pixel array having the pixels PIX shown in the first embodiment. .

[0171] In FIG. 8(A), the scanning line driving circuit 221a, the signal line driving circuit 231a, the signal line driving circuit 232a, and the common line driving circuit 241a each have a plurality of integrated circuits 4042 provided on the printed circuit board 4041. The integrated circuit 4042 is formed of single-crystalline semiconductor or polycrystalline semiconductor. The signal line driving circuit 231a and the signal line driving circuit 232a have the functions of the source driver circuit SD shown in the first embodiment. The scanning line driving circuit 221a has the functions of the gate driver circuit GD shown in the first embodiment. The common line driving circuit 241 a has the function of supplying a prescribed potential to the wiring VCOM shown in the first embodiment. , has the functions of the gate driver circuit GD shown in the first embodiment. The common line driving circuit 241 a has the function of supplying a prescribed potential to the wiring VCOM shown in the first embodiment.

[0172] The various signals and potentials supplied to the scanning line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and the signal line driving circuit 232a are supplied via an FPC (FPC: Flexible ible printed circuit) 4018.

[0173] The integrated circuits 4042 included in the scanning line driving circuit 221a and the common line driving circuit 241a have the function of supplying a selection signal to the display unit 215. The integrated circuits 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a have the function of supplying an image signal to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. have the function of supplying an image signal to the display unit 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. It is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.

[0174] Note that the connection method of the integrated circuit 4042 is not particularly limited, and wire bonding method, COG (Chip On Glass) method, TCP (Tape Carrier Package) method, COF (Chip On Film) method, etc. can be used.

[0175] FIG. 8(B) shows an example in which the integrated circuit 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a is implemented by the COG method. Also, part or all of the driving circuit can be integrally formed on the same substrate 4001 as the display unit 215 to form a system on panel.

[0176] In FIG. 8(B), an example is shown in which the scanning line driving circuit 221a and the common line driving circuit 241a are formed on the same substrate as the display unit 2 15. By forming the driving circuit at the same time as the pixel circuit in the display unit 215, the number of components can be reduced. Therefore, productivity can be improved.

[0177] Also, in FIG. 8(B), a sealing material 4005 is provided so as to surround the display unit 215 provided on the first substrate 4001, the scanning line driving circuit 221a, and the common line driving circuit 241a. Also, a second substrate 4006 is provided on the display unit 215, the scanning line driving circuit 221a, and the common line driving circuit 241a. Therefore, the display unit 215, the scanning line driving circuit 221a, and the common line driving circuit 241a are sealed together with the display element by the first substrate 4001, the sealing material 40 05, and the second substrate 4006.

[0178] Also, in FIG. 8(B), the signal line driving circuit 231a and the signal line driving circuit 232a are separately ​​​​​​​Although an example of forming and mounting on the first substrate 4001 is shown, the configuration is not limited to this. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line

[0179] driving circuit may be separately formed and mounted. Further, the display device may include a panel in a state where the display elements are sealed, and a module in a state where an IC or the like including a controller

[0180] is mounted on the panel. Further, the display unit and the scanning line driving circuit provided on the first substrate have a plurality of transistors An OS transistor or an Si transistor can be applied as the transistor.

[0181] The structure of the transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit may be the same or different. The transistors included in the peripheral driving circuit may all have the same structure, or two or more types of structures may be used in combination. Similarly, the transistors included in the pixel circuit may all have the same structure, or two or more types of structures may be used in combination.

[0182] Further, an input device 4200 (not shown. The input device 42 00 will be described later.) can be provided on the second substrate 4006. The configuration in which the input device 42 00 is provided in the display device shown in FIG. 8 can function as a touch panel.

[0183] There is no limitation to the detection element (also referred to as a sensor element) included in the touch panel according to one aspect of the present invention Various sensors capable of detecting the proximity or contact of a detected object such as a finger or a stylus It can be applied as a detection element.

[0184] As the sensor method, for example, various methods such as a capacitance method, a resistive film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure-sensitive method can be used.

[0185] In this embodiment, a touch panel having a capacitance-type detection element will be described as an example. will be described.

[0186] As the capacitance method, there are a surface capacitance method, a projected capacitance method, etc. Also, as the projected capacitance method, there are a self-capacitance method, a mutual-capacitance method, etc. Using the mutual-capacitance method is preferable because simultaneous multi-point detection becomes possible.

[0187] The touch panel according to one aspect of the present invention can adopt various configurations, such as a configuration in which a separately manufactured display device and a detection element are bonded together, or a configuration in which electrodes and the like constituting the detection element are provided on one or both of the substrate supporting the display element and the counter substrate.

[0188] Examples of the touch panel are shown in FIGS. 9(A) and (B). FIG. 9(A) is a perspective view of the touch panel 42 10. FIG. 9(B) is a perspective schematic view of the input device 4200. For clarity, only typical components are shown.

[0189] For clarity, only typical components are shown. The touch panel 4210 has a configuration in which a separately manufactured display device and a detection element are bonded together.

[0190] is a configuration in which a separately manufactured display device and a detection element are bonded together. The touch panel 4210 has an input device 4200 and a display device, and these are provided so as to overlap each other.

[0191] are provided so as to overlap each other. ​​The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, and a plurality of wirings 423. 7, a plurality of wirings 4238 and a plurality of wirings 4239. For example, the electrode 4227 has wiring The electrode 4228 can be electrically connected to the line 4237 or the wiring 4239. The FPC 4272b can be electrically connected to the wiring 4239. 7 and each of the plurality of wirings 4238. 73b may be provided.

[0192] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. A touch sensor may be provided between the first substrate 4001 and the second substrate 4006. In addition to capacitive touch sensors, optical touch sensors using photoelectric conversion elements are also used. may be applied.

[0193] FIG. 10 is a cross-sectional view of the portion indicated by the chain line N1-N2 in FIG. 8(B). The display device has an electrode 4015, and the electrode 4015 is connected to a terminal of an FPC 4018. The electrodes 40 are electrically connected via an anisotropic conductive layer 4019. 15 is inserted into an opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110. The wiring 4014 is electrically connected thereto.

[0194] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 They are formed from the same conductive layer.

[0195] The display unit 215 and the scanning line driver circuit 221a provided on the first substrate 4001 are It has a plurality of transistors. In FIG. 10, transistors 40 included in the display unit 215 10 and transistors 4011 included in the scanning line driving circuit 221a are illustrated. In FIG. 10, bottom gate type transistors are illustrated as transistors 4010 and 4011, but top gate type transistors may also be used. Also, transistor 4011 may be included in the gate driver circuit GD described in Embodiment 1.

[0196] In FIG. 10, an insulating layer 4112 is provided on transistors 4010 and 4011.

[0197] Also, transistors 4010 and 4011 are provided on an insulating layer 4102. Also, transistors 4010 and 4011 have an electrode 4017 formed on an insulating layer 411. 1. Electrode 4017 can function as a back gate electrode.

[0198] Also, the display device shown in FIG. 10 has a capacitor element 4020. Capacitor element 4020 has an electrode 4021 formed in the same process as the gate electrode of transistor 4010 and an electrode formed in the same process as the source electrode and the drain electrode. Each electrode overlaps via an insulating layer 4103. Note that capacitor element 4020 can be, for example, capacitor C1 of pixel PIX described in Embodiment 1. 4103. Note that capacitor element 4020 can be, for example, capacitor C1 of pixel PIX described in Embodiment 1.

[0199] Generally, the capacitance of the capacitor element provided in the pixel portion of the display device is set so that charge can be held for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion. ​ It suffices to set the capacitance of the capacitive element in consideration of the off-current of the transistor or the like.

[0200] FIG. 10 shows an example of a liquid crystal display device using a transmissive liquid crystal element as a display element. FIG. 10 In, the liquid crystal element 4013 as a display element includes a first electrode layer 4030, a second electrode layer 4 031, and a liquid crystal layer 4008. Note that insulating layers 4032 and 4033 that function as alignment films and sandwich the liquid crystal layer 4008 are provided. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap via the liquid crystal layer 4008. The transistor 4010 provided in the display unit 215 is electrically connected to the liquid crystal element 4013. That is, the transistor 4010 can be, for example, the transistor Tr1 described in Embodiment 1, and the liquid crystal element 4013 can be, for example, the liquid crystal element LC of the pixel PIX described in Embodiment 1. For the first electrode layer 4030 and the second electrode layer 4031, it is preferable to use a conductive material that transmits visible light. As the conductive material, for example, a material containing one or more selected from indium (In), zinc (Zn), and tin (Sn) can be used. Specifically, indium oxide, indium tin oxide (ITO), indium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (ITSO), zinc oxide, zinc oxide containing gallium, and the like can be mentioned. Note that a film containing graphene can be used. The film containing graphene is, for example,

[0201] For the first electrode layer 4030 and the second electrode layer 4031, it is preferable to use a conductive material that transmits visible light. As the conductive material, for example, a material containing one or more selected from indium (In), zinc (Zn), and tin (Sn) can be used. Specifically, indium oxide, indium tin oxide (ITO), indium zinc oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon oxide (ITSO), zinc oxide, zinc oxide containing gallium, and the like can be mentioned. Note that a film containing graphene can be used. The film containing graphene is, for example, a film obtained by forming graphene on a transparent substrate such as a glass substrate by a chemical vapor deposition method or a physical vapor deposition method, or a film obtained by doping graphene with a dopant such as boron or nitrogen. For example, a film obtained by forming graphene on a transparent substrate such as a glass substrate by a chemical vapor deposition method or a physical vapor deposition method, or a film obtained by doping graphene with a dopant such as boron or nitrogen can be used. It can be formed by reducing a film containing graphene oxide formed on a film.

[0202] As the liquid crystal element 4013, for example, a liquid crystal element to which a FFS (Fringe Field Switching) mode is applied can be used. Also, generally, liquid crystal materials include a positive liquid crystal material having a positive dielectric anisotropy (Δε) and a negative liquid crystal material having a negative dielectric anisotropy. For the liquid crystal element 4013 shown in this embodiment, both materials can be applied, and an optimal liquid crystal material can be used according to the applied mode and design. In the display device shown in this embodiment, it is preferable to use a negative liquid crystal material. In a negative liquid crystal, the influence of the flexoelectric effect derived from the polarization of liquid crystal molecules can be suppressed, and there is almost no difference in transmittance due to polarization. Therefore, it is possible to suppress the flicker from being visually recognized by the user of the display device. The flexoelectric effect is a phenomenon in which polarization occurs mainly due to the molecular shape and due to the orientation distortion. A negative liquid crystal material is less likely to cause orientation distortion such as spreading deformation and bending deformation.

[0203] Here, an element to which the FFS mode is applied is used as the liquid crystal element 4013, but the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, etc. In a negative liquid crystal, the influence of the flexoelectric effect derived from the polarization of liquid crystal molecules can be suppressed, and there is almost no difference in transmittance due to polarization. Therefore, it is possible to suppress the flicker from being visually recognized by the user of the display device. The flexoelectric effect is a phenomenon in which polarization occurs mainly due to the molecular shape and due to the orientation distortion. A negative liquid crystal material is less likely to cause orientation distortion such as spreading deformation and bending deformation. Here, an element to which the FFS mode is applied is used as the liquid crystal element 4013, but the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, etc. Here, an element to which the FFS mode is applied is used as the liquid crystal element 4013, but the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, etc. Here, an element to which the FFS mode is applied is used as the liquid crystal element 4013, but the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, etc. Here, an element to which the FFS mode is applied is used as the liquid crystal element 4013, but the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, etc.

[0204] Here, an element to which the FFS mode is applied is used as the liquid crystal element 4013, but the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, etc. Here, an element to which the FFS mode is applied is used as the liquid crystal element 4013, but the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, etc. Here, an element to which the FFS mode is applied is used as the liquid crystal element 4013, but the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, etc. Here, an element to which the FFS mode is applied is used as the liquid crystal element 4013, but the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, etc. Here, an element to which the FFS mode is applied is used as the liquid crystal element 4013, but the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, etc. Here, an element to which the FFS mode is applied is used as the liquid crystal element 4013, but the present invention is not limited to this, and liquid crystal elements to which various modes are applied can be used. For example, a VA (Vertical Alignment) mode, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, etc. D, FLC (Ferroelectric Liquid Crystal) mode, A FLC (AntiFerroelectric Liquid Crystal) mode , ECB (Electrically Controlled Birefringen ce) mode, VA-IPS mode, guest-host mode, etc. can be used for the liquid crystal element.

[0205] In addition, a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode, may be applied to the display device shown in this embodiment. As the vertical alignment mode , MVA (Multi-Domain Vertical Alignmen t) mode, PVA (Patterned Vertical Alignment) mode , ASV (Advanced Super View) mode, etc. can be used for this.

[0206] Note that the liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). As the liquid crystal used for the liquid crystal element, thermotropic liquid crystal, low molecular liquid crystal, high molecular liquid crystal, polymer dispersed liquid crystal (PDLC: Polyme r Dispersed Liquid Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions. r Dispersed Liquid Crystal), ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions.

[0207] In FIG. 10, an example of a display device having a vertical electric field type liquid crystal element is shown, but one aspect of the present invention​​​ It can be applied to a display device having a horizontal electric field type liquid crystal element. When adopting the horizontal electric field type, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used in the liquid crystal layer 4008 to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and shows optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects or damages of the liquid crystal display device during the manufacturing process can be reduced. When adopting the horizontal electric field type, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used in the liquid crystal layer 4008 to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and shows optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects or damages of the liquid crystal display device during the manufacturing process can be reduced. When adopting the horizontal electric field type, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used in the liquid crystal layer 4008 to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and shows optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects or damages of the liquid crystal display device during the manufacturing process can be reduced. When adopting the horizontal electric field type, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used in the liquid crystal layer 4008 to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and shows optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects or damages of the liquid crystal display device during the manufacturing process can be reduced. When adopting the horizontal electric field type, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used in the liquid crystal layer 4008 to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and shows optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects or damages of the liquid crystal display device during the manufacturing process can be reduced. When adopting the horizontal electric field type, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used in the liquid crystal layer 4008 to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and shows optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects or damages of the liquid crystal display device during the manufacturing process can be reduced. When adopting the horizontal electric field type, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used in the liquid crystal layer 4008 to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and shows optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects or damages of the liquid crystal display device during the manufacturing process can be reduced. When adopting the horizontal electric field type, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used in the liquid crystal layer 4008 to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and shows optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects or damages of the liquid crystal display device during the manufacturing process can be reduced. When adopting the horizontal electric field type, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used in the liquid crystal layer 4008 to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and shows optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects or damages of the liquid crystal display device during the manufacturing process can be reduced. When adopting the horizontal electric field type, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and it is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used in the liquid crystal layer 4008 to improve the temperature range. A liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent has a short response time and shows optical isotropy. In addition, a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent does not require alignment treatment and has little viewing angle dependence. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by rubbing treatment can be prevented, and defects or damages of the liquid crystal display device during the manufacturing process can be reduced.

[0208] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the interval (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that a spherical spacer may be used. The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the interval (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that a spherical spacer may be used. The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer, and is provided to control the interval (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that a spherical spacer may be used.

[0209] Also, if necessary, optical members (optical substrates) such as a black matrix (light shielding layer), a coloring layer (color filter), a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight unit, a side light unit, etc. may be used as the light source. Also, a micro LED, etc. may be used as the above backlight unit and side light unit. Also, if necessary, optical members (optical substrates) such as a black matrix (light shielding layer), a coloring layer (color filter), a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight unit, a side light unit, etc. may be used as the light source. Also, a micro LED, etc. may be used as the above backlight unit and side light unit. Also, if necessary, optical members (optical substrates) such as a black matrix (light shielding layer), a coloring layer (color filter), a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight unit, a side light unit, etc. may be used as the light source. Also, a micro LED, etc. may be used as the above backlight unit and side light unit. Also, if necessary, optical members (optical substrates) such as a black matrix (light shielding layer), a coloring layer (color filter), a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight unit, a side light unit, etc. may be used as the light source. Also, a micro LED, etc. may be used as the above backlight unit and side light unit. Also, if necessary, optical members (optical substrates) such as a black matrix (light shielding layer), a coloring layer (color filter), a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight unit, a side light unit, etc. may be used as the light source. Also, a micro LED, etc. may be used as the above backlight unit and side light unit. In the case of the display device shown in FIG. 10, for example, on the surface of the second substrate 4006 (the side opposite to the surface where the coloring layer 413 1 and the light shielding layer 4132 are provided), and on the back surface of the first substrate 4001 (the side opposite to the surface where the insulating layer 4102 is provided), polarizing substrates are respectively provided, and a backlight unit may be provided on the back surface side of the first substrate 4001 via the polarizing substrate (not shown). ).

[0210] In the display device shown in FIG. 10, a light shielding layer 4132, a coloring layer 4131, and an insulating layer 4133 are provided between the second substrate 4006 and the second electrode layer 4031.

[0211] Examples of materials that can be used as the light shielding layer 4132 include carbon black, titanium black, metals, metal oxides, composite oxides containing a solid solution of multiple metal oxides, etc. The light shielding layer may be a film containing a resin material or a thin film of an inorganic material such as a metal. Also, a laminated film of a film containing the material of the coloring layer 4131 can be used for the light shielding layer 4132. For example, a laminated structure of a film containing the material used for the coloring layer 4131 that transmits light of a certain color and a film containing the material used for the coloring layer 4131 that transmits light of another color can be used. By making the materials of the coloring layer 4131 and the light shielding layer 4132 common, the device can be made common and the process can be simplified, which is preferable.

[0212] Examples of materials that can be used for the coloring layer 4131 include metal materials, resin materials, resin materials containing pigments or dyes. The light shielding layer and the coloring layer can be formed in the same manner as the formation methods of the above-described respective layers. For example, an inkjet method or the like may be used.

[0213] ​​​​​​The insulating layer 4133 is preferably an overcoat having a planarizing function. Since the insulating layer 4133 has a planarizing function, a flat insulating film can be formed on the formation surfaces of the colored layers 41 31 and the light-shielding layer 4132 having different thicknesses respectively. By planarizing the insulating layer 4 133, the second electrode layer 4031 can be formed flat. Therefore, variations in the thickness of the liquid crystal layer 4008 can be reduced. Examples of such an insulating layer 41 33 include acrylic resins.

[0214] In addition, the display device shown in FIG. 10 has an insulating layer 4111 and an insulating layer 4102. As the insulating layer 4 111 and the insulating layer 4102, an insulating layer that hardly transmits impurity elements is used. By sandwiching the transistor with the insulating layer 41 11 and the insulating layer 4102, the intrusion of impurities from the outside into the semiconductor layer can be prevented.

[0215] In addition, in the present embodiment, although the configuration example of the display device has been described, depending on the situation, changes such as the circuit configuration and circuit elements may be made as appropriate. For example, since the transistor 4011 is easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably configured using a non-linear element.

[0216] Note that the present embodiment can be appropriately combined with other embodiments or examples shown in this specification.

[0217] (Embodiment 3) In the present embodiment, the configuration of a transistor that can be used for a semiconductor device or a display device according to an aspect of the present invention will be described.

[0218] A semiconductor device or a display device according to an aspect of the present invention can be manufactured using various types of transistors such as a bottom gate type transistor and a top gate type transistor. Therefore, according to an existing manufacturing line, the material of the semiconductor layer and the transistor structure used can be easily replaced. It can be manufactured using various types of transistors such as a bottom gate type transistor and a top gate type transistor. Therefore, according to an existing manufacturing line, the material of the semiconductor layer and the transistor structure used can be easily replaced. It can be manufactured using various types of transistors such as a bottom gate type transistor and a top gate type transistor. Therefore, according to an existing manufacturing line, the material of the semiconductor layer and the transistor structure used can be easily replaced. It can be manufactured using various types of transistors such as a bottom gate type transistor and a top gate type transistor. Therefore, according to an existing manufacturing line, the material of the semiconductor layer and the transistor structure used can be easily replaced.

[0219] 〔Bottom Gate Type Transistor〕 FIG. 11(A1) is a cross-sectional view of a channel protection type transistor 810 which is a type of bottom gate type transistor. In FIG. 11(A1), the transistor 810 is formed on a substrate 771. Also, the transistor 810 has an electrode 746 via an insulating layer 772 on the substrate 771. Further, the transistor 810 has a semiconductor layer 742 via an insulating layer 726 on the electrode 746. The electrode 746 can function as a gate electrode. The insulating layer 726 functions as a gate insulating layer. FIG. 11(A1) is a cross-sectional view of a channel protection type transistor 810 which is a type of bottom gate type transistor. In FIG. 11(A1), the transistor 810 is formed on a substrate 771. Also, the transistor 810 has an electrode 746 via an insulating layer 772 on the substrate 771. Further, the transistor 810 has a semiconductor layer 742 via an insulating layer 726 on the electrode 746. The electrode 746 can function as a gate electrode. The insulating layer 726 functions as a gate insulating layer. FIG. 11(A1) is a cross-sectional view of a channel protection type transistor 810 which is a type of bottom gate type transistor. In FIG. 11(A1), the transistor 810 is formed on a substrate 771. Also, the transistor 810 has an electrode 746 via an insulating layer 772 on the substrate 771. Further, the transistor 810 has a semiconductor layer 742 via an insulating layer 726 on the electrode 746. The electrode 746 can function as a gate electrode. The insulating layer 726 functions as a gate insulating layer. FIG. 11(A1) is a cross-sectional view of a channel protection type transistor 810 which is a type of bottom gate type transistor. In FIG. 11(A1), the transistor 810 is formed on a substrate 771. Also, the transistor 810 has an electrode 746 via an insulating layer 772 on the substrate 771. Further, the transistor 810 has a semiconductor layer 742 via an insulating layer 726 on the electrode 746. The electrode 746 can function as a gate electrode. The insulating layer 726 functions as a gate insulating layer. FIG. 11(A1) is a cross-sectional view of a channel protection type transistor 810 which is a type of bottom gate type transistor. In FIG. 11(A1), the transistor 810 is formed on a substrate 771. Also, the transistor 810 has an electrode 746 via an insulating layer 772 on the substrate 771. Further, the transistor 810 has a semiconductor layer 742 via an insulating layer 726 on the electrode 746. The electrode 746 can function as a gate electrode. The insulating layer 726 functions as a gate insulating layer. FIG. 11(A1) is a cross-sectional view of a channel protection type transistor 810 which is a type of bottom gate type transistor. In FIG. 11(A1), the transistor 810 is formed on a substrate 771. Also, the transistor 810 has an electrode 746 via an insulating layer 772 on the substrate 771. Further, the transistor 810 has a semiconductor layer 742 via an insulating layer 726 on the electrode 746. The electrode 746 can function as a gate electrode. The insulating layer 726 functions as a gate insulating layer.

[0220] Also, the transistor 810 has an insulating layer 741 on the channel formation region of the semiconductor layer 742. Also, the transistor 810 has an electrode 744a and an electrode 744b on the insulating layer 726 in contact with a part of the semiconductor layer 742. The electrode 744a can function as one of a source electrode or a drain electrode. The electrode 744b can function as the other of a source electrode or a drain electrode. A part of the electrode 744a and a part of the electrode 744b are formed on the insulating layer 741. Also, the transistor 810 has an insulating layer 741 on the channel formation region of the semiconductor layer 742. Also, the transistor 810 has an electrode 744a and an electrode 744b on the insulating layer 726 in contact with a part of the semiconductor layer 742. The electrode 744a can function as one of a source electrode or a drain electrode. The electrode 744b can function as the other of a source electrode or a drain electrode. A part of the electrode 744a and a part of the electrode 744b are formed on the insulating layer 741. Also, the transistor 810 has an insulating layer 741 on the channel formation region of the semiconductor layer 742. Also, the transistor 810 has an electrode 744a and an electrode 744b on the insulating layer 726 in contact with a part of the semiconductor layer 742. The electrode 744a can function as one of a source electrode or a drain electrode. The electrode 744b can function as the other of a source electrode or a drain electrode. A part of the electrode 744a and a part of the electrode 744b are formed on the insulating layer 741. Also, the transistor 810 has an insulating layer 741 on the channel formation region of the semiconductor layer 742. Also, the transistor 810 has an electrode 744a and an electrode 744b on the insulating layer 726 in contact with a part of the semiconductor layer 742. The electrode 744a can function as one of a source electrode or a drain electrode. The electrode 744b can function as the other of a source electrode or a drain electrode. A part of the electrode 744a and a part of the electrode 744b are formed on the insulating layer 741. Also, the transistor 810 has an insulating layer 741 on the channel formation region of the semiconductor layer 742. Also, the transistor 810 has an electrode 744a and an electrode 744b on the insulating layer 726 in contact with a part of the semiconductor layer 742. The electrode 744a can function as one of a source electrode or a drain electrode. The electrode 744b can function as the other of a source electrode or a drain electrode. A part of the electrode 744a and a part of the electrode 744b are formed on the insulating layer 741.

[0221] The insulating layer 741 can function as a channel protection layer. By providing the insulating layer 741 on the channel formation region, exposure of the semiconductor layer 742 that occurs during the formation of the electrodes 744a and 744b can be prevented. Therefore, during the formation of the electrodes 744a and 744b, the semiconductor The insulating layer 741 can function as a channel protection layer. By providing the insulating layer 741 on the channel formation region, exposure of the semiconductor layer 742 that occurs during the formation of the electrodes 744a and 744b can be prevented. Therefore, during the formation of the electrodes 744a and 744b, the semiconductor The insulating layer 741 can function as a channel protection layer. By providing the insulating layer 741 on the channel formation region, exposure of the semiconductor layer 742 that occurs during the formation of the electrodes 744a and 744b can be prevented. Therefore, during the formation of the electrodes 744a and 744b, the semiconductor This can prevent the channel formation region of the layer 742 from being etched. According to this method, a transistor having good electrical characteristics can be realized.

[0222] The transistor 810 has an insulating layer 744 a, an electrode 744 b, and an insulating layer 741. It has an edge layer 728 and an insulating layer 729 on top of the insulating layer 728 .

[0223] When an oxide semiconductor is used for the semiconductor layer 742, at least one of the electrodes 744a and 744b At least in the portion in contact with the semiconductor layer 742, oxygen is taken from a portion of the semiconductor layer 742, and oxygen deficiency is formed. It is preferable to use a material capable of generating oxygen vacancies in the semiconductor layer 742. The carrier concentration in the region where this occurs increases, the region becomes n-type, and the n-type region (n + Area) Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, oxygen is taken from the semiconductor layer 742, and oxygen deficiency occurs. Examples of materials that can cause damage include tungsten and titanium. can.

[0224] The source and drain regions are formed in the semiconductor layer 742, forming an electrode 744. a and the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. To improve the electrical characteristics of transistors, such as field effect mobility and threshold voltage. can be done.

[0225] When a semiconductor such as silicon is used for the semiconductor layer 742, the semiconductor layer 742 and the electrode 744 a and between the semiconductor layer 742 and the electrode 744b, It is preferable to provide a layer that functions as such. The layer that functions as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of a transistor.

[0226] The insulating layer 729 is preferably formed using a material having a function of preventing or reducing the diffusion of impurities from the outside into the transistor. Note that the insulating layer 729 can be omitted as necessary.

[0227] The transistor 811 shown in FIG. 11(A2) is different from the transistor 810 in that it has an electrode 723 that can function as a back gate electrode on the insulating layer 729. The electrode 723 can be formed by the same materials and methods as the electrode 746.

[0228] Generally, the back gate electrode is formed of a conductive layer and is disposed so as to sandwich the channel formation region of the semiconductor layer between the gate electrode and the back gate electrode. Therefore, the back gate electrode can function in the same manner as the gate electrode. The potential of the back gate electrode may be the same as the potential of the gate electrode, or may be a ground potential (GND potential) or any arbitrary potential. Further, by changing the potential of the back gate electrode independently without linking it to the potential of the gate electrode, the threshold voltage of the transistor can be changed.

[0229] Both the electrode 746 and the electrode 723 can function as gate electrodes. Therefore, the insulating layer 726, the insulating layer 728, and the insulating layer 729 can each function as a gate insulating layer. Note that the electrode 723 may be provided between the insulating layer 728 and the insulating layer 729.

[0230] ​​​​​​​​​​​When one of the electrodes 746 and 723 is referred to as a "gate electrode," the other is referred to as a "transistor." For example, in the transistor 811, the electrode 723 is called a "gate electrode." When referring to the back gate electrode, the electrode 746 is referred to as the "back gate electrode." When the transistor 811 is used as a "top electrode," the transistor 811 is a top-gate type transistor. In addition, either the electrode 746 or the electrode 723 can be considered as a type of The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0231] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, By setting the potentials of the electrodes 46 and 723 at the same potential, carriers flow in the semiconductor layer 742. The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-state current of the transistor 811 increases, the field-effect mobility increases.

[0232] Therefore, the transistor 811 is a transistor having a large on-current relative to its area. That is, the area occupied by the transistor 811 is According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0233] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, the outside of the transistor The function of preventing the electric field generated by the junction from acting on the semiconductor layer in which the channel formation region is formed ( In particular, it has an electric field shielding function against static electricity. Form it to be large, and cover the semiconductor layer with the back gate electrode, thereby enhancing the electric field shielding function. This can be achieved.

[0234] Also, by forming the back gate electrode with a conductive film having light-shielding properties, it is possible to prevent light from entering the semiconductor layer from the back gate electrode side. Therefore, light degradation of the semiconductor layer can be prevented, and deterioration of electrical characteristics such as shift of the threshold voltage of the transistor can be prevented. This can be achieved. This can be achieved. This can be achieved.

[0235] According to one aspect of the present invention, a transistor with good reliability can be realized. Also, a semiconductor device with good reliability can be realized. This can be achieved.

[0236] FIG. 11(B1) shows a cross-sectional view of a channel protection type transistor 820, which is one of the bottom gate type transistors. The transistor 820 has substantially the same structure as the transistor 810, but is different from the transistor 810 in that the insulating layer 741 covers the end of the semiconductor layer 742. Also, in the opening formed by selectively removing a part of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a are electrically connected. Also, in another opening formed by selectively removing a part of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 and the electrode 744b are electrically connected. The region of the insulating layer 741 overlapping the channel formation region can function as a channel protection layer. This can be achieved. This can be achieved. This can be achieved. This can be achieved. This can be achieved. This can be achieved. This can be achieved.

[0237] The transistor 821 shown in FIG. 11(B2) is different from the transistor 820 in that it has an electrode 723 that can function as a back gate electrode on the insulating layer 729. This can be achieved.

[0238] By providing the insulating layer 741, it is possible to prevent the exposure of the semiconductor layer 742 that occurs during the formation of the electrodes 744a and 744b. Therefore, it is possible to prevent the thinning of the semiconductor layer 742 during the formation of the electrodes 744a and 744b. Also, the distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are longer for the transistors 820 and 821 than for the transistors 810 and 811. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. Also, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one aspect of the present invention, a transistor with good electrical characteristics can be realized.

[0239] The transistor 825 shown in FIG. 11(C1) is a channel etching type transistor which is one of the bottom gate type transistors. The transistor 825 forms the electrodes 744a and 744b without using the insulating layer 741. For this reason, a part of the semiconductor layer 742 exposed during the formation of the electrodes 744a and 744b may be etched. On the other hand, since the insulating layer 741 is not provided, the productivity of the transistor can be increased.

[0240] The transistor 826 shown in FIG. 11(C2) is different from the transistor 825 in that it has an electrode 723 that can function as a back gate electrode on the insulating layer 729.

[0241]

[0242] 〔Top Gate Type Transistor〕 The transistor 842 illustrated in FIG. 12(A1) is one of the top gate type transistors. ​​​​​​​​​​​​That is. After forming the insulating layer 729, the electrodes 744a and electrodes 744b are formed at a point different from the transistors 810, 811, 820, 821, 825, 826 . The electrodes 744a and 744b are electrically connected to the semiconductor layer 742 at the openings formed in the insulating layer 728 and the insulating layer 729.

[0243] Also, a part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and impurities 755 are introduced into the semiconductor layer 742 using the insulating layer 726 and the remaining insulating layer 726 as a mask, so that impurity regions can be formed self-alignedly in the semiconductor layer 742. The transistor 842 has a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration in the region where the impurities 755 are introduced through the insulating layer 726 of the semiconductor layer 742 is smaller than that in the region where the impurities 755 are introduced without passing through the insulating layer 726. The semiconductor layer 7 42 has an LDD (Lightly Doped Drai n) region formed in a region that does not overlap with the electrode 746.

[0244] The transistor 843 shown in FIG. 12(A2) is different from the transistor 8 42 in that it has an electrode 723. The transistor 843 has an electrode 723 formed on the substrate 771. . The electrode 723 has a region that overlaps with the semiconductor layer 742 through the insulating layer 772. The electrode 72 3 can function as a back gate electrode.

[0245] Also, as in the transistor 844 shown in FIG. 12(B1) and the transistor 845 shown in FIG. 12(B2), all of the insulating layer 726 in the region that does not overlap with the electrode 746 may be removed. In addition, the transistor 846 shown in FIG. 12C1 and the transistor 847 shown in FIG. The insulating layer 726 may remain, as may the stadium 847.

[0246] After forming the electrode 746, the transistors 842 to 847 are also formed with the electrode 74. 6 as a mask, impurities 755 are introduced into the semiconductor layer 742, forming a semiconductor layer 74 According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner in the electric According to one embodiment of the present invention, a transistor having good characteristics can be realized. A highly integrated semiconductor device can be realized.

[0247] This embodiment mode may be combined as appropriate with other embodiment modes or examples shown in this specification. It is possible.

[0248] (Embodiment 4) In this embodiment, the present invention can be applied to the OS transistor described in the above embodiment. CAC-OS (Cloud-Aligned Composite Silicon-Oxide) Oxide Semiconductor), and CAAC-OS (c-axis Al The structure of the ignited Crystalline Oxide Semiconductor In this specification, CAC is a function or a part of the composition of a material. represents an example, and CAAC represents an example of a crystal structure.

[0249] <Metal oxide composition> CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has a function of insulating in part and a function of semiconductor in the whole material. In addition, CAC-OS or CAC-metal oxide is used as the active layer of a transistor. When used in a layer, the conductive function is the function of allowing electrons (or holes) serving as carriers to flow, while the insulating function is the function of not allowing electrons serving as carriers to flow. By causing the conductive function and the insulating function to act complementarily, respectively, a switching function (On / Off function) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be enhanced to the maximum extent. Moreover, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating

[0250] function. Also, in the material, the conductive region and the insulating region may be separated at the nanometer level. Moreover, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with a blurred periphery and connected in a cloud shape. Also, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively. Moreover, CAC-OS or CAC-metal oxide is composed of components having different band gaps.

[0251] For example, CAC-OS or CAC-metal oxide has a component having a wide band gap due to the insulating region and a component due to the conductive region. Also, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively.

[0252] In addition, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide has a component having a wide band gap due to the insulating region and a component due to the conductive region. In CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm It is composed of a component having a narrow gap and [component name]. In this configuration, when a carrier flows in the component having a narrow gap, the carrier mainly flows. Also, the component having a narrow gap acts complementarily to the component having a wide gap, and a carrier also flows in the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when using the above CAC-OS or CAC-metal oxide in the channel formation region of a transistor a high current driving force, that is, a large on-current, and a high field effect mobility can be obtained in the on-state of the transistor. That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite

[0253] material (matrix composite), or a metal matrix composite (metal matrix composite).

[0254] <Structure of Metal Oxide> Oxide semiconductors can be divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors , nc-OS (nanocrystalline oxide semiconduct or), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), and amorphous oxide semiconductors.

[0255] CAAC-OS has a c-axis orientation, and a plurality of nanocrystals are connected in the a-b plane direction, resulting in a crystal structure having strain. Note that strain means that a plurality of nanocrystals are connected ​​​In the region, it refers to the location where the orientation of the lattice array changes between the region with an aligned lattice array and another region with an aligned lattice array. The location where the orientation of the lattice array changes is pointed out.

[0256] The nanocrystals are based on a hexagon, but they are not necessarily regular hexagons and can be non-regular hexagons in some cases. Also, in terms of strain, there may be cases where the lattice array has pentagons and heptagons, etc. In CAAC-OS, even in the vicinity of strain, it is not possible to confirm a clear grain boundary (also called a grain boundary). That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice array. This is presumably because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice array. This is presumably because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes due to the substitution of metal elements. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice array.

[0257] Also, CAAC-OS tends to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. Also, CAAC-OS tends to have a layered crystal structure (also called a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. It should be noted that indium and element M can be mutually substituted. When element M in the (M,Zn) layer is substituted with indium, it can also be represented as the (In,M,Zn) layer. It should be noted that indium and element M can be mutually substituted. When element M in the (M,Zn) layer is substituted with indium, it can also be represented as the (In,M,Zn) layer. It should be noted that indium and element M can be mutually substituted. When element M in the (M,Zn) layer is substituted with indium, it can also be represented as the (In,M,Zn) layer. Also, when indium in the In layer is substituted with element M, it can also be represented as the (In,M) layer.

[0258] CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, since CAAC-OS cannot confirm a clear grain boundary, it can be said that a decrease in electron mobility due to the grain boundary is less likely to occur. CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, since CAAC-OS cannot confirm a clear grain boundary, it can be said that a decrease in electron mobility due to the grain boundary is less likely to occur. Also, the crystallinity of the oxide semiconductor is affected by factors such as the incorporation of impurities and the generation of defects. Since it may decrease, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the oxide semiconductor having CAAC-OS are stable. Therefore, the oxide semiconductor having CAAC-OS is heat-resistant and highly reliable. In addition, CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, when CAAC-OS is used for an OS transistor, the degree of freedom in the manufacturing process can be increased.

[0259] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS does not show regularity in the crystal orientation between different nano-crystals. Therefore, no orientation is observed in the entire film. Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or an amorphous oxide semiconductor.

[0260] a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity compared with nc-OS and CAAC-OS.

[0261] Oxide semiconductors have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, nc-OS, and CAAC-OS.

[0262] <Transistor having an oxide semiconductor> Subsequently, the case where the above oxide semiconductor is used for a transistor will be described.

[0263] Note that by using the above oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. Also, a highly reliable transistor can be realized.

[0264] Also, it is preferable to use an oxide semiconductor with a low carrier density for the transistor. When reducing the carrier density of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced and the density of defect levels may be reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, the oxide semiconductor has a carrier density of less than 8×10 / cm , preferably less than 1×10 / cm 11 / cm 3 , more preferably less than 1×10 11 / cm 3 , and preferably less than 1×10 10 / cm 3 . If it is 1×10 -9 / cm 3 or more, that is sufficient.

[0265] Also, since the oxide semiconductor film having high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels, the density of trap levels may also be low.

[0266] Also, the time required for the charge trapped in the trap levels of the oxide semiconductor to disappear is long, and it may behave as if it were a fixed charge. Therefore, a transistor having a channel formation region in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

[0267] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the oxide semiconductor It is effective to reduce. Also, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, a lkali metal, alkaline earth metal, iron, nickel, silicon, etc.

[0268] <Impurity> Here, the influence of each impurity in the oxide semiconductor will be described.

[0269] In the oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS:Secondary Ion Mass Spectrometry)) are set to 2×10 atoms / cm (SIMS:Secondary Ion Mass Spectrometry) by 2 or less, preferably 2×10 18 atoms / cm 3 or less. 17 a toms / cm 3 or less.

[0270] Also, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 atoms / cm or less, preferably 2×10 16 atoms / cm or less. 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm3 Make it as follows.

[0271] In addition, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, and the carrier density increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, in the oxide semiconductor, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is 5×10 atoms / cm less than, preferably 5×10 19 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, still more preferably 5×10 18 atoms / cm 3 or less, and even more preferably 5×10 17 atoms / cm 3 or less.

[0272] In addition, hydrogen contained in the oxide semiconductor may react with oxygen bonded to a metal atom to form water, thus forming oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons as carriers may be generated. In addition, a part of hydrogen may bond to oxygen bonded to a metal atom, thus generating electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by SIMS is 1×10 atoms / cm less than, preferably 1× 10 atoms / cm 20 less than, more preferably 5×10 3 atoms / cm 10 19 atoms / cm 3 less than, even more preferably 5×10 18 atoms / cm3 less than , more preferably 1×10 18 atoms / cm 3 less than that.

[0273] Using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of the transistor can impart stable electrical characteristics.

[0274] This embodiment can be appropriately combined with the descriptions of other embodiments or examples. .

[0275] (Embodiment 5) In this embodiment, product examples in which the semiconductor device or display device described in the above embodiment is applied to an electronic device will be described.

[0276] <Notebook personal computer> A semiconductor device or display device according to an aspect of the present invention can be applied to a display provided in an information terminal device. FIG. 13(A) shows a notebook personal computer, which is a type of information terminal device, and includes a housing 5401, a display unit 5402, a keyboard 5403, a pointing device 5404, etc.

[0277] <Smartwatch> A semiconductor device or display device according to an aspect of the present invention can be applied to a wearable terminal. FIG. 13(B) shows a smartwatch, which is a type of wearable terminal, and includes a housing 59 01, a display unit 5902, operation buttons 5903, an operator 5904, a band 5905, etc. Further, a display device with a function as a position input device may be used for the display unit 5902. Further, as the function as a position input device, a touch panel may be provided on the display device. It can be added by doing so. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. It can be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device. In addition, the operation button 5903 can be provided with any one of a power switch for starting the smartwatch, a button for operating the application of the smartwatch, a volume adjustment button, or a switch for lighting or turning off the display unit 5902. In addition, the operation button 5903 can be provided with any one of a power switch for starting the smartwatch, a button for operating the application of the smartwatch, a volume adjustment button, or a switch for lighting or turning off the display unit 5902. In addition, in the smartwatch shown in FIG. 13(B), the number of operation buttons 5903 is shown as two, but the number of operation buttons of the smartwatch is not limited to this. In addition, in the smartwatch shown in FIG. 13(B), the number of operation buttons 5903 is shown as two, but the number of operation buttons of the smartwatch is not limited to this. Also, the operator 5904 functions as a screw for adjusting the time of the smartwatch. Also, the operator 5904 functions as a screw for adjusting the time of the smartwatch. In addition to time adjustment, the operator 5904 may be used as an input interface for operating the application of the smartwatch. In addition to time adjustment, the operator 5904 may be used as an input interface for operating the application of the smartwatch. In the smartwatch shown in FIG. 13(B), it has a configuration having the operator 5904, but it is not limited to this, and a configuration not having the operator 5904 may also be used. In the smartwatch shown in FIG. 13(B), it has a configuration having the operator 5904, but it is not limited to this, and a configuration not having the operator 5904 may also be used.

[0278] <Video camera> The semiconductor device or display device according to one aspect of the present invention can be applied to a video camera. The video camera shown in FIG. 13(C) has a first housing 5801, a second housing 5802, a display unit 5 803, an operation key 5804, a lens 5805, a connection portion 5806, and the like. The operation key 58 04 and the lens 5805 are provided on the first housing 5801, and the display unit 5803 is provided on the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection It can be changed by the connection part 5806. The video on the display part 5803 is switched according to the angle between the first housing 5801 and the second housing 5802 in the connection part 580 6, and it may be configured in this way.

[0279] <Mobile phone> The semiconductor device or display device according to one aspect of the present invention can be applied to a mobile phone. FIG. 13(D) is a mobile phone having the functions of an information terminal, and has a housing 5501, a display part 5502 , a microphone 5503, a speaker 5504, and operation buttons 5505. Further, a display device with an added function as a position input device may be used for the display part 55 02. Also, the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can also be added by providing a photoelectric conversion element, also called a photosensor, in the pixel part of the display device. Further, the operation buttons 5 505 can be provided with any one of a power switch for starting the mobile phone, buttons for operating applications of the mobile phone, volume adjustment buttons, or a switch for turning on or off the display part 5502.

[0280] Also, in the mobile phone shown in FIG. 13(D), the number of operation buttons 5505 is shown as 2 , but the number of operation buttons of the mobile phone is not limited to this. Also, although not shown, the mobile phone shown in FIG. 13(D) may be configured to have a light emitting device for use as a flashlight or illumination.

[0281] <Television device> The semiconductor device or display device according to one aspect of the present invention can be applied to a television device. ​It cuts. The television device shown in FIG. 13(E) includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, etc. The television device can incorporate a large-screen display unit 9001, for example, 50 inches or more, or 100 inches or more.

[0282] <Mobile body> The semiconductor device or display device according to one aspect of the present invention can be applied to the periphery of the driver's seat of an automobile, which is a mobile body.

[0283] For example, FIG. 13(F) is a diagram showing the periphery of the windshield inside an automobile. In FIG. 13(F), in addition to the display panels 5701, 5 702, and 5703 attached to the dashboard, a display panel 5704 attached to the pillar is illustrated.

[0284] The display panels 5701 to 5703 can provide various information by displaying navigation information, a speedometer or a tachometer, the mileage, the fuel gauge, the gear state, the air conditioner settings, etc. Also, the display items and layout shown on the display panel can be appropriately changed according to the user's preference, and the design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

[0285] The display panel 5704 can complement the field of view (blind spot) blocked by the pillar by projecting the video from the imaging means provided on the vehicle body. That is, outside the automobile ​​​​​By displaying an image from the provided imaging means, blind spots can be compensated for and safety can be enhanced. Also, by projecting a video that complements the invisible parts, a safety check can be performed more naturally without a sense of discomfort. The display panel 5704 can also be used as a lighting device.

[0286] <Electronic device for electronic advertising> The semiconductor device or display device according to one aspect of the present invention can be applied to a display used for electronic advertising. FIG. 14(A) shows an example of an electronic signboard (digital signage) that can be attached to a wall. FIG. 14(A) shows a state where the electronic signboard 6200 is attached to the wall 6201.

[0287] <Foldable tablet-type information terminal> The semiconductor device or display device according to one aspect of the present invention can be applied to a tablet-type information terminal. FIG. 14(B) shows a tablet-type information terminal having a foldable structure. The information terminal shown in FIG. 14(B) includes a housing 5321a, a housing 5321b, a display unit 5322, and an operation button 5323. In particular, the display unit 5322 has a flexible substrate, and a structure that can be folded by the substrate can be realized.

[0288] Also, the housing 5321a and the housing 5321b are coupled by a hinge portion 5321c, and the hinge portion 5321c enables it to be folded in half. Also, the display unit 532 2 is provided on the housing 5321a, the housing 5321b, and the hinge portion 5321c.

[0289] Although not shown, FIGS. 13(A) to (C), (E), FIGS. 14(A), (B)​​​ The illustrated electronic device may have a microphone and a speaker. With this configuration, for example, a voice input function can be added to the above-described electronic device.

[0290] Although not shown, the electronic devices shown in FIGS. 13(A), (B), (D), 14(A), and (B) may have a camera.

[0291] Although not shown, the electronic devices shown in FIGS. 13(A) to (F), 14(A), and (B) may have a sensor (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays, etc.) inside the housing. In particular, by providing a detection device having a sensor for detecting any inclination, such as a gyro or an acceleration sensor, in the mobile phone shown in FIG. 13(D), it is possible to determine the orientation of the mobile phone (in which direction the mobile phone is facing with respect to the vertical direction) and automatically switch the display on the display unit 5502 according to the orientation of the mobile phone.

[0292] Although not shown, the electronic devices shown in FIGS. 13(A) to (F), 14(A), and (B) may have a device for acquiring biometric information such as fingerprint, vein, iris, or voiceprint. By applying this configuration, it is possible to realize an electronic device having a biometric authentication function.

[0293] Also, as the display unit of the electronic devices shown in FIGS. 13(A) to (F), 14(A), a flexible substrate may be used. Specifically, the display unit may be formed by disposing a transistor on a flexible substrate. ​​​​It may also be configured with a transistor, a capacitive element, a display element, etc. Applying this configuration makes it possible to realize not only a flat housing like the electronic devices shown in FIGS. 13(A) to (F) and FIG. 14(A), but also an electronic device with a housing having a curved surface like the dashboard and pillar shown in FIG. 13(F).

[0294] Examples of the flexible base material applicable to the display units in FIGS. 13(A) to (F) and FIGS. 14(A) and (B) include materials having translucency to visible light, such as polyethylene tere phthalate resin (PET), polyethylene naphthalate resin (PEN), polyethersulfone resin (PES), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate resin, polyamide resin, polycycloolefin resin, polystyrene resin, polyamideimide resin, polypropylene resin, polyether ester resin, polyhalogenated vinyl resin, aramid resin, epoxy resin, etc. These materials may also be used by mixing or laminating them.

[0295] Note that this embodiment can be appropriately combined with other embodiments or examples shown in this specification.

[0296] (Embodiment 6) In this embodiment, a semiconductor device applicable to the electronic device exemplified in the above embodiment will be described. The semiconductor device exemplified below can function as a storage device.

[0297] In this embodiment, as an example of a storage device using an oxide semiconductor, DOSRAM (registered This will explain the trademark. The name "DOSRAM" is derived from Dynamic Oxid e Semiconductor Random Access Memory. DOSRAM is a memory device in which the memory cell is a 1T1C (1 transistor 1 capacitor) type cell and the write transistor is a transistor to which an oxide semiconductor is applied. That's what it is.

[0298] Using Fig. 15, an example of the stacked structure of DOSRAM 1000 will be explained. DOSRAM 1000 has a sense amplifier section 1002 for reading data and a cell array section 1003 for storing data stacked thereon.

[0299] As shown in Fig. 15, the sense amplifier section 1002 is provided with bit lines BL, Si transistors Ta10, Ta11. The Si transistors Ta10, Ta11 have semiconductor layers on a single crystal silicon wafer. The Si transistors Ta10, Ta11 constitute a sense amplifier and are electrically connected to the bit lines BL.

[0300] The cell array section 1003 has a plurality of memory cells 1001. The memory cell 1001 has a transistor Tw1 and a capacitor element C10. In the cell array section 1003, two transistors Tw1 share a semiconductor layer. The semiconductor layer and the bit lines BL are electrically connected by a conductive body (not shown).

[0301] The stacked structure as shown in Fig. 15 can be applied to various semiconductor devices configured by stacking a plurality of circuits having transistor groups. That's applicable to various semiconductor devices configured by stacking multiple circuits having transistor groups.

[0302] The metal oxides, insulators, conductors, etc. in Fig. 15 may be single layers or stacked layers. For the fabrication of these, can use various film formation methods such as sputtering method, molecular beam epitaxy method (MBE method), pulsed laser ablation method (PLA method), CVD method, atomic layer deposition method (ALD method), etc. Note that the CVD method includes plasma CVD method, thermal CVD method, metalorganic CVD method and so on.

[0303] Here, the semiconductor layer of the transistor Tw1 is composed of a metal oxide (oxide semiconductor). Here, an example in which the semiconductor layer is composed of three metal oxide layers is shown. The semiconductor layer is preferably composed of a metal oxide containing In, Ga, and Zn.

[0304] Here, when an element that forms an oxygen deficiency or an element that binds to the oxygen deficiency is added to the metal oxide, the carrier density may increase and the resistance may decrease. For example, by selectively reducing the resistance of the semiconductor layer using a metal oxide, a source region or a drain region can be provided in the semiconductor layer.

[0305] Typical examples of the element for reducing the resistance of the metal oxide include boron or phosphorus. Also, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, noble gas elements, etc. may be used. Representative examples of noble gas elements include helium, neon, argon, krypton, and xenon. The concentration of the element can be measured using secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) or the like.

[0306] In particular, boron and phosphorus are used in the manufacturing process of amorphous silicon or low-temperature polysilicon. ​​​​​​​​​​It is preferable because the in-device can be used. By diverting the devices on the production line, equipment investment can be suppressed.

[0307] A transistor having a selectively low-resistance semiconductor layer can be formed, for example, by using a dummy gate. Specifically, a dummy gate is provided on the semiconductor layer, and an element for reducing the resistance of the semiconductor layer may be added using the dummy gate as a mask. That is, the element is added to a region of the semiconductor layer that does not overlap with the dummy gate, and a low-resistance region is formed. As a method for adding the element, an ion implantation method in which an ionized source gas is mass-separated and added, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, etc. can be used.

[0308] Conductive materials used for conductors include semiconductors typified by polycrystalline silicon doped with impurity elements such as phosphorus, silicides such as nickel silicide, metals such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or metal nitrides (tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride) containing the above-mentioned metals as components. In addition, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide doped with silicon oxide can be used.

[0309] Insulating materials used for insulators include aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, and the like. In this specification and the like, oxynitride refers to a compound in which the oxygen content is higher than the nitrogen content, and oxynitride refers to a compound in which the nitrogen content is higher than the oxygen content.

[0310] Note that this embodiment can be appropriately combined with other embodiments or examples shown in this specification.

Example

[0311] In the operation of the display device described in Embodiment 1, calculations were performed using a circuit simulator to confirm whether the correction of the image data was appropriately performed. In this example, the calculation and its results will be described.

[0312] The software used in the calculation is a circuit simulator called SmartSpice (version 4.26.7.R) from SILVACO. Using this circuit simulator, image data and correction data were used as input data, and the corrected image data was used as the output data for the calculation.

[0313] The circuit configuration used in the calculation is shown in FIG. 16. In FIG. 16, a source driver circuit SD, a correction data holding unit 104, and a display unit PA are shown.

[0314] In the source driver circuit SD of FIG. 16, only the digital-to-analog conversion circuit DAC and the operational amplifier OPA are shown. The operational amplifier OPA corresponds to the amplifier circuit AMP in FIG. 1 and is a CMOS circuit composed of Si transistors. The output terminal of the digital-to-analog conversion circuit DAC is electrically connected to the non-inverting input terminal of the operational amplifier OPA. Also, the inverting input terminal of the operational amplifier OPA is electrically connected to the output terminal of the operational amplifier OPA, and the output terminal of the operational amplifier OPA is electrically connected to the second terminal of the switch SW1 and the first terminal of the switch SW2 of the correction data holding unit 104, respectively. Note that the operational amplifier OPA functions as a voltage follower circuit according to the above-described connection configuration. Moreover, the high-power input terminal of the operational amplifier OPA is electrically connected to the wiring VDL, and the low-power input terminal of the operational amplifier OPA is electrically connected to the wiring VGL.

[0315] Regarding the correction data holding unit 104, refer to the description of the correction data holding unit 104 in FIG. 3 of the first embodiment. In the description of the first embodiment, it was described that the second terminal of the switch SW3 is electrically connected to the wiring VG. However, in the correction data holding unit 104 of FIG. 16, the second terminal of the switch SW3 is electrically connected to the wiring VGL via the DC power supply VD. Also, the switches SW1 to SW3 each apply an analog switch (a switch having a CMOS circuit configuration) as a switching element.

[0316]

[0317]

[0318]

[0319] ​​​​​​​​​​​​​In the display unit PA of FIG. 16, a resistance element Rpa indicating the resistance of the wiring SL (wiring DL) and , as a capacitance obtained by synthesizing the parasitic capacitance of the wiring SL (wiring DL) and the capacitance element C1 of the pixel PIX a capacitance element Cc is illustrated. Also, the electrical connection point of the resistance element Rpa and the capacitance element Cc is defined as a node ND.

[0320] Next, the calculation conditions will be described. The capacitance value of the capacitance element Cd in the correction data holding unit 104 is set to 1 pF, and the capacitance value of the capacitance element Cc is set to 31 pF. This corresponds to interpolating the voltage for the lower 5 bits with respect to the voltage output from the digital - analog conversion circuit DAC, as in the specific example of Embodiment Form 1.

[0321] Also, the voltage of the DC power supply VD is set to 0.5 V.

[0322] Also, the value of the resistance element Rpa is set to 10 kΩ.

[0323] The digital - analog conversion circuit DAC is assumed to output a potential in the range from 0.5 V to 8.5 V in 0.25 V increments.

[0324] Also, since the operational amplifier OPA has a configuration of a voltage follower circuit, the operational amplifier OPA must be a circuit that can handle the range of potentials that the digital - analog conversion circuit DAC can output. Therefore, the potential provided by the wiring VDL electrically connected to the high - power input terminal of the operational amplifier OPA is set to 9 V, and the potential provided by the wiring VGL electrically connected to the low - power input terminal of the operational amplifier OPA is set as the reference potential.

[0325] The graph shown in FIG. 17 shows the correction data output from the digital - analog conversion circuit DAC and ​​​shows the change in the potential of node ND during the first period and the second period. Specifically, in FIG. 1 7, the potential V of node ND is shown on the vertical axis ND , and the time is shown on the horizontal axis. Each of the first period and the second period is, in the operation example of Embodiment 1, from time T1 to time T2, and from time T2 to time T4. Specifically, time T1 is set to 0 seconds in FIG. 17 (starting point of calculation), and time T2 is set to 1.0×10 -5 seconds (image data writing completion time) .

[0326] During the first period, the switches SW1 and SW3 are turned on by the signal F1, the switch SW2 is turned off by the signal F2, and a potential of 4.0V corresponding to the image data is output from the digital-to-analog conversion circuit DAC and written to node ND. The operation is being performed.

[0327] During the second period, the switches SW1 and SW3 are turned off by the signal F1, the switch SW2 is turned on by the signal F2, and a series of potentials from 0.5V to 8.5V in 0.25V increments are output as correction data from the digital-to-analog conversion circuit DAC and written to node ND3. Then, by writing the potential corresponding to the correction data to node ND3, the potential V fluctuates. In this embodiment, the potentials from 0.5V to 8.5V in 0.25V increments corresponding to the correction data are respectively denoted as V0 to V , and in FIG. 17, only the symbols of V0, V ND , V are illustrated. are shown. 32 And in FIG. 17, only the symbols of V0, V 10 , V 20 , V 30 , V 32 are illustrated.

[0328] Here, consider the case where V0 (0.5V) is written as correction data to node ND3 in the second period. Since the potential of node ND3 was 0.5V in the first period, the potential of node ND3 remains unchanged at 0.5V even when transitioning from the first period to the second period. Therefore, due to capacitive coupling by the capacitive element Cd, the potential V does not fluctuate and remains at 4.0V. Next, consider the case where V (3.0V) is written as correction data to node ND3 in the second period. Since the potential of node ND3 was 0.5V in the first period, the potential of node ND3 rises by 2.5V when transitioning to the second period. Here, from equation (E2), the potential of potential V ND can be estimated to be 4 + 2.5 / 32 V (= 4.078125V), which generally agrees with the result in Figure 17.

[0329] Similarly, consider the cases where V 10 (5.5V), V (8.0V ), and V (8.5V) are each written as correction data to node ND3 in the second period. Since the potential of node ND3 was 0.5V in the first period, the potential of node ND3 rises by 5.0V, 7.5V, and 8.0V respectively in each case when transitioning to the second period. Here, from equation (E2), the potential of potential V ND can be estimated to be 4 + 5.0 / 32 V (= 4.15 625V), 4 + 7.5 / 32 V (= 4.234375V), and 4 + 8.0 / 32 V (= 4

[0330] .25V) respectively in each case, which generally agrees with the result in Figure 17. 20 (5.5V), V 30 (8.0V ), V 32 (8.5V) are each written as correction data to node ND3 in the second period. Since the potential of node ND3 was 0.5V in the first period, the potential of node ND3 rises by 5.0V, 7.5V, and 8.0V respectively in each case when transitioning to the second period. Here, from equation (E2), the potential of potential V can be estimated to be 4 + 5.0 / 32 V (= 4.15 625V), 4 + 7.5 / 32 V (= 4.234375V), and 4 + 8.0 / 32 V (= 4 (E2), the potential of potential V ND is estimated to be 4 + 5.0 / 32 V (= 4.15 625V), 4 + 7.5 / 32 V (= 4.234375V), 4 + 8.0 / 32 V (= 4 .25V) respectively in each case, and generally agrees with the result in Figure 17. ​

[0331] As described above, the digital-to-analog conversion circuit DAC outputs a potential in 0.25V increments. However, the correction data holding unit 104 can generate a potential with an increment width smaller than 0.25V. That is, by using the display device according to one aspect of the present invention, image data with a higher resolution than the digital-to-analog conversion circuit DAC included in the source driver circuit SD can be generated by the correction data holding unit. Further, by writing the image data to the pixels included in the display device, the display unit of the display device can display a multi-tone image.

[0332] That is, by using the display device according to one aspect of the present invention, image data with a higher resolution than the digital-to-analog conversion circuit DAC included in the source driver circuit SD can be generated by the correction data holding unit. Further, by writing the image data to the pixels included in the display device, the display unit of the display device can display a multi-tone image. That is, by using the display device according to one aspect of the present invention, image data with a higher resolution than the digital-to-analog conversion circuit DAC included in the source driver circuit SD can be generated by the correction data holding unit. Further, by writing the image data to the pixels included in the display device, the display unit of the display device can display a multi-tone image. can.

[0333] (Supplementary Note Regarding the Description in this Specification, etc.) Regarding the description of each configuration in the embodiments and examples described in this specification, the following supplementary note is provided. will be.

[0334] <Supplementary Note Regarding One Aspect of the Present Invention Described in the Embodiments and Examples> The configurations shown in each embodiment and example can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other. That is, the configurations shown in each embodiment and example can be appropriately combined with the configurations shown in other embodiments to form one aspect of the present invention. Further, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined with each other.

[0335] Note that the content described in one embodiment or example (even a part of the content) can be applied, combined, or replaced with at least one of the content described in another part of the same embodiment or example (even a part of the content) or the content described in one or more other embodiments (even a part of the content). That is, the content described in one embodiment or example (even a part of the content) can be applied, combined, or replaced with at least one of the content described in another part of the same embodiment or example (even a part of the content) or the content described in one or more other embodiments (even a part of the content). That is, the content described in one embodiment or example (even a part of the content) can be applied, combined, or replaced with at least one of the content described in another part of the same embodiment or example (even a part of the content) or the content described in one or more other embodiments (even a part of the content). That is, the content described in one embodiment or example (even a part of the content) can be applied, combined, or replaced with at least one of the content described in another part of the same embodiment or example (even a part of the content) or the content described in one or more other embodiments (even a part of the content).

[0336] Note that the content described in the embodiments or examples refers to the content described using various figures or the text described in the specification in each embodiment or example. In the embodiments or examples, it is the content described using various figures or the content described using the text described in the specification.

[0337] Note that the figure (even a part) described in a certain embodiment or example can be combined with another part of that figure, another figure (even a part) described in that embodiment or example, and at least one figure described in one or more other embodiments or examples to form more figures. That is, it can be combined with another part of the figure, another figure (even a part) described in that embodiment or example, and at least one figure described in one or more other embodiments or examples to form more figures. That is, it can be combined with another part of the figure, another figure (even a part) described in that embodiment or example, and at least one figure described in one or more other embodiments or examples to form more figures. That is, it can be combined with another part of the figure, another figure (even a part) described in that embodiment or example, and at least one figure described in one or more other embodiments or examples to form more figures.

[0338] <Appendix regarding ordinal numbers> In this specification and the like, ordinal numbers such as "first", "second", and "third" are attached to avoid confusion of components. Therefore, they do not limit the number of components. Also, they do not limit the order of components. For example, the component referred to as "first" in one of the embodiments (or examples) of this specification and the like may be the component referred to as "second" in another embodiment (or example) or in the claims. Also, for example, the component referred to as "first" in one of the embodiments (or examples) of this specification and the like may be omitted in another embodiment or in the claims. Also, for example, the component referred to as "first" in one of the embodiments (or examples) of this specification and the like may be omitted in another embodiment or in the claims.

[0339] <Appendix regarding the description of drawings> The embodiments (or examples) are described with reference to the drawings. However, the embodiments (or examples) can be implemented in many different ways, and the spirit and its scope are ​​​​Those skilled in the art can easily understand that the form and details can be variously changed without departing from it. Therefore, the present invention should not be construed as being limited to the description of the embodiments (or examples). In the configuration of the invention of the embodiments (or the configuration of the examples), the same reference numerals are commonly used for the same parts or parts having similar functions among different drawings, and the repetitive description thereof will be omitted.

[0340] In addition, in this specification and the like, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between the components with reference to the drawings. The positional relationship between the components changes appropriately according to the direction in which each component is depicted. Therefore, the terms indicating the arrangement are not limited to the description given in the specification and the like, and can be appropriately rephrased according to the situation. For example, in the expression "the insulator located on the upper surface of the conductor", by rotating the direction of the shown drawing by 180 degrees, it can be rephrased as "the insulator located on the lower surface of the conductor".

[0341]

[0342] , variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations, etc. can be included. It is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations, etc.

[0343] Also, in the drawings, in perspective views, etc., for the sake of clarity of the drawings, the description of some components may be omitted.

[0344] Also, in the drawings, the same reference numerals may be assigned to the same elements or elements having similar functions, elements of the same material, or elements formed simultaneously, etc., and the repeated description thereof may be omitted.

[0345] <Supplementary Note Regarding Descriptions That Can Be Reworded> In this specification, etc., when explaining the connection relationship of transistors, the notations "one of the source or drain" (or the first electrode, or the first terminal), "the other of the source or drain" (or the second electrode , or the second terminal) are used. This is because the source and drain of a transistor change depending on the structure or operating conditions of the transistor, etc. Note that the names of the source and drain of a transistor can be appropriately reworded according to the situation, such as the source (drain) terminal, the source (drain) electrode, etc. Also, in this specification, etc., the two terminals other than the gate may be referred to as the first terminal and the second terminal, or the third terminal and the fourth terminal. Note that , in this specification, etc., the channel formation region refers to the region where the channel is formed, and by applying a potential to the gate, this region is formed and current can flow between the source and drain. Also, the functions of the source and drain can change when transistors of different polarities are adopted, or in a circuit . In addition, in this specification, etc., the two terminals other than the gate may be referred to as the first terminal and the second terminal, or the third terminal and the fourth terminal. Note that , in this specification, etc., the channel formation region refers to the region where the channel is formed, and by applying a potential to the gate, this region is formed and current can flow between the source and drain. This region is formed, and current can flow between the source and drain.

[0346] Also, the functions of the source and drain can change when transistors of different polarities are adopted, or in a circuit In cases where the direction of the current changes during operation, etc., it may be interchanged. Therefore, in this specification and the like, the terms "source" and "drain" can be used interchangeably.

[0347] Also, in this specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and " wirings" are integrally formed.

[0348] Also, in this specification and the like, voltage and potential can be appropriately rephrased. Voltage is the potential difference from a reference potential. For example, if the reference potential is the ground potential (ground potential), the voltage can be rephrased as potential. The ground potential does not necessarily mean 0V. Note that potential is relative, and depending on the reference potential, the potential applied to wiring or the like may be changed.

[0349] In this specification and the like, terms such as "film" and "layer" can be interchanged with each other in some cases, or depending on the situation. For example, the term "conductive layer" may be changed to the term " conductive film". Or, for example, the term "insulating film" may be changed to the term " insulating layer". Or, in some cases, or depending on the situation, terms such as "film" and "layer" may be replaced with another term without using these terms. For example, the term "conductive layer" or "conductive film" may be changed to the term "conductor". Or, for example, the terms "insulating layer" and "insulating film" ​​ The term "insulator" may be changed to the term "insulator".

[0350] In this specification and the like, terms such as "wiring", "signal line", and "power line" may, in some cases or depending on the situation, be interchangeable with each other. For example, the term "wiring" may be changed to the term "signal line". Also, for example, the term "wiring" may be changed to terms such as "power line". Also the reverse is also true, and terms such as "signal line" and "power line" may be changed to the term "wiring" in some cases. Terms such as "power line" may be changed to terms such as "signal line" in some cases. Also, the reverse is also true, and terms such as "signal line" may be changed to terms such as "power line" in some cases. Also, the term "potential" applied to the wiring may, in some cases or depending on the situation, be changed to the term "signal" or the like in some cases. Also, the reverse is also true, and terms such as "signal" may be changed to the term "potential" in some cases.

[0351] <Appendix on the Definition of Terms> Hereinafter, the definitions of the terms mentioned in the above embodiments and examples will be described.

[0352] <<Regarding Impurities in Semiconductors>> The impurities in a semiconductor refer to, for example, components other than the main component constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are included, for example, DOS (Density of States) may be formed in the semiconductor , the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor When it is a solid, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., and particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phos phorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, for example, oxygen deficiency may be formed due to the mixing of impurities such as hydrogen. Also, when the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 1 3 elements, Group 15 elements, etc., excluding oxygen and hydrogen.

[0353] <<Regarding the switch>> In this specification, etc., a switch refers to something that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether to allow current to flow or not. Or, a switch refers to something that has the function of selecting and switching the path through which current flows.

[0354] As an example, an electrical switch or a mechanical switch, etc. can be used. That is to say, the switch only needs to be able to control current and is not limited to a specific one.

[0355] As an example of an electrical switch, there are transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) di odes, MIS (Metal Insulator Semiconductor) di odes, transistors connected in diode configuration, etc.), or logic circuits combined with these, etc. There are.

[0356] When a transistor is used as a switch, the "conductive state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited. Also, the "non-conductive state" of the transistor means a state in which the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. When the transistor is operated as a mere switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0357] As an example of a mechanical switch, there is a switch using MEMS (Micro-Electro-Mechanical System) technology, such as a Digital Micro-Mirror Device (DMD). The switch has an electrode that can be mechanically moved, and operates by controlling conduction and non-conduction as the electrode moves.

[0358] <<Regarding Connections>> In this specification and the like, when it is described that X and Y are connected, it shall include the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, but also includes those other than the connection relationship shown in the figure or the text.

[0359] X, Y, etc. used here are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0360] As an example of the case where X and Y are electrically connected, an example of the electrical connection between X and Y is enabled. An element capable of performing a function (e.g., a switch, transistor, capacitor, inductor, resistor, diode, display element, light-emitting element, load, etc.) can be connected by one or more between X and Y. Note that the switch has a function of controlling on / off. That is, the switch can be in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether to allow current to flow or not.

[0361] As an example of the case where X and Y are functionally connected, a circuit that enables the functional connection between X and Y (e.g., a logic circuit (such as an inverter, NAND circuit, NOR circuit, etc.), a signal conversion circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), a potential level conversion circuit ( a power supply circuit (boost circuit, buck circuit, etc.), a level shifter circuit that changes the potential level of a signal, etc. ), a voltage source, a current source, a switching circuit, an amplification circuit (a circuit that can increase the signal amplitude or current amount, etc., an operational amplifier, a differential amplification circuit, a source follower circuit, a buffer circuit, etc.), a signal generation circuit, a memory circuit, a control circuit, etc.) can be connected by one or more between X and Y. Note that, as an example, even if another circuit is sandwiched between X and Y, if the signal output from X is transmitted to Y, it is considered that X and Y are functionally connected.

[0362] When it is explicitly described that X and Y are electrically connected, it includes the case where X and Y are electrically connected (that is, when they are connected with another element or another circuit sandwiched between X and Y ), the case where X and Y are functionally connected (that is, when they are functionally connected with another circuit sandwiched between X and Y ), and the case where X and Y are directly connected. (That is, it includes the case where they are connected without sandwiching another element or another circuit between X and Y.) It shall be assumed that. That is, when it is explicitly described that they are electrically connected, it is the same as the case where it is only explicitly described that they are connected continuously.

[0363] For example, the source (or the first terminal, etc.) of a transistor is electrically connected to X via Z1 (or without passing through it), and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y via Z2 (or without passing through it), or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X, and the drain (or the second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. In such cases, it can be expressed as follows. It can be expressed as follows.

[0364] For example, it can be expressed as "X, Y, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are electrically connected to each other, and they are electrically connected in the order of X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y." Or, it can be expressed as "The source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or the first terminal, etc.) of the transistor, the drain (or the second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as "X is electrically connected to the source (or the first terminal, etc.) of the transistor ... ... ... ) and the drain (or the second terminal, etc.) are electrically connected to Y, and X, the source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) The source of the transistor (or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.) Y can be expressed as "is provided in this connection order." Using an expression method similar to these examples, by defining the connection order in the circuit configuration, the source of the transistor (or the first terminal, etc.) and the drain (or the second terminal, etc.) can be distinguished and the technical scope can be determined. Note that these expression methods are just examples and are not limited to these expression methods. Here, X, Y, Z1, and Z2 are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). In addition, even if components that are independent on the circuit diagram are shown as being electrically connected, there may be a case where one component has the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode components. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of multiple components within its scope.

[0365] In addition, even if components that are independent on the circuit diagram are shown as being electrically connected, there may be a case where one component has the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode components. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of multiple components within its scope. For example, when a part of the wiring also functions as an electrode, one conductive film has the functions of both the wiring and the electrode components. Therefore, the electrical connection in this specification includes such a case where one conductive film has the functions of multiple components within its scope.

Explanation of Reference Numerals

[0366] DD: Display device, DD1: Display device, DD2: Display device, DD3: Display device, PA: Display section, GD: Gate driver circuit, SD: Source driver circuit, PIX: Pixel, SR: Shift register, LAT: Latch circuit, LVS: Level shift circuit, DAC: Digital-to-analog conversion circuit, AMP: Amplifier circuit, GL: Wiring, GL1: Wiring, GL2: Wiring, SL: Wiring Line, VA: Wiring, VC: Wiring, VP: Wiring, VG: Wiring, DL: Wiring, AL: Wiring, VL : Wiring, VCOM: Wiring, CAT: Wiring, CRL1: Wiring, CRL2: Wiring, DB: Data Bus Wiring, Rp: Resistor Element, Cs: Capacitor Element, Cp: Capacitor Element, Cpa: Capacitor Element, C d: Capacitor Element, C1: Capacitor Element, C2: Capacitor Element, Tr1: Transistor, Tr2: Trans istor, Tr3: Transistor, Tr4: Transistor, Tr5: Transistor, SW T1: Transistor, SWT2: Transistor, SWT3: Transistor, SWC: Switch , SW1: Switch, SW2: Switch, SW3: Switch, LC: Liquid Crystal Element, LD : Light Emitting Element, ND1: Node, ND2: Node, ND3: Node, VDL: Wiring, VGL : Wiring, Rpa: Resistor Element, Cc: Capacitor Element, ND: Node, BL: Bit Line, Ta10 : Si Transistor, Ta11: Si Transistor, Tw1: Transistor, C10: Cap acity Element, 101: Image Data Holding Section, 102: Driving Circuit Section, 103: Display Element, 104: Correction Data Holding Section, 215: Display Section, 221a: Scanning Line Driving Circuit, 231a: Signal Line Driving Circuit, 232a: Signal Line Driving Circuit, 241a: Common Line Driving Circuit, 723: Electrode, 726: Insulating Layer, 728: Insulating Layer, 729: Insulating Layer, 741: Insulating Layer, 742: Semiconductor Layer, 744 a: Electrode, 744b: Electrode, 746: Electrode, 755: Impurity, 771: Substrate, 772: Ins ulating Layer, 810: Transistor, 811: Transistor, 820: Transistor, 821: Transistor, 825: Transistor, 826: Transistor, 842: Transistor, 843: Transistor, 844: Transistor, 845: Transistor, 846: Trans istor, 847: Transistor, 1000: DOSRAM, 1001: Memory Cell, 10 02: Sense amplifier section, 1003: Cell array section, 4001: First substrate, 4005: Sealing material, 4006: Second substrate, 4010: Transistor, 4011: Transistor, 4 013: Liquid crystal element, 4014: Wiring, 4015: Electrode, 4017: Electrode, 4018: FP C, 4019: Anisotropic conductive layer, 4020: Capacitor element, 4021: Electrode, 4030: First Electrode layer, 4031: Second electrode layer, 4032: Insulating layer, 4033: Insulating layer, 4035: Spacer 4041: Printed circuit board, 4042: Integrated circuit, 4102: Insulating layer, 4103: Insulating layer, 4110: Insulating layer, 4111: Insulating layer, 4112: Insulating layer, 4133 Insulating layer 4200: Input device, 4210: Touch panel, 4227: Electrode, 4228: Electrode, 4 237: Wiring, 4238: Wiring, 4239: Wiring, 4263: Substrate, 4272b: FPC 4273b: IC, 5321a: Housing, 5321b: Housing, 5321c: Hinge part, 5 322: Display section, 5323: Operation button, 5401: Housing, 5402: Display section, 5403 : Keyboard, 5404: Pointing device, 5501: Housing, 5502: Display section 5503: Microphone, 5504: Speaker, 5505: Operation button, 5701: Display panel 5702: Display panel, 5703: Display panel, 5704: Display panel, 5801: First housing, 5802: Second housing, 5803: Display section, 5804: Operation key, 5805: Le ns, 5806: Connection part, 5901: Housing, 5902: Display section, 5903: Operation button, 5904: Operating element, 5905: Band, 6200: Electronic notice board, 6201: Wall, 9000: Housing, 9001: Display section, 9003: Speaker, 9005: Operation key, 9006: Connection terminal Pin

Claims

1. comprising a first circuit, a second circuit, an image signal line, and a source driver circuit, wherein the first circuit includes an image data holding section and a display element, the second circuit includes a correction data holding section, the second circuit is electrically connected to the image signal line, the image signal line is electrically connected to the first circuit, the image data holding section is electrically connected to the display element, the correction data holding section includes first to third switches and a first capacitive element, the image data holding section includes a fourth switch and a second capacitive element, a first terminal of the first switch is electrically connected to a first terminal of the first capacitive element and the image signal line, a second terminal of the first switch is electrically connected to a first terminal of the second switch and an output of the source driver circuit, a second terminal of the first capacitive element is electrically connected to a second terminal of the second switch and a first terminal of the third switch, a reference potential is applied to a second terminal of the third switch, a first terminal of the fourth switch is electrically connected to the image signal line, a second terminal of the fourth switch is electrically connected to the second capacitive element and the display element, operations of the image data holding section and the correction data holding section are performed in order from time T1 to time T6, before time T1, the first switch, the third switch, and the fourth switch are in an off state, the second switch is in an on state, and after a potential of the output of the source driver circuit is applied to a second terminal of the first capacitive element, the second switch becomes in an off state, and a non-conductive state is established between the output of the source driver circuit and the second terminal of the first capacitive element, at time T1, the first switch, the third switch, and the fourth switch become in an on state, and the second switch remains in an off state, a potential V_data1 of the output of the source driver circuit is applied to the image signal line and a second terminal of the fourth switch, the reference potential is applied to the second terminal of the first capacitive element, at time T2, the first switch and the third switch are in an off state, the second switch remains in an off state, and the fourth switch remains in an on state, Between the image signal line and the output of the source driver circuit, a non-conductive state is established, and the image signal line and the second terminal of the fourth switch are in an electrically floating state. The second terminal of the first capacitor element is in an electrically floating state. Between the time T2 and the time T3. The potential V_data2 is output from the source driver circuit. At the time T3. The first switch and the third switch remain in the off state, the second switch becomes in the on state, and the fourth switch remains in the on state. The potential V_data2 is applied to the second terminal of the first capacitor element. Due to the capacitive coupling of the first capacitor element, the potentials of the image signal line and the second terminal of the fourth switch vary from the potential V_data1. At the time T4. The first switch and the third switch remain in the off state, the second switch becomes in the on state, and the fourth switch becomes in the off state. A non-conductive state is established between the image signal line and the second terminal of the fourth switch, and the potential that has varied from the potential V_data1 of the second terminal of the fourth switch is held by the second capacitor element. The display element displays an image corresponding to the potential that has varied from the potential V_data1. At the time T5. The first switch, the third switch, and the fourth switch remain in the off state, and the second switch becomes in the off state. A non-conductive state is established between the source driver circuit and the second terminal of the first capacitor element, the second terminal of the first capacitor element is in an electrically floating state, and the potential V_data2 of the second terminal of the first capacitor element is held by the first capacitor element. At the time T6. The first switch and the third switch become in the on state, and the second switch and the fourth switch remain in the off state. The potential V_AN is output from the source driver circuit. A display device in which the potential V_AN is applied to the image signal line.

2. In claim 1, Assuming that the varying potential from the potential V_data1 is ΔV_g, the capacitance of the first capacitor element is C_A, and the capacitance obtained by combining the parasitic capacitance of the image signal line and the second capacitor element is C_B, the ΔV_g can be estimated by the following formula (E1). When the potential applied to the display element is VND1, the display device is represented by the following formula (E2). 【Number 1】 【Number 2】 **Claim 3** In claim 2, the potential Vdata1 is a potential corresponding to the upper bits of the data of the image displayed by the display element, and the potential ΔVg is a potential corresponding to the lower bits of the data of the image displayed by the display element. A display device. **Claim 4** In any one of claims 1 to 3, at least one of the first to fourth switches is a transistor, and the transistor has either a metal oxide or silicon in a channel formation region. A display device. **Claim 5** In any one of claims 1 to 4, the display element is a liquid crystal element, and a first terminal of the liquid crystal element is electrically connected to a second terminal of the fourth switch. A display device. **Claim 6** An electronic device having the display device according to any one of claims 1 to 5 and a housing.

Images