Semiconductor device

Abstract

To provide a semiconductor device capable of operating stably even if a transistor is depletion type.SOLUTION: A semiconductor device according to an embodiment of disclosed invention includes: a first transistor having a function to supply a first voltage to first wiring; a second transistor having a function to supply a second voltage to the first wiring; a third transistor having a function to halt supply of a third voltage after supplying the third voltage to the gate of the first transistor for turning on the first transistor; a fourth transistor having a function to supply a second voltage to the gate of the first transistor; and a first circuit having a function to generate a second signal which is a first signal with an offset applied, the second signal is inputted to the gate of the fourth transistor, and the minimum value of the second signal is less than the value of the second voltage.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device and a display device. [Background technology]

[0002] With the spread of large display devices such as LCD TVs, the development of display devices with higher added value is progressing. In particular, technological development is underway to construct a drive circuit using transistors of only one conductivity type. This is being actively pursued (see Patent Document 1).

[0003] FIG. 23 shows the driving circuit described in Patent Document 1. The driving circuit in Patent Document 1 A transistor M1, a transistor M2, a transistor M3, a transistor M4, and a capacitance element C1 In Patent Document 1, when the signal OUT is set to a high level, the transistor M1 The gate of the transistor M1 is set in a floating state, and the capacitance of the capacitance element C1 is used to A bootstrap operation is performed to make the potential higher than the potential VDD. In order to make the gate of transistor M1 floating, a transistor connected to the gate of transistor M1 is The potential difference between the gate and source of a transistor (e.g., transistor M4) (hereafter referred to as Vgs) The transistor is turned off by setting the potential of the transistor (shown in Fig. 1) to 0 V.

[0004] Also, when the signal OUT is set to low level, the signal IN is set to high level and the This involves turning on transistor M2 and transistor M3. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-328643

Summary of the Invention

Problems to be Solved by the Invention

[0006] When the transistor is a depletion type (also referred to as normally-on type), even if the Vgs of the transistor is set to 0 [V], the transistor does not turn off. Therefore, when the signal OUT is set to a high level, since the transistors M3 and M4 do not turn off, the gate of the transistor M1 cannot be set to a floating state. If the gate of the transistor M1 cannot be set to a floating state, the bootstrap operation cannot be performed properly and malfunction may occur. Or, even if no malfunction occurs, the operable drive frequency range may become narrow.

[0007] Also, when the signal OUT is set to a low level, since the drive voltage of the drive circuit of the display device is large, the Vgs of the transistors M2 and M3 also becomes large. Therefore, the deterioration of the transistors progresses, and eventually the drive circuit

[0008] may malfunction. Therefore, one aspect of the present invention is to provide a semiconductor device that can operate stably even if the transistor is a depletion type. Another aspect is to suppress the deterioration of the transistor.

[0009] A semiconductor device according to one aspect of the disclosed invention has a function of supplying a first potential to a first wiring, and a second transistor having a function of supplying a transistor, a third transistor having a function of stopping the supply of a third potential after supplying the third potential for turning on the first transistor to the gate of the first transistor, a fourth transistor having a function of supplying a second potential to the gate of the first transistor, and a first circuit having a function of generating a second signal obtained by offsetting a first signal. The second signal is input to the gate of the fourth transistor. The low-level potential of the second signal is a potential lower than the second potential. One aspect of the semiconductor device disclosed is a first transistor having a function of supplying a first potential to a first wiring, a second transistor having a function of supplying a second potential to the first wiring, a third transistor having a function of stopping the supply of the third potential after supplying the third potential for turning on the first transistor to the gate of the first transistor,

[0010] a fourth transistor having a function of supplying the second potential to the gate of the first transistor, a capacitor element to which the first signal is input to one electrode, and a fifth transistor having a function of supplying a fourth potential to the other electrode of the capacitor element. The gate of the fourth transistor is connected to the other electrode of the capacitor element. The fourth potential is a potential lower than the second potential. In the semiconductor device, the first signal may be input to the gate of the second transistor.

[0011]

[0012] According to one aspect of the present invention, even if the transistor is a depletion type, the transistor ​​​​​​​​The can be turned off. Also, the drain current when the transistor is off can be made small. Therefore, malfunction of the circuit can be prevented. Also, according to one aspect of the present invention, the Vgs of the transistor can be made small, and deterioration of the transistor can be suppressed.

Brief Description of the Drawings

[0013]

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Embodiments for Carrying Out the Invention

[0014] An example of an embodiment for explaining the present invention will be described below with reference to the drawings. Note that it is easy for those skilled in the art to change the content of the embodiment without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the description of the embodiment shown below.

[0015] (Embodiment 1) In this embodiment, an example of a semiconductor device that generates a signal with an offset applied to an input signal and is driven by the signal will be described.

[0016] The configuration of the semiconductor device of this embodiment will be described with reference to FIG. 1(A). FIG. 1(A) shows a circuit diagram of the semiconductor device in this embodiment. The semiconductor device in FIG. 1(A) has a circuit 100 and a circuit 110. Circuit 100 includes wiring 11, wiring 12, wiring 14, and ​​It is connected to circuit 110. Circuit 110 is also connected to wiring 15, wiring 13, wiring 16 and circuit 100. Note that according to the configurations of circuit 100 and circuit 110, the wirings and the like connected to circuit 100 and circuit 110 may be changed as appropriate.

[0017] In the specification, when it is explicitly described that X and Y are connected, it shall include the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected.

[0018] A potential VL1 is supplied to wiring 13. The potential VL1 is a predetermined potential. Note that wiring 1 3 has a function of transmitting the potential VL1.

[0019] A potential VL2 is supplied to wiring 14. The potential VL2 is a predetermined potential. Also, the potential V L2 is a potential lower than the potential VL1. Note that wiring 14 has a function of transmitting the potential VL2 to.

[0020] A potential VH is supplied to wiring 15. The potential VH is a predetermined potential. Also, the potential VH is a potential exceeding the potential VL1. Note that wiring 15 has a function of transmitting the potential VH.

[0021] Note that wiring 13, wiring 14 and wiring 15 are also referred to as power lines. Also, the potential VL1, the potential V L2 and the potential VH are also referred to as power supply potentials. Also, the potential VL1, the potential VL2 and the potential VH are supplied from, for example, a power supply circuit or the like.

[0022] A signal IN is input to wiring 11. The signal IN is an input signal of the semiconductor device. Also, the signal IN is a digital signal, the high-level potential of the signal IN is VH, and the The low-level potential is VL1. That is, the potential VH and the potential VL1 are selectively supplied to the wiring 11. Note that the wiring 11 has a function of transmitting the signal IN. The signal SE is input to the wiring 12. The signal SE is a signal for controlling the timing for acquiring the offset voltage. Also, the signal SE is a digital signal, the high-level potential of the signal SE is a potential exceeding VL2, and the low-level potential of the signal SE is a potential of VL2 or lower than VL2. That is, a potential exceeding VL2 and a potential of VL2 or lower than VL2 are selectively supplied to the wiring 12. Note that the wiring 12 has a function of transmitting the signal SE.

[0023] The signal SE is input to the wiring 12. The signal SE is a signal for controlling the timing for acquiring the offset voltage. Also, the signal SE is a digital signal, the high-level potential of the signal SE is a potential exceeding VL2, and the low-level potential of the signal SE is a potential of VL2 or lower than VL2. That is, a potential exceeding VL2 and a potential of VL2 or lower than VL2 are selectively supplied to the wiring 12. Note that the wiring 12 has a function of transmitting the signal SE. The signal SE is input to the wiring 12. The signal SE is a signal for controlling the timing for acquiring the offset voltage. Also, the signal SE is a digital signal, the high-level potential of the signal SE is a potential exceeding VL2, and the low-level potential of the signal SE is a potential of VL2 or lower than VL2. That is, a potential exceeding VL2 and a potential of VL2 or lower than VL2 are selectively supplied to the wiring 12. Note that the wiring 12 has a function of transmitting the signal SE. The signal SE is input to the wiring 12. The signal SE is a signal for controlling the timing for acquiring the offset voltage. Also, the signal SE is a digital signal, the high-level potential of the signal SE is a potential exceeding VL2, and the low-level potential of the signal SE is a potential of VL2 or lower than VL2. That is, a potential exceeding VL2 and a potential of VL2 or lower than VL2 are selectively supplied to the wiring 12. Note that the wiring 12 has a function of transmitting the signal SE. The signal SE is input to the wiring 12. The signal SE is a signal for controlling the timing for acquiring the offset voltage. Also, the signal SE is a digital signal, the high-level potential of the signal SE is a potential exceeding VL2, and the low-level potential of the signal SE is a potential of VL2 or lower than VL2. That is, a potential exceeding VL2 and a potential of VL2 or lower than VL2 are selectively supplied to the wiring 12. Note that the wiring 12 has a function of transmitting the signal SE. The signal SE is input to the wiring 12. The signal SE is a signal for controlling the timing for acquiring the offset voltage. Also, the signal SE is a digital signal, the high-level potential of the signal SE is a potential exceeding VL2, and the low-level potential of the signal SE is a potential of VL2 or lower than VL2. That is, a potential exceeding VL2 and a potential of VL2 or lower than VL2 are selectively supplied to the wiring 12. Note that the wiring 12 has a function of transmitting the signal SE. The signal SE is input to the wiring 12. The signal SE is a signal for controlling the timing for acquiring the offset voltage. Also, the signal SE is a digital signal, the high-level potential of the signal SE is a potential exceeding VL2, and the low-level potential of the signal SE is a potential of VL2 or lower than VL2. That is, a potential exceeding VL2 and a potential of VL2 or lower than VL2 are selectively supplied to the wiring 12. Note that the wiring 12 has a function of transmitting the signal SE.

[0024] The signal OUT is output from the wiring 16. The signal OUT is an output signal of the semiconductor device. Also, the signal OUT is a digital signal, the high-level potential of the signal OUT is VH, and the low-level potential of the signal OUT is VL1. Note that the wiring 16 has a function of transmitting the signal OUT. The signal OUT is output from the wiring 16. The signal OUT is an output signal of the semiconductor device. Also, the signal OUT is a digital signal, the high-level potential of the signal OUT is VH, and the low-level potential of the signal OUT is VL1. Note that the wiring 16 has a function of transmitting the signal OUT. The signal OUT is output from the wiring 16. The signal OUT is an output signal of the semiconductor device. Also, the signal OUT is a digital signal, the high-level potential of the signal OUT is VH, and the low-level potential of the signal OUT is VL1. Note that the wiring 16 has a function of transmitting the signal OUT. The signal OUT is output from the wiring 16. The signal OUT is an output signal of the semiconductor device. Also, the signal OUT is a digital signal, the high-level potential of the signal OUT is VH, and the low-level potential of the signal OUT is VL1. Note that the wiring 16 has a function of transmitting the signal OUT.

[0025] Note that the wirings 11, 12, and 16 are also referred to as signal lines. Also, the signal IN is also referred to as an input signal, the signal SE as a control signal, and the signal OUT as an output signal. Note that the wirings 11, 12, and 16 are also referred to as signal lines. Also, the signal IN is also referred to as an input signal, the signal SE as a control signal, and the signal OUT as an output signal.

[0026] The circuit 100 has a function of generating a signal INO obtained by applying an offset to the signal IN. That is, the circuit 100 has a function of generating a signal INO obtained by reducing the potential of the signal IN by the offset voltage. Also, the circuit 100 has a function of outputting the signal INO to the circuit 110. The circuit 100 has a function of generating a signal INO obtained by applying an offset to the signal IN. That is, the circuit 100 has a function of generating a signal INO obtained by reducing the potential of the signal IN by the offset voltage. Also, the circuit 100 has a function of outputting the signal INO to the circuit 110. The circuit 100 has a function of generating a signal INO obtained by applying an offset to the signal IN. That is, the circuit 100 has a function of generating a signal INO obtained by reducing the potential of the signal IN by the offset voltage. Also, the circuit 100 has a function of outputting the signal INO to the circuit 110. The circuit 100 has a function of generating a signal INO obtained by applying an offset to the signal IN. That is, the circuit 100 has a function of generating a signal INO obtained by reducing the potential of the signal IN by the offset voltage. Also, the circuit 100 has a function of outputting the signal INO to the circuit 110.

[0027] Note that the low-level potential of the signal INO is a potential lower than the potential VL1 of the wiring 13. Further, the potential of the high level of the signal INO preferably exceeds VL1 and is less than VH. Preferably.

[0028] In response to the signal INO (the output signal of the circuit 100), the circuit 110 has a function of selecting whether to set the signal OUT to a high level or a low level. For example, when the circuit 110 functions as an inverter circuit, the circuit 110 sets the signal OUT to a low level when the signal INO is at a high level, and sets the signal OUT to a high level when the signal INO is at a low level. Further, the circuit 110 has a function of selecting whether to output the potential of the wiring 15 to the wiring 16 or output the potential of the wiring 13 to the wiring 16 in response to the signal INO. For example, the circuit 110 outputs the potential of the wiring 13 to the wiring 16 when the signal INO is at a high level, and outputs the potential of the wiring 15 to the wiring 16 when the signal INO is at a low level. Further, the circuit 110 has a function of making the potential of the high level of the signal OUT equal to the potential VH of the wiring 15 by a bootstrap operation. In response to the signal INO (the output signal of the circuit 100), the circuit 110 has a function of selecting whether to set the signal OUT to a high level or a low level. For example, when the circuit 110 functions as an inverter circuit, the circuit 110 sets the signal OUT to a low level when the signal INO is at a high level, and sets the signal OUT to a high level when the signal INO is at a low level. Further, the circuit 110 has a function of selecting whether to output the potential of the wiring 15 to the wiring 16 or output the potential of the wiring 13 to the wiring 16 in response to the signal INO. For example, the circuit 110 outputs the potential of the wiring 13 to the wiring 16 when the signal INO is at a high level, and outputs the potential of the wiring 15 to the wiring 16 when the signal INO is at a low level. Further, the circuit 110 has a function of making the potential of the high level of the signal OUT equal to the potential VH of the wiring 15 by a bootstrap operation. In response to the signal INO (the output signal of the circuit 100), the circuit 110 has a function of selecting whether to set the signal OUT to a high level or a low level. For example, when the circuit 110 functions as an inverter circuit, the circuit 110 sets the signal OUT to a low level when the signal INO is at a high level, and sets the signal OUT to a high level when the signal INO is at a low level. Further, the circuit 110 has a function of selecting whether to output the potential of the wiring 15 to the wiring 16 or output the potential of the wiring 13 to the wiring 16 in response to the signal INO. For example, the circuit 110 outputs the potential of the wiring 13 to the wiring 16 when the signal INO is at a high level, and outputs the potential of the wiring 15 to the wiring 16 when the signal INO is at a low level. Further, the circuit 110 has a function of making the potential of the high level of the signal OUT equal to the potential VH of the wiring 15 by a bootstrap operation. In response to the signal INO (the output signal of the circuit 100), the circuit 110 has a function of selecting whether to set the signal OUT to a high level or a low level. For example, when the circuit 110 functions as an inverter circuit, the circuit 110 sets the signal OUT to a low level when the signal INO is at a high level, and sets the signal OUT to a high level when the signal INO is at a low level. Further, the circuit 110 has a function of selecting whether to output the potential of the wiring 15 to the wiring 16 or output the potential of the wiring 13 to the wiring 16 in response to the signal INO. For example, the circuit 110 outputs the potential of the wiring 13 to the wiring 16 when the signal INO is at a high level, and outputs the potential of the wiring 15 to the wiring 16 when the signal INO is at a low level. Further, the circuit 110 has a function of making the potential of the high level of the signal OUT equal to the potential VH of the wiring 15 by a bootstrap operation. In response to the signal INO (the output signal of the circuit 100), the circuit 110 has a function of selecting whether to set the signal OUT to a high level or a low level. For example, when the circuit 110 functions as an inverter circuit, the circuit 110 sets the signal OUT to a low level when the signal INO is at a high level, and sets the signal OUT to a high level when the signal INO is at a low level. Further, the circuit 110 has a function of selecting whether to output the potential of the wiring 15 to the wiring 16 or output the potential of the wiring 13 to the wiring 16 in response to the signal INO. For example, the circuit 110 outputs the potential of the wiring 13 to the wiring 16 when the signal INO is at a high level, and outputs the potential of the wiring 15 to the wiring 16 when the signal INO is at a low level. Further, the circuit 110 has a function of making the potential of the high level of the signal OUT equal to the potential VH of the wiring 15 by a bootstrap operation. In response to the signal INO (the output signal of the circuit 100), the circuit 110 has a function of selecting whether to set the signal OUT to a high level or a low level. For example, when the circuit 110 functions as an inverter circuit, the circuit 110 sets the signal OUT to a low level when the signal INO is at a high level, and sets the signal OUT to a high level when the signal INO is at a low level. Further, the circuit 110 has a function of selecting whether to output the potential of the wiring 15 to the wiring 16 or output the potential of the wiring 13 to the wiring 16 in response to the signal INO. For example, the circuit 110 outputs the potential of the wiring 13 to the wiring 16 when the signal INO is at a high level, and outputs the potential of the wiring 15 to the wiring 16 when the signal INO is at a low level. Further, the circuit 110 has a function of making the potential of the high level of the signal OUT equal to the potential VH of the wiring 15 by a bootstrap operation. In response to the signal INO (the output signal of the circuit 100), the circuit 110 has a function of selecting whether to set the signal OUT to a high level or a low level. For example, when the circuit 110 functions as an inverter circuit, the circuit 110 sets the signal OUT to a low level when the signal INO is at a high level, and sets the signal OUT to a high level when the signal INO is at a low level. Further, the circuit 110 has a function of selecting whether to output the potential of the wiring 15 to the wiring 16 or output the potential of the wiring 13 to the wiring 16 in response to the signal INO. For example, the circuit 110 outputs the potential of the wiring 13 to the wiring 16 when the signal INO is at a high level, and outputs the potential of the wiring 15 to the wiring 16 when the signal INO is at a low level. Further, the circuit 110 has a function of making the potential of the high level of the signal OUT equal to the potential VH of the wiring 15 by a bootstrap operation. In response to the signal INO (the output signal of the circuit 100), the circuit 110 has a function of selecting whether to set the signal OUT to a high level or a low level. For example, when the circuit 110 functions as an inverter circuit, the circuit 110 sets the signal OUT to a low level when the signal INO is at a high level, and sets the signal OUT to a high level when the signal INO is at a low level. Further, the circuit 110 has a function of selecting whether to output the potential of the wiring 15 to the wiring 16 or output the potential of the wiring 13 to the wiring 16 in response to the signal INO. For example, the circuit 110 outputs the potential of the wiring 13 to the wiring 16 when the signal INO is at a high level, and outputs the potential of the wiring 15 to the wiring 16 when the signal INO is at a low level. Further, the circuit 110 has a function of making the potential of the high level of the signal OUT equal to the potential VH of the wiring 15 by a bootstrap operation. In response to the signal INO (the output signal of the circuit 100), the circuit 110 has a function of selecting whether to set the signal OUT to a high level or a low level. For example, when the circuit 110 functions as an inverter circuit, the circuit 110 sets the signal OUT to a low level when the signal INO is at a high level, and sets the signal OUT to a high level when the signal INO is at a low level. Further, the circuit 110 has a function of selecting whether to output the potential of the wiring 15 to the wiring 16 or output the potential of the wiring 13 to the wiring 16 in response to the signal INO. For example, the circuit 110 outputs the potential of the wiring 13 to the wiring 16 when the signal INO is at a high level, and outputs the potential of the wiring 15 to the wiring 16 when the signal INO is at a low level. Further, the circuit 110 has a function of making the potential of the high level of the signal OUT equal to the potential VH of the wiring 15 by a bootstrap operation. In response to the signal INO (the output signal of the circuit 100), the circuit 110 has a function of selecting whether to set the signal OUT to a high level or a low level. For example, when the circuit 110 functions as an inverter circuit, the circuit 110 sets the signal OUT to a low level when the signal INO is at a high level, and sets the signal OUT to a high level when the signal INO is at a low level. Further, the circuit 110 has a function of selecting whether to output the potential of the wiring 15 to the wiring 16 or output the potential of the wiring 13 to the wiring 16 in response to the signal INO. For example, the circuit 110 outputs the potential of the wiring 13 to the wiring 16 when the signal INO is at a high level, and outputs the potential of the wiring 15 to the wiring 16 when the signal INO is at a low level. Further, the circuit 110 has a function of making the potential of the high level of the signal OUT equal to the potential VH of the wiring 15 by a bootstrap operation.

[0029] Next, specific examples of the circuit 100 and the circuit 110 will be described with reference to FIG. 1(A).

[0030] The circuit 100 includes a capacitive element 101 and a transistor 102. One electrode of the capacitive element 101 is connected to the wiring 11. The first terminal (either the source or the drain) of the transistor 102 is connected to the wiring 14, the second terminal of the transistor 102 is connected to the other electrode of the capacitive element 101, and the gate of the transistor 102 is connected to the wiring 12. The circuit 100 includes a capacitive element 101 and a transistor 102. One electrode of the capacitive element 101 is connected to the wiring 11. The first terminal (either the source or the drain) of the transistor 102 is connected to the wiring 14, the second terminal of the transistor 102 is connected to the other electrode of the capacitive element 101, and the gate of the transistor 102 is connected to the wiring 12. The circuit 100 includes a capacitive element 101 and a transistor 102. One electrode of the capacitive element 101 is connected to the wiring 11. The first terminal (either the source or the drain) of the transistor 102 is connected to the wiring 14, the second terminal of the transistor 102 is connected to the other electrode of the capacitive element 101, and the gate of the transistor 102 is connected to the wiring 12. The circuit 100 includes a capacitive element 101 and a transistor 102. One electrode of the capacitive element 101 is connected to the wiring 11. The first terminal (either the source or the drain) of the transistor 102 is connected to the wiring 14, the second terminal of the transistor 102 is connected to the other electrode of the capacitive element 101, and the gate of the transistor 102 is connected to the wiring 12.

[0031] Circuit 110 includes transistor 111, transistor 112, transistor 113, and transistor 114. The first terminal of transistor 111 is connected to wiring 15, and the second terminal of transistor 111 is connected to wiring 16. The first terminal of transistor 112 is connected to wiring 13, the second terminal of transistor 112 is connected to wiring 16, and the gate of transistor 112 is connected to the gate of transistor 114. The first terminal of transistor 113 is connected to wiring 15, the second terminal of transistor 113 is connected to the gate of transistor 111, and the gate of transistor 113 is connected to wiring 15. The first terminal of transistor 114 is connected to wiring 13, the second terminal of transistor 114 is connected to the gate of transistor 111, and the gate of transistor 114 is connected to the other electrode of capacitor element 101. Note that the connection

[0032] point between the gate of transistor 111 and other transistors (e.g., transistor 113, transistor 114, etc.) is defined as node N1. Capacitor element 101 has the function of holding the potential difference

[0033] between wiring 11 and the second terminal of transistor 102. Therefore, when the second terminal of transistor 102 is in a floating state, the potential of the second terminal of transistor 102 also varies according to the signal input to wiring 11. That is, the potential of signal INO also varies according to signal

[0034] Note that the transistor 102 may supply a potential lower than the potential VL1 to the other electrode of the capacitor element 101. Specifically, the transistor 102 may supply a potential lower than the potential of the first terminal of the transistor 114 to the other electrode of the capacitor element 101.

[0035] The transistor 111 has a function of supplying the potential VH of the wiring 15 to the wiring 16. Also the transistor 111 has a function of holding the potential difference between the gate and the second terminal. Therefore, when the node N1 is in a floating state, if the potential of the wiring 16 rises, the potential of the node N 1 also rises.

[0036] Note that when a signal is input to the wiring 15, the transistor 111 has a function of supplying the signal of the wiring 15 to the wiring 16.

[0037] The transistor 112 has a function of supplying the potential VL1 of the wiring 13 to the wiring 16. The timing at which the transistor 112 supplies the potential VL1 to the wiring 16 is controlled by the signal INO output from the circuit 100 (the potential of the other electrode of the capacitor element 101).

[0038] The transistor 113 has a function of supplying the potential VH of the wiring 15 to the gate of the transistor 111. Also, the transistor 113 has a function of stopping the supply of the potential VH to the gate of the transistor 111 after supplying the potential VH to the gate of the transistor 111. Also the transistor 113 has a function of supplying the potential VH to the gate of the transistor 111 from after the transistor 111 is turned on until the transistor 11

[0039] Note that the potential supplied by transistor 113 to the gate of transistor 111 may be a potential at which transistor 111 turns on.

[0040] Transistor 114 has a function of supplying the potential VL1 of wiring 13 to the gate of transistor 111. The timing at which transistor 114 supplies the potential VL1 to the gate of transistor 111 is controlled by the signal INO output from circuit 100.

[0041] Note that the transistors (for example, transistor 102, transistor 111, transistor 112, transistor 113, and transistor 114 ) included in the semiconductor device of this embodiment have the same conductivity type. In this embodiment, the transistors included in the semiconductor device of this embodiment will be described as being N-channel type.

[0042] Next, an example of a driving method of the semiconductor device in FIG. 1(A) will be described with reference to FIG. 1(B). FIG. 1(B) is an example of a timing chart for explaining the driving method of the semiconductor device in FIG. 1(A).

[0043] The driving method of the semiconductor device in FIG. 1(A) will be described separately for period T0 and period T1.

[0044] Period T0 is a period for holding an offset voltage in capacitor element 101. First, with signal IN at a low level, the potential of one electrode of capacitor element 101 is set to VL1. Also, with signal SE at a high level, transistor 102 is turned on. Then, the potential VL2 of wiring 14 is supplied to the other electrode of capacitor element 101, and the potential of the other electrode of capacitor element 101 is set to VL2. Thus, in capacitor element 101, the low-level potential VL1 of signal IN and ​ The difference (VL1 - VL2) between the potential VL2 of wiring 14 supplied by transistor 102 is held. This difference (VL1 - VL2) corresponds to the offset voltage.

[0045] Note that in period T0, transistor 102 may supply a potential lower than VL1 to the other electrode of capacitor element 101.

[0046] Period T1 is a period for applying an offset to signal IN to generate signal INO and driving circuit 110 with signal INO. First, with signal SE at a low level, transistor 102 is turned off, floating the other electrode of capacitor element 101. Since capacitor element 101 holds the potential difference VL1 - VL2 in period T0, signal INO, which is a signal obtained by subtracting a value corresponding to the potential difference VL1 - VL2 from signal IN, is generated. Thus, when signal IN becomes low level, signal INO also becomes low level, and the potential of the low level of signal INO is lower than VL1. Also, when signal IN becomes high level, signal INO also becomes high level, and the potential of the high level of signal INO is lower than VH.

[0047] Regarding the driving method of the semiconductor device in FIG. 1(A) in period T1, the case where signal IN is high level and the case where signal IN is low level will be described separately.

[0048] In period T1, when signal IN becomes high level, signal INO also becomes high level, so transistors 112 and 114 turn on. Thus, the potential VL1 of wiring 13 is supplied to wiring 16 by transistor 112. Also, the potential VL of wiring 13 ​​​​​​​​​​​1 is supplied to node N1 by transistor 114. The potential VH of wiring 15 is also supplied to node N1 by transistor 113. However, if the W (channel width) / L (channel length) ratio of transistor 114 is made sufficiently larger than the W / L ratio of transistor 113, the potential of node N1 becomes a potential such that transistor 111 turns off. Therefore, transistor 111 turns off. Thus, signal OUT becomes a low level, and its potential becomes VL1. On the other hand, in period T1, when signal IN becomes a low level, signal INO also becomes a low level. Therefore, transistors 112 and 114 turn off. Since the potential VH of wiring 15 is supplied to node N1 by transistor 113, the potential of node N1 rises. Therefore, transistor 111 turns on, and the potential VH of wiring 15 is supplied to wiring 16 by transistor 111, so the potential of wiring 16 rises. Eventually, when the potential of node N1 rises to a potential obtained by subtracting the threshold voltage of transistor 113 from potential VH, transistor 113 turns off, and node N1 becomes a floating state. Even when node N1 becomes a floating state, the potential of wiring 16 is rising. Also, between the gate of transistor 111 and the second terminal, the potential difference between node N1 and wiring 16 when transistor 113 turns off is held. Therefore, as the potential of wiring 16 rises, the potential of node N1 further rises and becomes higher than potential VH. This is a so-called bootstrap operation. Thus, signal OUT becomes a high level, and its potential becomes VH.

[0049]

[0050] ​​​​​​​​​​​​​​​When a signal is input to wiring 15, the signal on wiring 15 is output to wiring 16. . For example, when a clock signal is input to wiring 15, during the period when signal IN is at a low level , the clock signal is output from wiring 15 to wiring 16.

[0051] As described above, when signal OUT is at a high level, the potential of the gate of transistor 114 becomes less than VL1, so the Vgs of transistor 114 can be made a negative value . Therefore, even if transistor 114 is a depletion type, transistor 1 14 can be turned off. Or, even if transistor 114 is a transistor with a large drain current when Vgs is 0 [V] , the drain current of transistor 114 can be made small. Therefore, the gate of transistor 111 can be set in a floating state , and malfunction of circuit 110 can be prevented.

[0052] Also, similar to transistor 114, the Vgs of transistor 112 can also be made a negative value . Therefore, even if transistor 112 is a depletion type, transistor 112 can be turned off. Or, even if transistor 112 is a transistor with a large drain current when Vgs is 0 [V ], the drain current of transistor 112 can be made small. Therefore, the current flowing from wiring 16 to wiring 13 can be prevented or suppressed, so power consumption can be reduced.

[0053] Also, when signal OUT is at a low level, the potential of the gates of transistor 112 and transistor 114 becomes a potential less than VH, so transistor 112 and transistor The Vgs of transistor 114 can be decreased. Therefore, deterioration of transistor 112 and transistor 114 can be suppressed.

[0054] As described above, the driving method of the semiconductor device in Fig. 1(A) has been explained.

[0055] Next, a semiconductor device different from that in Fig. 1(A) will be described with reference to Figs. 2(A), 2(B), 3(A ), 3(B), 4(A), 4(B), 5(A), and 5(B). Hereinafter, the parts different from those in Fig. 1(A) will be described.

[0056] As shown in Fig. 2(A), in the semiconductor device of Fig. 1(A), wiring 14 may be omitted, and the first terminal of transistor 102 may be connected to wiring 13. Then, potential VL2 may be supplied to wiring 13 during period T0, and potential VL1 may be supplied to wiring 13 during period T1. Even in this case, since potential VL2 can be supplied to the other electrode of capacitor element 101 during period T0, the same operation as that of the semiconductor device in Fig. 1(A) can be performed. Therefore, the same effect as that of the semiconductor device in Fig. 1(A) can be achieved. Also, since wiring 14 can be omitted, the number of wirings can be reduced as compared with the semiconductor device in Fig. 1(A).

[0057] In the semiconductor device of Fig. 2(A), during period T0, the potential of wiring 13 may be kept at potential VL1, and the potential of wiring 11 may be set to a potential exceeding potential VL1 and less than potential VH. Even in this case, when signal IN is at a low level during period T1, the potential of the other electrode of capacitor element 101 can be made less than potential VL1. Therefore, the same operation as that of the semiconductor device in Fig. 1(A) can be performed. Thus, the same effect as that of the semiconductor device in Fig. 1(A) can be achieved. ​ This is possible. Also, since the power supply potential can be made constant, the configuration of a power supply circuit or the like that supplies potential to the wiring 13 can be simplified.

[0058] As shown in FIG. 2(B), in the semiconductor device of FIG. 1(A), the wiring 14 may be omitted, and the first terminal of the transistor 102 may be connected to the wiring 15. Then, a potential VL2 may be supplied to the wiring 15 during the period T0, and a potential VH may be supplied to the wiring 15 during the period T1. Even in this case, since a potential VL2 can be supplied to the other electrode of the capacitive element 101 during the period T0, the same operation as that of the semiconductor device of FIG. 1(A) can be performed. Therefore, the same effects as those of the semiconductor device of FIG. 1(A) can be achieved. Also, since the wiring 14 can be omitted, the number of wirings can be reduced as compared with the semiconductor device of FIG. 1(A).

[0059] As shown in FIG. 3(A), in the semiconductor device of FIG. 1(A), the wiring 14 may be omitted, the first terminal of the transistor 102 may be connected to the wiring 12, and the second terminal and the gate of the transistor 102 may be connected to the other electrode of the capacitive element 101. Then, the signal SE may be set to a low level during the period T0, and the signal SE may be set to a high level during the period T1. Even in this case, since the other electrode of the capacitive element 101 can be made less than the potential VL1 during the period T0, the same operation as that of the semiconductor device of FIG. 1(A) can be performed. Therefore, the same effects as those of the semiconductor device of FIG. 1(A) can be achieved. Also, since the wiring 14 can be omitted, the number of wirings can be reduced as compared with the semiconductor device of FIG. 1(A).

[0060] As shown in FIG. 3(B), in the semiconductor device of FIG. 1(A), wiring 12 and wiring 14 are omitted, the first terminal of transistor 102 is connected to wiring 13, and the second terminal and the gate of transistor 102 may be connected to the other electrode of capacitor element 101. Then, during period T0, potential VL2 is supplied to wiring 13, and during period T1, potential VL1 is supplied to wiring 13. Even in this case, since the other electrode of capacitor element 101 can be made less than potential VL1 during period T0, the same operation as that of the semiconductor device of FIG. 1(A) can be performed . Therefore, the same effect as that of the semiconductor device of FIG. 1(A) can be achieved. Also, since wiring 12 and wiring 14 can be omitted, the number of wirings can be reduced as compared with the semiconductor device of FIG. 1(A).

[0061] As shown in FIG. 4(A), in the semiconductor device of FIG. 1(A), wiring 12 and wiring 14 are omitted, the first terminal of transistor 102 is connected to wiring 15, and the second terminal and the gate of transistor 102 may be connected to the other electrode of capacitor element 101. Then, during period T0, potential VL2 is supplied to wiring 15, and during period T1, potential VH is supplied to wiring 15 . Even in this case, since the other electrode of capacitor element 101 can be made less than potential VL1 during period T0, the same operation as that of the semiconductor device of FIG. 1(A) can be performed. Therefore, the same effect as that of the semiconductor device of FIG. 1(A) can be achieved. Also, since wiring 12 and wiring 14 can be omitted, the number of wirings can be reduced as compared with the semiconductor device of FIG. 1(A).

[0062] As shown in FIG. 4(B), in the semiconductor device of FIG. 1(A), the gate of transistor 112 ート may be connected to wiring 11. In the semiconductor device of FIG. 4(B), transistor 112 The timing for supplying the potential VL1 of wiring 13 to wiring 16 is controlled by signal IN. Since signal IN has shorter fall time and rise time than signal INO, compared with the case where the gate of transistor 112 is connected to the other electrode of capacitive element 101, the timing at which transistor 112 turns on or off can be advanced. Therefore, the timing for supplying the potential VL1 of wiring 13 to wiring 16 also becomes earlier, so the fall time of signal OUT can be shortened. Also, when the timing at which transistor 112 turns off becomes earlier , the time during which the through-current between wiring 15 and wiring 13 occurs can be shortened, so power consumption can be reduced.

[0063] Note that, similar to the semiconductor device of FIG. 4(B), in the semiconductor devices of FIGS. 2(A), 2(B), 3(A), 3 (B), and 4(A), the gate of transistor 112 may also be connected to wiring 1 1. Even in this case, the same effects as those of the semiconductor device of FIG. 4(B) can be achieved.

[0064] As shown in FIG. 5(A), in the semiconductor device of FIG. 1(A), a first terminal is connected to wiring 13 , a second terminal is connected to the gate of transistor 111, and a transistor 115 whose gate is connected to wiring 12 may be provided. Transistor 115 has a function of supplying the potential V L1 of wiring 13 to the gate of transistor 111. The timing at which transistor 115 supplies the potential VL1 to the gate of transistor 111 is controlled by the signal SE on wiring 12. In the semiconductor device of FIG. 5(A), during period T0, the potential VL1 of wiring 13 Since it can be supplied to the gate of the transistor 111, the semiconductor device can be initialized. Thus, malfunction of the semiconductor device can be prevented.

[0065] In the semiconductor device of FIG. 5(A), the first terminal of the transistor 115 may be connected to the wiring 14. Even in this case, the same operation as the case where the first terminal of the transistor 115 is connected to the wiring 13 can be performed.

[0066] When the timing for acquiring the offset voltage is different from the timing for performing initialization, the gate of the transistor 115 may be connected to the wiring to which the initialization signal is input.

[0067] In the semiconductor devices of FIGS. 2(A), 2(B), 3(A), 3(B), 4(A) and 4(B) as well, a transistor 115 may be provided in which the first terminal is connected to the wiring 13 or the wiring 14, the second terminal is connected to the gate of the transistor 111, and the gate is connected to the wiring 12. Even in this case, the same effect as the semiconductor device of FIG. 5(A) can be achieved.

[0068] As shown in FIG. 5(B), in the semiconductor device of FIG. 1(A), the second terminal and the gate of the transistor 113 may be connected to the wiring 17. The potential VH may be supplied to the wiring 17, a potential exceeding the potential VL1 and less than the potential VH may be supplied, or a signal may be input. An example of the signal input to the wiring 17 is the inverted signal of the signal IN. Therefore, the wiring 11 may be connected to the wiring 17 via an inverter circuit. In this way, when the transistor 114 is turned on, the transistor 113 is turned off, so that when the wiring 15 and the wiring 13 ​​​​​​​ It is possible to prevent current from flowing between them. Therefore, power consumption can be reduced. In addition, since it is not necessary to make the W / L ratio of transistor 114 sufficiently larger than the W / L ratio of transistor 113, the size of the transistor can be reduced. .

[0069] Note that in the semiconductor devices of FIGS. 2(A), 2(B), 3(A), 3(B), 4(A), 4(B), and 5(A) as well, the second terminal and the gate of transistor 113 may be connected to wiring 17. Even in this case, the same effects as those of the semiconductor device of FIG. 5(B) can be obtained.

[0070] As shown in FIG. 22(A), in the semiconductor device of FIG. 1(A), wiring 14 is omitted, the first terminal of transistor 102 is connected to wiring 13, and a capacitor element 103 may be provided in which one electrode is connected to wiring 12 and the other electrode is connected to the other electrode of capacitor element 101. Capacitor element 103 has a function of holding the potential difference between wiring 12 and the other electrode of capacitor element 101. Further, in the semiconductor device of FIG. 22(A), transistor 102 has a function of supplying the potential VL1 of wiring 13 to the other electrode of capacitor element 101. In the semiconductor device of FIG. 22(A), during period T0, a low-level signal IN is input to one electrode of capacitor element 101, and the potential VL1 of wiring 13 is supplied to the other electrode of capacitor element 101 by transistor 102. Then, when signal SE changes from high level to low level, transistor 102 turns off, and the potential of the other electrode of capacitor element 101 decreases from potential VL1 due to the capacitive coupling of capacitor element 103. Therefore, during period T0, the other electrode of capacitor element 101 Since the electrode can be set to a potential lower than VL1, the same operation as that of the semiconductor device in Fig. 1(A) can be performed. Therefore, the same effect as that of the semiconductor device in Fig. 1(A) can be achieved. Also, since wiring 14 can be omitted, the number of wirings can be reduced compared to the semiconductor device in Fig. 1(A). Moreover, since the potential VL2 is not required, the number of power supply potentials can be reduced.

[0071] As shown in Fig. 22(B), in the semiconductor device of Fig. 22(A), the first terminal of transistor 102 may be connected to wiring 11. Even in this case, during period T0, the low-level signal IN can be supplied to the other electrode of capacitor element 101 by transistor 102. Therefore, the same operation as that of the semiconductor device in Fig. 22(A) can be performed. Thus, the same effect as that of the semiconductor device in Fig. 22(A) can be achieved.

[0072] Note that in the semiconductor devices of Fig. 22(A) and Fig. 22(B), capacitor element 103 may be omitted. In this case, instead of capacitor element 103, the parasitic capacitance between the gate of transistor 102 and the second terminal may be used.

[0073] Note that in the semiconductor devices of Fig. 22(A) and Fig. 22(B), one electrode of capacitor element 103 may be connected to a new wiring different from wiring 12. The signal input to this wiring is preferably a signal that changes from high level to low level after signal SE changes from high level to low level during period T0. The timing to reach the high level is preferably during the period when the signal SE is at the high level. Yes.

[0074] In addition, in the semiconductor devices of FIGS. 2(A), 2(B), 3(A), 3(B), 4(A), 4(B), 5(A) and 5(B), the wiring 14 may be omitted, and the first terminal of the transistor 1 02 may be connected to the wiring 11 or the wiring 13, and a capacitor element 103 may be provided in which one electrode is connected to the wiring 12 and the other electrode is connected to the other electrode of the capacitor element 101. .

[0075] Although not shown, in the semiconductor devices of FIGS. 2(A), 2(B), 3(A), 3(B), 4(A), 4(B), 5(A), 5(B), 22(A) and 22(B), a capacitor element may be connected between the gate and the second terminal of the transistor 111. In this way, the capacitance value between the wiring 16 and the node N1 can be increased. Therefore, compared with the case where no capacitor element is provided between the gate and the second terminal of the transistor 111, the node N1 can be made higher during the period when the signal IN is at the low level. That is, the Vgs of the transistor 111 can be increased. Therefore, the drain current of the transistor 1 11 can be increased, and the rising time of the signal OUT can be shortened. That is, the drain current of the transistor 111 can be increased, and the rising time of the signal OUT can be shortened. That is possible.

[0076] Although not shown, in the semiconductor devices of FIGS. 2(A), 2(B), 3(A), 3(B), 4(A), 4(B), 5(A), 5(B), 22(A) and 22(B), a MOS capacitor may be used as the capacitor element 101. In this case, when used as a MOS capacitor, Connect the gate of the transistor to wiring 11, and connect the source or drain of the transistor to the second terminal of transistor 102. This is preferable. In this case, since the potential of wiring 11 is higher than the potential of the second terminal of transistor 102, the capacitance value per unit area can be increased.

[0077] Above, a semiconductor device having a configuration different from that of FIG. 1(A) has been described.

[0078] Note that the larger the W / L ratio of transistor 111, the shorter the rise time of signal OUT can be made. Therefore, the W / L ratio of transistor 111 is preferably the largest among the transistors included in the semiconductor device. That is, the W / L ratio of transistor 111 is preferably larger than the W / L ratio of transistor 102, the W / L ratio of transistor 112, the W / L ratio of transistor 11 3, and the W / L ratio of transistor 114.

[0079] Note that transistor 112 supplies a potential to the load connected to wiring 16, while transistor 114 supplies a potential to the gate of transistor 111. Also, the larger the W / L ratio of transistor 112, the shorter the fall time of signal OUT can be made. Therefore, the W / L ratio of transistor 112 is preferably larger than the W / L ratio of transistor 114.

[0080] Note that since transistor 102 only needs to supply charge to the other electrode of capacitor element 101 during period T0, there is no need to increase the W / L ratio of transistor 102. Therefore, the W / L ratio of transistor 102 is preferably smaller than the W / L ratio of transistor 112 or transistor 114. ​​​​​

[0081] Note that, the larger the capacitance value of the capacitive element 101 is than the sum of the gate capacitances of the transistor 112 and the transistor 1 14, the closer the amplitude voltage of the signal INO can be to the amplitude voltage of the signal IN. Therefore, the capacitance value of the capacitive element 101 is preferably larger than the sum of the gate capacitances of the transistor 112 and the transistor 114. Also, when one electrode of the capacitive element 101 is made of the same material as the gate electrode of the transistor and the other electrode of the capacitive element 10 1 is made of the same material as the source electrode or the drain electrode of the transistor, the overlapping area between one electrode and the other electrode of the capacitive element 101 is preferably larger than the sum of the overlapping area between the gate and the source of the transistor 112, the overlapping area between the gate and the drain of the transistor 112, the overlapping area between the gate and the source of the transistor 114, and the overlapping area between the gate and the drain of the transistor 114. Note that, during the period T0, the wiring 13 may be left floating without supplying the potential VL1 to the wiring 13. Or, during the period T0, the wiring 15 may be left floating without supplying the potential VH to the wiring 15. By doing so, malfunction during the period T0 can be prevented. Note that, during the period T1, the wiring 14 may be left floating without supplying the potential VL2 to the wiring 14. Note that, during the period when the signal IN is at the high level, a low-level signal may be input to the wiring 15. By doing so, when the transistor 114 turns on, the transistor 11 1 is made of the same material as the source electrode or the drain electrode of the transistor, the overlapping area between one electrode and the other electrode of the capacitive element 101 is preferably larger than the sum of the overlapping area between the gate and the source of the transistor 112, the overlapping area between the gate and the drain of the transistor 112, the overlapping area between the gate and the source of the transistor 114, and the overlapping area between the gate and the drain of the transistor 114. 1 is made of the same material as the source electrode or the drain electrode of the transistor, the overlapping area between one electrode and the other electrode of the capacitive element 101 is preferably larger than the sum of the overlapping area between the gate and the source of the transistor 112, the overlapping area between the gate and the drain of the transistor 112, the overlapping area between the gate and the source of the transistor 114, and the overlapping area between the gate and the drain of the transistor 114. 1 is made of the same material as the source electrode or the drain electrode of the transistor, the overlapping area between one electrode and the other electrode of the capacitive element 101 is preferably larger than the sum of the overlapping area between the gate and the source of the transistor 112, the overlapping area between the gate and the drain of the transistor 112, the overlapping area between the gate and the source of the transistor 114, and the overlapping area between the gate and the drain of the transistor 114. 1 is made of the same material as the source electrode or the drain electrode of the transistor, the overlapping area between one electrode and the other electrode of the capacitive element 101 is preferably larger than the sum of the overlapping area between the gate and the source of the transistor 112, the overlapping area between the gate and the drain of the transistor 112, the overlapping area between the gate and the source of the transistor 114, and the overlapping area between the gate and the drain of the transistor 114.

[0082] Note that, during the period T0, the wiring 13 may be left floating without supplying the potential VL1 to the wiring 13. Or, during the period T0, the wiring 15 may be left floating without supplying the potential VH to the wiring 15. By doing so, malfunction during the period T0 can be prevented. Note that, during the period T0, the wiring 13 may be left floating without supplying the potential VL1 to the wiring 13. Or, during the period T0, the wiring 15 may be left floating without supplying the potential VH to the wiring 15. By doing so, malfunction during the period T0 can be prevented. Note that, during the period T0, the wiring 13 may be left floating without supplying the potential VL1 to the wiring 13. Or, during the period T0, the wiring 15 may be left floating without supplying the potential VH to the wiring 15. By doing so, malfunction during the period T0 can be prevented.

[0083] Note that, during the period T1, the wiring 14 may be left floating without supplying the potential VL2 to the wiring 14. Note that, during the period T1, the wiring 14 may be left floating without supplying the potential VL2 to the wiring 14.

[0084] Note that, during the period when the signal IN is at the high level, a low-level signal may be input to the wiring 15. By doing so, when the transistor 114 turns on, the transistor 11 Note that, during the period when the signal IN is at the high level, a low-level signal may be input to the wiring 15. By doing so, when the transistor 114 turns on, the transistor 11 Since the transistor 3 is turned off, it is possible to prevent a current from flowing between the wiring 15 and the wiring 13. Therefore, the power consumption can be reduced. Since the W / L ratio of the transistor 114 does not need to be sufficiently large, the transistor The size of the transistor can be reduced.

[0085] This embodiment mode can be implemented in appropriate combination with other embodiment modes, etc.

[0086] (Embodiment 2) In this embodiment, a semiconductor device according to one embodiment of the present invention is used in a shift register circuit. The case where the present invention is used in a flip-flop circuit will be described. The differences from embodiment 1 will be explained below.

[0087] The semiconductor device of this embodiment will be described with reference to FIG. A circuit diagram of a semiconductor device according to this embodiment is shown. A first terminal of the transistor 111 is connected to the wiring 23, and a gate of the transistor 113 is connected to the wiring 21. 1A, one electrode of the capacitor 101 is connected to the wiring 22. This is different from the semiconductor device.

[0088] A signal IN1 is input to the wiring 21. The signal IN1 is an input signal of the semiconductor device. A signal that functions as a start pulse. For example, signal IN1 is a digital signal, and signal The high level potential of the signal IN1 is VH, and the low level potential of the signal IN1 is VL1. The wiring 21 has a function of transmitting a signal IN1.

[0089] A signal IN2 is input to the wiring 22. The signal IN2 is an input signal of the semiconductor device, and is a signal that functions as a reset signal. For example, the signal IN2 is a digital signal, and the high-level potential of the signal IN2 is VH, and the low-level potential of the signal IN2 is VL1. Note that the wiring 22 has a function of transmitting the signal IN2.

[0090] A signal CK is input to the wiring 23. The signal CK is an input signal of the semiconductor device. For example, the signal CK is a digital signal, the high-level potential of the signal CK is VH, and the low-level potential of the signal CK is VL1. Also, the signal CK is a clock signal that repeats between a high level and a low level. Note that the wiring 23 has a function of transmitting the signal CK.

[0091] Note that the wirings 21, 22, and 23 are also called signal lines. In particular, the wiring 23 is also called a clock signal line.

[0092] Next, an example of a driving method of the semiconductor device in FIG. 6(A) will be described with reference to FIG. 7. FIG. 7 is an example of a timing chart for explaining the driving method of the semiconductor device in FIG. 6(A). It is.

[0093] In period T0, with the signal IN2 at the low level, the potential of one electrode of the capacitor element 101 is set to VL1. Also, with the signal SE at the high level, the transistor 102 is turned on. Then, the potential VL2 of the wiring 14 is supplied to the other electrode of the capacitor element 101, and the potential of the other electrode of the capacitor element 101 is set to VL2. Thus, in the capacitor element 101, the potential VL1 of the low level of the signal IN2 and the potential VL2 of the wiring 14 supplied by the transistor 102 are combined. The difference (VL1-VL2) is maintained. This difference (VL1-VL2) corresponds to the offset voltage. do.

[0094] In the period T1, the signal SE is set to a low level to turn off the transistor 102. During the period T0, the other electrode of the capacitor 101 is in a floating state. Since the potential difference VL1-VL2 is maintained, the signal IN2 is Therefore, when the signal IN2 goes low, the signal IN2O is generated. Then, the signal IN2O also goes low, and the potential of the low level of the signal IN2O is lower than VL1. When the signal IN2 becomes high level, the signal IN2O also becomes high level. The high-level potential of the signal IN2O becomes a potential lower than VH.

[0095] Regarding the method of driving the semiconductor device of FIG. 6A in the period T1, The period Tc and the period Td will be described separately.

[0096] During the period Ta, the signal IN2 becomes low level, and the signal IN2O also becomes low level. The transistor 112 and the transistor 114 are turned off. Since the potential VH of the wiring 15 becomes low, the transistor 113 is turned on. Since the potential of the node N1 is supplied to the node N1, the potential of the node N1 rises. Then, the transistor 111 is turned on, and the signal CK on the wiring 23 is supplied to the wiring 16. During the period Ta, the signal CK is at a low level, so the signal OUT is at a low level. In addition, when the potential of the node N1 is changed from VH to the threshold voltage of the transistor 113, the potential of the node N1 is changed to VL1. When the potential of the node N1 rises to the potential lower than the potential of the node N1, the transistor 113 is turned off. becomes floating. Also, when the transistor 113 is turned off, the potential difference between the node N1 and the wiring 1 6 is held between the gate of the transistor 111 and the second terminal.

[0097] During the period Tb, since the signal IN2 remains at the low level, the signal IN2O also remains at the low level and the transistors 112 and 114 remain off. Also, since the signal IN1 becomes low level, the transistor 113 remains off. Therefore, the node N1 remains floating. Also, since the potential of the node N1 keeps the potential in the period Ta , the transistor 111 remains on and the signal CK on the wiring 23 remains supplied to the wiring 1 6. In the period Tb, since the signal CK becomes high level, the potential of the wiring 16 rises. At this time, between the gate of the transistor 111 and the second terminal, the potential difference between the node N1 and the wiring 16 in the period Ta is held. Therefore, with the potential of the wiring 1 6, the potential of the node N1 further rises and becomes higher than VH. Therefore, the signal OUT becomes high level and its potential becomes VH.

[0098] In the period Tc, since the signal IN2 becomes high level and the signal IN2O becomes high level , the transistors 112 and 114 turn on. Therefore, the potential VL1 of the wiring 13 is supplied to the wiring 16 by the transistor 112 and further supplied to the node N1 by the transistor 114 . Also, since the signal IN1 remains at the low level, the transistor 113 remains off. Therefore, the potential of the node N1 becomes VL1 and the transistor 111 turns off. Therefore, the signal OUT becomes low level and its potential becomes VL1 . .

[0099] During the period Td, since the signal IN2 becomes low level and the signal IN2O becomes low level, the transistors 112 and 114 turn off. Also, since the signal IN1 remains low level, the transistor 113 remains off. Therefore, the node N1 maintains the potential VL1 at the period Tc, and the transistor 111 turns off. Also, since the wiring 16 maintains the potential VL1 at the period Tc, the signal OUT remains low level.

[0100] As described above, when the signal IN2 is at a low level, since the potential of the gate of the transistor 114 becomes less than VL1, the Vgs of the transistor 114 can be made a negative value. Therefore, even if the transistor 114 is a depletion type, the transistor 114 can be turned off. Or, even if the transistor 114 is a transistor with a large drain current when Vgs is 0 [V], the drain current of the transistor 114 can be made small. Therefore, the gate of the transistor 111 can be made in a floating state, and malfunction of the circuit 110 can be prevented.

[0101] Also, when the signal IN2 is at a high level, since the potential of the gates of the transistors 112 and 114 becomes a potential less than VH, the Vgs of the transistors 112 and 114 can be made small. Therefore, deterioration of the transistors 112 and 114 can be suppressed.

[0102]

[0103] The driving method of the semiconductor device in Fig. 6(A) has been described above.

[0103] Next, for a semiconductor device different from that in FIG. 6(A), it will be described with reference to FIGS. 6(B), 8(A), 8(B ), 9(A), 9(B) and 10(A). Also, hereinafter will describe the parts different from those in FIG. 6(A).

[0104] As shown in FIG. 6(B), in the semiconductor device of FIG. 6(A), the first terminal of the transistor 113 may be connected to the wiring 21. In the semiconductor device of FIG. 6(B), during the period Ta , the transistor 113 supplies the signal IN1 of the wiring 21 to the node N1. Since the signal IN1 is at a high level during the period Ta, the potential of the node N1 rises. Then, when the potential of the node N1 becomes a value obtained by subtracting the threshold voltage of the transistor 113 from VH, the transistor 1 13 turns off. Also, during the periods Tb, Tc and Td, the transistor 113 turns off. Therefore, the same operation as that of the semiconductor device of FIG. 6(A) can be performed. Thus it can achieve the same effect as the semiconductor device of FIG. 6(A). Also, since the wiring 15 can be omitted , the number of wirings can be reduced as compared with the semiconductor device of FIG. 6(A).

[0105] As shown in FIG. 8(A), in the semiconductor device of FIG. 6(B), instead of connecting the circuit 100 to the wiring 22 , it may be connected to the wiring 21. In the semiconductor device of FIG. 8(A), an offset is applied to the signal IN1 of the wiring 21 of the circuit 100, and the signal IN1O obtained by applying the offset to the signal IN1 is supplied to the gate of the transistor 113. One electrode of the capacitor element 101 is connected to the wiring 21 , and the other electrode of the capacitor element 101 is connected to the gate of the transistor 113. The first terminal of the transistor 102 is connected to the wiring 14, and the second terminal of the transistor 102 is connected to the capacitor ​It is connected to the other electrode of the capacitor element 101, and the gate of the transistor 102 is connected to the wiring 12. Also, the capacitor element 101 has a function of holding the potential difference between the wiring 21 and the gate of the transistor 113. The transistor 102 has a function of supplying the potential VL1 of the wiring 14 to the gate of the transistor 113. In the semiconductor device of Fig. 8(A), the Vgs of the transistor 113 can be set to a negative value. Therefore, without worrying about the amount of charge supplied to the node N1, the W / L ratio of the transistor 113 can be increased. Thus, during the period Ta, the time until the potential of the node N1 reaches a predetermined potential can be shortened, and the driving frequency can be increased. As shown in Fig. 8(B), in the semiconductor device of Fig. 6(B), the circuit 100 may be provided on the wiring 22, and may also be provided on the wiring 21. In Fig. 8(B), the circuit 100 provided on the wiring 22,

[0106] the capacitor element 101 and the transistor 102 included in the circuit 100 are respectively denoted as circuit 10 0A, capacitor element 101A, and transistor 102A. Also, the circuit 100 provided on the wiring 21, the capacitor element 101 and the transistor 102 included in the circuit 100 are respectively denoted as circuit 100B, capacitor element 101B, and transistor 102B. The circuit 100A is the same as the circuit 100 shown in Fig. 6(A), and the circuit 100B is the same as the circuit 100 shown in Fig. 8(A). Therefore, the description thereof is omitted. In the semiconductor device of Fig. 8(B), the same effects as those of the semiconductor device of Fig. 6(B) and the same effects as those of the semiconductor device of Fig. 8(A) can be achieved. As shown in Fig. 9(A), in the semiconductor device of Fig. 6(A), the gate of the transistor 112

[0107] ート may be connected to wiring 24. Signal IN3 is input to wiring 24. Wiring 24 has a function of transmitting signal IN3. Signal IN3 is a digital signal. The high-level potential of signal IN3 is VH, and the low-level of signal IN3 is VL1. Also, as signal IN3, there is a clock signal which is the inverted signal of signal CK or a clock signal with a phase shift from signal CK. In the semiconductor device of Fig. 9(A), during period Td, since transistor 112 repeats on and off, the potential VL1 of wiring 13 can be periodically supplied to wiring 16, and it can be made easier to maintain the potential of wiring 16 at VL1.

[0108] Note that in the semiconductor devices of Fig. 6(B), Fig. 8(A), and Fig. 8(B) as well, the gate of transistor 112 may be connected to wiring 24. Even in this case, the same effect as the semiconductor device of Fig. 9(A) can be achieved.

[0109] Note that in the semiconductor devices of Fig. 6(A), Fig. 6(B), Fig. 8(A), and Fig. 8(B), a transistor may be provided where the first terminal is connected to wiring 13, the second terminal is connected to wiring 16, and the gate is connected to wiring 24. Even in this case, the same effect as the semiconductor device of Fig. 9(A) can be achieved.

[0110] As shown in Fig. 9(B), in the semiconductor device of Fig. 6(A), a transistor 116 may be provided where the first terminal is connected to wiring 23, the second terminal is connected to wiring 25, and the gate is connected to the gate of transistor 111. Transistor 116 has a function of supplying the signal CK of wiring 23 to wiring 25. When transistor 116 supplies the signal of wiring 23 to wiring 25 The timing for supplying CK is controlled by the potential of node N1. Also, the transistor 116 has a function of holding the potential difference between wiring 25 and node N1. Also, from the wiring 25, a signal OUT is output. The wiring 25 has a function of transmitting the signal OUT. In addition, in FIG. 9(B), the signal OUT output from the wiring 16 is shown as signal OUTA, and the signal OUT output from the wiring 25 is shown as signal OUTB. The signal OUTA is a signal in which the high level and the low level are inverted at the same timing as the signal OUTB. In the semiconductor device of FIG. 9(B), one of the signal OUTA and the signal OUTB is used as a transfer signal for the shift register, and the other of the signal OUTA and the signal OUTB can be used as a drive signal for a load or the like. Therefore, by using the semiconductor device of FIG. 9(B) as a flip-flop circuit, even when driving a large load, it can operate normally. In addition, in the semiconductor devices of FIGS. 6(B), 8(A), 8(B), and 9(A) as well, a transistor 116 may be provided in which the first terminal is connected to the wiring 23, the second terminal is connected to the wiring 25, and the gate is connected to the gate of the transistor 111. Even in this case, the same effect as that of the semiconductor device of FIG.

[0111] 9(B) can be achieved. As shown in FIG. 10(A), in the semiconductor device of FIG. 6(A), a circuit 120 for generating a signal IN2 may be provided. The circuit 120 is connected to node N1, the wiring 12, and one electrode of the capacitive element 1 01. The circuit 120 has a function of generating a signal IN2 corresponding to the signals SE of node N1 and the wiring 12 and outputting the signal IN2 to one electrode of the capacitive element 101. Even in this case, the same effect as that of the semiconductor device of FIG. 9(B) can be achieved.

[0112] As shown in FIG. 10(A), in the semiconductor device of FIG. 6(A), a circuit 120 for generating a signal IN2 may be provided. The circuit 120 is connected to node N1, the wiring 12, and one electrode of the capacitive element 1 01. The circuit 120 generates a signal IN2 corresponding to the signals SE of node N1 and the wiring 12, and has a function of outputting the signal IN2 to one electrode of the capacitive element 101. Even in this case, the same effect as that of the semiconductor device of FIG. 9(B) can be achieved. For example, when the signal SE is at a high level, the circuit 120 sets the signal IN2 to a low level regardless of the potential of the node N1. Also, when the signal SE is at a low level, the circuit 120 sets the signal IN2 to a low level when the potential of the node N1 is high (such as during period Ta, period Tb, etc.), and sets the signal IN2 to a high level when the potential of the node N1 is low (such as during period Tc, period Td, etc.). That is, the circuit 120 has the function of a NOR circuit. Note that the circuit 120 may be connected to the wiring 16 instead of the node N1. In addition, in the semiconductor devices of FIGS. 6(B), 8(A), 8(B), 9(A), and 9(B), a circuit 120 for generating the signal IN2 may also be provided. Although not shown, in the semiconductor devices of FIGS. 6(A), 6(B), 8(A), 8(B), 9(A), 9(B), and 10(A), the second terminal of the transistor 102 may be connected to the wiring 13 in the same manner as in the semiconductor device of FIG. 2(A). Even in this case, the same effect as that of the semiconductor device of FIG. 2(A) is achieved. Although not shown, in the semiconductor devices of FIGS. 6(A), 6(B), 8(A), 8(B), 9(A), 9(B), and 10(A), the second terminal of the transistor 102 may be connected to the wiring 15 in the same manner as in the semiconductor device of FIG. 2(B). Even in this case, the same effect as that of the semiconductor device of FIG. 2(B) is achieved.

[0113]

[0114]

[0115]

[0116]

[0117] ​​​​​​​​​​​​In the semiconductor devices of FIGS. 9(B) and 10(A), similar to the semiconductor device of FIG. 3(A), the first terminal of the transistor 102 may be connected to the wiring 12, and the gate of the transistor 102 may be connected to the second terminal of the transistor 102. Even in this case, the same effects as those of the semiconductor device of FIG. 3(A) are achieved. Connect the first terminal of the transistor 102 to the wiring 12, and the gate of the transistor 102 may be connected to the second terminal of the transistor 102. Even in this case, the same effects as those of the semiconductor device of FIG. 3(A) are achieved. Even in this case, the same effects as those of the semiconductor device of FIG. 3(A) are achieved.

[0118] Although not shown, in the semiconductor devices of FIGS. 6(A), 6(B), 8(A), 8(B), 9(A), 9(B) and 10(A), similar to the semiconductor device of FIG. 3(B), the first terminal of the transistor 102 may be connected to the wiring 13, and the gate of the transistor 102 may be connected to the second terminal of the transistor 102. Even in this case, the same effects as those of the semiconductor device of FIG. 3(B) are achieved. Although not shown, in the semiconductor devices of FIGS. 6(A), 6(B), 8(A), 8(B), 9(A), 9(B) and 10(A), similar to the semiconductor device of FIG. 3(B), the first terminal of the transistor 102 may be connected to the wiring 13, and the gate of the transistor 102 may be connected to the second terminal of the transistor 102. Even in this case, the same effects as those of the semiconductor device of FIG. 3(B) are achieved. Connect the first terminal of the transistor 102 to the wiring 13, and the gate of the transistor 102 may be connected to the second terminal of the transistor 102. Even in this case, the same effects as those of the semiconductor device of FIG. 3(B) are achieved. Even in this case, the same effects as those of the semiconductor device of FIG. 3(B) are achieved.

[0119] Although not shown, in the semiconductor devices of FIGS. 6(A), 6(B), 8(A), 8(B), 9(A), 9(B) and 10(A), similar to the semiconductor device of FIG. 4(A), the first terminal of the transistor 102 may be connected to the wiring 15, and the gate of the transistor 102 may be connected to the second terminal of the transistor 102. Even in this case, the same effects as those of the semiconductor device of FIG. 4(A) are achieved. Although not shown, in the semiconductor devices of FIGS. 6(A), 6(B), 8(A), 8(B), 9(A), 9(B) and 10(A), similar to the semiconductor device of FIG. 4(A), the first terminal of the transistor 102 may be connected to the wiring 15, and the gate of the transistor 102 may be connected to the second terminal of the transistor 102. Even in this case, the same effects as those of the semiconductor device of FIG. 4(A) are achieved. Connect the first terminal of the transistor 102 to the wiring 15, and the gate of the transistor 102 may be connected to the second terminal of the transistor 102. Even in this case, the same effects as those of the semiconductor device of FIG. 4(A) are achieved. Even in this case, the same effects as those of the semiconductor device of FIG. 4(A) are achieved.

[0120] Although not shown, in the semiconductor devices of FIGS. 6(A), 6(B), 8(A), 8(B), 9(A), 9(B) and 10(A), similar to the semiconductor device of FIG. 4(B), the gate of the transistor 112 may be connected to one electrode of the capacitor element 101. Even in this case, the same effects as those of the semiconductor device of FIG. 4(B) are achieved. Although not shown, in the semiconductor devices of FIGS. 6(A), 6(B), 8(A), 8(B), 9(A), 9(B) and 10(A), similar to the semiconductor device of FIG. 4(B), the gate of the transistor 112 may be connected to one electrode of the capacitor element 101. Even in this case, the same effects as those of the semiconductor device of FIG. 4(B) are achieved. The gate of the transistor 112 may be connected to one electrode of the capacitor element 101. Even in this case, the same effects as those of the semiconductor device of FIG. 4(B) are achieved.

[0121] Although not shown, in the semiconductor devices of FIGS. 6(A), 6(B), 8(A), 8(B), 9(A), 9(B) and 10(A) In the semiconductor devices of FIGS. 9(B) and 10(A), similar to the semiconductor device of FIG. 5(A), the first terminal of 1 is connected to wiring 13, the second terminal is connected to the gate of transistor 111, and a transistor 115 may be provided whose gate is connected to wiring 12. Even in this case, the same effects as those of the semiconductor device of FIG. 5(A) are achieved.

[0122] Although not shown, in the semiconductor devices of FIGS. 6(A), 6(B), 8(A), 8(B), 9(A), FIGS. 9(B) and 10(A), similar to the semiconductor devices of FIGS. 22(A) and 22(B), wiring 14 may be omitted, the first terminal of transistor 102 may be connected to wiring 22 or wiring 13, and a capacitor element 103 may be provided in which one electrode is connected to wiring 12 and the other electrode is connected to the other electrode of capacitor element 101. Even in this case, the same effects as those of the semiconductor devices of FIGS. 22(A) and 22(B) are achieved.

[0123] The semiconductor device of the present embodiment having a configuration different from that of FIG. 6(A) has been described above.

[0124] Next, a specific example of circuit 120 will be described.

[0125] FIG. 10(B) shows a circuit diagram of circuit 120. Circuit 120 includes transistors 121, transistor 122, and transistor 123. The first terminal of transistor 121 is connected to wiring 15, the second terminal of transistor 121 is connected to one electrode of capacitor element 101, and the gate of transistor 121 is connected to wiring 15. The first terminal of transistor 122 is connected to wiring 13, the second terminal of transistor 122 is connected to one electrode of capacitor element 101, and the gate of transistor 122 is connected to The first terminal of the transistor 123 is connected to the wiring 13, and the second terminal of the transistor 123 is connected to one electrode of the capacitive element 101, and the gate of the transistor 123 is connected to the wiring 12. is allowed.

[0126] The transistor 121 has a function of supplying the potential VH of the wiring 15 to one electrode of the capacitive element 101. The transistor 122 has a function of supplying the potential VL1 of the wiring 13 to one electrode of the capacitive element 101. The transistor 123 has a function of supplying the potential VL1 of the wiring 13 to one electrode of the capacitive element 101. Note that the timing at which the transistor 122 supplies the potential VL1 of the wiring 13 to one electrode of the capacitive element 101 is controlled by the potential of the node N1. The timing at which the transistor 123 supplies the potential VL1 of the wiring 13 to one electrode of the capacitive element 101 is controlled by the signal SE of the wiring 12.

[0127] During the period T0, since the signal SE is at a high level, the transistor 123 turns on. Therefore, regardless of whether the transistor 122 is on or off, the potential VL1 of the wiring 13 is supplied to one electrode of the capacitive element 101 by the transistor 123, so the signal IN2 becomes a low level.

[0128] During the period T1, since the signal SE is at a low level, the transistor 123 turns off. Therefore, when the potential of the node N1 becomes high and the transistor 122 turns on, the potential VL1 of the wiring 13 is supplied to one electrode of the capacitive element 101 by the transistor 122, so the signal IN2 becomes a low level. On the other hand, when the potential of the node N1 becomes low and the When the transistor 122 is turned off, the potential VL1 of the wiring 13 is not supplied to one of the electrodes of the capacitor element 101, so that the signal IN2 becomes high level.

[0129] As shown in Fig. 10(C), in the circuit 120 of Fig. 10(B), transistors 124, transistor 125 and transistor 126 may be provided. The first terminal of the transistor 124 is connected to the wiring 15, the second terminal of the transistor 124 is connected to one of the electrodes of the capacitor element 101, and the gate of the transistor 124 is connected to the second terminal of the transistor 121, the second terminal of the transistor 122, and the second terminal of the transistor 123. The first terminal of the transistor 125 is connected to the wiring 13, the second terminal of the transistor 125 is connected to one of the electrodes of the capacitor element 101, and the gate of the transistor 125 is connected to the node N1. The first terminal of the transistor 126 is connected to the wiring 13, the first terminal of the transistor 126 is connected to one of the electrodes of the capacitor element 101, and the gate of the transistor 126 is connected to the wiring 12. In the semiconductor device of Fig. 10(C), the high level potential of the signal IN2 can be set to VH using the bootstrap operation, and the low level potential of the signal IN2 can be set to VL1. level potential of the signal IN2 can be set to VL1. In the circuit 120 of Fig. 10(C), instead of the wiring 15, the wiring 23 may be used.

[0130] That is, the first terminal of the transistor 121, the gate of the transistor 121, and the first terminal of the transistor 124 may be connected to the wiring 23. In this way, during the period Td, the signal IN2 can be a signal that repeats between high level and low level. Therefore, during the period Td, the signal IN2 can be a signal that repeats between high level and low level. Therefore, Thus, the time for transistors 112 and 114 to turn on can be shortened Therefore, degradation of transistors 112 and 114 can be suppressed.

[0131] As described above, a specific example of circuit 120 has been explained.

[0132] Note that if signal IN2 is set to a high level during all or part of period Td , transistors 112 and 114 turn on. Thus, the potential of wiring 13 is supplied to wiring 16 by transistor 112, and further supplied to node N1 by transistor 114. Therefore, even during period Td, it becomes easier to maintain the potentials of wiring 16 and node N1 at VL1.

[0133] This embodiment can be implemented in appropriate combination with other embodiments etc.

[0134] (Embodiment 3) In this embodiment, a shift register circuit using the semiconductor device described in Embodiment 2 as a flip - flop circuit will be described. Note that in this embodiment, parts different from Embodiments 1 and 2 will be described.

[0135] The shift register circuit of this embodiment will be described with reference to FIG. 11. FIG. 11 shows a circuit diagram of the shift register circuit in this embodiment. The shift register circuit of FIG. 11 has N (N is a natural number) flip - flop circuits 200. However, in FIG. 11, only the first to third - stage flip - flop circuits 200 (shown as flip - flop circuit 200_1, flip - flop circuit 200_2, and flip - flop circuit 200_3) are shown.

[0136] In the shift register circuit of FIG. 11, as the flip-flop circuit 200, the semiconductor device of FIG. 6( A) is used. However, the flip-flop circuit 200 is not limited to the semiconductor device of FIG. 6( A), and the semiconductor device in Embodiment 2 can be appropriately used.

[0137] The connection relationship of the shift register circuit in FIG. 11 will be described. The flip-flop circuit 200 in the i-th (where i is any one of 2 to N-1) stage is connected to the wiring 31 in the i-th stage (denoted as wiring 31_i), the wiring 31 in the (i-1)-th stage (denoted as wiring 31_i-1), the wiring 31 in the (i+1)-th stage (denoted as wiring 31_i+1), the wiring 32, the wiring 33, the wiring 34, one of the wiring 35 and the wiring 36, and the wiring 37. Specifically, in the flip-flop circuit 200 in the i-th stage, the wiring 16 is connected to the wiring 31 in the i-th stage, the wiring 21 is connected to the wiring 31 in the (i-1)-th stage, and the wiring 22 is connected to the wiring 31 in the (i+1)-th stage. Also, the wiring 15 is connected to the wiring 32, the wiring 13 is connected to the wiring 33, the wiring 14 is connected to the wiring 34, the wiring 23 is connected to one of the wiring 35 and the wiring 36, and the wiring 12 is connected to the wiring 37. Note that, in the flip-flop circuit 200 in the first stage, the connection where the wiring 21 is connected to the wiring 38 is different from that of the flip-flop circuit 200 in the i-th stage.

[0138] A signal OUT is output from the wiring 31, and the wiring 31 has a function of transmitting the signal OUT.

[0139] A potential VH is supplied to the wiring 32, and the wiring 32 has a function of transmitting the potential VH.

[0140] ​​​​​A potential VL1 is supplied to wiring 33, and wiring 33 has a function of transmitting the potential VL1.

[0141] A potential VL2 is supplied to wiring 34, and wiring 34 has a function of transmitting the potential VL2.

[0142] A signal CK1 is input to wiring 35, and wiring 35 has a function of transmitting the signal CK1. Also a signal CK2 is input to wiring 36, and has a function of transmitting the signal CK2. The signals CK 1 and CK2 are signals similar to the signal CK. However, the signals CK1 and CK2 are signals inverted from each other, or signals having different phases from each other.

[0143] A signal SE is input to wiring 37, and wiring 37 has a function of transmitting the signal SE.

[0144] A signal SP is input to wiring 38, and wiring 38 has a function of transmitting the signal SP. The signal SP is a start pulse of the shift register circuit. Also, the signal SP is a digital signal whose high-level potential is VH and whose low-level potential is VL1.

[0145] Next, an example of a driving method of the shift register circuit in FIG. 11 will be described with reference to FIG. 12. FIG. 12 shows an example of a timing chart for explaining the driving method of the shift register circuit in FIG. 11. In FIG. 12, the signal OUT of the first-stage flip-flop circuit 200, the signal OUT of the second-stage flip-flop circuit 200, and the signal OUT of the Nth-stage flip-flop circuit 200 are respectively denoted as signals OUT1, OUT2, and OUTN.

[0146] During period T0, the signal SE becomes high level. Therefore, from the first stage to the Nth stage of the flip Each of the flip-flop circuits 200 performs the operation in the period T0 described in the second embodiment. Performs.

[0147] In the period T1, the signal SE becomes a low level. Therefore, each of the first to N-th flip-flop circuits 200 Performs the operation in the period T1 described in the second embodiment. Specifically, when the signal OUT of the (i - 1)-th flip-flop circuit 200 becomes a high level, the i-th flip-flop circuit 200 performs the operation in the period Ta described in the second embodiment. Therefore, the signal OUT of the i-th flip-flop circuit 200 becomes a low level. After that, when the signals CK1 and CK2 are inverted, the i-th flip-flop circuit 200 performs the operation in the period Tb described in the second embodiment. Therefore, the signal OUT of the i-th flip-flop circuit 200 becomes a high level. After that, when the signals CK1 and CK2 are inverted, and the signal OUT of the (i + 1)-th flip-flop circuit 200 becomes a high level, the i-th flip-flop circuit 200 performs the operation in the period Tc described in the second embodiment. Therefore, the signal OUT of the i-th flip-flop circuit 200 becomes a low level. After that, until the signal OUT of the (i - 1)-th flip-flop circuit 200 becomes a high level again, the i-th flip-flop circuit 200 performs the operation in the period Td described in the second embodiment. Therefore, the signal OUT of the i-th flip-flop circuit 200 maintains a low level. Since the shift register circuit in FIG. 11 uses the semiconductor device in FIG. 6(A) as the flip-flop circuit 200, it can achieve the same effect as the semiconductor device in FIG. 6(A). Maintains a low level.

[0148] The shift register circuit in FIG. 11 uses the semiconductor device in FIG. 6(A) as the flip-flop circuit 200, so it can achieve the same effect as the semiconductor device in FIG. 6(A). Since the shift register circuit in FIG. 11 uses the semiconductor device in FIG. 6(A) as the flip-flop circuit 200, it can achieve the same effect as the semiconductor device in FIG. 6(A).

[0149] The driving method of the shift register circuit in FIG. 11 has been described above.

[0150] In the shift register circuit of FIG. 11, wiring 37 may be omitted, and in each flip-flop circuit 200, wiring 12 may be connected to wiring 38. In this way, the number of wirings can be reduced. In addition, an offset voltage can be periodically held in the capacitor element 101.

[0151] When the semiconductor device in FIG. 9(A) is used as the flip-flop circuit 200, when connecting wiring 23 to wiring 35, it is preferable to connect wiring 24 to wiring 36. In this way, an increase in the number of wirings can be suppressed.

[0152] When the semiconductor device in FIG. 9(B) is used as the flip-flop circuit, it is preferable to connect wiring 25 to wiring 31 and connect wiring 16 to a load. In this way, since the flip-flop circuits 200 of other stages can be driven by the signal OUTB of wiring 25 that is not affected by the load, the shift register circuit can be stably driven.

[0153] This embodiment can be implemented in appropriate combination with other embodiments and the like.

[0154] (Embodiment 4) In this embodiment, a display device using the shift register circuit of Embodiment 3 as a driving circuit will be described.

[0155] In addition, part or all of the driving circuit can be integrally formed on the same substrate as the pixel portion to form a system-on-panel.

[0156] ​​​​​​As display elements used in a display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light emitting display element) can be applied. The light emitting element includes, in its category, an element whose luminance is controlled by current or voltage. Specifically, it includes inorganic EL (Electro Luminescence), organic EL, etc. Further, a display medium whose contrast changes by an electrical action, such as electronic ink, can also be applied. By the light emitting element is meant an element whose luminance is controlled by current or voltage, and specifically includes inorganic EL (Electro Luminescence), organic EL, etc. In FIG. 13(A), a sealing material 4005 is provided so as to surround a pixel portion 4002 provided on a first substrate 4001, and is sealed by a second substrate 4006. In FIG. 13(A), a scanning line driving circuit 4004 and a signal line driving circuit 4003 are mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Also, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC4018a (Flexible printed circuit), FPC4018b. In FIGS. 13(B) and 13(C), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005 and the second substrate 4006. In FIGS. 13(B) and 13(C), the sealing material 4005 on the first substrate 4001 In FIG. 13(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and is sealed by the second substrate 4006. In the region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a scanning line driving circuit 4004 and a signal line driving circuit 4003 are mounted on a separately prepared substrate. Also, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC4018a (Flexible printed circuit), FPC4018b.

[0157] In FIG. 13(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and is sealed by the second substrate 4006. In FIG. 13(A), a scanning line driving circuit 4004 and a signal line driving circuit 4003 are mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Also, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC4018a (Flexible printed circuit), FPC4018b. In FIG. 13(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and is sealed by the second substrate 4006. In the region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a scanning line driving circuit 4004 and a signal line driving circuit 4003 are mounted on a separately prepared substrate. Also, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC4018a (Flexible printed circuit), FPC4018b. In FIG. 13(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and is sealed by the second substrate 4006. In the region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a scanning line driving circuit 4004 and a signal line driving circuit 4003 are mounted on a separately prepared substrate. Also, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC4018a (Flexible printed circuit), FPC4018b. In FIG. 13(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and is sealed by the second substrate 4006. In the region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a scanning line driving circuit 4004 and a signal line driving circuit 4003 are mounted on a separately prepared substrate. Also, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC4018a (Flexible printed circuit), FPC4018b. In FIG. 13(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and is sealed by the second substrate 4006. In the region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a scanning line driving circuit 4004 and a signal line driving circuit 4003 are mounted on a separately prepared substrate. Also, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC4018a (Flexible printed circuit), FPC4018b. In FIG. 13(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and is sealed by the second substrate 4006. In the region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a scanning line driving circuit 4004 and a signal line driving circuit 4003 are mounted on a separately prepared substrate. Also, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC4018a (Flexible printed circuit), FPC4018b. In FIG. 13(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and is sealed by the second substrate 4006. In the region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a scanning line driving circuit 4004 and a signal line driving circuit 4003 are mounted on a separately prepared substrate. Also, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC4018a (Flexible printed circuit), FPC4018b. In FIG. 13(A), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001, and is sealed by the second substrate 4006. In the region different from the region surrounded by the sealing material 4005 on the first substrate 4001, a scanning line driving circuit 4004 and a signal line driving circuit 4003 are mounted on a separately prepared substrate. Also, various signals and potentials given to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004 or the pixel portion 4002 are supplied from FPC4018a (Flexible printed circuit), FPC4018b.

[0158] In FIGS. 13(B) and 13(C), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005 and the second substrate 4006. In FIGS. 13(B) and 13(C), the sealing material 4005 on the first substrate 4001 In FIGS. 13(B) and 13(C), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005 and the second substrate 4006. In FIGS. 13(B) and 13(C), the sealing material 4005 on the first substrate 4001 In FIGS. 13(B) and 13(C), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005 and the second substrate 4006. In FIGS. 13(B) and 13(C), the sealing material 4005 on the first substrate 4001 In FIGS. 13(B) and 13(C), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005 and the second substrate 4006. In FIGS. 13(B) and 13(C), the sealing material 4005 on the first substrate 4001 In FIGS. 13(B) and 13(C), a sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004. Also, a second substrate 4006 is provided on the pixel portion 4002 and the scanning line driving circuit 4004. Therefore, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the display element by the first substrate 4001, the sealing material 4005 and the second substrate 4006. In FIGS. 13(B) and 13(C), the sealing material 4005 on the first substrate 4001 In FIGS. 13(B) and 13(C), the sealing material 4005 on the first substrate 4001 A signal line driving circuit 4003 is mounted on a separately prepared substrate in a region different from the region surrounded by . In FIGS. 13(B) and 13(C), various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4002 are supplied from the FPC 4018.

[0159] In FIGS. 13(B) and 13(C), an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0160] Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or a TAB (Tape Automated Bonding) method can be used. FIG. 13(A) is an example in which the signal line driving circuit 4003 and the scanning line driving circuit 4004 are mounted by the COG method, FIG. 13(B) is an example in which the signal line driving circuit 4003 is mounted by the COG method, and FIG. 13(C) is an example in which the signal line driving circuit 4003 is mounted by the TAB method.

[0161] Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel.

[0162] Note that the display device in this specification refers to an image display device, a display device, or a light source (including an illumination device). Also, a connector, for example, an FPC or a TAB tape ​ or a module with TCP attached, a printed wiring board on the tip of TAB tape or TCP A module with a display element or a display device with an IC (integrated circuit) directly mounted on it using the COG method. The display device includes all installed modules.

[0163] In addition, the pixel portion provided over the first substrate has a plurality of transistors.

[0164] When liquid crystal elements are used as display elements, thermotropic liquid crystal, low molecular weight liquid crystal, high molecular weight liquid crystal, etc. Liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. are used. These liquid crystal materials Depending on the conditions, the phase can be cholesteric, smectic, cubic, or chiral nematic. It shows the lattice phase, isotropic phase, etc.

[0165] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. When the temperature of the cholesteric liquid crystal is increased, the cholesteric phase transitions to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to improve the liquid crystal layer, it is recommended to use a liquid crystal composition containing 5% by weight or more of a chiral agent. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec or less. Since the film is short and optically isotropic, no alignment treatment is required, and the viewing angle dependency is small. Since no film is required, rubbing is not required. This can prevent electrostatic damage caused by the liquid crystal display device during the manufacturing process. This makes it possible to improve the productivity of the liquid crystal display device.

[0166] The specific resistance of the liquid crystal material is 1×10 9Above Ω·cm, preferably 1×10 1 1 Above Ω·cm, more preferably 1×10 12 Above Ω·cm. In this specification, the value of the resistivity is the value measured at 20°C.

[0167] The size of the holding capacitance provided in the liquid crystal display device is set so that it can hold charges for a predetermined period in consideration of the leakage current etc. of the transistor arranged in the pixel portion. The size of the holding capacitance may be set in consideration of the off-current etc. of the transistor.

[0168] In the liquid crystal display device, TN (Twisted Nematic) mode, IPS (In- Plane-Switching) mode, FFS (Fringe Field Swi tching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, FLC (Ferroelectric Liqu id Crystal) mode, AFLC (AntiFerroelectric Li quid Crystal) mode, etc. are used.

[0169] Also, a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be used. Examples of the vertical alignment mode include but are not limited to, for example, MVA (Multi-Domain Vertical Alignment ) mode, PVA (Patterned Vertical Alignment) mode, ASV mode, etc. can be used.

[0170] ​ In addition, it can also be applied to VA type liquid crystal display devices. The VA type liquid crystal display device is a kind of method for controlling the alignment of liquid crystal molecules in a liquid crystal display panel. The VA type liquid crystal display device is a method in which liquid crystal molecules are oriented in the vertical direction with respect to the panel surface when no voltage is applied . Also, a method called multi-domain or multi-domain design is used, in which pixels (picture elements) are divided into several regions (sub-pixels), and the molecules are tilted in different directions to be tilted. can be used.

[0171] In addition, in the display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, and an anti-reflection member are provided as appropriate. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Also, a backlight, a side light, etc. may be used as the light source . can be used.

[0172] In addition, as the display method in the pixel portion, a progressive method, an interlace method, etc. can be used . Also, when performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, RGBW (W represents white ), or RGB with one or more colors such as yellow, cyan, and magenta added. Note that , the size of the display area may be different for each dot of the color elements. However, the disclosed invention is not limited to a color display device, and can also be applied to a monochrome display device .

[0173] In addition, as a display element included in the display device, a light-emitting element that utilizes electroluminescence can be applied . The light-emitting element that utilizes electroluminescence is a light-emitting material It is distinguished according to whether the material is an organic compound or an inorganic compound. Generally, the former is an organic EL element, and the latter is called an inorganic EL element.

[0174] In an organic EL element, by applying a voltage to the light-emitting element, electrons and holes are respectively injected into the layer containing the light-emitting organic compound, and a current flows. Then, when those carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state and emits light when the excited state returns to the ground state. From this mechanism, such a light-emitting element is called a current-excited light-emitting element.

[0175] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element structures. Dispersed inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emitting mechanism is donor- acceptor recombination emission that utilizes donor levels and acceptor levels. Thin-film inorganic EL elements have a structure in which the light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized emission that utilizes inner-shell electron transitions of metal ions.

[0176] Also, as a display device, it is possible to provide electronic paper that drives electronic ink. Electronic paper is also called an electrophoretic display device (electrophoretic display), and has the advantages of being as easy to read as paper, having lower power consumption compared to other display devices, and being able to be made thin and light.

[0177] Although various forms of electrophoretic display devices are conceivable, a first particle having a positive charge and a microcapsule containing a second particle having a negative charge are complex-dispersed in a solvent or a solute. By applying an electric field to the microcapsule, only the color of the particles that have moved in opposite directions to each other and aggregated on one side in the microcapsule is displayed. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless). Thus, the electrophoretic display device is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region. The above-mentioned microcapsule dispersed in a solvent is called electronic ink, and this electronic ink can be printed on the surface of glass, plastic, cloth, paper, etc. Also, color display is possible by using particles having a color filter or a dye. Note that for the first particle and the second particle in the microcapsule, a material selected from a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof may be used. In addition, a display device using a twist ball display method can also be applied as electronic paper. The twist ball display method is to arrange spherical particles painted white and black between a first electrode layer and a second electrode layer, which are electrode layers using the display element.

[0178] For the first electrode layer and the second electrode layer.

[0179]

[0180]

[0181] ​​​​​​​​​​A method of performing display by generating a potential difference in an electrode layer to control the orientation of spherical particles It is.

[0182] By applying the shift register circuit of Embodiment 3 to the display device described in this embodiment , a display device capable of stable driving can be provided even if the transistor is a depletion type. It can be provided.

[0183] This embodiment can be implemented in appropriate combination with other embodiments and the like.

[0184] (Embodiment 5) In this embodiment, the semiconductor device of Embodiment 1, the semiconductor device of Embodiment 2, the shift register circuit of Embodiment 3, and the transistor that can be used in the display device of Embodiment 4 will be described. It will be described.

[0185] <Regarding oxide semiconductors> Hereinafter, oxide semiconductors will be described in detail.

[0186] As the oxide semiconductor to be used, it preferably contains at least indium (In) or zinc (Zn). In particular, it is preferably contained In and Zn. Further, as a stabilizer to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it preferably has gallium (Ga) in addition to them. Further, it preferably has tin (Sn) as a stabilizer. Further, it preferably has hafnium (Hf) as a stabilizer. Further, it preferably has aluminum (Al) as a stabilizer. It is preferable to have.

[0187] Also, as other stabilizers, lanthanum (La), cerium, which are lanthanoids (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), It may have any one or more of lutetium (Lu).

[0188] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, binary metal oxides such as In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides such as In-Ga-Zn oxides (also denoted as IGZO), In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides such as In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides such as In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides such as In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, I n-Lu-Zn oxides, In-Sn-Ga-Zn oxides which are quaternary metal oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al -Zn oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Zn oxides can be used.

[0189] The In-Ga-Zn-based oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and has the characteristic of a high field-effect mobility. Also, a transistor using an In-Sn-Zn-based oxide semiconductor material can have a field-effect mobility three times or more higher than that of a transistor using an In-Ga-Zn-based oxide semiconductor material, and has the characteristic of being easily made to have a positive threshold voltage. These semiconductor materials are one of the suitable materials that can be used for the transistors constituting the semiconductor device in one aspect of the present invention. Here, for example, the In-Ga-Zn-based oxide means an oxide mainly composed of In, Ga, and Zn, and the ratio of In, Ga, and Zn does not matter. Also, metal elements other than In, Ga, and Zn may be included.

[0190] In addition, here, for example, the In-Ga-Zn-based oxide means an oxide mainly composed of In, Ga, and Zn, and the ratio of In, Ga, and Zn does not matter. Also, metal elements other than In, Ga, and Zn may be included.

[0191] Also, as the oxide semiconductor, a material represented by InMO3(ZnO) m (m > 0 and m is not an integer ) may be used. Here, M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Also, as the oxide semiconductor, In3SnO 5(ZnO) (n > 0 and n is an integer) may be used. n

[0192] For example, In-Ga-Zn-based oxides having an atomic ratio of In:Ga:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3) or In: Ga:Zn = 2:2:1 (= 2 / 5:2 / 5:1 / 5) and oxides in the vicinity of the composition thereof can be used. Alternatively, In:Sn:Zn = 1:1:1 (= 1 / 3:1 / 3:1 / 3), In:Sn:Zn = 2:1:3 (= 1 / 3: 1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) It is preferable to use an In-Sn-Zn oxide having an atomic ratio of 100% or an oxide having a composition close to that.

[0193] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In order to obtain the required semiconductor characteristics, Carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to set the degree, etc., appropriately.

[0194] For example, high mobility can be obtained relatively easily with In-Sn-Zn oxides. However, in the case of In-Ga-Zn oxides, the mobility can be improved by reducing the defect density in the bulk. It can be raised.

[0195] For example, the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b +c=1), the atomic ratio of the oxide is In:Ga:Zn=A:B:C (A+B+ C=1) is close to the oxide composition when a, b, and c are (a-A) 2 +(b-B) 2 +(c-C) 2 ≦r 2 The above condition is satisfied, and r can be set to, for example, 0.05. The same is true for other oxides. .

[0196] In addition, impurities such as moisture or hydrogen that act as electron donors are not included in the oxide semiconductor layer. It is preferable that the amount of impurities is reduced and the oxide semiconductor is highly purified. The body layer is analyzed using secondary ion mass spectrometry (SIMS). The hydrogen concentration measured by spectrometer was 5×10 19 / cm 3 The following are the preferred Or 5×10 18 / cm 3 Less than or equal to 5×10 17 / cm 3 The following are more preferred Or 1×10 16 / cm 3 The oxides that can be measured by Hall effect measurement are as follows. The carrier density of the semiconductor layer is 1×10 14 / cm 3 Less than 1 x 10 12 / cm 3 less than 1×10 11 / cm 3 is less than.

[0197] Here, the analysis of the hydrogen concentration in the oxide semiconductor layer will be described. The concentration is measured by secondary ion mass spectrometry. In principle, SIMS analysis is performed near the sample surface. It is known that it is difficult to obtain accurate data on the interface between layers of different materials. Therefore, when analyzing the distribution of hydrogen concentration in the thickness direction of a layer by SIMS, Within the range where the target layer exists, the value does not fluctuate dramatically and an almost constant value is obtained. The average value in the region is adopted as the hydrogen concentration. In this case, we found a region where the hydrogen concentration in the adjacent layer is almost constant. In this case, the maximum hydrogen concentration or The minimum value is adopted as the hydrogen concentration in the layer. If there is no mountain-shaped peak having a maximum value or a valley-shaped peak having a minimum value, the inflection point The value is taken as the hydrogen concentration.

[0198] When producing an oxide semiconductor layer using a sputtering method, it is important to reduce not only the hydrogen concentration in the target but also the water and hydrogen present in the chamber as much as possible. Specifically, it is effective to bake the inside of the chamber before the formation, reduce the water and hydrogen concentrations in the gas introduced into the chamber, and prevent backflow in the exhaust system that exhausts the gas from the chamber. The oxide semiconductor may be single crystal or polycrystal. In the latter case, it may be amorphous or polycrystalline. Also, it may have a structure including a crystalline portion in the amorphous or non - amorphous state. An amorphous oxide semiconductor can relatively easily obtain a flat surface. Therefore, when a transistor is fabricated using this, interface scattering can be reduced, and relatively easily, a relatively high mobility can be obtained. Also, in a crystalline oxide semiconductor, more bulk defects can be reduced, and if the surface flatness is increased, a mobility higher than that of an amorphous oxide semiconductor can be obtained.

[0199] To increase the surface flatness, it is preferable to form the oxide semiconductor on a flat surface. Specifically, it may be formed on a surface with an average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less. Note that Ra is the center - line average roughness defined in JIS B0601 extended three - dimensionally so that it can be applied to the surface, and is "the average of the absolute values of the deviations from the reference surface to the specified surface".

[0200]

[0201]

[0202] It can be expressed as the "following value" and is defined by the following formula.

[0203]

Number

[0204] Note that in the above, S0 refers to the area of the measurement surface (a rectangular area surrounded by four points represented by the coordinates (x1, y1), (x1, y2), (x2, y1), and (x2, y2)), and Z0 refers to the average height of the measurement surface. Ra can be evaluated by an atomic force microscope (AFM: Atomic Force Microscope).

[0205] The oxide semiconductor film takes a state such as single crystal, polycrystal (also called polycrystal), or amorphous.

[0206] Preferably, the oxide semiconductor film is a CAAC-OS (C Axis Aligned C rystalline Oxide Semiconductor) film.

[0207] The CAAC-OS film is neither a perfect single crystal nor a perfect amorphous. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed phase structure with crystal parts and amorphous parts in an amorphous phase. Note that the crystal part is often sized to fit within a cube with a side length of less than 100 nm. Also, in the observation image by a transmission electron microscope (TEM: Transmission Electr on Microscope), the boundary between the amorphous part and the crystal part contained in the CAAC-OS film is not clear. Also, no grain boundaries (also called grain boundaries) can be confirmed in the CAAC-OS film by TEM. Therefore, the CAAC-OS film

[0208] has suppressed reduction in electron mobility due to grain boundaries.

[0208] The crystal parts contained in the CAAC-OS film have their c-axes aligned in a direction parallel to the normal vector of the film-forming surface of the CAAC-OS film or the normal vector of the surface, and have an atomic arrangement in a triangular or hexagonal shape when viewed from a direction perpendicular to the ab-plane. When viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and b-axis may be different between different crystal parts. In this specification, when simply described as perpendicular, the range of 85° or more and 95° or less is also included. Also, when simply described as parallel, - the range of 5° or more and 5° or less is also included.

[0209] Note that in the CAAC-OS film, the distribution of the crystal parts may not be uniform. For example, when crystal growth is performed from the surface side of the oxide semiconductor film during the formation process of the CAAC-OS film, the proportion of the crystal parts may be higher near the surface than near the film-forming surface. Also, by adding impurities to the CAAC-OS film, the crystal parts may become amorphous in the impurity-added region.

[0210] Since the c-axes of the crystal parts contained in the CAAC-OS film are aligned in a direction parallel to the normal vector of the film-forming surface of the CAAC-OS film or the normal vector of the surface, depending on the shape of the CAAC-OS film (the cross-sectional shape of the film-forming surface or the cross-sectional shape of the surface), they may face different directions from each other. Note that the direction of the c-axis of the crystal part is the same as the direction parallel to the normal vector of the film-forming surface of the CAAC-OS film when the CAAC-OS film is formed. The crystal parts are formed by film formation or by performing a crystallization treatment such as heat treatment after film formation.

[0211] The transistor using the CAAC-OS film can reduce the change in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

[0212] Note that part of the oxygen constituting the oxide semiconductor film may be substituted with nitrogen.

[0213] When forming the CAAC-OS film using the sputtering method, it is preferable that the ratio of oxygen gas in the atmosphere is high. For example, when performing the sputtering method in a mixed gas atmosphere of argon and oxygen, the oxygen gas ratio is preferably 30% or more, and more preferably 40% or more. This is because the crystallization of CAAC is promoted by the replenishment of oxygen from the atmosphere.

[0214] When forming the CAAC-OS film using the sputtering method, it is preferable to heat the substrate on which the CAAC-OS film is formed to 150°C or higher, and more preferably to 170°C or higher. This is because the crystallization of CAAC is promoted as the substrate temperature rises.

[0215] After heat-treating the CAAC-OS film in a nitrogen atmosphere or in a vacuum, it is preferable to perform heat treatment in an oxygen atmosphere or in a mixed atmosphere of oxygen and another gas. This is because the oxygen deficiency generated in the previous heat treatment can be restored by the supply of oxygen from the atmosphere in the subsequent heat treatment.

[0216] The film surface (film-forming surface) on which the CAAC-OS film is formed is preferably flat. Since the CAAC-OS film has a c-axis that is substantially perpendicular to the film-forming surface, the film-forming surface The unevenness present in [it] will induce the generation of crystal grain boundaries in the CAAC-OS film. Therefore, before the CAAC-OS film is formed, it is preferable to perform planarization processing such as chemical mechanical polishing (CMP) on the surface to be coated. Also, the average roughness of the surface to be coated is preferably 0.5 nm or less, more preferably 0.3 nm or less.

[0217] Next, an example of the crystal structure contained in CAAC will be described in detail with reference to FIGS. 14 to 16. Unless otherwise specified, in FIGS. 14 to 16, the upward direction is the c-axis direction, and the plane orthogonal to the c-axis direction is the ab-plane. In addition, when simply referring to the upper half and the lower half, it means the upper half and the lower half when divided by the ab-plane. Also, in FIG. 14, O enclosed by a circle indicates O with 4 coordination, and O enclosed by a double circle indicates O with 3 coordination.

[0218] FIG. 14(A) shows a structure having one 6-coordinate In and six 4-coordinate oxygen atoms (hereinafter 4-coordinate O) adjacent to In. Here, the structure showing only the adjacent oxygen atoms for one metal atom is called a small group. The structure of FIG. 14(A) has an octahedral structure, but is shown in a planar structure for simplicity. In addition, there are three 4-coordinate O atoms each in the upper half and the lower half of FIG. 14(A). The small group shown in FIG. 14(A) has a charge of 0.

[0219] FIG. 14(B) shows a structure having one 5-coordinate Ga, three 3-coordinate oxygen atoms (hereinafter 3-coordinate O) adjacent to Ga, and two adjacent 4-coordinate O. The 3-coordinate O are all present on the ab-plane. There is one 4-coordinate O atom each in the upper half and the lower half of FIG. 14(B). ​​There is an O. Also, since In also takes a 5 - coordinate structure, it can have the structure shown in Fig. 14(B). Fig. 1 The small group shown in Fig. 14(B) has a charge of 0.

[0220] Fig. 14(C) shows a structure having one 4 - coordinate Zn and four 4 - coordinate O's adjacent to the Zn. There is one 4 - coordinate O in the upper half of Fig. 14(C) and three 4 - coordinate O's in the lower half. Or, there may be three 4 - coordinate O's in the upper half of Fig. 14(C) and one 4 - coordinate O in the lower half. The small group shown in Fig. 14(C) has a charge of 0.

[0221] Fig. 14(D) shows a structure having one 6 - coordinate Sn and six 4 - coordinate O's adjacent to the Sn. There are three 4 - coordinate O's in the upper half of Fig. 14(D) and three 4 - coordinate O's in the lower half. The small group shown in Fig. 14(D) has a charge of + 1.

[0222] Fig. 14(E) shows a small group containing two Zn. There is one 4 - coordinate O in the upper half of Fig. 14(E) and one 4 - coordinate O in the lower half. The small group shown in Fig. 14(E) has a charge of - 1.

[0223] Here, an aggregate of a plurality of small groups is called a medium group, and an aggregate of a plurality of medium groups is called a large group (also referred to as a unit cell).

[0224] Here, the rule for the combination of these small groups will be explained. As shown in Fig. 14(A), the three O's in the upper half of the 6 - coordinate In each have three adjacent In's downward, and the three O's in the lower half each have three adjacent In's upward. The one O in the upper half of the 5 - coordinate Ga shown in Fig. 14(B) has one adjacent Ga downward, and the one O in the lower half has one has adjacent Ga. One of the upper half of the four-coordinate Zn shown in Fig. 14(C) has one adjacent Zn downward, and each of the three Os in the lower half has three adjacent Zns upward. In this way, the number of four-coordinate Os above the metal atom and the number of adjacent metal atoms below that O are equal. Similarly, the number of four-coordinate Os below the metal atom and the number of adjacent metal atoms above that O are equal. Since O is four-coordinate, the sum of the number of adjacent metal atoms below and the number of adjacent metal atoms above is 4. Therefore, when the sum of the number of four-coordinate Os above the metal atom and the number of four-coordinate Os below another metal atom is 4, two types of small groups having metal atoms can bond to each other. The reason is shown below. For example, when a six-coordinate metal atom (In or Sn) bonds through the four-coordinate Os in the lower half, since there are 3 four-coordinate Os, it will bond to either a five-coordinate metal atom (Ga or In) or a four-coordinate metal atom (Zn). Metal atoms having these coordination numbers bond through four-coordinate Os in the c-axis direction. In addition, a plurality of small groups bond to form a medium group so that the total charge of the layer structure becomes 0. Fig. 15(A) shows a model diagram of the medium group constituting the layer structure of the In-Sn-Zn-O system. Fig. 15(B) shows a large group composed of three medium groups. Fig. 15(C) shows the atomic arrangement when observing the layer structure of Fig. 15(B) from the c-axis direction. In Fig. 15(A), for simplicity, three-coordinate Os are omitted, and only the number of four-coordinate Os is shown.

[0225]

[0226]

[0227] ​​​​​​​​​​Thus, for example, it is shown as 3 in the circle that there are three 4 - coordinated O atoms each in the upper and lower halves of Sn. Similarly, in Fig. 15(A), there is one 4 - coordinated O atom each in the upper and lower halves of In, which is shown as 1 in the circle. Also, similarly, in Fig. 15(A), there is one 4 - coordinated O atom in the lower half, and there are three 4 - coordinated O atoms in the upper half for Zn, and there is one 4 - coordinated O atom in the upper half and three 4 - coordinated O atoms in the lower half for Zn, which are shown. In Fig. 15(A), the middle group that constitutes the layer structure of the In - Sn - Zn - O system is, in order from the top, Sn with three 4 - coordinated O atoms each in the upper and lower halves, which combines with In having one 4 - coordinated O atom each in the upper and lower halves. That In combines with Zn having three 4 - coordinated O atoms in the upper half. Through one 4 - coordinated O atom in the lower half of that Zn, it combines with In having three 4 - coordinated O atoms each in the upper and lower halves. That In combines with a small group consisting of two Zn atoms having one 4 - coordinated O atom in the upper half. Through one 4 - coordinated O atom in the lower half of this small group, it combines with Sn having three 4 - coordinated O atoms each in the upper and lower halves. This middle group combines in multiple numbers to form a large group. Here, in the case of 3 - coordinated O and 4 - coordinated O, the charge per bond can be considered to be - 0.667 and - 0.5 respectively. For example, the charges of In (6 - coordinated or 5 - coordinated), Zn (4 - coordinated), and Sn (5 - coordinated or 6 - coordinated) are + 3, + 2, and + 4 respectively. Therefore, the small group containing Sn has a charge of + 1. Thus, in order to form a layer structure containing Sn, a charge of - 1 that cancels out the charge + 1 is required. As a structure that takes a charge of - 1, in the figure For example, in the upper and lower halves of Sn, there are three 4 - coordinated O atoms each, which are shown as 3 in the circle. Similarly, in Fig. 15(A), in the upper and lower halves of In, there is one 4 - coordinated O atom each, which is shown as 1 in the circle. Also, in Fig. 15(A), in the lower half, there is one 4 - coordinated O atom, and in the upper half, there are three 4 - coordinated O atoms for Zn, and in the upper half, there is one 4 - coordinated O atom and in the lower half, there are three 4 - coordinated O atoms for Zn, which are shown. For example, in the upper and lower halves of Sn, there are three 4 - coordinated O atoms each, which are shown as 3 in the circle. Similarly, in Fig. 15(A), in the upper and lower halves of In, there is one 4 - coordinated O atom each, which is shown as 1 in the circle. Also, in Fig. 15(A), in the lower half, there is one 4 - coordinated O atom, and in the upper half, there are three 4 - coordinated O atoms for Zn, and in the upper half, there is one 4 - coordinated O atom and in the lower half, there are three 4 - coordinated O atoms for Zn, which are shown. For example, in the upper and lower halves of Sn, there are three 4 - coordinated O atoms each, which are shown as 3 in the circle. Similarly, in Fig. 15(A), in the upper and lower halves of In, there is one 4 - coordinated O atom each, which is shown as 1 in the circle. Also, in Fig. 15(A), in the lower half, there is one 4 - coordinated O atom, and in the upper half, there are three 4 - coordinated O atoms for Zn, and in the upper half, there is one 4 - coordinated O atom and in the lower half, there are three 4 - coordinated O atoms for Zn, which are shown.

[0228] In Fig. 15(A), the middle group that constitutes the layer structure of the In - Sn - Zn - O system is, in order from the top, Sn with three 4 - coordinated O atoms each in the upper and lower halves, which combines with In having one 4 - coordinated O atom each in the upper and lower halves. That In combines with Zn having three 4 - coordinated O atoms in the upper half. Through one 4 - coordinated O atom in the lower half of that Zn, it combines with In having three 4 - coordinated O atoms each in the upper and lower halves. That In combines with a small group consisting of two Zn atoms having one 4 - coordinated O atom in the upper half. Through one 4 - coordinated O atom in the lower half of this small group, it combines with Sn having three 4 - coordinated O atoms each in the upper and lower halves. This middle group combines in multiple numbers to form a large group. In Fig. 15(A), the middle group that constitutes the layer structure of the In - Sn - Zn - O system is, in order from the top, Sn with three 4 - coordinated O atoms each in the upper and lower halves, which combines with In having one 4 - coordinated O atom each in the upper and lower halves. That In combines with Zn having three 4 - coordinated O atoms in the upper half. Through one 4 - coordinated O atom in the lower half of that Zn, it combines with In having three 4 - coordinated O atoms each in the upper and lower halves. That In combines with a small group consisting of two Zn atoms having one 4 - coordinated O atom in the upper half. Through one 4 - coordinated O atom in the lower half of this small group, it combines with Sn having three 4 - coordinated O atoms each in the upper and lower halves. This middle group combines in multiple numbers to form a large group. In Fig. 15(A), the middle group that constitutes the layer structure of the In - Sn - Zn - O system is, in order from the top, Sn with three 4 - coordinated O atoms each in the upper and lower halves, which combines with In having one 4 - coordinated O atom each in the upper and lower halves. That In combines with Zn having three 4 - coordinated O atoms in the upper half. Through one 4 - coordinated O atom in the lower half of that Zn, it combines with In having three 4 - coordinated O atoms each in the upper and lower halves. That In combines with a small group consisting of two Zn atoms having one 4 - coordinated O atom in the upper half. Through one 4 - coordinated O atom in the lower half of this small group, it combines with Sn having three 4 - coordinated O atoms each in the upper and lower halves. This middle group combines in multiple numbers to form a large group. In Fig. 15(A), the middle group that constitutes the layer structure of the In - Sn - Zn - O system is, in order from the top, Sn with three 4 - coordinated O atoms each in the upper and lower halves, which combines with In having one 4 - coordinated O atom each in the upper and lower halves. That In combines with Zn having three 4 - coordinated O atoms in the upper half. Through one 4 - coordinated O atom in the lower half of that Zn, it combines with In having three 4 - coordinated O atoms each in the upper and lower halves. That In combines with a small group consisting of two Zn atoms having one 4 - coordinated O atom in the upper half. Through one 4 - coordinated O atom in the lower half of this small group, it combines with Sn having three 4 - coordinated O atoms each in the upper and lower halves. This middle group combines in multiple numbers to form a large group. In Fig. 15(A), the middle group that constitutes the layer structure of the In - Sn - Zn - O system is, in order from the top, Sn with three 4 - coordinated O atoms each in the upper and lower halves, which combines with In having one 4 - coordinated O atom each in the upper and lower halves. That In combines with Zn having three 4 - coordinated O atoms in the upper half. Through one 4 - coordinated O atom in the lower half of that Zn, it combines with In having three 4 - coordinated O atoms each in the upper and lower halves. That In combines with a small group consisting of two Zn atoms having one 4 - coordinated O atom in the upper half. Through one 4 - coordinated O atom in the lower half of this small group, it combines with Sn having three 4 - coordinated O atoms each in the upper and lower halves. This middle group combines in multiple numbers to form a large group. In Fig. 15(A), the middle group that constitutes the layer structure of the In - Sn - Zn - O system is, in order from the top, Sn with three 4 - coordinated O atoms each in the upper and lower halves, which combines with In having one 4 - coordinated O atom each in the upper and lower halves. That In combines with Zn having three 4 - coordinated O atoms in the upper half. Through one 4 - coordinated O atom in the lower half of that Zn, it combines with In having three 4 - coordinated O atoms each in the upper and lower halves. That In combines with a small group consisting of two Zn atoms having one 4 - coordinated O atom in the upper half. Through one 4 - coordinated O atom in the lower half of this small group, it combines with Sn having three 4 - coordinated O atoms each in the upper and lower halves. This middle group combines in multiple numbers to form a large group. In Fig. 15(A), the middle group that constitutes the layer structure of the In - Sn - Zn - O system is, in order from the top, Sn with three 4 - coordinated O atoms each in the upper and lower halves, which combines with In having one 4 - coordinated O atom each in the upper and lower halves. That In combines with Zn having three 4 - coordinated O atoms in the upper half. Through one 4 - coordinated O atom in the lower half of that Zn, it combines with In having three 4 - coordinated O atoms each in the upper and lower halves. That In combines with a small group consisting of two Zn atoms having one 4 - coordinated O atom in the upper half. Through one 4 - coordinated O atom in the lower half of this small group, it combines with Sn having three 4 - coordinated O atoms each in the upper and lower halves. This middle group combines in multiple numbers to form a large group. In Fig. 15(A), the middle group that constitutes the layer structure of the In - Sn - Zn - O system is, in order from the top, Sn with three 4 - coordinated O atoms each in the upper and lower halves, which combines with In having one 4 - coordinated O atom each in the upper and lower halves. That In combines with Zn having three 4 - coordinated O atoms in the upper half. Through one 4 - coordinated O atom in the lower half of that Zn, it combines with In having three 4 - coordinated O atoms each in the upper and lower halves. That In combines with a small group consisting of two Zn atoms having one 4 - coordinated O atom in the upper half. Through one 4 - coordinated O atom in the lower half of this small group, it combines with Sn having three 4 - coordinated O atoms each in the upper and lower halves. This middle group combines in multiple numbers to form a large group.

[0229] Here, in the case of 3 - coordinated O and 4 - coordinated O, the charge per bond can be considered to be - 0.667 and - 0.5 respectively. For example, the charges of In (6 - coordinated or 5 - coordinated), Zn (4 - coordinated), and Sn (5 - coordinated or 6 - coordinated) are + 3, + 2, and + 4 respectively. Therefore, the small group containing Sn has a charge of + 1. Thus, in order to form a layer structure containing Sn, a charge of - 1 that cancels out the charge + 1 is required. As a structure that takes a charge of - 1, in the figure Here, in the case of 3 - coordinated O and 4 - coordinated O, the charge per bond can be considered to be - 0.667 and - 0.5 respectively. For example, the charges of In (6 - coordinated or 5 - coordinated), Zn (4 - coordinated), and Sn (5 - coordinated or 6 - coordinated) are + 3, + 2, and + 4 respectively. Therefore, the small group containing Sn has a charge of + 1. Thus, in order to form a layer structure containing Sn, a charge of - 1 that cancels out the charge + 1 is required. As a structure that takes a charge of - 1, in the figure Here, in the case of 3 - coordinated O and 4 - coordinated O, the charge per bond can be considered to be - 0.667 and - 0.5 respectively. For example, the charges of In (6 - coordinated or 5 - coordinated), Zn (4 - coordinated), and Sn (5 - coordinated or 6 - coordinated) are + 3, + 2, and + 4 respectively. Therefore, the small group containing Sn has a charge of + 1. Thus, in order to form a layer structure containing Sn, a charge of - 1 that cancels out the charge + 1 is required. As a structure that takes a charge of - 1, in the figure Here, in the case of 3 - coordinated O and 4 - coordinated O, the charge per bond can be considered to be - 0.667 and - 0.5 respectively. For example, the charges of In (6 - coordinated or 5 - coordinated), Zn (4 - coordinated), and Sn (5 - coordinated or 6 - coordinated) are + 3, + 2, and + 4 respectively. Therefore, the small group containing Sn has a charge of + 1. Thus, in order to form a layer structure containing Sn, a charge of - 1 that cancels out the charge + 1 is required. As a structure that takes a charge of - 1, in the figure Here, in the case of 3 - coordinated O and 4 - coordinated O, the charge per bond can be considered to be - 0.667 and - 0.5 respectively. For example, the charges of In (6 - coordinated or 5 - coordinated), Zn (4 - coordinated), and Sn (5 - coordinated or 6 - coordinated) are + 3, + 2, and + 4 respectively. Therefore, the small group containing Sn has a charge of + 1. Thus, in order to form a layer structure containing Sn, a charge of - 1 that cancels out the charge + 1 is required. As a structure that takes a charge of - 1, in the figure As shown in 14(E), small groups containing two Zn can be mentioned. For example, if there is one small group containing Sn and one small group containing two Zn for each one small group containing Sn, the charges can be cancelled out, so that the total charge of the layer structure can be set to 0.

[0230] Specifically, by repeating the large group shown in Fig. 15(B), a crystal of the In-Sn-Zn-O system (In2SnZn3O8) can be obtained. Incidentally, the obtained layer structure of the In-Sn-Zn-O system is In2SnZn2O7(ZnO) (m is 0 or a natural number. ) and can be represented by a composition formula. m (m is 0 or a natural number. ) and can be represented by a composition formula.

[0231] In addition, there are also oxides of quaternary metals such as In-Sn-Ga-Zn oxides, oxides of ternary metals such as In-Ga-Zn oxides (also denoted as IGZO), In -Al-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn -Al-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In -Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-S m-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb -Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er -Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Z n oxides, and oxides of binary metals such as In-Zn oxides, Sn-Zn oxides, A l-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, etc. The same applies when used.

[0232] For example, FIG. 16(A) shows a model diagram of the middle group that constitutes the layer structure of an In-Ga-Zn-O system.

[0233] In FIG. 16(A), in the middle group that constitutes the layer structure of the In-Ga-Zn-O system, there are three 4-coordinate O atoms each in the upper and lower halves for In, and In is bonded to Zn with one 4-coordinate O atom in the upper half. Through three 4-coordinate O atoms in the lower half of the Zn, it is bonded to Ga with one 4-coordinate O atom each in the upper and lower halves, and through one 4-coordinate O atom in the lower half of the Ga, it is bonded to In with three 4-coordinate O atoms each in the upper and lower halves. This is the configuration. Multiple of these middle groups are combined to form a large group.

[0234] FIG. 16(B) shows a large group composed of three middle groups. Note that FIG. 16(C) shows the atomic arrangement when observing the layer structure of FIG. 16(B) from the c-axis direction.

[0235] Here, since the charges of In (6-coordinate or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are +3, +2, and +3 respectively, a small group containing any of In, Zn, and Ga has a charge of 0. Therefore, for any combination of these small groups, the total charge of the middle group is always 0.

[0236] Also, the middle group that constitutes the layer structure of the In-Ga-Zn-O system is not limited to the middle group shown in FIG. 16(A), and large groups formed by combining middle groups with different arrangements of In, Ga, and Zn are also possible.

[0237] <Regarding a transistor in which a channel is formed in an oxide semiconductor layer> 17A to 17D are views showing a transistor in which a channel is formed in an oxide semiconductor layer. 17A to 17D are cross-sectional views showing examples of the structure of a transistor. This is a formula diagram.

[0238] The transistor shown in FIG. 17(A) includes a conductive layer 601(a), an insulating layer 602(a), and The oxide semiconductor layer 603(a), the conductive layer 605a(a), the conductive layer 605b(a), and the insulating layer It includes an edge layer 606(a) and a conductive layer 608(a).

[0239] The conductive layer 601(a) is provided on the element formation layer 600(a).

[0240] An insulating layer 602(a) is disposed on the conductive layer 601(a).

[0241] The oxide semiconductor layer 603(a) overlaps the conductive layer 601(a) via the insulating layer 602(a). To fold.

[0242] Each of the conductive layer 605a(a) and the conductive layer 605b(a) is an oxide semiconductor layer 603. It is provided on (a) and is electrically connected to the oxide semiconductor layer 603(a).

[0243] The insulating layer 606(a) is formed by insulating the oxide semiconductor layer 603(a), the conductive layer 605a(a), and the conductive The conductive layer 605a(b) is disposed on the conductive layer 605a(b).

[0244] The conductive layer 608(a) overlaps the oxide semiconductor layer 603(a) via the insulating layer 606(a). To fold.

[0245] Note that it is not always necessary to provide either the conductive layer 601(a) or the conductive layer 608(a). In addition, if the conductive layer 608(a) is not provided, the insulating layer 606(a) may not be provided. stomach.

[0246] The transistor shown in FIG. 17(B) includes a conductive layer 601(b), an insulating layer 602(b), an oxide semiconductor layer 603(b), a conductive layer 605a(b), a conductive layer 605b(b), and an insulating layer 606(b), and a conductive layer 608(b).

[0247] The conductive layer 601(b) is provided on the device formation layer 600(b).

[0248] The insulating layer 602(b) is provided on the conductive layer 601(b).

[0249] Each of the conductive layer 605a(b) and the conductive layer 605b(b) is provided on a part of the insulating layer 602(b).

[0250] The oxide semiconductor layer 603(b) is provided on the conductive layer 605a(b) and the conductive layer 605b(b), and is electrically connected to the conductive layer 605a(b) and the conductive layer 605b(b). Further, the oxide semiconductor layer 603(b) overlaps the conductive layer 601(b) with the insulating layer 602(b) therebetween.

[0251] The insulating layer 606(b) is provided on the oxide semiconductor layer 603(b), the conductive layer 605a(b), and the conductive layer 605b(b).

[0252] The conductive layer 608(b) overlaps the oxide semiconductor layer 603(b) with the insulating layer 606(b) therebetween.

[0253] Note that it is not always necessary to provide either the conductive layer 601(b) or the conductive layer 608(b). When the conductive layer 608(b) is not provided, the insulating layer 606(b) may not

[0254] The transistor shown in FIG. 17(C) includes a conductive layer 601(c), an insulating layer 602(c), an oxide semiconductor layer 603(c), a conductive layer 605a(c), and a conductive layer 605b(c).

[0255] The oxide semiconductor layer 603(c) includes a region 604a(c) and a region 604b(c). The region 604a(c) and the region 604b(c) are spaced apart from each other and are regions doped with dopants respectively. Note that the region between the region 604a(c) and the region 604b(c) becomes a channel formation region. The oxide semiconductor layer 603(c) is provided on the device formation layer 600(c). Note that it is not necessarily required to provide the region 604a(c) and the region 604b(c).

[0256] The conductive layer 605a(c) and the conductive layer 605b(c) are provided on the oxide semiconductor layer 603(c) and are electrically connected to the oxide semiconductor layer 603(c). Further, the side surfaces of the conductive layer 605a(c) and the conductive layer 605b(c) are tapered.

[0257] Further, the conductive layer 605a(c) overlaps a part of the region 604a(c), but is not necessarily limited thereto. By overlapping the conductive layer 605a(c) with a part of the region 604a(c), the resistance value between the conductive layer 605a(c) and the region 604a(c) can be reduced. Further, the entire region of the oxide semiconductor layer 603(c) overlapping the conductive layer 605a(c) may be the region 604a(c).

[0258] Further, the conductive layer 605b(c) overlaps a part of the region 604b(c), but is not necessarily limited thereto. By overlapping the conductive layer 605b(c) with a part of the region 604b(c), ​​​​​​​​​​​​ This can reduce the resistance between the conductive layer 605b(c) and the region 604b(c). Also, all regions of the oxide semiconductor layer 603(c) that overlap with the conductive layer 605b(c) may be the region 604b(c).

[0259] The insulating layer 602(c) is provided over the oxide semiconductor layer 603(c), the conductive layer 605a(c), and the conductive layer 605b(c).

[0260] The conductive layer 601(c) overlaps with the oxide semiconductor layer 603(c) with the insulating layer 602(c) therebetween. The region of the oxide semiconductor layer 603(c) that overlaps with the conductive layer 601(c) with the insulating layer 602(c) therebetween becomes the channel formation region.

[0261] Also, the transistor shown in FIG. 17(D) includes a conductive layer 601(d), an insulating layer 602(d ), an oxide semiconductor layer 603(d), a conductive layer 605a(d), and a conductive layer 605b(d ).

[0262] The conductive layer 605a(d) and the conductive layer 605b(d) are provided over the element formation layer 600(d). Also, the side surfaces of the conductive layer 605a(d) and the conductive layer 605b(d) are tapered.

[0263] The oxide semiconductor layer 603(d) includes a region 604a(d) and a region 604b(d). The region 604a(d) and the region 604b(d) are spaced apart from each other and are regions doped with pantothenic acid, respectively. Also, the region between the region 604a(d) and the region 604b(d) becomes the channel formation region. The oxide semiconductor layer 603(d) is provided, for example, over the conductive layer 605 a(d), the conductive layer 605b(d), and the element formation layer 600(d), and conducts​ It is electrically connected to layer 605a(d) and conductive layer 605b(d). Note that it is not necessarily required to provide regions 604a(d) and region 604b(d).

[0264] Region 604a(d) is electrically connected to conductive layer 605a(d).

[0265] Region 604b(d) is electrically connected to conductive layer 605b(d).

[0266] Insulating layer 602(d) is provided over oxide semiconductor layer 603(d).

[0267] Conductive layer 601(d) overlaps oxide semiconductor layer 603(d) with insulating layer 602(d) therebetween. The region of oxide semiconductor layer 60 3(d) that overlaps conductive layer 601(d) with insulating layer 602(d) therebetween becomes a channel formation region.

[0268] Furthermore, each component shown in FIGS. 17(A) to 17(D) will be described.

[0269] As element formation layers 600(a) to 600(d), for example, an insulating layer, or a substrate having an insulating surface or the like can be used. Also, a layer on which elements are previously formed can be used as element formation layers 600(a) to 600(d).

[0270] Each of conductive layers 601(a) to 601(d) has a function as a gate of a transistor. Note that a layer having a function as a gate of a transistor is also referred to as a gate electrode or a gate wiring.

[0271] As conductive layers 601(a) to 601(d), for example, molybdenum, magnesium ​​​Mu, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, or a layer of a metal material such as scandium, or an alloy material mainly composed of these can be used. Also, the conductive layers 601(a) to 601(d) can be formed by laminating layers of materials applicable to the formation of the conductive layers 601(a) to 601(d).

[0272] Each of the insulating layers 602(a) to 602(d) has a function as a gate insulating layer of a transistor.

[0273] As the insulating layers 602(a) to 602(d), for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, a hafnium oxide layer, or a lanthanum oxide layer can be used. Also, the insulating layers 602(a) to 602(d) can be formed by laminating layers of materials applicable to the insulating layers 602(a) to 602(d).

[0274] Also, as the insulating layers 602(a) to 602(d), for example, an insulating layer of a material containing a Group 13 element and an oxygen element in the periodic table can be used. For example, when the oxide semiconductor layers 603(a) to 603(d) contain a Group 13 element, by using an insulating layer containing a Group 13 element as the insulating layer in contact with the oxide semiconductor layers 603(a) to 603(d), the state of the interface between the insulating layer and the oxide semiconductor layer can be improved.

[0275] Examples of materials containing Group 13 elements and oxygen elements include, for example, gallium oxide, aluminum oxide, aluminum gallium oxide, gallium aluminum oxide, and the like. Note that aluminum gallium oxide refers to a substance in which the aluminum content (atomic %) is higher than the gallium content (atomic %), and gallium aluminum oxide refers to a substance in which the gallium content (atomic %) is equal to or higher than the aluminum content (atomic %). For example, Al2O (x = 3 + α, where α is a value greater than 0 and less than 1), Ga2O (x = 3 + α, where α is a value greater than 0 and less than 1), or Ga x Al x O (where x is a value greater than 0 and less than 2, and α is a value greater than 0 and less than 1) can also be used. x Al 2-x O 3+α (x is a value greater than 0 and less than 2, and α is a value greater than 0 and less than 1) can also be used. In addition, the insulating layers 602(a) to 602(d) can also be formed by laminating layers of materials applicable to the insulating layers 602(a) to 602(d). For example, the insulating layers 602(a) to 602(d) may be formed by laminating a plurality of layers containing gallium oxide represented by Ga2O

[0276] . Further, the insulating layers 602(a) to 602(d) may be formed by laminating an insulating layer containing gallium oxide represented by Ga2O and an insulating layer containing aluminum oxide represented by Al2O a2O x . 602(d). x In addition, when the channel length of the transistor is 30 nm, the thickness of the oxide semiconductor layers 603(a) to 603(d) may be, for example, about 5 nm. At this time, the oxidation layer and an insulating layer containing aluminum oxide represented by Al2O x can also be used. (a) to the insulating layer 602(d) may be formed.

[0277] In addition, when the channel length of the transistor is 30 nm, the thickness of the oxide semiconductor layers 603(a) to 603(d) may be, for example, about 5 nm. At this time, the oxidation layer and an insulating layer containing aluminum oxide represented by Al2O The oxide semiconductor layer 603(a) to the oxide semiconductor layer 603(d) are oxide semiconductor layers of CAAC. If present, the short channel effect in the transistor can be suppressed.

[0278] Region 604a(c), region 604b(c), region 604a(d), and region 604b( d) is a dopant that imparts N-type or P-type conductivity to the source of a transistor. The dopant may be, for example, 1 Group 3 elements (e.g. boron, etc.), Group 15 elements in the periodic table (e.g. nitrogen, phosphorus, and arsenic), and rare gas elements (e.g., helium, argon, and xenon One or more of the following can be used. The region that functions as the drain of a transistor is also called the source region. The region having the drain electrode is also called a drain region. Dopants are added to regions 604a(d) and 604b(d) to form contacts with the conductive layer. Since the contact resistance can be reduced, the transistors can be miniaturized.

[0279] The conductive layers 605a(a) to 605a(d) and the conductive layers 605b(a) to 605b(d) are Each of the layers 605b(d) functions as a source or drain of a transistor. Note that the layer functioning as the source of the transistor is called a source electrode or a source wiring. The layer having the function of the drain of a transistor may be called a drain electrode or a drain wiring. Also called a line.

[0280] The conductive layers 605a(a) to 605a(d) and the conductive layers 605b(a) to 605b(d) are As the layer 605b(d), for example, a metal material such as aluminum, magnesium, chromium, copper, tantalum , titanium, molybdenum, or tungsten, or a layer of an alloy material having these metal materials as a main component can be used. For example, a layer of an alloy material containing copper, magnesium, and aluminum can form the conductive layers 605a(a) to 605a(d), and the conductive layers 605b(a) to 605b(d). Also, by laminating layers of materials applicable to the conductive layers 605a(a) to 605a(d) and the conductive layers 605b(a) to 605b(d), the conductive layers 605a(a) to 605a(d) and the conductive layers 605b(a) to 605b(d) can also be formed. For example, a layer formed by laminating a layer of an alloy material containing copper, magnesium, and aluminum and a layer containing copper can form the conductive layers 605a(a) to 605a(d) and the conductive layers 605b(a) to 605b(d).

[0281] Also, as the conductive layers 605a(a) to 605a(d) and the conductive layers 605b(a) to 605b(d), a layer containing a conductive metal oxide can also be used. As the conductive metal oxide, for example, indium oxide, tin oxide, zinc oxide, indium tin oxide, or indium zinc oxide can be used. Note that the conductive metal oxide applicable to the conductive layers 605a(a) to 605a(d) and the conductive layers 605b(a) to 605b(d) may contain silicon oxide.

[0282] As the insulating layers 606(a) and 606(b), the insulating layers 602(a) to the insulating A layer of a material applicable to 602(d) can be used. Also, the insulating layer 606(a) and the insulating layer 606(b) may be formed by laminating materials applicable to them. For example, the insulating layer 606(a) and the insulating layer 606(b) may be formed by a silicon oxide layer, an aluminum oxide layer, etc. For example, by using an aluminum oxide layer, the effect of suppressing the intrusion of impurities (water) into the oxide semiconductor layer 603(a) and the oxide semiconductor layer 603(b) can be further enhanced, and the effect of suppressing the desorption of oxygen in the oxide semiconductor layer 603(a) and the oxide semiconductor layer 603(b)

[0283] Each of the conductive layers 608(a) and 608(b) has a function as a gate of the transistor. Note that when the transistor has a structure including both the conductive layer 601(a) and the conductive layer 608(a), or both the conductive layer 601(b) and the conductive layer 608(b), one of the conductive layer 601(a) and the conductive layer 608(a), or one of the conductive layer 601(b) and the conductive layer 608(b) is also referred to as a back gate, a back gate electrode, or a back gate wiring. By providing a plurality of conductive layers having a function as a gate via a channel formation layer, it is possible to easily control the threshold voltage

[0284] As the conductive layers 608(a) and 608(b), for example, a layer of a material applicable to the conductive layer 601(a) to the conductive layer 601(d) can be used. Also, the conductive layers 608(a) and 608(b) may be formed by laminating layers of materials applicable to them.

[0285] Also, an insulating layer having a function as a channel protection layer may be formed by laminating materials applicable to the insulating layers 602(a) to 602(d).

[0286] Also, a base layer may be formed on the device formation layers 600(a) to 600(d), and a transistor may be formed on the base layer. At this time, as the base layer, for example, a layer of a material applicable to the insulating layers 602(a) to 602(d) can be used. Also, the base layer may be formed by laminating materials applicable to the insulating layers 602(a) to 602(d). For example, by forming the base layer by laminating an aluminum oxide layer and a silicon oxide layer, desorption of oxygen contained in the base layer through the oxide semiconductor layers 603(a) to 603(d) can be suppressed.

[0287] Also, by making the oxygen in the insulating layer in contact with the oxide semiconductor layers 603(a) to 603(d) excessive, it becomes easier to supply the oxide semiconductor layers 603(a) to 603(d). Therefore, oxygen defects in the oxide semiconductor layers 603(a) to 603(d) or at the interface between the insulating layer and the oxide semiconductor layers 603(a) to 603(d) can be reduced, so that the carrier density of the oxide semiconductor layers 603(a) to 603(d) can be further reduced. Also, not limited to this, even when oxygen in the oxide semiconductor layers 603(a) to 603(d) is made excessive during the manufacturing process, the above insulating layer in contact with the oxide semiconductor layers 603(a) to 603(d) can prevent the oxide semiconductor layers 603(a) to 603(d) from being oxidized. It is possible to suppress the desorption of oxygen from the oxide semiconductor layer 603(d).

[0288] <Regarding the characteristics of a transistor in which a channel is formed in an oxide semiconductor layer> A transistor having an oxide semiconductor containing In, Sn, and Zn as main components in a channel formation region can obtain good characteristics by heating the substrate during film formation when forming the oxide semiconductor, or by performing heat treatment after forming the oxide semiconductor layer. Here, the main component refers to an element contained at 5 atomic% or more in terms of the composition ratio.

[0289] Intentionally heating the substrate after forming an oxide semiconductor layer containing In, Sn, and Zn as main components makes it possible to improve the field-effect mobility of the transistor. Also, it becomes possible to shift the threshold voltage of the transistor to positive and make it normally-off.

[0290] For example, FIGS. 18(A) to (C) show an oxide semiconductor layer containing In, Sn, and Zn as main components, with a channel length L of 3 μm and a channel width W of 10 μm, and the characteristics of a transistor using a gate insulating layer with a thickness of 100 nm. Here, V is set to 10 V. d

[0291] FIG. 18(A) shows the transistor characteristics when an oxide semiconductor layer containing In, Sn, and Zn as main components is formed by sputtering without intentionally heating the substrate. At this time, a field-effect mobility of 18.8 cm / Vsec is obtained. On the other hand, when the substrate is intentionally heated to form an oxide semiconductor layer containing In, Sn, and Zn as main components, it becomes possible to improve the field-effect mobility. FIG. 18(B) shows the case where the substrate is heated to 200°C to form an oxide semiconductor layer containing In, Sn, and Zn as main components. 2 Sn, and Zn as main components, it becomes possible to improve the field-effect mobility. FIG. 18(B) shows the case where the substrate is heated to 200°C to form an oxide semiconductor layer containing In, Sn, and Zn as main components. It shows the transistor characteristics when an oxide semiconductor layer is formed, and the field-effect mobility is 32. 2 cm 2 / Vsec is obtained.

[0292] The field-effect mobility can be further increased by performing heat treatment after forming an oxide semiconductor layer mainly composed of In, Sn, and Zn. FIG. 18(C) shows the transistor characteristics when an oxide semiconductor layer mainly composed of In, Sn, and Z n is formed by sputtering at 200° C. and then heat-treated at 650° C. At this time, the field-effect mobility is 34.5 cm / 2 / Vsec is obtained.

[0293] Also, substrate heating and heat treatment have the effect of preventing hydrogen and hydroxyl groups, which are harmful impurities to the oxide semiconductor, from being contained in the film or removing them from the film. That is, high purity can be achieved by removing hydrogen, which becomes a donor impurity in the oxide semiconductor, and by doing so, the transistor can be made normally off, and the off current can be made 1 aA / μm or less by high-purifying the oxide semiconductor. Here, the unit of the off current value indicates the current value per 1 μm of channel width.

[0294]

[0295] FIG. 19 shows the relationship between the off current of the transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. Here, for simplicity, the value obtained by multiplying the reciprocal of the substrate temperature at the time of measurement by 1000 (1000 / T) is used as the horizontal axis. / T) is used as the horizontal axis.

[0295] As shown in FIG. 19, when the substrate temperature is 125° C., it is 0.1 aA / μm (1×10 -1 9 A / μm) or less, and when it is 85° C., it is 10 zA / μm (1×10 -20Below A / μm Since the logarithm of the current value is proportional to the reciprocal of the temperature, at room temperature (27 °C), it is 0. 1 zA / μm (1×10 -22 A / μm) or less is expected. Therefore, the off-current At 125 °C, it can be made 1 aA / μm (1×10 -18 A / μm) or less, at 85 °C, it can be made 10 0 zA / μm (1×10 -19 A / μm) or less, and at room temperature, it can be made 1 zA / μm (1×10 -21 A / μm) or less.

[0296] By using the transistor of the present embodiment in the semiconductor device described in Embodiment 1 and Embodiment 2, the semiconductor device can be stably operated. In particular, by using the transistor of the present embodiment as the transistor 102, the off-current of the transistor 102 can be reduced. Therefore, the amount of charge lost from the capacitive element 101 can be reduced, and the number of times of holding the offset voltage in the capacitive element 101 can be reduced. .

[0297] The present embodiment can be implemented in appropriate combination with other embodiments and the like.

[0298] (Embodiment 6) In the present embodiment, an example of an electronic device including the semiconductor device, the shift register circuit, or the display device described in the above embodiment will be described.

[0299] Fig. 20(A) shows a portable game machine, which has a housing 9630, a display unit 9631, a speaker 963 3, operation keys 9635, connection terminals 9636, a recording medium reading unit 9672, etc. The portable game machine shown in Fig. 2 0(A) reads the program or data recorded on the recording medium​​​​​ A function to take out and display on the display unit, and a function to wirelessly communicate with other portable gaming machines to share information , etc. The functions of the portable gaming machine shown in Fig. 20(A) are not limited to this , and have various functions.

[0300] Fig. 20(B) is a digital camera, which has a housing 9630, a display unit 9631, a speaker 96 33, operation keys 9635, connection terminals 9636, a shutter button 9676, an imaging unit 967 7, etc. The digital camera shown in Fig. 20(B) has functions such as taking still pictures, taking moving pictures , automatically or manually correcting the taken images, obtaining various information from the antenna , saving the taken images or the information obtained from the antenna, and displaying the taken images or the information obtained from the antenna on the display unit, etc. Note that the functions of the digital camera shown in Fig 20(B) are not limited to this, and it has various functions .

[0301] Fig. 20(C) is a television receiver, which has a housing 9630, a display unit 9631, a speaker 963 3, operation keys 9635, connection terminals 9636, etc. The television receiver shown in Fig. 20(C) has functions such as processing television radio waves and converting them into image signals, processing the image signals and converting them into signals suitable for display , and converting the frame frequency of the image signals, etc. Note that the functions of the television receiver shown in Fig. 20(C) are not limited to this, and it has various functions .

[0302] Fig. 20(D) is a monitor (also called a PC monitor) for use in an electronic computer (personal computer), which has a housing 9630, a display unit 9631, etc. The monitor shown in Fig. 20(D) is also called a PC monitor and has a housing 9630, a display unit 9631, etc. The monitor shows an example in which a window-type display unit 9653 is provided in the display unit 9631. For the purpose of explanation, a window-type display unit 9653 is shown in the display unit 9631. The display may be a symbol, such as an icon, image, etc. In many cases, image signals are rewritten only when they are input. This is preferable when applying the driving method of the device. The functions are not limited to these, and various functions are available.

[0303] FIG. 21A shows a computer, which includes a housing 9630, a display unit 9631, and a speaker 963. 3. Operation keys 9635, connection terminals 9636, pointing device 9681, external connection The computer shown in FIG. 21A has various information (still images, Functions for displaying videos, text images, etc. on the display, various software (programs) A function for controlling processing by wireless communication or wired communication, a communication function using the communication function, Ability to connect to various computer networks and transmit various data using communication functions The functions of the computer shown in FIG. is not limited to this and has various functions.

[0304] Next, FIG. 21B shows a mobile phone, which includes a housing 9630, a display portion 9631, and a speaker 96 33, operation keys 9635, a microphone 9638, etc. Mobile phones have the ability to display various information (still images, videos, text images, etc.), calendar , a function to display the date or time on the display unit, and a function to operate or edit the information displayed on the display unit It has functions such as a function of controlling processing by various software (programs), etc. Oh, the functions of the mobile phone shown in Fig. 21(B) are not limited to this, and it has various functions. It has.

[0305] Next, Fig. 21(C) is an electronic paper (also called an E-book), which has a housing 9630, a display unit 9631, operation keys 9632, etc. The electronic paper shown in Fig. 21(C) has functions such as a function of displaying various information (still images, moving images, text images, etc.), a function of displaying a calendar, date or time, etc. on the display unit, a function of operating or editing the information displayed on the display unit, and a function of controlling processing by various software (programs), etc. Note that the functions of the electronic paper shown in Fig. 21 (C) are not limited to this, and it has various functions. The configuration of another electronic paper is shown in Fig. 21(D). The electronic paper shown in Fig. 21(D) shows the configuration in which a solar cell 9651 and a battery 9652 are added to the electronic paper of Fig. 21(C). When a reflective display device is used as the display unit 9631, it is expected to be used under a relatively bright situation, and power generation by the solar cell 9651 and charging of the battery 965 2 can be efficiently performed, which is preferable. As the battery 9652, using a lithium ion battery has advantages such as achieving miniaturization.

[0306] By applying the semiconductor device of Embodiment 1, the semiconductor device of Embodiment 2, the shift register circuit of Embodiment 3 or the display device of Embodiment 4 to the electronic devices described in this embodiment, even if the transistor is of the depletion type, an electronic device that can be driven can be provided. It can be done.

[0307] ​​This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

Description of Reference Numerals

[0308] 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 17 Wiring 21 Wiring 22 Wiring 23 Wiring 24 Wiring 25 Wiring 31 Wiring 31_i Wiring 31_i - 1 Wiring 32 Wiring 33 Wiring 34 Wiring 35 Wiring 36 Wiring 37 Wiring 38 Wiring 100 Circuit 101 Capacitor 102 Transistor 103 Capacitor 110 Circuit 111 Transistor 112 Transistor 113 Transistor 114 Transistor 115 Transistor 116 Transistor 120 Circuit 121 Transistor 122 Transistor 123 Transistor 124 Transistor 125 Transistor 126 Transistor 200 Flip - Flop Circuit 200_1 Flip - Flop Circuit 200_2 Flip - Flop Circuit 200_3 Flip-Flop Circuit 600 Element Formation Layer 601 Conductive Layer 602 Insulating Layer 603 Oxide Semiconductor Layer 606 Insulating Layer 608 Conductive Layer 100A Circuit 100B Circuit 101A Capacitor Element 101B Capacitor Element 102A Transistor 102B Transistor 4001 Substrate 4002 Pixel Section 4003 Signal Line Driver Circuit 4004 Scanning Line Driver Circuit 4005 Sealing Material 4006 Substrate 4018 FPC 4018a FPC 4018b FPC 604a Region 604b Region 605a Conductive Layer 605b Conductive Layer 9630 Housing 9631 Display Section 9632 Operation Key 9633 Speaker 9635 Operation Key 9636 Connection Terminal 9638 Microphone 9651 Solar Cell 9652 Battery 9653 Window-Type Display Section 9672 Recording Medium Reading Section 9676 Shutter Button 9677 Image Receiving Section 9680 External Connection Port 9681 Pointing Device IN Signal INO Signal IN1 Signal IN1O Signal IN2 signal IN2O signal IN3 signal SE signal OUT signal OUTA signal OUTB signal OUT1 signal OUT2 signal OUTN signal VH potential VDD potential VL1 potential VL2 potential N1 node T0 period T1 period Ta period Tb period Tc period Td period CK signal CK1 signal CK2 signal SP signal M1 transistor M2 transistor M3 transistor M4 transistor C1 capacitor

Claims

Claim 1. A device having a first transistor to a tenth transistor, wherein one of the source or drain of the first transistor is electrically connected to a first wiring, the other of the source or drain of the first transistor is electrically connected to a second wiring, a first power supply potential is supplied to one of the source or drain of the second transistor, the other of the source or drain of the second transistor is electrically connected to the first wiring, one of the source or drain of the third transistor is electrically connected to the gate of the first transistor, the other of the source or drain of the third transistor is electrically connected to a third wiring, one of the source or drain of the fourth transistor is electrically connected to a power supply line, the other of the source or drain of the fourth transistor is electrically connected to the gate of the first transistor, the gate of the fourth transistor is electrically connected to the gate of the second transistor, one of the source or drain of the fifth transistor is electrically connected to the power supply line, the other of the source or drain of the fifth transistor is electrically connected to the gate of the second transistor, the gate of the fifth transistor is electrically connected to a fourth wiring, one of the source or drain of the sixth transistor is electrically connected to the other of the source or drain of the seventh transistor, the other of the source or drain of the sixth transistor is electrically connected to a fifth wiring, the gate of the sixth transistor is electrically connected to the fifth wiring, one of the source or drain of the seventh transistor is electrically connected to the power supply line, the other of the source or drain of the seventh transistor is electrically connected to the gate of the tenth transistor, the gate of the seventh transistor is electrically connected to the fourth wiring, one of the source or drain of the eighth transistor is electrically connected to the power supply line, the other of the source or drain of the eighth transistor is electrically connected to the gate of the tenth transistor, the gate of the eighth transistor is electrically connected to the gate of the first transistor, one of the source or drain of the ninth transistor is electrically connected to the power supply line, The other of the source or drain of the ninth transistor is electrically connected to the gate of the third transistor, One of the source or drain of the tenth transistor is electrically connected to the gate of the second transistor, The gate of the tenth transistor is electrically connected to one of the source or drain of the sixth transistor, A MOS capacitor is formed between the gate of the tenth transistor and one of the source or drain of the tenth transistor, Semiconductor device. **Claim 2**: Having the first transistor to the tenth transistor, One of the source or drain of the first transistor is electrically connected to the first wiring, The other of the source or drain of the first transistor is electrically connected to the second wiring, A first power supply potential is supplied to one of the source or drain of the second transistor, The other of the source or drain of the second transistor is electrically connected to the first wiring, One of the source or drain of the third transistor is electrically connected to the gate of the first transistor, The other of the source or drain of the third transistor is electrically connected to the third wiring, One of the source or drain of the fourth transistor is electrically connected to the power supply line to which the first power supply potential is supplied, The other of the source or drain of the fourth transistor is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor, One of the source or drain of the fifth transistor is electrically connected to the power supply line, The other of the source or drain of the fifth transistor is electrically connected to the gate of the second transistor, The gate of the fifth transistor is electrically connected to the fourth wiring, One of the source or drain of the sixth transistor is electrically connected to the other of the source or drain of the seventh transistor, The other of the source or drain of the sixth transistor is electrically connected to the fifth wiring, The gate of the sixth transistor is electrically connected to the fifth wiring, One of the source or drain of the seventh transistor is electrically connected to the power supply line, The other of the source or drain of the seventh transistor is electrically connected to the gate of the tenth transistor, The gate of the seventh transistor is electrically connected to the fourth wiring, One of the source or drain of the eighth transistor is electrically connected to the power supply line, The other of the source or drain of the eighth transistor is electrically connected to the gate of the tenth transistor, The gate of the eighth transistor is electrically connected to the gate of the first transistor, One of the source or drain of the ninth transistor is electrically connected to the power supply line, The other of the source or drain of the ninth transistor is electrically connected to the gate of the third transistor, One of the source or drain of the tenth transistor is electrically connected to the gate of the second transistor, The gate of the tenth transistor is electrically connected to one of the source or drain of the sixth transistor, A MOS capacitor is formed between the gate of the tenth transistor and one of the source or drain of the tenth transistor, Semiconductor device.

3. Having the first transistor to the tenth transistor, One of the source or drain of the first transistor is electrically connected to the first wiring, The other of the source or drain of the first transistor is electrically connected to the second wiring, A first power supply potential is supplied to one of the source or drain of the second transistor, The other of the source or drain of the second transistor is electrically connected to the first wiring, One of the source or drain of the third transistor is electrically connected to the gate of the first transistor, The other of the source or drain of the third transistor is electrically connected to the third wiring, One of the source or drain of the fourth transistor is electrically connected to the power supply line, The other of the source or drain of the fourth transistor is electrically connected to the gate of the first transistor, The gate of the fourth transistor is electrically connected to the gate of the second transistor, One of the source or drain of the fifth transistor is electrically connected to the power supply line, The other of the source or drain of the fifth transistor is electrically connected to the gate of the second transistor, The gate of the fifth transistor is electrically connected to the fourth wiring. One of the source or drain of the sixth transistor is electrically connected to the other of the source or drain of the seventh transistor. The other of the source or drain of the sixth transistor is electrically connected to the fifth wiring. The gate of the sixth transistor is electrically connected to the fifth wiring. One of the source or drain of the seventh transistor is electrically connected to the power supply line. The other of the source or drain of the seventh transistor is electrically connected to the gate of the tenth transistor. The gate of the seventh transistor is electrically connected to the fourth wiring. One of the source or drain of the eighth transistor is electrically connected to the power supply line. The other of the source or drain of the eighth transistor is electrically connected to the gate of the tenth transistor. The gate of the eighth transistor is electrically connected to the gate of the first transistor. One of the source or drain of the ninth transistor is electrically connected to the power supply line. The other of the source or drain of the ninth transistor is electrically connected to the gate of the third transistor. The ninth transistor has a function of supplying the first power potential of the power supply line to the gate of the third transistor. One of the source or drain of the tenth transistor is electrically connected to the gate of the second transistor. The gate of the tenth transistor is electrically connected to one of the source or drain of the sixth transistor. A MOS capacitor is formed between the gate of the tenth transistor and one of the source or drain of the tenth transistor. Semiconductor device.

4. In any one of Claims 1 to 3, The first wiring has a function of outputting a signal. The second wiring has a function of supplying a clock signal. Semiconductor device.

Images