Plasma excitation with ion energy control

Abstract

The embodiments provided herein generally include apparatus, plasma processing systems, and methods for generation of a waveform for plasma processing of a substrate in a processing chamber. One embodiment includes a waveform generator having a voltage source selectively coupled to an output node, where the output node is configured to be coupled to an electrode disposed within the processing chamber, and the output node is selectively coupled to a ground node. The waveform generator may also include a radio frequency (RF) signal generator and a first filter coupled between the RF signal generator and the output node.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to systems used in semiconductor device manufacturing. More particularly, embodiments of the present disclosure relate to plasma processing systems used to process substrates.

Background Art

[0002] Ensuring the creation of high aspect ratio features is one of the major technical challenges for next-generation semiconductor devices. One way to form high aspect ratio features is to use a plasma-assisted etching process, in which a plasma is formed in a processing chamber and ions from the plasma are accelerated towards the surface of the substrate to form an opening in a material layer disposed under a mask layer formed on the surface of the substrate.

[0003] In a typical plasma-assisted etching process, the substrate is placed on a substrate support disposed in the processing chamber, a plasma is formed over the substrate, and ions are accelerated from the plasma towards the substrate across a plasma sheath, i.e., a region depleted of electrons, formed between the plasma and the surface of the substrate.

[0004] Conventional RF plasma-assisted etching processes that supply only a sinusoidal waveform containing an RF signal to one or more of the electrodes in a plasma processing chamber do not properly or desirably control sheath characteristics and the generated ion energy, which has been found to lead to undesirable plasma processing results. Undesirable processing results may include excessive sputtering of the mask layer and the generation of sidewall defects in high aspect ratio features.

[0005] Accordingly, there is a need in the art for plasma processing and biasing methods that can provide desirable plasma-assisted etching process results.

Summary of the Invention

[0006] Embodiments provided herein generally include an apparatus, a plasma processing system, and a method for generating waveforms for plasma processing of a substrate in a processing chamber.

[0007] One embodiment of the present disclosure is directed to a waveform generator for plasma processing. The waveform generator generally includes a voltage source selectively coupled to an output node, wherein the output node is configured to be coupled to an electrode disposed within a processing chamber, and the output node is selectively coupled to a ground node, a voltage source, a radio frequency (RF) signal generator, and a first filter coupled between the RF signal generator and the output node.

[0008] One embodiment of the present disclosure is directed to a method for waveform generation. The method generally includes coupling a voltage source to an output node during a first phase of a waveform, wherein the output node is coupled to an electrode disposed within a processing chamber, and coupling a ground node to the output node during a second phase of the waveform, wherein the RF signal generator is coupled to the output node through a filter.

[0009] One embodiment of the present disclosure is directed to an apparatus for waveform generation. The apparatus generally includes a memory and one or more processors coupled to the memory. The memory and the one or more processors are configured to couple a voltage source to an output node during a first phase of a waveform, wherein the output node is coupled to an electrode disposed within a processing chamber, and couple a ground node to the output node during a second phase of the waveform, wherein the RF signal generator is coupled to the output node through a filter.

[0010] To enable a more detailed understanding of the features of the present disclosure set forth above, a more detailed description of the present disclosure, briefly summarized above, may be made by reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only exemplary embodiments and, accordingly, should not be regarded as limiting the scope thereof, and other equally effective embodiments may be recognized.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2A

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Figure 3A

Figure 3B

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Figure 8

Modes for Carrying Out the Invention

[0012] As technology nodes advance toward 2nm, the fabrication of smaller features with larger aspect ratios involves atomic precision for plasma processing. In etching processes where plasma ions play an important role, ion energy control is an issue for the semiconductor device industry. Conventionally, RF bias techniques use sine waves to excite the plasma and accelerate the ions.

[0013] Some embodiments of the present disclosure generally relate to techniques for generating waveforms for controlling the ion energy distribution (IED). For example, pulse voltage waveforms and radio frequency (RF) waveforms can be applied to the same node in a plasma chamber to implement low-energy peaks and high-energy peaks in an IED function that has little intermediate energy between the low-energy peak and the high-energy peak, as described in more detail herein. The ions associated with the high-energy peak have the energy and directionality to reach the bottom of the high aspect ratio feature being etched and enable the etching reaction. Ions with low energy cannot reach the bottom of the feature during etching, but low-energy ions are still important for the etching process. Ions with intermediate energy do not have the desired directionality and will hit the sidewalls of the feature being etched, often causing undesirable bowing of the sidewalls in the etched feature, so ions with intermediate energy are not beneficial for the etching process. Some embodiments relate to techniques for generating waveforms having high-energy peaks and low-energy peaks with little intermediate energy ions.

[0014] Example Plasma Processing System FIG. 1 is a schematic cross-sectional view of a processing system 10 configured to perform one or more of the plasma processing methods described herein. In some embodiments, the processing system 10 is configured for a plasma-assisted etching process, such as reactive ion etching (RIE) plasma processing. However, the embodiments described herein may also be used with a processing system configured for other plasma-assisted processes, such as plasma deposition processes, e.g., plasma chemical vapor deposition (PECVD) processes, plasma physical vapor deposition (PEPVD) processes, plasma atomic layer deposition (PEALD) processes, plasma treatment processes, or plasma-based ion implantation processes, e.g., plasma doping (PLAD) processes.

[0015] As shown, the processing system 10 is configured to form a capacitively coupled plasma (CCP), and the processing chamber 100 includes an upper electrode (e.g., chamber lid 123) disposed in the processing volume 129, and the upper electrode faces a lower electrode (e.g., substrate support assembly 136) also disposed in the processing volume 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source is electrically coupled to one of the upper or lower electrodes to supply an RF signal, which is capacitively coupled to each of the upper and lower electrodes to ignite and sustain a plasma (e.g., plasma 101) disposed in the processing region between the upper and lower electrodes. Generally, one of the opposing upper or lower electrodes is coupled to ground or to a second RF power source for additional plasma excitation. As shown, the processing system 10 includes a processing chamber 100, a support assembly 136, and a system controller 126.

[0016] The processing chamber 100 generally includes a chamber body 113 that collectively defines a processing volume 129, including a chamber lid 123, one or more sidewalls 122, and a chamber base 124. The one or more sidewalls 122 and the chamber base 124 generally include materials sized and shaped to form a structural support for the elements of the processing chamber 100 and are configured to withstand the pressures and additional energy applied to the one or more sidewalls 122 and the chamber base 124 while the plasma 101 is generated within the vacuum environment maintained in the processing volume 129 of the processing chamber 100 during processing. In one example, the one or more sidewalls 122 and the chamber base 124 are formed from a metal such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0017] A gas inlet 128 disposed through the chamber lid 123 is used to supply one or more processing gases to the processing volume 129 from a processing gas source 119 that is in fluid communication with the processing volume 129. A substrate 103 is loaded into and removed from the processing volume 129 through an opening (not shown) in one of the one or more sidewalls 122 that is sealed by a slit valve (not shown) during plasma processing of the substrate 103.

[0018] In some embodiments, a plurality of lift pins 20 movably disposed through openings formed in the substrate support assembly 136 are used to facilitate transfer of the substrate to and from the substrate support surface 105A. In some embodiments, the plurality of lift pins 20 are disposed above, coupled to, and / or engageable with a lift pin hoop (not shown) disposed in the processing volume 129. The lift pin hoop may be coupled to a shaft (not shown) that extends sealingly through the chamber base 124. The shaft may be coupled to an actuator (not shown) used to raise and lower the lift pin hoop. When the lift pin hoop is in the raised position, the lift pin hoop engages the plurality of lift pins 20 to raise the upper surfaces of the lift pins above the substrate support surface 105A, lift the substrate 103 from the substrate support surface 105A, and allow access to the non-active (back) surface of the substrate 103 by a robot handler (not shown). When the lift pin hoop is in the lowered position, the plurality of lift pins 20 are flush with the substrate support surface 105A or retracted below the substrate support surface 105A, and the substrate 103 rests on the substrate support surface 105A.

[0019] As used herein, the system controller 126, also referred to as a process chamber controller, includes a central processing unit (CPU) 133, a memory 134, and support circuitry 135. The system controller 126 is used to control the process sequences used to process the substrate 103, including the substrate bias methods described herein. The CPU 133 is a general-purpose computer processor configured for use in an industrial setting to control a processing chamber and sub-processors associated with the processing chamber. The memory 134, generally non-volatile memory as described herein, may include random access memory, read-only memory, floppy or hard disk drives, or other suitable forms of digital storage, local or remote. The support circuitry 135 is conventionally coupled to the CPU 133 and includes cache, clock circuits, input / output subsystems, power supplies, etc., and combinations thereof. Software instructions (programs) and data may be coded and stored in the memory 134 to instruct the processor within the CPU 133. A software program (or computer instructions) readable by the CPU 133 in the system controller 126 determines which tasks are executable by components within the processing system 10.

[0020] Generally, a program readable by the CPU 133 in the system controller 126 includes code that, when executed by the processor (CPU 133), performs tasks related to the plasma processing methods described herein. The program may include instructions used to control various hardware and electrical components within the processing system 10 to perform the various process tasks and various process sequences used to implement the methods described herein. In one embodiment, the program includes instructions used to perform one or more of the operations described below with respect to FIG. 8.

[0021] A plasma control system generally includes a first source assembly 196 for establishing at least a first pulse voltage (PV) waveform at a bias electrode 104 and a second source assembly 197 for establishing at least a second PV waveform at an edge control electrode 115. The first PV waveform or the second PV waveform can be generated using one or more components within a waveform generator assembly 150 that can correspond to a waveform generator described in more detail herein with respect to FIGS. 4 and 5. In some embodiments, the waveform generator can be used to generate (maintain and / or ignite) a plasma 101 in a processing region disposed between a substrate support assembly 136 and a chamber lid 123, and supply an RF signal to a support base 107 (e.g., a power electrode or a cathode) or a bias electrode 104.

[0022] In some embodiments, the RF signal uses the processing gas disposed in the processing volume 129 and the electric field generated by the RF power (RF signal) supplied to the support base 107 and / or the bias electrode 104 to ignite and maintain the processing plasma 101. In some aspects, the RF signal can be generated by a waveform generator assembly 150. The processing volume 129 is fluidly coupled through a vacuum outlet 120 to one or more dedicated vacuum pumps, which maintains the processing volume 129 at near-atmospheric pressure conditions and exhausts the processing gas and / or other gases from the processing volume 129. In some embodiments, the substrate support assembly 136 disposed in the processing volume 129 is grounded and disposed on a support shaft 138 that extends through the chamber base 124. The waveform generator assembly 150 can include an RF generator 506, as shown in FIG. 5. As shown in FIG. 5, the RF generator 506 can be implemented using an RF signal source 580 and an RF matching network 582 in some embodiments. In some embodiments, as further described below, the RF generator 506 is configured to supply an RF signal having a frequency greater than 40 MHz, such as between about 40 MHz and about 200 MHz.

[0023] The substrate support assembly 136 briefly described above generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 can further include an insulator plate 111 and a ground plate 112, as further described below. The support base 107 is electrically insulated from the chamber base 124 by the insulator plate 111, and the ground plate 112 is inserted between the insulator plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to the support base 107 and disposed on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing. In some embodiments, the support base 107 includes one or more cooling channels (not shown) disposed within the support base 107, and the one or more cooling channels are fluidly coupled to a coolant source (not shown), such as a refrigerant source or a water source having a relatively high electrical resistance, and are in fluid connection with the coolant source. In some embodiments, the substrate support 105 includes a heater (not shown), such as a resistive heating element embedded in the dielectric material of the substrate support 105. As used herein, the support base 107 is formed from a corrosion-resistant, thermally conductive material, such as a corrosion-resistant metal, e.g., aluminum, an aluminum alloy, or stainless steel, and is coupled to the substrate support by an adhesive or by mechanical means.

[0024] Generally, the substrate support 105 is formed from a dielectric material, such as a bulk sintered ceramic material, such as a corrosion-resistant metal oxide or metal nitride material, e.g., aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In the embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in the dielectric material of the substrate support 105.

[0025] In one configuration, the bias electrode 104 is a chucking electrode used to fix (i.e., chuck) the substrate 103 to the substrate support surface 105A of the substrate support 105 and to bias the substrate 103 with respect to the processing plasma 101 using one or more of the pulse voltage bias methods described herein. Generally, the bias electrode 104 is formed from one or more conductive portions such as one or more metal meshes, foils, plates, or combinations thereof.

[0026] In some embodiments, the bias electrode 104 is electrically coupled to a clamping network, and the clamping network uses an electrical conductor such as a coaxial power supply line 106 (e.g., a coaxial cable) to provide a clamping voltage, such as a static DC voltage between approximately -5000V and approximately 5000V, to the bias electrode 104. As further described below, the clamping network includes a DC power supply 155 (e.g., a high voltage DC (HVDC) power supply) and a filter 151 (e.g., a low pass filter).

[0027] The substrate support assembly 136 may further include an edge control electrode 115, which is disposed below the edge ring 114, surrounds the bias electrode 104, and / or is disposed at a distance from the center of the bias electrode 104. Generally, in the case of a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular in shape, made of a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, such as those shown in FIG. 1, the edge control electrode 115 is disposed within the region of the substrate support 105. In some embodiments, as shown in FIG. 1, the edge control electrode 115 includes a conductive mesh, foil, and / or plate disposed at the same distance (i.e., in the Z direction) from the substrate support surface 105A of the substrate support 105 as the bias electrode 104.

[0028] The edge control electrode 115 can be biased by the use of a waveform generator assembly different from the waveform generator assembly 150 used to bias the bias electrode 104. In some embodiments, the edge control electrode 115 can be biased by the use of the waveform generator assembly 150, and the waveform generator assembly 150 is also used to bias the bias electrode 104 by splitting a portion of the power to the edge control electrode 115. In one configuration, the first waveform generator assembly 150 of the first source assembly 196 is configured to bias the bias electrode 104, and the second waveform generator assembly 150 of the second source assembly 197 is configured to bias the edge control electrode 115.

[0029] The power supply line 157 electrically connects the output of the waveform generator assembly 150 of the first source assembly 196 to the bias electrode 104. The following description mainly focuses on the power supply line 157 of the first source assembly 196 used to couple the waveform generator assembly 150 to the bias electrode 104, but the power supply line 158 of the second source assembly 197 that couples the waveform generator assembly 150 to the edge control electrode 115 will include the same or similar components. The electrical conductor(s) in various portions of the power supply line 157 can include (a) one or a combination of coaxial cables such as a flexible coaxial cable connected in series with a rigid coaxial cable, (b) an insulated high-voltage corona-resistant hookup wire, (c) a bare wire, (d) a metal bar, (e) an electrical connector, or (f) any combination of the electrical elements in (a) to (e).

[0030] In some embodiments, the processing chamber 100 further includes a quartz pipe 110 or collar that at least partially circumscribes a portion of the substrate support assembly 136 to prevent the substrate support 105 and / or the support base 107 from contacting corrosive processing gases or plasmas, cleaning gases or plasmas, or their by-products. Generally, the quartz pipe 110, insulator plate 111, and ground plate 112 are circumscribed by the liner 108. In some embodiments, a plasma screen 109 is disposed between the cathode liner 108 and the sidewall 122 to prevent plasma from forming in the volume under the plasma screen 109 between the liner 108 and one or more sidewalls 122.

[0031] FIG. 2A shows a voltage waveform that can be established at the electrodes of the processing chamber. FIG. 2B shows an example of different types of voltage waveforms 225 and 230 established on the substrate by different voltage waveforms similar to the voltage waveform shown in FIG. 2A, which are established separately at the electrodes in the processing chamber. Those waveforms include, as shown, two stages, namely, an ion current stage and a sheath collapse stage. At the beginning of the ion current stage, a drop in the substrate voltage creates a high voltage sheath above the substrate and accelerates positive ions towards the substrate. The positive ions that impact the surface of the substrate during the ion current stage deposit positive charges on the substrate surface, which, if uncompensated, causes the substrate voltage to increase gradually positively during the ion current stage, as shown by the voltage waveform 225 in FIG. 2B. However, the uncontrolled accumulation of positive charges on the substrate surface undesirably discharges the sheath capacitor and the chuck capacitor gradually, causing the sheath voltage drop to decrease gently and bringing the substrate potential closer to 0, as shown by the voltage waveform 225. The accumulation of positive charges causes a voltage droop in the voltage waveform established at the substrate (FIG. 2B). However, as shown in FIG. 2A, a voltage waveform established at the electrodes having a negative slope during the ion current stage can be generated to establish a square region (e.g., a nearly 0 slope) for the substrate voltage waveform shown by the curve 230 in FIG. 2B. Implementing the slope in the waveform established at the electrodes during the ion current stage is sometimes referred to as current compensation. The voltage difference between the beginning and the end of the ion current phase determines the ion energy distribution function (IEDF) width. The larger the voltage difference, the wider the IEDF width. To achieve monoenergetic ions and a narrower IEDF width, an operation is performed to flatten the substrate voltage waveform in the ion current phase using current compensation. In some embodiments of the present disclosure, an RF signal is overlaid on the voltage waveform shown in FIG. 2A.

[0032] Generation techniques for waveform generation Some of the present embodiments generally relate to techniques for waveform generation that facilitate plasma processing of a substrate while reducing an undesirable IED bowing profile formed in an etched high aspect ratio feature, using simultaneous plasma generation and ion energy distribution (IED) control. For example, a pulsed voltage (PV) waveform can be generated with an RF signal overlaid on the PV waveform. In some embodiments, the generated waveform can also include a ramp signal to facilitate current compensation, as described herein.

[0033] FIG. 3A shows a typical IED when using a single RF frequency excitation waveform. As shown, the IED has a bimodal shape with a high energy peak 306, a low energy peak 302, and intermediate energy ions (associated with, e.g., intermediate energy region 304). From the perspective of a plasma etching process, only the ions at or near the high energy peak have the energy and directionality to overcome the ion generation charging effect created in the etched material, reach the bottom of the feature, and enable the etching reaction. Ions with intermediate energy have no directionality and tend to hit the sidewalls of the feature, often resulting in an undesirable IED bowing profile, so ions with intermediate energy are not beneficial to the etching process. Ions with low energy are important for the etching process because they clean the mask surface, maintain the shape of the mask layer, and prevent clogging of the holes. Some embodiments of the present disclosure are directed to creating an energy profile that has a high energy peak and a low energy peak with little intermediate energy between the high energy peak and the low energy peak.

[0034] Figure 3B is a graph showing an IED function (IEDF) according to some embodiments of the present disclosure. As shown, the IEDF includes a low energy peak 301 and a high energy peak 303. The energy associated with the low energy peak may be less than a few hundred eV (e.g., less than 1 keV), and the energy associated with the high energy peak can be from a few hundred eV to tens of thousands of eV, depending on the aspect ratio of the feature to be formed in the substrate. For example, in some cases, the energy associated with the high energy peak can be between 4 keV and 10 keV. As shown, there are no (or at least fewer than in conventional implementations) ions between the low energy peak 301 and the high energy peak 303. Some embodiments are directed to techniques for implementing the ion energy distribution shown in Figure 3B using waveform shaping techniques, as described in more detail herein.

[0035] Figure 4 shows a waveform 400 generated using a waveform generator according to some embodiments of the present disclosure. As shown, the waveform 400 includes a waveform region 401 and a waveform region 405. The waveform region 401 includes a direct current (DC) signal overlaid with an RF signal 404, and the waveform region 405 includes a voltage ramp (e.g., for current compensation) overlaid with the RF signal 404.

[0036] The RF signal 404 sustains the plasma in the chamber and creates the low energy peak 301 described with respect to FIG. 3B. The RF signal 404 may have a frequency between 40 MHz and 200 MHz in some embodiments. The frequency of the RF signal 404 may be higher than the ion sheath transit frequency. In this case, the average ion transit time across the sheath thickness is longer than the period of the RF signal 404, and the ions experience multiple cycles of the RF signal 404 and acquire the average energy associated with the multiple cycles, resulting in creating the low energy peak 301. Thus, the ions are accelerated by the average sheath potential induced by the RF signal 404, and thus a single ion energy peak is achieved. High frequency RF excitation creates ions with a monoenergetic peak. In other words, the ions traveling across the sheath experience the average sheath potential driven by the RF signal 404 and create a single ion energy peak rather than a continuous energy distribution.

[0037] During a portion of the pulse waveform cycle, the bulk plasma electrons are attracted to the surface of the substrate (e.g., substrate 103) by the rising edge 402 of the pulse step. However, the bulk plasma electrons may not be able to establish a negative DC sheath potential to create the higher energy peak 303. The substrate surface and the electrode (e.g., support base 107) are (e.g., electrostatic chuck capacitor (C esc) called) a capacitive element is formed, and the capacitive element, in some embodiments, as shown in FIG. 1, includes a dielectric material layer of the substrate support 105 disposed between the bias electrode 104 and the substrate support surface 105A. (For example, compared to the negative charge on the substrate) There is an equal amount of positive charge on the electrode, canceling out the electric field generated by the plasma bulk electrons. At the falling edge 403 of the waveform 400, the ions are neutralized by the electrons due to the application of the waveform to the electrode. Thus, a negative DC sheath potential is established on the substrate surface. This is the starting point of the higher energy peak 303. The DC sheath potential (Vdc), or the higher ion energy, can be approximated based on the following equation using the magnitude of the falling edge (ΔV) and the ratio between C esc and the sheath capacitance (C sheath ). TIFF0007705962000001.tif14170 Thus, the waveform region 401 serves to sustain the plasma in the chamber (for example, while creating the lower energy peak 301) and establish the DC sheath potential for the higher energy peak 303.

[0038] Since the incoming ions neutralize the electrons on the substrate surface, the DC sheath potential would decrease in the absence of a means of compensation. Thus, the ions incident on the substrate become non-monochromatic. In some embodiments, a voltage ramp is implemented in the waveform region 405 to supply an increasing amount of electrons to the electrode to cancel out the otherwise increasing electric field caused by the positive charge due to the incoming ions, thereby maintaining a constant sheath potential (monoenergetic peak). The DC supply current for implementing the ramp can be controlled to equalize and compensate for the ion current provided in the ion current stage. The ion current (I ion ) is calibrated by using ion energy diagnostics or calculated based on the following equation by sampling the electrode voltage (V0) (for example, to calculate the time derivative of V0) and the value of the sheath potential. As shown in TIFF0007705962000002.tif14170, the RF signal 404 can also be overlaid on the lamp signal in region 405 to continue to sustain the plasma in the chamber (e.g., while creating a lower energy peak 301) and to establish the DC sheath potential for the higher energy peak 303.

[0039] Figure 5 shows an exemplary implementation of a waveform generator 500 for biasing a substrate to achieve IED control, according to some embodiments of the present disclosure. The waveform generator 500 can be used to implement the waveform generator assembly 150 as described with respect to FIG. 1. As shown, the waveform generator 500 can generate the waveform 400 described with respect to FIG. 4.

[0040] The waveform generator 500 includes a main voltage source 502 (e.g., a DC voltage source) for implementing a positive voltage in the waveform region 401, a current source 505 for implementing a ramp voltage in the waveform region 405, and an RF generator 506 (also referred to as an RF signal generator) for providing the RF signal 404. The waveform generator 500 generates the waveform 400 at the output node 504. The output node 504 can be coupled to a bias electrode 104 or a support base 107 in the substrate support 105 (e.g., a ceramic package). When the output node 504 is coupled to the support base 107, the total capacitance between the output node 504 and the substrate 103 (e.g., 1 / C total =1 / C esc +1 / C SB where C SB is the capacitance of the dielectric layer disposed between the support base 107 and the bias electrode 104) is greater than when the output node 504 is coupled to the bias electrode 104 (e.g., C esc ). The larger capacitance can result in a lower voltage drop across C esc and more voltage drop across the sheath.

[0041] As shown, a switch 520 (e.g., a high voltage solid state relay) may be coupled between the main voltage source 502 and the output node 504, and a switch 522 (e.g., a high voltage solid state relay) may be coupled between the ground node 508 and the output node 504. As shown, an RF filter 540 may be implemented in the path between the voltage source 502 and the switch 520, an RF filter 542 may be implemented in the path between the ground node 508 and the switch 522, and an RF filter 544 may be implemented between the current source 505 and the output node 504. The RF filters 540, 542, 544 may be implemented as low pass filters configured to block the (one or more) RF signals provided by the RF generator 506. The voltage source 502 and the current source 505 are protected from the output of the RF generator 506 by their respective RF filters 540, 544. In other words, the RF filters 540, 544 are configured to block high frequency RF signals provided by the RF generator 506. The ground node 508 is isolated from the RF generator 506 by the RF filter 542 (e.g., a low pass filter) when the switch 522 is closed. In some embodiments, each of the RF filters 540, 542, 544 may be implemented as a parallel LC topology, as shown in FIG. 6.

[0042] FIG. 6 shows a parallel LC filter topology 600 having a capacitive element 602 and an inductive element 604. As shown, the capacitive element 602 can be coupled in parallel to the inductive element 604 and between nodes 610 and 612. Each of the RF filters 540, 542, 544 can be implemented using the parallel LC filter topology 600. For example, in the case of RF filter 542, node 610 can be coupled to ground node 508 and node 612 can be coupled to switch 522. As an example, for a 40 MHz RF signal, the capacitive element 602 can be 100 picofarads (pF) and the inductive element 604 can be 158 nanohenries (nH) to block the 40 MHz RF signal. In other words, the LC filter topology 600 effectively acts as an open circuit for a 40 MHz signal and is a resonant circuit that isolates the voltage source 502, the ground node 508, or the current source 505 from the 40 MHz RF signal.

[0043] FIG. 7 is a timing diagram 700 showing the states of switch 520 (labeled "S1") and switch 522 (labeled "S2") according to some embodiments of the present disclosure. As shown, switch 520 and switch 522 cannot be closed simultaneously to avoid electrically shorting the voltage source 502 to the ground node 508. In some embodiments, during phase 1 of a waveform cycle (e.g., a cycle of waveform 400), switch 520 can be closed to create the rising edge 402 as shown in FIG. 4. Switch 520 can be closed for a period ranging from 20 ns to 2000 ns to allow a sufficient number of electrons to be collected on the substrate surface. After the period associated with waveform region 401, switch 520 can be opened and switch 522 can be closed to create the falling edge 403 during phase 2 of the waveform cycle. After opening switch S1, switch S2 can be closed for a time period ranging from 10 ns to 100 ns.

[0044] In some embodiments, during phase 1 while switch S1 is closed, positive charges accumulate on substrate 103 as shown in FIG. 1. The voltage on substrate 103 cannot change instantaneously due to the capacitive effect. Thus, during phase 2, when switch S1 is opened and switch S2 is closed, the voltage at output node 504 (e.g., at electrode 104 as shown in FIG. 1) drops from a positive voltage to a negative voltage as shown in FIG. 4. The drop from the positive voltage to the negative voltage is thought to be due to negative charges forming on electrode 104 and canceling out the positive charges on substrate 104. In other words, the positive charges on substrate 103 attract electrons to electrode 104, causing the drop to the negative voltage at output node 504 when switch S2 is closed.

[0045] During phase 3 of the waveform cycle, both switches 520, 522 remain open. As shown in FIG. 5, RF generator 506 and current source 505 can always be connected to output node 504 (e.g., to the chamber). In some embodiments, a high-pass filter 546 can be coupled between RF generator 506 and output node 504. High-pass filter 546 isolates the RF generator from the DC component at output node 504 (caused, for example, by current source 505 when switch 520 is closed, voltage source 502, or ground node 508 when switch 522 is closed). High-pass filter 546 can be implemented as an alternating current (AC) blocking capacitor in some embodiments.

[0046] In some embodiments, impedance 570 can be coupled between the output of current source 505 and the ground node to shunt the output current from current source 505 when switch 520 is closed. In other words, a rapid impedance change can occur due to the coupling of voltage source 502 to output node 504. Impedance 570 provides a path for current from current source 505 to ground when switch 520 closes, allowing for a gradual decrease in the current from current source 505 after rise edge 402. As shown, impedance 570 can be implemented using an inductor - resistor (RL) circuit having inductive element 574 and resistive element 572. When using a 40 MHz RF signal, the impedance of the inductive element can be 2 microhenries (μH), and the resistance of resistive element 572 can be 100 ohms.

[0047] Embodiments of the present disclosure provide a process - friendly dual - peak IED and a method for achieving such an IED on a substrate surface in a plasma processing chamber with simultaneous plasma excitation and sustainment. One advantage of embodiments of the present disclosure compared to conventional ion energy control techniques is the simultaneous plasma generation and IED control. As shown in FIG. 4 by a partial view of a second voltage waveform cycle that repeats after one PV waveform cycle is completed, a plurality of additional PV waveform cycles will be repeated continuously a plurality of times. In some embodiments, the voltage waveform established at the electrode is defined as the ratio of the ion current time period (e.g., the length of waveform region 405) to the waveform period T P (e.g., the length of waveform region 401 + the length of waveform region 405) and has an on - time greater than 50% or greater than 70%, such as between 80% and 95%. In some embodiments, the period T is about 2.5 μs PA PV waveform having a waveform cycle with [specific condition] has a burst period between about 100 microseconds (μs) and about 10 milliseconds (ms), and is continuously repeated within the PV waveform burst. The burst of the PV waveform can have a burst duty cycle between about 5% and 100%, such as between about 50% and about 95%. The duty cycle is the ratio of the burst period divided by the non-burst period (i.e., when the PV waveform is not generated) that separates the burst period + the burst period.

[0048] FIG. 8 is a process flow diagram showing a method 800 for waveform generation. The method 800 can be implemented by a waveform generation system that includes a waveform generator such as waveform generator 500, and / or a system controller such as system controller 126.

[0049] In activity 802, the waveform generation system couples a voltage source (e.g., voltage source 502) to an output node (e.g., output node 504) (e.g., by closing switch 520) during a first phase of a waveform (e.g., waveform 400) (e.g., phase 1 shown in FIG. 7). The output node can be coupled to an electrode disposed within a processing chamber (e.g., processing chamber 100). For example, the output node can be coupled to electrode 104 or support base 107.

[0050] In activity 804, the waveform generation system couples a ground node (e.g., ground node 508) to the output node (e.g., by closing switch 522) during the second phase of the waveform (e.g., phase 2 shown in FIG. 7). In some embodiments, an RF signal generator (e.g., RF generator 506) is coupled to the output node through a filter (e.g., filter 546) during the first phase. The RF signal generator may be coupled to the output node during the first, second, and third phases of the waveform (e.g., phase 3 shown in FIG. 7). The voltage source and the ground node are decoupled from the output node during the third phase (e.g., by opening switches 520, 522). In some embodiments, the voltage source is coupled to the output node through a filter (e.g., filter 540), and the ground node is coupled to the output node through a filter (e.g., filter 542).

[0051] In some embodiments, a current source (e.g., current source 505) is coupled to the output node during the third phase of the waveform, and the voltage source and the ground node are decoupled from the output node during the third phase. The current source may be coupled to the output node through a filter (e.g., filter 544).

[0052] The term "coupled" as used herein is used to refer to a direct or indirect coupling between two objects. For example, if object A physically contacts object B and object B contacts object C, objects A and C can still be considered to be coupled to each other even if objects A and C do not directly physically contact each other. For example, a first object can be coupled to a second object even if the first object never directly physically contacts the second object.

[0053] The foregoing is directed to embodiments of the present disclosure, but other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which is determined by the following claims.

Claims

1. A waveform generator for plasma processing, a voltage source selectively coupled to an output node, wherein the output node is configured to be coupled to an electrode disposed in a processing chamber, the output node being selectively coupled to a ground node, a voltage source, a radio frequency (RF) signal generator, a first filter coupled between the RF signal generator and the output node and including a high-pass filter, and a current source coupled to the output node comprising a waveform generator.

2. A waveform generator for plasma processing, a voltage source selectively coupled to an output node, wherein the output node is configured to be coupled to an electrode disposed in a processing chamber, the output node being selectively coupled to a ground node, a voltage source, a radio frequency (RF) signal generator, a first filter coupled between the RF signal generator and the output node, a current source coupled to the output node, a second filter coupled between the current source and the output node, and a ground node coupled between the current source and the output node via an impedance comprising a waveform generator.

3. The waveform generator according to claim 2, wherein the impedance comprises an inductive element and a resistive element.

4. The waveform generator according to any one of claims 1 to 3, wherein the waveform generator is configured to generate a pulsed voltage signal by selectively coupling the voltage source and the ground node to the output node, and the RF signal generator is configured to generate an RF signal overlaid on the pulsed voltage signal.

5. The waveform generator according to any one of claims 1 to 3, wherein the voltage source is selectively coupled to the output node via a switch.

6. The waveform generator according to any one of claims 1 to 3, wherein the ground node is selectively coupled to the output node via a switch.

7. The waveform generator according to any one of claims 1 to 3, further comprising a second filter coupled between the voltage source and the output node.

8. The waveform generator according to any one of claims 1 to 3, further comprising a second filter coupled between the ground node and the output node.

9. The waveform generator according to claim 8, wherein the second filter includes a low-pass filter.

10. The waveform generator according to claim 9, wherein the low-pass filter includes a capacitive element in parallel with an inductive element.

11. A second filter coupled between the current source and the output node The waveform generator according to claim 1, further comprising.

12. A first switch configured to couple the voltage source to the output node during a first phase; A second switch configured to couple the ground node to the output node during a second phase The waveform generator according to claim 11, further comprising, wherein the first switch and the second switch are further configured to decouple the voltage source and the ground node from the output node during a third phase, and the RF signal generator is coupled to the output node during the third phase.

13. An apparatus for waveform generation, comprising: A memory; One or more processors coupled to the memory Wherein the memory and the one or more processors are configured to: Coupling a voltage source to an output node during a first phase of a waveform, wherein the output node is coupled to an electrode disposed within a processing chamber; Coupling a ground node to the output node during a second phase of the waveform; Coupling a current source to the output node during a third phase of the waveform Configured to perform, wherein an RF (radio frequency) signal generator is coupled to the output node through a filter including a high-pass filter during the first phase. Apparatus.

14. An apparatus for waveform generation, comprising: A memory; One or more processors coupled to the memory Wherein the memory and the one or more processors are configured to: Coupling a voltage source to an output node during a first phase of a waveform, wherein the output node is coupled to an electrode disposed within a processing chamber; Coupling a ground node to the output node during a second phase of the waveform; Coupling a current source to the output node through a second filter during a third phase of the waveform, wherein the current source and the output node include a ground node coupled through an impedance. configured to perform, and a radio frequency (RF) signal generator is coupled to the output node through a filter during the first phase, Apparatus.

15. The apparatus according to claim 14, wherein the impedance comprises an inductive element and a resistive element.

16. The apparatus according to any one of claims 13 to 15, wherein the voltage source and the ground node are decoupled from the output node during the third phase.

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