Semiconductor device

Abstract

To provide a display device capable of performing good display without generating delay or dullness of signals.SOLUTION: A display device has first and second gate drivers. Each of the first and second gate drivers has a plurality of flip-flop circuits and a plurality of transfer signal generation circuits. Both the flip-flop circuit and the transfer signal generation circuit delay a signal inputted to a first input terminal by a half clock cycle and then output the resultant. An output terminal of the transfer signal generation circuit is directly connected with the first input terminal of the post-stage flip-flop circuit. Therefore, delay or dullness of signals inputted from the transfer signal generation circuits to the flip-flop circuits can be reduced.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] One embodiment of the present invention relates to a display device driven by an active matrix method. The present invention relates to an electronic device equipped with the display device. [Background technology]

[0002] In a display device driven by the active matrix method, each pixel has a switch such as a transistor. When the switch is on, the element is electrically connected to the pixel and the pixel is imaged. A drive circuit (source driver) that outputs image signals and a and a drive circuit (gate driver).

[0003] In addition, it is possible to configure not only the switches for each pixel but also the gate drivers using transistors. Therefore, a transistor formed using a non-single crystal semiconductor provided on an insulating substrate is Display devices have also been developed that use transistors to configure the switches and gate drivers for each pixel. There are.

[0004] The above-mentioned gate driver is provided in the vicinity of the pixel portion of the display device. When a gate driver is provided close to one side of the pixel area, the display area is biased toward one side of the display device. Therefore, display devices with gate drivers divided into the left and right sides of the pixel area have been developed. (See, for example, Patent Document 1).

[0005] The configuration of the display device disclosed in Patent Document 1 is shown in FIG. A first gate driver 1002A and a second gate driver 1002B are disposed on either side of the pixel section 1001. The first gate driver 1002A is provided so as to face the odd-numbered rows. The second gate driver 1002B has an output terminal electrically connected to the gate lines of the even rows. The output terminal is electrically connected to the first gate line. A electrically connects the pixels arranged in odd-numbered rows of the pixel section 1001 to the source driver. The second gate driver 1002B controls the pixels arranged in the even-numbered rows of the pixel section. The electrical connection between the pixel and the source driver is controlled.

[0006] Furthermore, the first gate driver 1002A and the second gate driver 1002B Each of the first and second shift registers has a plurality of shift registers. The output terminal of the first shift register (SRC1) is 10031 is connected to one of the input terminals of the second shift register (SRC2) via the first gate line 10031. The output terminal of the second shift register (SRC2) is electrically connected to the second gate Electrically connected to one of the input terminals of the third shift register (SRC3) via line 10032. The kth shift register (SRC k ) output terminal of the kth gate line 1003 k The k+1th shift register (SRC k+1 ) to one of the input terminals. In other words, each pixel in a row is electrically connected to the source driver. A signal that electrically connects the output terminals to each of the pixels arranged in the next row is This signal is used as a start pulse signal for the shift register. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 4163416 Summary of the Invention

Problems to be Solved by the Invention

[0008] Various parasitic capacitances and parasitic resistances occur in the gate lines extending in the pixel portion. In particular, due to the high definition of the pixel portion the influence of the parasitic capacitance and parasitic resistance generated in the gate lines becomes greater. As described above the display device shown in FIG. 10 has a start pulse signal of the shift register input via the gate line Therefore, it can be said that the display device shown in FIG. 10 is a display device in which signals are likely to be delayed or dulled due to high definition or large size

[0009] In view of the above problems, one aspect of the present invention is to provide a display device capable of providing good video display as one of the problems

[0010] Another aspect of the present invention is to provide a display device in which a gate driver is configured using a unipolar transistor as one of the problems

[0011] Another aspect of the present invention is to provide a display device having a gate driver with a reduced circuit area as one of the problems

Means for Solving the Problems

[0012] One aspect of the present invention includes a plurality of gate lines each arranged in parallel or substantially parallel, a first gate driver electrically connected to each of the odd-numbered rows of the gate lines, and a second gate driver electrically connected to each of the even-numbered rows of the gate lines. The first gate driver has an output terminal electrically connected to the k-th (k is an odd number of 3 or more) gate line, a first input terminal electrically connected to the output terminal of the k-2 transfer signal generation circuit, and a second input terminal connected to the clock signal each electrically connected to each other, and the first gate driver has an output terminal electrically connected to the k-th (k is an odd number of 3 or more) gate line, a first input terminal electrically connected to the output terminal of the k-2 transfer signal generation circuit, and a second input terminal connected to the clock signal and the second input terminal is electrically connected to the output terminal of the k-2 transfer signal generation circuit, and the second input terminal is connected to the clock signal The first input terminal is electrically connected to the output terminal of the k-2 transfer signal generation circuit, and the second input terminal is connected to the clock signal ​​electrically connected to the signal line, and the third input terminal is the stop pulse for the k-th flip-flop circuit The k-th flip-flop circuit, which is electrically connected to the signal line, and the output terminal is the k+2-th The first input terminal is electrically connected to the first input terminal of the flip-flop circuit, and the first input terminal is the k-th f The lip-flop circuit is electrically connected to the output terminal, and the second input terminal is the inverted clock signal The line is electrically connected, and the third input terminal is the stop pulse signal for the k-th transfer signal generation circuit The line is electrically connected, and the second gate driver has The output terminal is electrically connected to the k+1-th gate line, and the first input terminal is the k-1-th transfer The signal generation circuit is electrically connected to the output terminal, and the second input terminal is the inverted clock signal line The line is electrically connected, and the third input terminal is the stop pulse for the k+1-th flip-flop circuit The signal line is electrically connected, and the output terminal is the k+ The first input terminal of the 3 flip-flop circuit is electrically connected, and the first input terminal is the above-mentioned The output terminal of the k+1-th flip-flop circuit is electrically connected, and the second input terminal is the above-mentioned The clock signal line is electrically connected, and the third input terminal is the stop signal for the k-th transfer signal generation circuit The pulse signal line is electrically connected, and the display device having the k+1-th transfer signal generation circuit It is.

[0013] In addition, a display device in which the circuit configurations of the k-th flip-flop circuit and the k-th transfer signal generation circuit are the same Is also one aspect of the present invention.

[0014] Note that the above-mentioned stop pulse signal line is a wiring for inputting a stop pulse signal to each circuit It is.

[0015] Specifically, as the stop pulse signal for the k-th flip-flop circuit, the output signal of the k-th transmission signal generation circuit can be applied.

[0016] Also, as the stop pulse signal for the k-th flip-flop circuit, the output signal of the (k + 1)-th flip flop circuit can also be applied.

[0017] Similarly, as the stop pulse signal for the k-th transfer signal generation circuit, the output signal of the (k + 2)-th flip-fl op circuit can be applied.

[0018] Also, as the stop pulse signal for the k-th transfer signal generation circuit, the output signal of the (k + 1)-th transfer signal generation circuit can also be applied.

[0019] Furthermore, an electronic device including a display device having the above configuration is also an aspect of the present invention.

Advantages of the Invention

[0020] The first gate driver and the second gate driver of the display device according to an aspect of the present invention have a transfer signal generation circuit that outputs an input signal with a half clock cycle delay. Therefore, it is possible to provide a display device that can perform good display without signal delay or dullness.

Brief Description of the Drawings

[0021]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Embodiments for Carrying Out the Invention

[0022] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.

[0023] (Embodiment 1) In this embodiment, an example of a display device according to an aspect of the present invention is shown. Specifically, an active matrix type display device having a first and a second gate driver will be described with reference to FIGS. 1 to 3.

[0024] <Configuration Example of Display Device> FIG. 1 is a diagram showing an active matrix type display device 100. The display device 100 includes a pixel portion 101, a source driver 102, a first gate driver 103A, and a second gate driver 103B, and m (m is a positive integer) source lines 1041 to 104 each arranged parallel or substantially parallel to each other, and m n (n is a positive integer) gate lines 1051 to 105 n each arranged parallel or substantially parallel to each other. The pixel portion 101 is provided at the central portion of the display device 100, the source driver 102 is provided close to one side of the pixel portion 101, and the first gate driver 103A and the second gate driver 103B are provided close to a side different from the side where the source driver 10 2 is provided, and are arranged to face each other with the pixel portion 101 therebetween. The source driver 102 is electrically connected to the pixel portion 101 via m source lines 1041 to 104 m through, the first gate driver 103A is electrically connected to the pixel portion 101 via the odd-numbered ones of the n gate lines 1051 to 105 n , and the second gate driver 103B is electrically connected to the pixel portion n 101 via the even-numbered ones of the n gate lines 1051 to 105.

[0025] In addition, the source driver 102, the first gate driver 103A, and the second gate driver To the Ibar 103B, signals (such as a clock signal and a start pulse signal) are input via the flexible printed circuit boards 106A and 106B.

[0026] Furthermore, the pixel section 101 has n × m pixels 107 11 ~107 nm Note that the pixels 107 11 ~107 nm are arranged in n rows and m columns. Also, each of the m source lines 1041 ~104 m is electrically connected to n pixels arranged in each column, and each of the n gate lines 1 051~105 n is electrically connected to m pixels arranged in each row. In other words, for the pixel 1 05 ij arranged at the i-th row and j-th column (i and j are positive integers, where 1 ≤ i ≤ n and 1 ≤ j ≤ m), it is j electrically connected to the source line 104 i and the gate line 105.

[0027] That is, the source driver 102 is electrically connected to each pixel of the pixel section 101 via the m source lines 1041~104 m . The first gate driver 103A is electrically connected to each pixel arranged in the odd rows of the pixel section 101 via the odd-numbered ones of the n gate lines 1051~105 , and the second gate driver 103B is electrically connected to each pixel arranged in the even rows of the pixel section 101 via the even-numbered ones of the n gate lines 10 51~105 n . In the display device 100, the source driver 102 51~105 n is electrically connected to each pixel 10 7

[0028] <Operation Example of Display Device> has in the pixel section 101. 7 11~107 nm A circuit that outputs a video signal. The first gate driver 103A and the second gate driver 103B control the electrical connection between the source driver 102 and the pixels 107 11 ~107 n m .

[0029] The display device 100 inputs a video signal to each of the n×m pixels 107 11 ~107 nm to cause the pixel section 101 to display an image. The specific operation of the display device 100 will be described below .

[0030] First, the first gate driver 103A selects the m pixels arranged in the first row (the source driver 102 is electrically connected to the m pixels arranged in the first row), and via the source lines 104 1~104 m , a video signal is input to the m pixels 107 11 ~107 1m arranged in the first row. Next, the second gate driver 103B selects the m pixels arranged in the second row, and via the source lines 1041~104 , a video signal is input to the m pixels 10 arranged in the second row. Subsequently, in the same manner, the first gate driver 1 m 03A and the second gate driver 103B alternately select the m pixels in each row, and a video signal is input to each pixel 7 21 ~107 2m . By continuously performing the above operations, the display device 100 displays an image . .

[0031] <Configuration Example of Gate Driver> FIG. 2 shows the first gate driver 10 of the active matrix type display device 100 ​​It is a block diagram showing a detailed configuration example of a 3A and a second gate driver 103B.

[0032] The first gate driver 103A and the second gate driver 103B each have a plurality of flip - flop circuits and transfer signal generation circuits having at least three input terminals and one output terminal.

[0033] The first flip - flop circuit (F1) of the first gate driver 103A has an output terminal electrically connected to the first gate line 1051, a first input terminal electrically connected to the first start pulse signal (SP1) line, a second input terminal electrically connected to the clock signal (CK) line, and a third input terminal electrically connected to the stop pulse signal for the first flip - flop circuit (STP(F1)) line. (STP(F1)) line.

[0034] Also, the first transfer signal generation circuit (T1) of the first gate driver 103A has an output terminal electrically connected to the first input terminal of the third flip - flop circuit (F3), a first input terminal electrically connected to the output terminal of the first flip - flop circuit (F1), a second input terminal electrically connected to the inverted clock signal (CKB) line, and a third input terminal electrically connected to the stop pulse signal for the first transfer signal generation circuit (STP(T1)) line. (STP(T1)) line. (STP(T1)) line. .

[0035] The second flip - flop circuit (F2) of the second gate driver 103B has an output terminal electrically connected to the second gate line 1052, a first input terminal electrically connected to the second start pulse signal (SP2) line, a second input terminal electrically connected to the inverted clock signal (CKB ) line, and a third input terminal electrically connected to the stop pulse signal for the second flip - flop circuit It is electrically connected to the STP(F2) signal line.

[0036] Also, the second transfer signal generation circuit (T2) of the second gate driver 103B outputs The power terminal is electrically connected to the first input terminal of a fourth flip-flop circuit (not shown), The first input terminal is electrically connected to the output terminal of the second flip-flop circuit (F2), The second input terminal is electrically connected to the clock signal (CK) line, and the third input terminal is electrically connected to the second transfer signal stop pulse signal (STP(T2)) line.

[0037] The k-th (where k is an odd number of 3 or more) flip-flop circuit (F ) of the first gate driver 103A has an output terminal electrically connected to the k-th gate line 105 k k The first input terminal is electrically connected to the output terminal of the (k - 2)-th transfer signal generation circuit (T ) k-2 The second input terminal is electrically connected to the clock signal (CK) line, and the third input terminal is electrically connected to the stop pulse signal (STP(F )) line for the k-th flip-flop circuit. k

[0038] Also, the k-th transfer signal generation circuit (T k ) of the first gate driver 103A outputs The power terminal is electrically connected to the (k + 2)-th flip-flop circuit (F k+2 ) The first input terminal is electrically connected to the output terminal of the k-th flip-flop circuit (F k ) The second input terminal is electrically connected to the inverted clock signal (CKB) line, and the third input terminal is electrically connected to the stop pulse signal (STP(T )) line for the k-th transfer signal generation circuit. k

[0039] The (k + 1)-th flip-flop circuit (F k+1 ) included in the second gate driver 103B has an output terminal electrically connected to the (k + 1)-th gate line 105 k+1 , a first input terminal electrically connected to the output terminal of the (k - 1)-th transfer signal generation circuit (T k-1 ), a second input terminal electrically connected to the inverted clock signal (CKB) line, and a third input terminal electrically connected to the stop pulse signal (STP(F )) line for the (k + 1)-th flip-flop circuit k+1 .

[0040] Also, the (k + 1)-th transfer signal generation circuit (T k+1 ) included in the second gate driver 103B has an output terminal electrically connected to the first input terminal of the (k + 3)-th flip-flop circuit (F k+3 ), a first input terminal electrically connected to the output terminal of the (k + 1)-th flip-flop circuit (F ), a second input terminal electrically connected to the clock signal (CK) line, and k+1 a third input terminal electrically connected to the stop pulse signal (STP(T )) line for the (k + 1)-th transfer signal. k+1

[0041] The multiple flip-flop circuits and multiple transfer signal generation circuits included in the above-described first gate driver 103A and second gate driver 103B have common points and different points in their respective electrical connection relationships. Specific differences are listed below.

[0042] First, in the flip-flop circuit and transfer signal generation circuit included in the first gate driver, and in the flip-flop circuit and transfer signal generation circuit included in the second gate driver, Describe the differences in electrical connection relationships.

[0043] The second input terminal of the flip-flop circuit included in the first gate driver 103A is electrically connected to the clock signal (CK) line, and the second input terminal of the transfer signal generation circuit is electrically connected to the inverted clock signal (CKB) line. In contrast, the second input terminal of the flip-flop circuit included in the second gate driver 103B is electrically connected to the inverted clock signal (CKB) line, and the second input terminal of the transfer signal generation circuit is electrically connected to the clock signal (CK) line. continued. connected, and the third input terminal of all flip-flop circuits and the third input of the transfer signal generation circuit

[0044] Next, describe the differences in electrical connection relationships in all flip-flop circuits and transfer signal generation circuits.

[0045] Starting from the output terminal of the first flip-flop (F1) circuit being electrically connected to the first gate line 1051, the output terminals of each flip-flop circuit are electrically connected to the gate lines provided in the same row. On the other hand, starting from the output terminal of the first transfer signal generation circuit (T1) being electrically connected to the first input terminal of the third flip-flop circuit (F3), the output terminals of each transfer signal generation circuit are electrically connected to the first input terminals of the flip-flop circuits provided in the lower row. Note that the first input terminals of the first flip-flop circuit (F1) and the second flip-flop circuit (F2) where no transfer signal generation circuit is provided in the upper row are electrically connected to the first start pulse signal (SP1) line and the second start pulse signal (SP2) line, respectively.

[0046] Also, the third input terminals of all flip-flop circuits and the third input of the transfer signal generation circuit​​​​​​​​​​​​ The power terminals are electrically connected to different stop pulse signal (STP) lines respectively.

[0047] <Operation Example of Gate Driver> FIG. 3 is a diagram showing a timing chart. In FIG. 3, there are a clock signal (CK) , an inverted clock signal (CKB), a first start pulse signal (SP1), a second start pulse signal (SP2), output signals (F1OUT) to (F4OUT) of the first to fourth flip-flop circuits, and output signals (T1OUT) to (T4OUT) of the first to fourth transfer signal generation circuits shown. . The clock signal (CK) is a signal that repeats a high (hereinafter referred to as H) level signal and a low (hereinafter referred to as L) level signal at a constant period, and the inverted clock signal (CKB) is a signal in which the H level and the L level of the clock signal are inverted.

[0048] In period T1, the first start pulse signal (SP1) rises to the H level, and the H level signal is input to the first input terminal of the first flip-flop circuit (F1).

[0049] In period T2, the second start pulse signal (SP2) rises to the H level, and the H level signal is input to the first input terminal of the second flip-flop circuit (F2). Also, an H level signal is output from the first flip-flop circuit (F1). The H level signal output from the first flip-flop circuit (F1) is input to each pixel 107 of the first row arranged in the pixel section 101 via the first gate line 1051 11 ~107 1m . Thereby, each pixel 107 of the first row ~107 11 ~1071m and the source driver 102 are electrically connected, and video signals are input from the source driver 102 to each pixel 107 11 ~1071 arranged in the first row. Also, an H-level signal output from the first flip-flop circuit (F1) is input to the first input terminal of the first transfer signal generation circuit (T1). m

[0050] During period T3, an H-level signal is output from the second flip-flop circuit (F2). Similar to when the output signal of the aforementioned first flip-flop circuit (F1) is at the H level, the H-level signal output from the second flip-flop circuit (F2) is input to each pixel 107 in the second row arranged in the pixel section 101 via the second gate line 1052. 21 ~107 2m 21 ~107 2m and the source driver 10 21 ~ 107 2m and an H-level signal is output from the first transfer signal generation circuit (T1) and input to the first input terminal of the third flip-flop circuit (F3).

[0051] After period T4, the operations described above are repeated. That is, H-level signals are sequentially output from the flip-flop circuits after the third flip-flop circuit (F3), and accordingly, video signals are input to the plurality of arranged pixels for each row.

[0052] The display device described in this embodiment has active gate drivers of the first and second types. It is a matrix display device. Also, the first and second gate drivers each have a plurality of flip-flop circuits and a plurality of transfer signal generation circuits. Both the flip-flop circuit and the transfer signal generation circuit are circuits that delay the signal input to the first input terminal by half a cycle of the clock signal and output it. Also, the output terminal of the transfer signal generation circuit is directly connected to the first input terminal of the subsequent flip flop circuit. Therefore, it is possible to reduce the delay or attenuation of the signal input from the transfer signal generation circuit to the flip flop circuit.

[0053] In addition, in this embodiment, an example of a display device having one source driver and two gate drivers has been shown, but the embodiments of the present invention are not limited to this configuration. For example , a configuration in which the display device has only two gate drivers and a video signal is input from the outside, two , a configuration having two source drivers and two gate drivers, and the video signal is input from two source drivers , or a configuration in which each pixel is electrically connected to the gate driver via two gate lines are also aspects of the present invention.

[0054] (Embodiment 2) In this embodiment, specific examples of circuits applicable to the flip-flop circuit and the transfer signal generation circuit shown in Embodiment 1 will be described with reference to FIGS. 4 and 5. Specifically, an example of configuring the flip-flop circuit and the transfer signal generation circuit using transistors will be shown. Note that since the source terminal and drain terminal of the transistor change depending on the structure and operating conditions of the transistor, etc. , it is difficult to identify which is the source terminal or the drain terminal. Therefore, hereinafter, one of the source terminal and the drain terminal will be referred to as the first terminal, and the other will be referred to as the second terminal. will be referred to as the second terminal. The other of the source terminal and the drain terminal shall be denoted and distinguished as the second terminal.

[0055] <Circuit configuration example> FIG. 4 is a diagram showing an example of a circuit applicable to the k-th flip-flop circuit (F) and the k-th transfer signal generation circuit (T) included in the first gate driver 103A shown in Embodiment 1. Note that the k-th flip-flop circuit (F) shown in this embodiment includes the first transistor 401 to the fourth transistor 404, and the k-th transfer signal generation circuit (T) includes the fifth transistor 405 to the eighth transistor 408. Also, in this embodiment, the output signal (TOUT) of the k-th transfer signal generation circuit is used as the stop pulse signal (STP(F)) for the k-th flip-flop circuit, and the output signal (FOUT) of the (k + 2)-th flip-flop circuit is used as the stop pulse signal (STP(T)) for the k-th transfer signal generation circuit. -flop circuit (F k ) and the k-th transfer signal generation circuit (T k ) is shown. Note that the k-th flip-flop circuit (F k ) in this embodiment has the first transistor 401 to the fourth transistor 404, and the k-th transfer signal generation circuit (T k ) has the fifth transistor 405 to the eighth transistor 408. Also, in this embodiment, the output signal of the k-th transfer signal generation circuit is used as the stop pulse signal (STP(F k )) for the k-th flip-flop circuit, and the output signal (T k OUT) of the k-th transfer signal generation circuit is used, and the output signal (F k OUT) of the (k + 2)-th flip-flop circuit is used as the stop pulse signal (STP(T )) for the k-th transfer signal generation circuit. k+2

[0056] The gate terminal and the first terminal of the first transistor 401 are electrically connected to the output terminal of the (k - 2)-th transfer signal generation circuit (not shown).

[0057] The gate terminal of the second transistor 402 is electrically connected to the output terminal of the k-th transfer signal generation circuit (T k ), the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the second terminal of the first transistor 401.

[0058] The third transistor 403 has its gate terminal electrically connected to the second terminal of the first transistor 401 and the second terminal of the second transistor 402, its first terminal electrically connected to the clock signal (C K) line, and its second terminal electrically connected to the first input k end of the k-th transfer signal generation circuit (T ).

[0059] The fourth transistor 404 has its gate terminal electrically connected to the output k end of the k-th transfer signal generation circuit (T ), its first terminal electrically connected to the ground potential (VSS) line, and its second terminal electrically connected to the first input terminal of the k-th transfer signal generation circuit (T k ) and the second terminal of the third transistor 403.

[0060] The fifth transistor 405 has its gate terminal and first terminal electrically connected to the output terminal of the k-th flip-flop circuit k (F

[0061] The sixth transistor 406 has its gate terminal electrically connected to the output terminal of the (not shown) k+2-th flip-flop circuit, its first terminal electrically connected to the ground potential (VSS) line, and its second terminal electrically connected to the second terminal of the fifth transistor 405. connected, and its second terminal electrically connected to the second terminal of the fifth transistor 405.

[0062] The seventh transistor 407 has its gate terminal electrically connected to the second terminal of the fifth transistor 405 and the second terminal of the sixth transistor 406, its first terminal electrically connected to the inverted clock signal (CKB) line, and its second terminal electrically connected to the k third input terminal of the k-th flip-flop circuit (F ) and the first input terminal of the k+2-th flip-flop circuit (not shown).​

[0063] The eighth transistor 408 has a gate terminal electrically connected to the output terminal of the (not shown) (k + 2)-th flip-flop circuit, a first terminal electrically connected to the ground potential (VSS) line, and a second terminal electrically connected to the third input terminal of the k-th flip-flop circuit (F ), the first input terminal of the (k + 2)-th flip-flop circuit (not shown), and the second terminal of the seventh transistor 407 . k ) As shown in FIG. 4, the same circuit configuration can be applied to the k-th flip-flop circuit (F ) and the k-th transfer signal generation circuit (

[0064] T k ). However, it is preferable to pay attention to the following points when designing the circuit k .

[0065] The k-th flip-flop circuit (F k ) is a circuit that drives the k-th gate line, and the k-th transfer signal generation circuit (T ) is a circuit that drives the (k + 2)-th flip-flop circuit k . As described above, various parasitic resistances and parasitic capacitances exist in the k-th gate line. Therefore, the load of the k-th flip-flop circuit (F ) is larger than the load of the k-th transfer signal generation circuit (T ). That is, when designing the above-described circuit, it is preferable that the current driving ability of the first transistor 40 k 1 is higher than the current driving ability of the fifth transistor 405 k . For example, the channel width of the first transistor 401 may be made larger than the channel width of the fifth transistor 405 . For the same reason, the current driving ability of the second transistor 402 nel width. For the same reason, the current driving ability of the second transistor 402 ​​​​The ability is higher than the current driving ability of the sixth transistor 406, and the current driving ability of the third transistor 4 03 is higher than the current driving ability of the seventh transistor 407. The current driving ability of the fourth transistor 404 is preferably higher than the current driving ability of the eighth transistor 408. For example, the current driving ability can be improved by increasing the ratio of the channel width to the channel length (channel width / channel length (W / L)) of the channel.

[0066] Also, among the first transistor 401 to the fourth k transistors 404 of the k-th flip-flop circuit (F ), it is preferable that the current driving ability of the third transistor 403 directly involved in driving the k-th gate line is the highest. Similarly, among the fifth transistor 405 to the eighth transistor 408 of the k-th transfer signal generation circuit (T ), it is preferable that the current driving ability of the seventh transistor 407 directly involved in driving the (k + 2)-th flip-flop circuit is the highest. k

[0067] Also, the circuit configuration shown in FIG. 4 can be applied to the first flip-flop circuit (F1) and the first transfer signal generation circuit (T1) of the first gate driver 103A. However, in the first flip-flop circuit (F1), the gate terminal and the first terminal of the first transistor 401 are electrically connected to the first start pulse signal (SP1) line, which is different from the configuration of FIG. 4.

[0068] Also, the (k + 1)-th flip-flop circuit (F k +1 ​​​​​​​​​​​) and the (k + 1)-th transfer signal generation circuit (T k+1 ) can also apply the circuit configuration shown in FIG. 4. However, in the (k + 1)-th flip-flop circuit (F ) and the (k + 1)-th k+1 ) transfer signal generation circuit (T ), the first terminal of the third transistor 403 is electrically connected to the inverted k+1 clock signal (CKB) line, and the first terminal of the seventh transistor 407 is electrically connected to the clock signal (CK) line, which is different from the configuration of FIG. 4.

[0069] Also, the second flip-flop circuit (F2) and the second transfer signal generation circuit (T2) included in the second gate driver 103B can also apply the circuit configuration shown in FIG. 4. However, in the second flip-flop circuit (F2) and the second transfer signal generation circuit (T2), the gate terminal and the first terminal of the first transistor 401 are electrically connected to the second start pulse signal (SP2) line, and the first terminal of the third transistor 403 is electrically connected to the inverted clock signal (CKB) line, and the first terminal of the seventh transistor 407 is electrically connected to the clock signal (CK) line, which is different from the configuration of FIG. 4.

[0070] Note that in this embodiment, the output signal (F k OUT) of the (k + 2)-th flip-flop circuit is used as the stop pulse signal (STP(T k+2 )) for the k-th transfer signal generation circuit. Therefore, for a plurality of pixels arranged in n rows, a (n + 1)-th flip-flop circuit is provided as a dummy circuit in the first gate driver 103A, and a (n + 2)-th flip-flop circuit needs to be provided as a dummy circuit in the second gate driver . 103B. Note that as the dummy circuit, a flip-flop circuit that only supplies the stop pulse signal for the transfer signal generation circuit and does not drive the gate line can be applied. Also, by providing a wiring (dummy gate line) that does not participate in display together with the dummy circuit, as the dummy circuit, a flip-flop circuit that supplies the stop pulse signal for the transfer signal generation circuit and drives the wiring can also be applied.

[0071] <Circuit operation example> FIG. 5 is a diagram showing the timing charts of the input signals and output signals of the k-th flip-flop circuit (F k ) and the k-th transfer signal generation circuit (T ) shown in FIG. 4. The operations of the k-th flip-flop circuit (F k ) and the k-th transfer signal generation circuit (T ) will be described below. k k

[0072] During period t1, the output signal (T k-2 OUT) of the (k - 2)-th transfer signal generation circuit rises to the H level. As a result, the diode-connected first transistor 401 turns on , and the potential of the gate terminal of the third transistor 403 rises to the H level. Therefore, the L-level signal, which is the clock signal (CK) during period t1, is output as the output signal (F OUT) of the k-th flip-flop circuit. k

[0073] During period t2, the output signal (T k-2 OUT) of the (k - 2)-th transfer signal generation circuit drops to the L level and the clock signal (CK) rises to the H level. As a result, the diode-connected first transistor 401 turns off, and the third transistor, which has become in a floating state ​​​​​​​​​​ The potential of the gate terminal of transistor 403 is lifted (bootstrap operation) by the H-level signal input to the first terminal of the third transistor 403 and further increases. Also, the third transistor 403 maintains its on state, and the H-level signal is output as the output signal (F OUT) of the k-th flip-flop circuit (F ). This H-level signal is input to the gate terminal and the first terminal of the fifth transistor 405. As a result, the fifth diode-connected transistor 405 turns on, and the potential of the gate terminal of the seventh transistor 407 rises to the H level. Therefore, the L-level signal, which is the inverted clock signal (CKB ) during period t2, is output as the output signal (T k OUT) of the k-th transfer signal generation circuit. k k

[0074] During period t3, the clock signal (CK) drops to the L level while the inverted clock signal (CKB) rises to the H level. As a result, the diode-connected fifth transistor 405 turns off, and the potential of the gate terminal of the seventh transistor 407, which has become floating, is lifted (bootstrap operation) by the H-level signal input to the first terminal of the seventh transistor 407 and further increases. Also, the seventh transistor 407 maintains its on state, and the H-level signal is output as the output signal (T k k OU T) of the k-th transfer signal generation circuit (T ). This H-level signal is input to the gate terminals of the second transistor 402 and the fourth transistor 404. As a result, the second transistor 402 turns on, and the potential of the gate terminal of the third transistor 403 drops to the L level. Therefore, ​​​​​​​​​​​​​​ The third transistor 403 turns off. Also, since the fourth transistor 404 also turns on, a signal at the L level is output as the output signal (F k ) of the k-th flip-flop circuit (F k OUT).

[0075] During period t4, the output signal (F k+2 OUT) of the (k + 2)-th flip-flop circuit rises to the H level. As a result, the sixth transistor 406 turns on, and the potential of the gate terminal of the seventh transistor 407 drops to the L level. Therefore, the seventh transistor 4 07 turns off. Also, since the eighth transistor 408 also turns on, a signal at the L level is output as the output signal (T ) of the k-th transfer signal generation circuit (T k OUT). k k

[0076] Note that the circuit operations of the first flip-flop circuit and the first transfer signal generation circuit, the (k + 1)-th flip-flop circuit and the (k + 1)-th transfer signal generation circuit, and the second flip-flop circuit and the second transfer signal generation circuit are the same as those of the k-th flip-flop circuit (F ) and the k k-th transfer signal generation circuit (T k k ) described above.

[0077] <Modification Example> In this embodiment, as the stop pulse signal (STP(F k )) for the k-th flip-flop circuit and the stop pulse signal (STP(T k )) for the k-th transfer signal generation circuit, the output signal of the k-th transfer signal generation circuit (T k ) and the output signal of the (k + 2)-th flip-flop circuit ( F k+2 ​​​)'s output signal was applied, but the configuration of this embodiment is not limited to this configuration.

[0078] For example, as the stop pulse signal (STP(F k )) for the k-th flip-flop circuit and the stop pulse signal (STP(T )) for the k-th transfer signal generation circuit, the output signals of the (k + k 1)-th flip-flop circuit (F ) and the (k + 1)-th transfer signal generation circuit (T k+1 ) can be applied respectively. In this case, the stop pulse signal (STP(F k+1 )) for the k-th flip-flop circuit and the stop pulse signal (STP(T )) for the k-th transfer signal generation circuit will be a delayed or dulled signal compared to the above-described configuration. However, since the output signals of the k-th flip-flop circuit (F k ) and the k-th transfer signal generation circuit (T ) during this period will be at the L level, the delay and dulling of the stop pulse signal (STP) will not be a problem. k )) During this period, the k-th flip-flop circuit (F k ) and the k-th transfer signal generation circuit (T k ) Since the output signals are at the L level, the delay and dulling of the stop pulse signal (STP) will not be a problem.

[0079] (Embodiment 3) In this embodiment, specific examples different from those of Embodiment 2 of the circuit applicable to the flip-flop circuit and the transfer signal generation circuit shown in Embodiment 1 will be described with reference to FIGS. 6 and 7.

[0080] <Circuit Configuration Example> FIG. 6 is a diagram showing an example of a circuit applicable to the k-th flip-flop circuit (F ) and the k-th transfer signal generation circuit (T k ) included in the first gate driver 103A shown in Embodiment 1. The k-th flip-flop circuit (F k ) shown in this embodiment FIG. 6 is a diagram showing an example of a circuit applicable to the k-th flip-flop circuit (F k) has the first transistor 601 to the fifth transistor 605, and an inverter circuit 600, and the k-th transfer signal generation circuit (T k ) has the sixth transistor 606 to the eighth transistor 608 . Note that the circuit shown in FIG. 6 is the k-th flip-flop circuit (F k ) shown in FIG. 4 with an inverter circuit 600 and a fifth transistor 605 added, and the k-th transfer signal generation circuit (T k ) can be said to be a circuit in which the eighth transistor 408 is deleted. .

[0081] Since the electrical connection relationships of the first transistor 601, the second transistor 602, and the third transistor 60 3 are the same as those of the circuit shown in FIG. 4, the description of Embodiment 2 will be referred to .

[0082] The input terminals of the inverter circuit 600 are electrically connected to the second terminal of the first transistor 601, the second terminal of the second transistor 60 2, and the gate terminal of the third transistor 603. continued.

[0083] The gate terminal of the fourth transistor 604 is electrically connected to the output terminal of the inverter circuit 600, the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is the second terminal of the third transistor 60 3 and the first input terminal of the k-th transfer signal generation circuit (T ) are electrically connected. k connected.

[0084] The gate terminal of the fifth transistor 605 is electrically connected to the output terminal of the inverter circuit 600, the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is the first terminal of the first transistor 60 connected. The second terminal of the transistor 601, the second terminal of the second transistor 602, the gate terminal of the third transistor 603, and the input terminal of the inverter circuit 600 are electrically connected.

[0085] The k-th transfer signal generation circuit (T k ) shown in FIG. 6 is a circuit obtained by removing the eighth transistor 408 from the k-th transfer signal generation circuit shown in FIG. 4. Since the electrical connection relationships of the other transistors k are the same as those of the circuit shown in FIG. 4, the description of Embodiment 2 will be incorporated by reference. However, when designing the circuit shown in FIG. 6, it is necessary to design as follows.

[0086] When an H-level signal is input to the inside of the k-th flip-flop circuit (F

[0087] k ) (the diode-connected first transistor 6 01), it is necessary to design such that an H-level signal is surely input to the input terminal of the inverter circuit 600. More specifically, it is necessary to make the current driving ability of the first transistor 601 higher than that of the fifth transistor 605. For example, it is necessary to make the channel width of the first transistor 601 larger than the channel width of the fifth transistor 605.

[0088] Also, in the period t4 shown in FIG. 5, it is necessary to design such that the output signal (T k OU T) of the k-th transfer signal generation circuit becomes an L level. More specifically, it is necessary to make the current driving ability of the eighth transistor 608 higher than that of the seventh transistor 607. Thereby, when an H-level signal is input to the gate terminal of the seventh transistor 607 ​​​​As a result, the seventh transistor 607 turns on, and the ground potential (VSS) is input to the gate terminal of the eighth transistor 608, causing the eighth transistor 608 to turn off. Before this operation is performed, the output signal (T OUT) of the k-th transfer signal generation circuit can be reduced to the L level, which is the inverted clock signal (CKB) in period t4. Also, when designing the circuit shown in FIG. 6, it is preferable to pay attention to the points described in Embodiment 2. That is, it is preferable that the current driving ability of the first transistor 601 is higher than that of the sixth transistor 606, the current driving ability of the second transistor 602 is higher than that of the seventh transistor 607, and the current driving ability of the third transistor 603 is higher than that of the eighth transistor 608. k

[0089] Among the first transistor 601 to the fifth transistor 605 included in the k-th flip-flop circuit (F ), it is preferable that the current driving ability of the third transistor 603 is the highest. Among the sixth transistor 606 to the eighth transistor 608 included in the k-th transfer signal generation circuit (T

[0090] ), it is preferable that the current driving ability of the eighth transistor 608 is the highest. Note that FIG. 6 shows only the k-th flip-flop circuit (F

[0091] k ) and the k-th transfer signal generation circuit (T

[0092] k ), but the (k + 1)-th flip-flop circuit and the (k + 1)-th transfer signal generation k circuit are not shown.

[0092] Note that FIG. 6 shows only the k-th flip-flop circuit (F k ) and the k-th transfer signal generation circuit (T k ) for the k-th flip-flop circuit and the k-th transfer signal generation circuit. For the (k + 1)-th flip-flop circuit and the (k + 1)-th transfer signal generation ​The circuit shown in FIG. 6 is also applicable to a circuit or the like. However, as described in Embodiment 2, the electrical connection relationships of some terminals are different. The specific differences in the connection relationships will be referred to the description of Embodiment 2.

[0093] FIGS. 7(A) and 7(B) are diagrams showing specific examples of circuits applicable to the inverter circuit 600 shown in FIG. 6. In FIGS. 7(A) and 7(B), the wiring marked with "IN" is the input wiring, and the wiring marked with "OUT" is the output wiring.

[0094] The inverter circuit 600A shown in FIG. 7(A) is composed of a diode-connected transistor 7 01A and a transistor 702A.

[0095] The gate terminal and the first terminal of the transistor 701A are electrically connected to the power supply potential (VDD) line, and the second terminal is electrically connected to the output terminal of the inverter circuit 600A.

[0096] The gate terminal of the transistor 702A is electrically connected to the input terminal of the inverter circuit 600A, the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the output terminal of the inverter circuit 600A and the second terminal of the transistor 701A.

[0097] Since the inverter circuit 600A shown in FIG. 7(A) is composed of two transistors 701A and 702 A, an increase in the circuit area can be minimized.

[0098] However, when the inverter circuit 600A shown in FIG. 7(A) is applied as the inverter circuit 600 in FIG. 6, when the transistor 702A is on, the output signal is at the L level. ​​​​​It is necessary to design it to be so. More specifically, the current driving ability of transistor 702A needs to be higher than the current driving ability of transistor 701A. For example, making the channel length of transistor 702A smaller than the channel length of transistor 701A, or making the channel width of transistor 702A larger than the channel width of transistor 701A is necessary.

[0099] The inverter circuit 600B shown in FIG. 7(B) is composed of a diode-connected transistor 7 01B and transistors 702B, 703B, and 704B.

[0100] The gate terminal and the first terminal of transistor 701B are electrically connected to the power supply potential (VDD) line.

[0101] The gate terminal of transistor 702B is electrically connected to the input terminal of inverter circuit 600B, the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the second terminal of transistor 701B.

[0102] The gate terminal of transistor 703B is electrically connected to the second terminal of transistor 701B and the second terminal of transistor 702B, the first terminal is electrically connected to the power supply potential (VDD) line, and the second terminal is electrically connected to the output terminal of inverter circuit 600B.

[0103] The gate terminal of transistor 704B is electrically connected to the input terminal of inverter circuit 600B, the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the output terminal of inverter circuit 600B and the second terminal of transistor 703B.

[0104] In the inverter circuit 600B shown in FIG. 7(B), the diode-connected transistor 7 01B is not directly connected to the output terminal of the inverter circuit 600B. Therefore, the output signal can be suppressed from decreasing from the power supply potential (VDD) or increasing from the ground potential (VSS). It is possible.

[0105] However, when applying the inverter circuit 600B shown in FIG. 7(B) as the inverter circuit 600 in FIG. 6, when the transistor 702B is on, the transistor 703 B needs to be designed to turn off. More specifically, it is necessary to make the current driving ability of the transistor 702B higher than that of the transistor 701B. For example , it is necessary to make the channel length of the transistor 702B smaller than the channel length of the transistor 701B , or to make the channel width of the transistor 702B larger than the channel width of the transistor 701B . There is a need.

[0106] <Difference from the circuit shown in Embodiment 2> The k-th flip-flop circuit (F k ) shown in FIG. 6 includes an inverter circuit 600 and a gate terminal of which is electrically connected to the output terminal of the inverter circuit 600, a first terminal is electrically connected to the ground potential (V SS) line, and a second terminal is electrically connected to the input terminal of the inverter circuit 600 and the fifth transistor 605. Thus, the fifth transistor 605 electrically connected to the inverter circuit 600 always remains on once it is turned on . When the fifth transistor 605 is in the on state, the potential of the gate terminal of the third transistor 603 is kept at the ground potential (VSS). Therefore, the third transistor 605 The potential of the gate terminal is maintained at the ground potential (VSS). Therefore, the third transistor Even when noise enters the gate terminal of the transistor 603, the third transistor 603 will not turn on. That is, it will not cause defects in the image or video of the display device, and the performance of the display device can be improved.

[0107] The k-th transfer signal generation circuit (T k ) shown in FIG. 6 is composed of three transistors 606 to 608 , so it is possible to reduce the circuit area.

[0108] <Modification Example> In this embodiment, the flip-flop circuit is composed of five transistors 601 to 605 and an inverter circuit 600, and the transfer signal generation circuit is composed of three transistors 606 to 608 has been shown. However, the embodiment is not limited to this configuration. For example, the k-th flip-flop circuit (F k ) and the k-th transfer signal generation circuit (T k ) may both have the same configuration as the k-th flip-flop circuit (F k ) or the k-th transfer signal generation circuit (T k ) shown in FIG. 6. Also, the circuit shown in Embodiment 2 (FIG. 4) and the circuit shown in this embodiment (FIG. 6) may be combined to form a flip-flop circuit and a transfer signal generation circuit .

[0109] Also, in this embodiment, the stop pulse signal for the k-th flip-flop circuit (STP (F k )) and the stop pulse signal for the k-th transfer signal generation circuit (STP(T k )) are respectively the output signal of the k-th transfer signal generation circuit (T ) and the output signal of the k + 2-th flip-flop k circuit (F ) and the output signal of the k + 2-th flip-flop circuit (F k+2) The output signal was applied, but the configuration of this embodiment is not limited to this configuration. No.

[0110] (Embodiment 4) In this embodiment, specific examples different from those of Embodiments 2 and 3 of the circuit applicable to the flip-flop circuit and the transfer signal generation circuit shown in Embodiment 1 will be described with reference to FIGS. 8 and 9. using FIGS. 8 and 9. will be described.

[0111] <Circuit configuration example> FIG. 8 shows an example of a circuit applicable to the k-th flip-flop circuit (F ) and the k-th transfer signal generation circuit (T k ) included in the first gate driver 103A shown in Embodiment 1. This is a diagram showing an example of a circuit applicable to the k-th flip-flop circuit (F k ) and the k-th transfer signal generation circuit (T ) shown in this embodiment. The k-th flip-flop circuit (F k ) shown in this embodiment includes a first transistor 801 to a fifth transistor 805 and a control circuit 800, and the k-th transfer signal generation circuit (T ) includes a sixth transistor 806 to a ninth transistor 809. The circuit shown in FIG. 8 can be rephrased as a circuit in which a control circuit 800 and a fifth transistor 805 are added to the circuit shown in FIG. 4, and the first terminal of the sixth transistor 806 (corresponding to the fifth transistor 4 05 in FIG. 4) is not a gate terminal but is electrically connected to the power supply potential (VDD) line. k ) has a sixth transistor 806 to a ninth transistor 809. Note that the electrical connection relationships of the first transistor 801, the second transistor 802, and the third transistor 80 3 are the same as those of the circuits shown in FIGS. 4 and 6, so the description of Embodiment 2 will be incorporated. 05) is not the gate terminal but is electrically connected to the power supply potential (VDD) line. It can be said that the circuit shown in FIG. 8 is a circuit in which a control circuit 800 and a fifth transistor 805 are added to the circuit shown in FIG. 4, and the first terminal of the sixth transistor 806 (corresponding to the fifth transistor 4

[0112] The electrical connection relationships of the first transistor 801, the second transistor 802, and the third transistor 80 3 are the same as those of the circuits shown in FIGS. 4 and 6, so the description of Embodiment 2 will be incorporated. shall be incorporated.

[0113] The control circuit 800 has a first input terminal connected to a second terminal of the first transistor 801, a second terminal of the transistor 802 and a gate terminal of the third transistor 803; The first input terminal is electrically connected to a clock signal (CK) line.

[0114] The fourth transistor 804 has a gate terminal electrically connected to the output terminal of the control circuit 800. The first terminal is electrically connected to a ground potential (VSS) line, and the second terminal is connected to a third transistor. The second terminal of the transfer signal generating circuit (T k ) to the first input terminal Connected.

[0115] The fifth transistor 805 has a gate terminal electrically connected to the output terminal of the control circuit 800. The first terminal is electrically connected to a ground potential (VSS) line, and the second terminal is connected to a first transistor. a second terminal of the first transistor 801, a second terminal of the second transistor 802, a second terminal of the third transistor 80 3 and a first input terminal of the control circuit 800.

[0116] The sixth transistor 806 has a gate terminal connected to the kth flip-flop circuit (F k ) The first terminal is electrically connected to the input terminal, and the second terminal is electrically connected to a power supply potential (VDD) line.

[0117] A seventh transistor 807, an eighth transistor 808, and a ninth transistor 80 The electrical connection relationship of the sixth transistor 606 and the seventh transistor 607 shown in FIG. Since the transistors are the same as the transistors 607 and 608, the description of the second embodiment is applicable. It has been decided that.

[0118] However, when designing the circuit shown in Fig. 8, it is necessary to design as follows.

[0119] When a signal of H level is input to the inside of the k-th flip-flop circuit (F k ), specifically, the diode-connected first transistor 8 01, it is necessary to design so that a signal of H level is surely input to the input terminal of the control circuit 800. More specifically, it is necessary to make the current driving ability of the first transistor 801 higher than that of the fifth transistor 8 05. For example, it is necessary to make the channel width of the first transistor 801 larger than that of the fifth transistor 805 .

[0120] Also, when designing the circuit shown in Fig. 8, it is preferable to pay attention to the points described in Embodiment 2. That is, it is preferable that the current driving ability of the first transistor 801 is higher than that of the sixth transistor 806, the current driving ability of the second transistor 802 is higher than that of the seventh transistor 8

[0121] 07, the current driving ability of the third transistor 803 is higher than that of the eighth transistor 808, and the current driving ability of the fourth transistor 804 is higher than that of the ninth transistor 809.

[0122] Also, among the first transistor 801 to the fifth k transistors 805 of the k-th flip-flop circuit (F ), it is preferable that the current driving ability of the third transistor 803 is the highest. Among the sixth transistor 806 to the ninth transistor 8 of the k-th transfer signal generation circuit (T ), it is preferable that the current driving ability of the third transistor 803 is the highest. Among the sixth transistor 806 to the ninth transistor 8 of the k-th transfer signal generation circuit (T k ), it is preferable that the current driving ability of the third transistor 803 is the highest. Among the switches 809, it is preferable that the current driving ability of the eighth transistor 808 is the highest. Yes.

[0123] Note that FIG. 8 shows only the k-th flip-flop circuit (F k ) and the k-th transfer signal generation circuit (T k ), but the circuit of FIG. 8 is also applicable to the (k + 1)-th flip-flop circuit (F k+1 ) and the (k + 1)-th transfer signal generation circuit (T k+1 ), etc. However, as described in Embodiment 2, the electrical connection relationships of some terminals are different. The specific differences in the connection relationships shall be based on the description of Embodiment 2.

[0124] FIGS. 9(A) and 9(B) are diagrams showing specific examples of circuits applicable to the control circuit 800 shown in FIG. 8. In FIGS. 9(A) and 9(B), the wiring marked with "IN" is the first input wiring, the wiring marked with "CK" is the second input wiring electrically connected to the clock signal (CK) line, and the wiring marked with "OUT" is the output wiring.

[0125] The control circuit 800A shown in FIG. 9(A) is composed of a capacitor element 901A and a transistor 902A.

[0126] One terminal of the capacitor element 901A is electrically connected to the clock signal (CK) line, and the other terminal is electrically connected to the output terminal of the control circuit 800A.

[0127] The gate terminal of the transistor 902A is electrically connected to the first input terminal of the control circuit 800A, the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the output terminal of the control circuit 80 0A and the other terminal of the capacitor element 901A.

[0128] After the period t3 shown in FIG. 5, a signal of the L level is input to the first input terminal of the control circuit 800A, and the transistor 902A is turned off. As a result, the output signal of the control circuit 800A becomes a floating state. Therefore, a signal synchronized with the clock signal (CK) is output as the output signal of the control circuit 800A. However, when the control circuit 800A shown in FIG. 9(A) is applied as the control circuit 800 in FIG. 8, when changing from the period t2 to the period t3, it is necessary to design such that the output terminal of the control circuit 800A becomes a floating state after the potential of one terminal of the capacitive element 901A drops to the L level. However, when the control circuit 800A shown in FIG. 9(A) is applied as the control circuit 800 in FIG. 8, when changing from the period t2 to the period t3, it is necessary to design such that the output terminal of the control circuit 800A becomes a floating state after the potential of one terminal of the capacitive element 901A drops to the L level. However, when the control circuit 800A shown in FIG. 9(A) is applied as the control circuit 800 in FIG. 8, when changing from the period t2 to the period t3, it is necessary to design such that the output terminal of the control circuit 800A becomes a floating state after the potential of one terminal of the capacitive element 901A drops to the L level.

[0129] However, when the control circuit 800A shown in FIG. 9(A) is applied as the control circuit 800 in FIG. 8, when changing from the period t2 to the period t3, it is necessary to design such that the output terminal of the control circuit 800A becomes a floating state after the potential of one terminal of the capacitive element 901A drops to the L level. However, when the control circuit 800A shown in FIG. 9(A) is applied as the control circuit 800 in FIG. 8, when changing from the period t2 to the period t3, it is necessary to design such that the output terminal of the control circuit 800A becomes a floating state after the potential of one terminal of the capacitive element 901A drops to the L level. However, when the control circuit 800A shown in FIG. 9(A) is applied as the control circuit 800 in FIG. 8, when changing from the period t2 to the period t3, it is necessary to design such that the output terminal of the control circuit 800A becomes a floating state after the potential of one terminal of the capacitive element 901A drops to the L level. However, when the control circuit 800A shown in FIG. 9(A) is applied as the control circuit 800 in FIG. 8, when changing from the period t2 to the period t3, it is necessary to design such that the output terminal of the control circuit 800A becomes a floating state after the potential of one terminal of the capacitive element 901A drops to the L level.

[0130] The control circuit 800B shown in FIG. 9(B) is composed of a diode-connected transistor 901B, a transistor 902B, a transistor 903B, and a transistor 904B. The control circuit 800B shown in FIG. 9(B) is composed of a diode-connected transistor 901B, a transistor 902B, a transistor 903B, and a transistor 904B. The control circuit 800B shown in FIG. 9(B) is composed of a diode-connected transistor 901B, a transistor 902B, a transistor 903B, and a transistor 904B.

[0131] The gate terminal and the first terminal of the transistor 901B are electrically connected to the clock signal (CK) line. The gate terminal and the first terminal of the transistor 901B are electrically connected to the clock signal (CK) line.

[0132] The gate terminal of the transistor 902B is electrically connected to the first input terminal of the control circuit 800B, the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the second terminal of the transistor 901B. The gate terminal of the transistor 902B is electrically connected to the first input terminal of the control circuit 800B, the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the second terminal of the transistor 901B. The gate terminal of the transistor 902B is electrically connected to the first input terminal of the control circuit 800B, the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the second terminal of the transistor 901B.

[0133] The gate terminal of the transistor 903B is electrically connected to the second terminal of the transistor 901B and the second terminal of the transistor 902B, and the first terminal is electrically connected to the clock signal (CK) line. The gate terminal of the transistor 903B is electrically connected to the second terminal of the transistor 901B and the second terminal of the transistor 902B, and the first terminal is electrically connected to the clock signal (CK) line. is connected, and the second terminal is electrically connected to the output terminal of the control circuit 800B.

[0134] The gate terminal of the transistor 904B is electrically connected to the input terminal of the control circuit 800B , the first terminal is electrically connected to the ground potential (VSS) line, and the second terminal is electrically connected to the output terminal of the control circuit 800B and the second terminal of the transistor 903B.

[0135] However, when the control circuit 800B shown in FIG. 9(B) is applied as the control circuit 800 in FIG. 8, it is necessary to design such that the transistor 903B turns off when the transistor 902B is on. More specifically, it is necessary to make the current driving ability of the transistor 902B higher than that of the transistor 901B. For example, it is necessary to make the channel length of the transistor 902B smaller than the channel length of the transistor 901B, or to make the channel width of the transistor 902B larger than the channel width of the transistor 901B.

[0136] <Differences from the circuits shown in Embodiments 2 and 3> The control circuits 800A and 800B shown in FIGS. 9(A) and 9(B) output a clock signal (CK) or a signal synchronized with the clock signal (CK). Therefore, even when noise enters the gate terminal of the third transistor 80 3, the noise can be removed by the fourth transistor 804 and the fifth transistor 805 turning on. Also, the fourth transistor 804 and the fifth transistor 805 do not always turn on, and the deterioration of the fourth transistor 804 and the fifth transistor 805 can be suppressed. ​​​​That is, it is possible to improve the performance and reliability of the display device without causing defects in the video of the display device. It can be done.

[0137] <Modification Example> In this embodiment, an example in which the flip-flop circuit is composed of five transistors 801 to 805 and the control circuit 800, and the transfer signal generation circuit is composed of four transistors 806 to 809 is shown. However, the embodiment is not limited to this configuration. For example, the k-th flip-flop circuit (F ) and the k-th transfer signal generation circuit (T ) may both have the same configuration as the k-th flip-flop circuit (F ) or the k-th transfer signal generation circuit (T k ) shown in FIG. 8. Also, the circuit shown in Embodiment 2 (FIG. 4) or Embodiment 3 (FIG. 6) and the circuit shown in this embodiment (FIG. 8) may be combined to form a flip-flop circuit and a transfer signal generation circuit. k The k-th flip-flop circuit (F k ) or the k-th transfer signal generation circuit (T k ) may have the same configuration. In addition, in this embodiment, the k-th flip-flop circuit stop pulse signal (STP (F )) and the k-th transfer signal generation circuit stop pulse signal (STP (T

[0138] )) are respectively the output signal of the k-th transfer signal generation circuit (T (F k )) and the output signal of the k + 2-th flip-flop circuit (F k ). However, the configuration of this embodiment is not limited to this configuration. k The circuit (F k+2 ) is not limited to this configuration.

[0139] (Embodiment 5) In this embodiment, specific examples of the transistors included in the flip-flop circuit and the transfer signal generation circuit shown in Embodiments 2 to 4 will be described.

[0140] As the transistor, transistors with various materials and structures can be applied. That is, there is no limitation on the type of transistor to be used. For example, amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as microcrystal, nanocrystal, semi-amorphous) silicon and the like, a thin film transistor (TFT) having a non-single crystal semiconductor film can be used.

[0141] When manufacturing a display device using a thin film transistor, there are various advantages. First, since the thin film transistor can be manufactured at a lower temperature than a transistor using single crystal silicon, it is possible to reduce the manufacturing cost of the display device or to reduce the size of the manufacturing equipment. Also, since the thin film transistor has a low manufacturing temperature, it can be manufactured on a substrate with low heat resistance. Therefore, a transistor can be manufactured on a substrate having low heat resistance and light transmissivity. Also, since the thin film transistor has a thin film thickness, light can be transmitted through a part of the film forming the transistor. Therefore, the aperture ratio can be improved.

[0142] Also, as the transistor, a MOS transistor, a junction transistor, a bipolar transistor, etc. can also be used. By using a MOS transistor as the transistor, the size of the transistor can be reduced. Also, by using a bipolar transistor as the transistor, a large current can be passed. Therefore, the circuit can be operated at high speed. Note that a MOS transistor and a bipolar transistor may be mixed and formed on one substrate. Thus, ​Thus, low power consumption, miniaturization, high-speed operation, etc. can be achieved.

[0143] When manufacturing polycrystalline silicon, by using a catalyst (such as nickel), the crystallinity can be further improved, and a thin-film transistor with good electrical characteristics can be manufactured. As a result, a gate driver, a source driver, and a signal processing circuit (such as a signal generation circuit, a gamma correction circuit, a DA conversion circuit, etc.) can be integrally formed on a substrate.

[0144] Also, when manufacturing microcrystalline silicon, by using a catalyst (such as nickel), the crystallinity can be further improved, and a transistor with good electrical characteristics can be manufactured. At this time, it is also possible to improve the crystallinity only by applying heat treatment without performing laser irradiation. As a result, a part of the source driver (such as an analog switch) and the gate driver can be integrally formed on a substrate. Note that when laser irradiation is not performed, non-uniformity of the crystallinity of silicon can be suppressed. Therefore, an image with improved image quality can be displayed.

[0145] However, polycrystalline silicon or microcrystalline silicon can also be manufactured without using a catalyst (such as nickel).

[0146] Also, although it is desirable to improve the crystallinity of silicon for the entire silicon, it is not limited thereto. The crystallinity of silicon may be improved only in some regions. Selectively improving the crystallinity can be achieved by, for example, selectively irradiating laser light. For example, laser light is irradiated only to regions such as the gate driver and the source driver. This is also possible. As a result, the crystallinity of silicon can be improved only in the area where high-speed operation of the circuit is required. Since the pixel portion does not need to operate at high speed, the pixel circuit can operate without problems even if the crystallinity is not improved. As a result, the area where the crystallinity needs to be improved can be reduced, and the manufacturing process can be shortened. Therefore, the throughput can be increased and the manufacturing cost of the display device can be reduced.

[0147] Moreover, the transistor is not limited to a transistor using silicon. As the transistor, a compound semiconductor such as silicon germanium or gallium arsenide, or a transistor using an oxide semiconductor such as zinc oxide, zinc oxide containing indium and gallium, etc. can also be applied. Also, a thin film transistor having a thin film of these compound semiconductors or oxide semiconductors can be applied. Since these can be manufactured at low temperatures, for example, it becomes possible to manufacture a transistor at room temperature. As a result, a transistor can be directly formed on a substrate with low heat resistance, for example, a plastic substrate or a film substrate. In addition, these compound semiconductors or oxide semiconductors can be used not only for the channel portion of the transistor but also for other applications. For example, these compound semiconductors or oxide semiconductors can be used as wiring, a resistance element, a pixel electrode, or an electrode having translucency. Since they can be formed or deposited simultaneously with the transistor, the manufacturing cost of the display device can be reduced.

[0148]

[0148]

[0148] Also, as the transistor, a transistor having an organic semiconductor or a carbon nanotube can be used. A stud can also be used. By these, transistors can be formed on a substrate that can be bent. A display device using such a substrate has high impact resistance.

[0149] Moreover, the manufacturing method of the transistor is not limited. As the manufacturing method, a photolithography method, an inkjet method, a printing method, or the like can be applied. In the inkjet method and the printing method, since a mask (reticle) is not used during manufacturing, the layout of the transistor can be easily changed. Furthermore, since it is possible to manufacture without using a resist, the material cost can be reduced and the number of processes can be reduced. Also, since it is possible to form a film only on necessary portions, the material is not wasted and the manufacturing cost of the display device can be reduced.

[0150]

[0151] Therefore, it is possible to improve the S value.

[0152] In addition, as the transistor, a structure in which a gate terminal is disposed above the channel region , a structure in which a gate terminal is disposed below the channel region, a forward staggered structure, a reverse staggered structure, a structure in which the channel region is divided into a plurality of regions, a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in series can also be applied.

[0153] In addition, as the transistor, a transistor having a structure in which a source terminal or a drain terminal overlaps with the channel region (or a part thereof) can also be used. By forming a structure in which a source terminal or a drain terminal overlaps with the channel region (or a part thereof), it is possible to prevent the operation from becoming unstable due to the accumulation of charges in a part of the channel region.

[0154] In addition, as the transistor, a structure provided with an LDD region can also be applied. By providing an LDD region, it is possible to reduce the off-current or improve the breakdown voltage (improve the reliability) of the transistor. Further, by providing an LDD region, even when the voltage between the drain and the source changes during operation in the saturation region, the drain current does not change much, and the slope of the voltage -current characteristic can be made flat.

[0155] Note that the transistor can be formed using various substrates. That is, the type of the substrate is not limited to a specific one. As an example of the substrate, a semiconductor substrate ( for example, a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic A substrate having a ceramic substrate, a metal substrate, a stainless steel substrate, or a stainless steel foil , a tungsten substrate, a substrate having a tungsten foil, a flexible substrate, a laminated film , a paper containing a fibrous material, or a base film. As an example of the glass substrate , there are barium borosilicate glass, aluminoborosilicate glass, or soda lime glass . As an example of the flexible substrate, there are plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or a flexible synthetic resin such as acrylic . As an example of the laminated film , there are polypropylene, polyester, vinyl, polyvinyl fluoride, or vinyl chloride . As an example of the base film, there are polyester, polyamide, polyimide, an inorganic vapor deposition film, or papers . In particular, by manufacturing a transistor using a semiconductor substrate, a single crystal substrate, or an SOI substrate , etc., it is possible to manufacture a transistor with less dispersion in characteristics, size, or shape, high current capacity, and small size . When a circuit is configured with such a transistor, it is possible to reduce the power consumption of the circuit or increase the integration of the circuit .

[0156] In addition, a transistor may be formed using a certain substrate, and then the transistor may be transferred to another substrate and disposed on another substrate . As an example of the substrate to which the transistor is transferred , in addition to the substrate on which the above-described transistor can be formed, a paper substrate, a cellophane substrate, a stone substrate, a wood substrate, a cloth substrate (natural fibers (silk, cotton, linen), synthetic fibers (nylon , polyurethane, polyester) or recycled fibers (acetate, cupra, rayon, etc.)​ There are leather substrates, rubber substrates, etc. that include (such as recycled polyester). By using these substrates, it is possible to form transistors with good characteristics, form transistors with low power consumption, manufacture durable devices, impart heat resistance, reduce weight, or make them thinner.

[0157] (Embodiment 6) In this embodiment, an example of an electronic device equipped with the display device shown in Embodiment 1 will be described with reference to FIGS. 11 to 13.

[0158] FIGS. 11(A) to (F) and FIGS. 12(A) to (D) are diagrams showing electronic devices having the display device shown in Embodiment 1. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or an operation switch), connection terminals 5006, a sensor 5007 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, visible light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 5008, etc. These electronic devices have the display device shown in Embodiment 1 incorporated in the display unit 5001.

[0159] FIG. 11(A) is a diagram showing a mobile computer, which can have a switch 5009, an infrared port 5010, etc. in addition to those described above. FIG. 11(B) is a diagram showing a portable image playback device (for example, a DVD playback device) equipped with a recording medium, which can have a second display unit 5002, a recording medium reading unit 5011, etc. in addition to those described above. . FIG. 11(C) is a diagram showing a projector, and in addition to those described above, it can have a light source 5033, a projection lens 5034, and the like. FIG. 11(D) is a diagram showing a portable game machine and, in addition to those described above, it can have a recording medium reading unit 5011, and the like. FIG. 1 1(E) is a diagram showing a television receiver, and in addition to those described above, it can have a tuner, an image processing unit , and the like. FIG. 11(F) is a diagram showing a portable television receiver, and, in addition to those described above, it can have a charger 5017 capable of transmitting and receiving signals, and the like. FIG. 12(A) is a diagram showing a display, and in addition to those described above, it can have a support base 5018, and the like. FIG. 12(B) is a diagram showing a camera, and in addition to those described above , it can have an external connection port 5019, a shutter button 5015, an image receiving unit 5016, and the like. FIG. 12(C) is a diagram showing a computer, and in addition to those described above, it can have a pointing device 5020, an external connection port 5019, a reader / writer 5021, and the like. FIG. 12(D) is a diagram showing a mobile phone, and in addition to those described above , it can have an antenna, a tuner for a one-segment partial reception service for mobile phones and mobile terminals, and the like.

[0160] The electronic devices shown in FIGS. 11(A) to (F) and FIGS. 12(A) to (D) can have various functions. For example, a function of displaying various information (still images, moving images, text, images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, etc., a function of controlling processing by various software (programs), a wireless communication function, a function of connecting to various computer networks using the wireless communication function, a function of connecting to various computer networks using the wireless communication function, ​​A function for transmitting or receiving data, a program or data recorded on a recording medium It can have functions such as reading and displaying on a display unit. Furthermore, in an electronic device having a plurality of display units One display unit mainly displays image information, and another display unit Mainly displays character information, or has a function of displaying a stereoscopic image by displaying an image considering parallax on a plurality of display units And so on. Furthermore, in an electronic device having an imaging unit It can have functions such as a function of taking a still image, a function of taking a moving image, a function of automatically or manually correcting the taken image, a function of storing the taken image in a recording medium (external or built into the camera), and a function of displaying the taken image on a display unit. Note that the functions that the electronic devices shown in FIGS. 11(A) to (F) and FIGS. 12(A) to (D) can have Are not limited to these, and can have various functions. Are not limited to these, and can have various functions. Are not limited to these, and can have various functions. Are not limited to these, and can have various functions.

[0161] Next, an example of an electronic device provided integrally with a building will be described with reference to FIGS. 13(A) and 13(B).

[0162] FIG. 13(A) is a diagram showing an example of an electronic device provided integrally with a building. The Electronic device includes a housing 5022, a display unit 5023, a speaker 5025, etc. Also, the Electronic device can be operated by a remote control device 5024. The electronic device is Wall-mounted and integrated with the building, and can be installed without requiring a large installation space.

[0163] FIG. 13(B) is a diagram showing an example of an electronic device provided integrally with a building. The Electronic device includes a display unit 5026 and is attached near a bathtub 5027. When taking a bath ​​The viewer can view the display unit 5026.

[0164] In this embodiment, a wall and a bathroom are taken as examples of buildings. However, this embodiment is not limited to this, and display panels can be installed in various buildings.

[0165] Next, an example in which an electronic device is provided integrally with a moving body will be described with reference to FIGS. 13(C) and (D). will be described.

[0166] FIG. 13(C) is a diagram showing an example of an electronic device provided in an automobile. The electronic device includes a display unit 5028 and is attached to the vehicle body 5029 of the automobile. The electronic device can display on demand the operation of the vehicle body or information input from inside and outside the vehicle body. Note that the electronic device may have a navigation function.

[0167] FIG. 13(D) is a diagram showing an example of an electronic device provided in a passenger airplane. More specifically, FIG. 13(D) is a diagram showing the shape of the electronic device when in use, which is provided on the ceiling 5030 above the seat of the passenger airplane. The electronic device is integrally attached via the ceiling 5030 and the hinge portion 5032. By expanding and contracting the hinge portion 5032, the passenger can view the display unit 5031. The electronic device has a function of displaying information by being operated by the passenger. can view the display unit 5031. The electronic device has a function of displaying information by being operated by the passenger. has a function of displaying information by being operated by the passenger.

[0168] In this embodiment, examples of the moving body are given as an automobile body and an airplane body. However, the moving body is not limited to this, and it can be installed in various vehicles such as motorcycles, automobiles (including cars, buses, etc.), trains (including monorails, railways, etc.), ships, etc. However, it is not limited to this, and it can be installed in various vehicles such as motorcycles, automobiles (including cars, buses, etc.), trains (including monorails, railways, etc.), ships, etc. can be installed in various vehicles such as motorcycles, automobiles (including cars, buses, etc.), trains (including monorails, railways, etc.), ships, etc.

[0169] The electronic device described in this embodiment has a display unit for displaying some information , and is characterized in that the display device shown in Embodiment 1 is incorporated in the display unit.

Example

[0170] In this example, the attenuation and delay of signals in a gate driver equipped with a transfer signal generation circuit are verified by comparing with a conventional example through circuit simulation.

[0171] FIG. 14 shows models for circuit simulation of a conventional gate driver and the gate driver of this specification. FIG. 14(A) is a diagram showing the configuration of a conventional gate driver, and the output signal of each flip-flop circuit is used as the start pulse signal of the next-stage flip-flop circuit . FIG. 14(B) is a diagram showing the configuration of the gate driver of this specification, and a transfer signal generation circuit is provided between the flip-flop circuits. In this example, the output signal of the flip-flop circuit when the flip-flop circuit and the transfer signal generation circuit are configured by the circuits shown in FIG. 4 is calculated by circuit simulation. Note that PSpice is used as the calculation software. Also, the threshold voltage of the transistors constituting the flip-flop circuit and the transfer signal generation circuit is assumed to be 8 (V), and the field-effect mobility

[0172] is assumed to be 0.5 (cm / Vs). Also, it is assumed that a parasitic capacitance of 100 (pF) is formed in each gate line . Further, the voltage amplitude of the clock signal is assumed to be 30 (V) (the potential of the H level is 30 V, and the potential of the L level is 0 V), the ground potential is 0 (V), and the clock frequency is assumed to be 41.7 (kHz) (period: 24 (μs)). 2 (the potential of the H level is 30 V, and the potential of the L level is 0 V), the ground potential is 0 (V), and the clock frequency is assumed to be 41.7 (kHz) (period: 24 (μs)).

[0173] ​​​​​ Figure 15 shows the output signal of the flip-flop circuit obtained by circuit simulation. As shown in Figure 15, it was confirmed that the gate driver in this specification has reduced signal delay and attenuation.

Explanation of Signs

[0174] 100 Display device 101 Pixel section 102 Source driver 103A First gate driver 103B Second gate driver 1041 Source line 104 n Source line 1051 Gate line 1052 Gate line 1053 Gate line 105 m Gate line 106A Flexible printed circuit board 106B Flexible printed circuit board 107 11 Pixel 107 nm Pixel 401 Transistor 402 Transistor 403 Transistor 404 Transistor 405 Transistor 406 Transistor 407 Transistor 408 Transistor 600 Inverter circuit 600A Inverter circuit 600B Inverter circuit 601 Transistor 602 Transistor 603 Transistor 604 Transistor 605 Transistor 606 Transistor 607 Transistor​ 608 Transistor 701A Transistor 701B Transistor 702A Transistor 702B Transistor 703B Transistor 704B Transistor 800 Control Circuit 800A Control Circuit 800B Control Circuit 801 Transistor 802 Transistor 803 Transistor 804 Transistor 805 Transistor 806 Transistor 807 Transistor 808 Transistor 809 Transistor 901A Capacitor Element 901B Transistor 902A Transistor 902B Transistor 903B Transistor 904B Transistor 1001 Pixel Section 1002A First Gate Driver 1002B Second Gate Driver 10031 Gate Line 10032 Gate Line 1003 k Gate Line 5000 Housing 5001 Display Section 5002 Second Display Section 5003 Speaker 5004 LED Lamp 5005 Operation Key 5006 Connection Terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared Port 5011 Recording medium reading unit 5015 Shutter button 5016 Image receiving unit 5018 Support stand 5019 External connection port 5020 Pointing device 5021 Reader / writer 5022 Housing 5023 Display unit 5024 Remote control device 5025 Speaker 5026 Display unit 5027 Bathtub 5028 Display unit 5029 Vehicle body 5030 Ceiling 5031 Display unit 5032 Hinge part 5033 Light source 5034 Projection lens

Claims

【Claim 1】 It has a pixel portion and a gate driver adjacent to the pixel portion, The gate driver has a first circuit and a second circuit, The first circuit has first to seventh transistors, The second circuit has eighth to tenth transistors, One of the source or drain of the first transistor is always conducting with a first clock signal line, The other of the source or drain of the first transistor is always conducting with a gate signal line, One of the source or drain of the second transistor is always conducting with the gate signal line, The other of the source or drain of the second transistor is always conducting with a first power supply line, One of the source or drain of the third transistor is always conducting with the gate of the first transistor, The other of the source or drain of the third transistor is always conducting with a first signal line, The gate of the third transistor is always conducting with the first signal line, One of the source or drain of the fourth transistor is always conducting with the gate of the first transistor, The gate of the fourth transistor is always conducting with an output signal line, One of the source or drain of the fifth transistor is always conducting with the gate of the first transistor, The gate of the fifth transistor is always conducting with the gate of the second transistor, One of the source or drain of the sixth transistor is always conducting with the gate of the second transistor, The other of the source or drain of the sixth transistor is always conducting with a first wiring, The gate of the sixth transistor is always conducting with the first wiring, One of the source or drain of the seventh transistor is always conducting with the gate of the second transistor, The gate of the seventh transistor is always conducting with the gate of the first transistor, One of the source or drain of the eighth transistor is always conducting with a second clock signal line, The other of the source or drain of the eighth transistor is always conducting with the output signal line, One of the source or drain of the ninth transistor is always conducting with the gate of the eighth transistor, The other of the source or drain of the ninth transistor is always conducting with the gate signal line, The gate of the ninth transistor is always conducting with the gate signal line, One of the source or drain of the tenth transistor is always in conduction with the gate of the eighth transistor. The gate of the tenth transistor is always in conduction with the second signal line. When the first wiring is in a conductive state with the gate of the second transistor and the gate of the fifth transistor via at least the channel formation region of the sixth transistor, a potential having a value at which the second transistor turns on and a potential having a value at which the fifth transistor turns on are input to the gate of the second transistor and the gate of the fifth transistor via at least the channel formation region of the sixth transistor. When the other of the source or drain of the fourth transistor is in a conductive state with the gate of the first transistor and the gate of the seventh transistor via at least the channel formation region of the fourth transistor, a potential having a value at which the first transistor turns off and a potential having a value at which the seventh transistor turns off are input to the gate of the first transistor and the gate of the seventh transistor via at least the channel formation region of the fourth transistor. When the other of the source or drain of the fifth transistor is in a conductive state with the gate of the first transistor and the gate of the seventh transistor via at least the channel formation region of the fifth transistor, a potential having a value at which the first transistor turns off and a potential having a value at which the seventh transistor turns off are input to the gate of the first transistor and the gate of the seventh transistor via at least the channel formation region of the fifth transistor. When the other of the source or drain of the seventh transistor is in a conductive state with the gate of the second transistor via at least the channel formation region of the seventh transistor, a potential having a value at which the second transistor turns off is input to the gate of the second transistor via at least the channel formation region of the seventh transistor. When the other of the source or drain of the tenth transistor is in conduction with the gate of the eighth transistor through at least the channel formation region of the tenth transistor, a potential having a value at which the eighth transistor turns off is input to the gate of the eighth transistor through at least the channel formation region of the tenth transistor, The W / L (W is the channel width and L is the channel length) of the first transistor is larger than the W / L of the eighth transistor, The W / L of the third transistor is larger than the W / L of the fifth transistor, The W / L of the fourth transistor is larger than the W / L of the tenth transistor, The W / L of the seventh transistor is larger than the W / L of the sixth transistor, A semiconductor device in which the W / L of the eighth transistor is larger than the W / L of the tenth transistor. **Claim 2** A pixel unit and a gate driver adjacent to the pixel unit, The gate driver has a first circuit and a second circuit, The first circuit has first to seventh transistors, The second circuit has eighth to tenth transistors, One of the source or drain of the first transistor is always in conduction with the first clock signal line, The other of the source or drain of the first transistor is always in conduction with the gate signal line, One of the source or drain of the second transistor is always in conduction with the gate signal line, One of the source or drain of the third transistor is always in conduction with the gate of the first transistor, The other of the source or drain of the third transistor is always in conduction with the first signal line, The gate of the third transistor is always in conduction with the first signal line, One of the source or drain of the fourth transistor is always in conduction with the gate of the first transistor, The other of the source or drain of the fourth transistor is always in conduction with the first power supply line, The gate of the fourth transistor is always in conduction with the output signal line, One of the source or drain of the fifth transistor is always in conduction with the gate of the first transistor, The other of the source or drain of the fifth transistor is always in conduction with the first power supply line, The gate of the fifth transistor is always in conduction with the gate of the second transistor, One of the source or drain of the sixth transistor is always in conduction with the gate of the second transistor, The other of the source or drain of the sixth transistor is always in conduction with the first wiring, The gate of the sixth transistor is always in conduction with the first wiring, One of the source or drain of the seventh transistor is always in conduction with the gate of the second transistor, The other of the source or drain of the seventh transistor is always in conduction with the first power supply line, The gate of the seventh transistor is always in conduction with the gate of the first transistor, One of the source or drain of the eighth transistor is always in conduction with the second clock signal line, The other of the source or drain of the eighth transistor is always in conduction with the output signal line, One of the source or drain of the ninth transistor is always in conduction with the gate of the eighth transistor, The other of the source or drain of the ninth transistor is always in conduction with the gate signal line, The gate of the ninth transistor is always in conduction with the gate signal line, One of the source or drain of the tenth transistor is always in conduction with the gate of the eighth transistor, The other of the source or drain of the tenth transistor is always in conduction with the first power supply line, The gate of the tenth transistor is always in conduction with the second signal line, When the first wiring is in conduction with the gate of the second transistor and the gate of the fifth transistor through at least the channel formation region of the sixth transistor, a potential having a value at which the second transistor turns on and a potential having a value at which the fifth transistor turns on are input to the gate of the second transistor and the gate of the fifth transistor through at least the channel formation region of the sixth transistor, When the other of the source or drain of the second transistor is in conduction with the gate signal line through at least the channel formation region of the second transistor, a potential having a value at which the gate signal line becomes the L level is input to the gate signal line through at least the channel formation region of the second transistor, The W / L (W is the channel width, L is the channel length) of the first transistor is larger than the W / L of the eighth transistor, The W / L of the third transistor is larger than the W / L of the fifth transistor, The W / L of the fourth transistor is larger than the W / L of the tenth transistor, The W / L of the seventh transistor is larger than the W / L of the sixth transistor, A semiconductor device in which the W / L of the eighth transistor is larger than the W / L of the tenth transistor.

Images