Semiconductor device

Abstract

To obtain a semiconductor device with a high yield that can be easily manufactured.SOLUTION: A first main electrode 10 and a first control electrode pad 15 are formed on a first principal surface of a semiconductor chip 1. A second main electrode 29 and a second control electrode pad 31 are formed on a second principal surface of the semiconductor chip 1. The second main electrode 29 and the second control electrode pad 31 are bonded with first and second metal patterns 39 and 40 of an insulation substrate 36, respectively. Bonding parts of first and second wires 42 and 43 are overlapped with a junction of the second main electrode 29 or the second control electrode pad 31, in a plan view. A thickness of the first and second metal patterns 39 and 40 is equal to or less than 0.2 mm.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] A semiconductor device having a double gate structure with control electrode pads on the cathode side surface and the anode side surface respectively has been proposed as a switching element, and a form of wire bonding to the control electrode pads on both sides is shown as an example (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] If the opposite side cannot be fixed when performing wire bonding, cracks or chips may occur in the semiconductor chip due to the impact of ultrasonic waves. Therefore, it is difficult to perform wire bonding to the control electrode pads on both sides, and even if it can be manufactured by a special method, it has been difficult to improve mass productivity.

[0005] The present disclosure has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device with high yield and easy manufacturing.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure includes a semiconductor chip having a first main surface and a second main surface on opposite sides of each other, a first main electrode formed on the first main surface and electrically connected to the semiconductor chip, a first control electrode pad formed on the first main surface with a first insulating film interposed therebetween and the semiconductor chip, a second main electrode formed on the second main surface and electrically connected to the semiconductor chip, a second control electrode pad formed on the second main surface with a second insulating film interposed therebetween and the semiconductor chip, a first wire bonded to the first main electrode, a second wire bonded to the first control electrode pad, and an insulating substrate having first and second metal patterns separated from each other, wherein the second main electrode and the second control electrode pad are respectively joined to the first and second metal patterns, and the bonding portions of the first and second wires overlap the joining portions of the second main electrode or the second control electrode pad in a plan view. The second control electrode pad is formed at the center of the second main surface of the semiconductor chip, and a slit is formed from the center of the second main surface toward the outer peripheral portion where the second main electrode does not exist. The second metal pattern is drawn out from the center of the semiconductor chip through the slit to the outside of the semiconductor chip in a plan view. It is characterized by this.

Advantages of the Invention

[0007] In the present disclosure, the second main electrode and the second control electrode pad of the semiconductor chip are respectively joined to the first and second metal patterns of the insulating substrate. Thereby, it can be easily assembled by a general soldering process flow. Further, the bonding portions of the first and second wires overlap the joining portions of the second main electrode or the second control electrode pad in a plan view. Since the opposite surface of the bonding portion is fixed by the metal pattern, breakage of the semiconductor chip during bonding can be prevented. Also, the thickness of the metal pattern is set to 0.2 mm or less. As a result, the pattern accuracy of the metal pattern is improved, so that it becomes easier to match the shape of the metal pattern of the insulating substrate to the shapes of the collector electrode and the second gate electrode pad, and the bonding area between the two can be widened. Therefore, the mechanical strength is increased and the thermal resistance is reduced. Thus, the semiconductor device according to the present embodiment has a high yield and is easy to manufacture.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] The semiconductor device according to the embodiment will be described with reference to the drawings. The same or corresponding components may be denoted by the same reference numerals, and repeated description may be omitted.

[0010] Embodiment 1. FIG. 1 is a cross-sectional view showing a semiconductor chip having a double-gate structure. The semiconductor chip 1 is an IGBT chip having emitter-side main surfaces and collector-side main surfaces on opposite sides. An n - -type drift layer 2 is formed in the semiconductor chip 1. An n - -type drift layer 2, a p-type base layer 3 with a predetermined thickness is formed. A plurality of trenches 4 penetrate the p-type base layer 3 and reach the n - -type drift layer 2. The plurality of trenches 4 are arranged at a predetermined pitch (interval) and have a stripe structure extending parallel to the direction perpendicular to the plane of FIG. 1, or an annular structure that extends parallel and is routed at its tip.

[0011] The p-type base layer 3 is separated into a plurality by the plurality of trenches 4. A part of them is a p-channel layer 5 that constitutes a channel region. An n + -type emitter region 6 is formed on the side surface of the trench 4 in the surface layer portion of the p-channel layer 5. The n + -type emitter region 6 has a higher impurity concentration than the n - -type drift layer 2. A gate electrode 7 made of doped polysilicon or the like is formed in the trench 4 via a gate insulating film 8. An insulating film 9 is formed on the emitter-side main surface of the semiconductor chip 1 so as to cover the upper part of the gate electrode 7.

[0012] The emitter electrode 10 is formed on the insulating film 9. The emitter electrode 10 is electrically connected to the n + -type emitter region 6 and the p-channel layer 5 through the contact hole 11 formed in the insulating film 9.

[0013] The p-type diffusion layer 12 is formed on the n - -type drift layer 2 so as to surround the p-type base layer 3. The doped polysilicon layer 13 is formed on the p-type diffusion layer 12 via the insulating film 9. The doped polysilicon layer 13 is electrically connected to the gate electrode 7 and is electrically connected to the first gate electrode pad 15 through the contact hole 14 formed in the insulating film 9. Therefore, the gate electrode 7 is electrically connected to the outside through the doped polysilicon layer 13 and the first gate electrode pad 15. In this way, the emitter-side IGBT region is configured.

[0014] In the outer peripheral region surrounding the emitter-side IGBT region, a plurality of p-type guard ring layers 16 are formed in a multi-ring structure on the n - -type drift layer 2. The p-type diffusion layer 12 and the p-type guard ring layer 16 are formed deeper than the p-type base layer 3. A plurality of outer peripheral electrodes 17 are formed on the insulating film 9 and are connected to the plurality of p-type guard ring layers 16 through the contact holes 18, respectively. The plurality of outer peripheral electrodes 17 are electrically separated from each other and have a multi-ring structure similar to that of the p-type guard ring layer 16.

[0015] An n - -type layer 19 is formed in the surface layer portion of the n + -type drift layer 2 so as to surround the p-type guard ring layer 16. An electrode 20 is formed on the n + -type layer 19. The n + -type layer 19 and the electrode 20 are electrically connected to each other to form an equipotential ring (EQR) structure. The portion where no electrical connection is made in the outer peripheral region is covered with a protective film 21. In this way, the outer peripheral voltage withstand holding structure 22 is configured in the outer peripheral region of the emitter-side main surface.

[0016] n - type drift layer 2 has a p + type collector layer 23 formed beneath it. n - type drift layer 2 and a p + type collector layer 23, there is an n - type field stop layer 24 having an impurity concentration higher than that of the n + type drift layer 2 formed between them. p + On the collector-side surface of the p + type collector layer 23, a high-concentration n

[0017] A plurality of trenches 26 penetrate through the p + type collector layer 23, n + type collector layer 25, and the n + type field stop layer 24 to reach the n - type drift layer 2. The plurality of trenches 26 are formed at a predetermined interval, for example, arranged in a stripe pattern at equal intervals. A control gate electrode 27 made of doped polysilicon or the like is formed in the trench 26 via a gate insulating film 28. All the control gate electrodes 27 are electrically connected to each other in a cross-sectional view.

[0018] The collector electrode 29 is in contact with and electrically connected to the p + type collector layer 23 and n + type collector layer 25. An insulating film 30 is formed on the collector-side main surface of the semiconductor chip 1 so as to cover the control gate electrode 27.

[0019] The second gate electrode pad 31 is electrically connected to the doped polysilicon layer 33 through a contact hole 32 formed in the insulating film 30. The doped polysilicon layer 33 is connected to the control gate electrode 27 through a contact hole 34 formed in the insulating film 30. The collector electrode 29 is disposed so as to surround the second gate electrode pad 31 whose periphery is covered with the protective film 35, and is separated from the control gate electrode 27 by the insulating film 30 and the protective film 35. In this way, the collector side IGBT region is configured.

[0020] FIG. 2 is a cross-sectional view showing a semiconductor device according to Embodiment 1. An emitter electrode 10 and a first gate electrode pad 15 are formed on the emitter side main surface of the semiconductor chip 1. An outer peripheral withstand voltage holding structure 22 is formed in an outer peripheral region surrounding the emitter electrode 10 and the first gate electrode pad 15 on the emitter side main surface. A collector electrode 29 and a second gate electrode pad 31 are formed on the collector side main surface of the semiconductor chip 1.

[0021] The insulating substrate 36 has an insulating material 37, a metal layer 38 formed on the lower surface of the insulating material 37, and metal patterns 39, 40 formed on the upper surface of the insulating material 37. The metal patterns 39, 40 are separated from each other, and are joined to the collector electrode 29 and the second gate electrode pad 31 of the semiconductor chip 1 by solder 41, respectively. By separating the metal patterns 39, 40, a control signal of about several volts to 20 volts can be applied between the collector electrode 29 and the second gate electrode pad 31.

[0022] Wires 42, 43 are bonded to the emitter electrode 10 and the first gate electrode pad 15, respectively. Wires 44, 45 are bonded to the metal patterns 39, 40, respectively. The joint of the wire 42 bonded to the emitter electrode 10 and the joint of the wire 43 bonded to the first gate electrode pad 15 overlap the solder joint of the collector electrode 29 or the second gate electrode pad 31 in plan view. Thereby, cracking due to ultrasonic waves during wire bonding can be prevented.

[0023] FIG. 3 is a top view of the semiconductor chip. The position of the first gate electrode pad 15 is slightly offset from the center of the chip towards one of the sides. Not limited to this, even if the first gate electrode pad 15 is at the center of the chip or near one of the corners, the wire 43 can be bonded.

[0024] FIG. 4 is a bottom view of the semiconductor chip. The second gate electrode pad 31 is formed at a corner of the chip. Not limited to this, the second gate electrode pad 31 may be provided at the center of the chip or on any side. Providing the second gate electrode pad 31 at a corner or on a side of the chip makes it easier to form patterns without the metal pattern 39 joined to the collector electrode 29 and the metal pattern 40 joined to the second gate electrode pad 31 intersecting. Although the second gate electrode pad 31 can also be formed at the center of the chip, as will be described later, it is necessary to insulate the metal patterns 39 and 40 from each other or use an insulating substrate 36 of a multilayer electrode layer and vias.

[0025] FIG. 5 is a plan view showing the positional relationship between the metal patterns of the insulating substrate and the semiconductor chip according to Embodiment 1. The dotted line indicates the semiconductor chip 1. The portion where the metal patterns 39 and 40 of the insulating substrate 36 are not formed is made to coincide with the portion where the collector electrode 29 and the second gate electrode pad 31 of the semiconductor chip 1 are not formed. This prevents a short circuit between the collector electrode 29 and the second gate electrode pad 31 and enables a control signal to be applied to the second gate electrode pad 31. In the present embodiment, the pattern pitch of the insulating substrate 36 is made narrower than the pattern pitch of the semiconductor chip 1. Not limited to this, as long as the collector electrode 29 and the second gate electrode pad 31 are not in contact and short-circuited, the pattern pitch of the semiconductor chip 1 may be wider or the two patterns may coincide.

[0026] Next, the effects of the present embodiment will be described in comparison with a comparative example. FIG. 6 is a cross-sectional view showing a semiconductor device according to the comparative example. In the comparative example, a wire 46 is directly bonded to the second gate electrode pad 31 on the lower surface of the chip. However, since there is also wire bonding on the upper surface of the chip, the upper surface of the chip cannot be fixed with solder or the like. Therefore, the semiconductor chip 1 is cracked or chipped due to the impact of ultrasonic waves during wire bonding. To avoid this, when soldering the lower surface of the chip is performed first, the insulating substrate 36 gets in the way and the tip of the needle (tool) for applying ultrasonic waves to melt the wire cannot be applied to the second gate electrode pad 31. Therefore, the semiconductor device of the comparative example is difficult to manufacture, and even if it can be manufactured by a special method, it is difficult to improve mass productivity.

[0027] On the other hand, in the present embodiment, the collector electrode 29 of the semiconductor chip 1 and the second gate electrode pad 31 are solder-bonded to the metal patterns 39 and 40 of the insulating substrate 36, respectively. Thereby, it can be easily assembled by a general solder-bonding process flow.

[0028] Also, the bonding portions of the wires 42 and 43 overlap the solder bonding portions of the collector electrode 29 or the second gate electrode pad 31 in plan view. Since the opposite surface of the bonding portion is fixed, breakage of the semiconductor chip 1 during bonding can be prevented.

[0029] FIG. 7 is an enlarged cross-sectional view of the joint between the insulating substrate and the semiconductor chip. Considering the alignment accuracy of the patterns of the semiconductor chip 1 and the insulating substrate 36 and the insulation distance between the electrodes, the distance between the collector electrode 29 and the second gate electrode pad 31 is set to 0.5 mm or less. Since the thinner the metal pattern, the finer the processing can be, it is necessary to reduce the thickness of the metal patterns 39 and 40 connected to the collector electrode 29 and the second gate electrode pad 31. Wet etching with high mass productivity is used for processing the metal patterns 39 and 40. Therefore, considering the side etching by the pattern thickness from both sides, the thickness of the metal patterns 39 and 40 is set to 0.2 mm or less. As a result, the pattern accuracy of the metal patterns 39 and 40 is improved, so that the shape of the metal patterns 39 and 40 on the insulating substrate 36 can be easily matched to the shapes of the collector electrode 29 and the second gate electrode pad 31, and the joint area between the two can be widened. Therefore, the mechanical strength is increased and the thermal resistance is reduced. Thus, the semiconductor device according to this embodiment has a high yield and is easy to manufacture.

[0030] Note that the thicker the metal pattern, the smaller the lateral electrical resistance and the larger the current that can flow, and the smaller the lateral thermal resistance and the heat spreads around the chip, improving the heat dissipation. For this reason, the thickness of a general metal pattern was about 0.3 mm. In contrast, in the present disclosure, the thickness of the metal patterns 39 and 40 is deliberately set to 0.2 mm or less for the above reasons.

[0031] Figure 8 is a bottom view showing a first modification example of the semiconductor chip according to the first embodiment. A second gate electrode pad 31 is formed at the center of the bottom surface of the semiconductor chip 1, and a collector electrode 29 is formed around it. A slit 47 where the collector electrode 29 does not exist is formed in a part of the bottom surface of the semiconductor chip 1 from the center to the outer peripheral portion of the semiconductor chip 1. Figure 9 is a top view showing the metal patterns of the insulating substrate according to the first modification example of the first embodiment. The metal patterns 39 and 40 are separated from each other. The metal pattern 40 is drawn out from the center of the semiconductor chip 1 through the slit 47 to the outside of the semiconductor chip 1 in a plan view. Thereby, since the metal pattern 40 does not contact the collector electrode 29, a short circuit between the collector electrode 29 and the second gate electrode pad 31 can be prevented.

[0032] Figure 10 is a bottom view showing a second modification example of the semiconductor chip according to the first embodiment. A second gate electrode pad 31 is formed at the center of the bottom surface of the semiconductor chip 1, and a collector electrode 29 is formed around it. An insulating film 48 is formed so as to cover a part of the collector electrode 29 from the center to the outer peripheral portion of the semiconductor chip 1. The metal patterns 39 and 40 of the insulating substrate 36 are the same as those in the first modification example. The metal pattern 40 is drawn out from the center of the semiconductor chip 1 through the region where the insulating film 48 is formed to the outside of the semiconductor chip 1 in a plan view. Thereby, since the metal pattern 40 does not contact the collector electrode 29, a short circuit between the collector electrode 29 and the second gate electrode pad 31 can be prevented. Note that the insulating film 48 may be formed after combining the first and second modification examples to avoid interference by patterning the collector electrode 29. Also, if the collector electrode 29 and the second gate electrode pad 31 do not short-circuit, other patterns such as arranging the second gate electrode pad 31 at the chip corner may be used.

[0033] Second Embodiment. FIG. 11 is a cross-sectional view showing a semiconductor device according to Embodiment 2. The semiconductor chip 1 is mounted with its top and bottom reversed compared to Embodiment 1. The emitter electrode 10 and the first gate electrode pad 15 of the semiconductor chip 1 are soldered to the metal patterns 39 and 40 of the insulating substrate 36, respectively. Wires 42 and 43 are bonded to the collector electrode 29 and the second gate electrode pad 31, respectively. Since the emitter side of the semiconductor chip 1, which generates a large amount of heat, is joined to the insulating substrate 36, which is a heat dissipation path, the heat dissipation performance is superior to that of Embodiment 1.

[0034] Also, when electrode pads for temperature sensing or current sensing are formed on the emitter side of the semiconductor chip 1, these electrode pads can also be joined to the metal pattern of the insulating substrate 36. When the first gate electrode pad 15 is arranged at the center of the chip, the configurations of Modifications 1 and 2 of Embodiment 1 are applied.

[0035] FIG. 12 is a cross-sectional view showing a modification of the semiconductor device according to Embodiment 2. A voltage of several thousand volts is applied between the outer peripheral portion of the outer peripheral breakdown voltage holding structure 22 and the metal pattern 39. Therefore, in order to insulate, a part of the metal pattern 39 is partially thinned compared to the periphery in the region facing the outer peripheral breakdown voltage holding structure 22, and the distance between the two is widened.

[0036] Embodiment 3. FIG. 13 is a bottom view showing a semiconductor chip according to Embodiment 3. The second gate electrode pad 31 is formed at the center of the bottom surface of the semiconductor chip 1, and the collector electrode 29 is formed around it.

[0037] FIG. 14 is a top view showing an insulating substrate according to Embodiment 3. The metal pattern 39 is formed around the metal pattern 40. The metal pattern 49 is formed at a position outside the semiconductor chip 1 in plan view. The metal patterns 39, 40, and 49 are separated from each other.

[0038] FIG. 15 is a cross-sectional view showing a semiconductor device according to Embodiment 3. The metal layer 38 formed on the lower surface of the insulating layer 37a is used for ground or the like and is not used as a metal pattern for safety reasons. A metal layer 50 is formed on the insulating layer 37a. An insulating layer 37b is formed on the metal layer 50. Metal patterns 39, 40, and 49 are formed on the insulating layer 37b. Therefore, this insulating substrate has three conductor layers.

[0039] An opening 51 is formed in the insulating layer 37b. The metal layer 50 inside the substrate is connected to the metal pattern 40 through the opening 51. The metal layer 50 is connected to the metal pattern 49 through a via 52 formed in the insulating layer 37b. Thereby, the second gate electrode pad 31 formed at the center of the lower surface of the semiconductor chip 1 can be led out to the outside through the metal pattern 40, the metal layer 50, and the metal pattern 49. Other configurations and effects are the same as those in Embodiment 1.

[0040] FIG. 16 is a cross-sectional view showing a modification 1 of the semiconductor device according to Embodiment 3. By combining the configuration of Embodiment 2, the semiconductor chip 1 is mounted with its top and bottom reversed compared to Embodiment 3. The emitter electrode 10 and the first gate electrode pad 15 of the semiconductor chip 1 are soldered to the metal patterns 39 and 40 of the insulating substrate 36, respectively. Wires 42 and 43 are bonded to the collector electrode 29 and the second gate electrode pad 31, respectively. Since the emitter side of the semiconductor chip 1 with large heat generation is joined to the insulating substrate 36 which is a heat dissipation path, the heat dissipation performance is superior to that of Embodiment 3.

[0041] Also, when electrode pads for temperature sensing or current sensing are formed on the emitter side of the semiconductor chip 1, these electrode pads can also be joined to the metal patterns of the insulating substrate 36. When the first gate electrode pad 15 is arranged at the center of the chip, the configurations of Modifications 1 and 2 of Embodiment 1 are applied.

[0042] FIG. 17 is a cross-sectional view showing a modification 2 of the semiconductor device according to Embodiment 3. By combining the configuration of Embodiment 2, a voltage of several thousand volts is applied between the outer peripheral portion of the outer peripheral breakdown voltage holding structure 22 and the metal pattern 39. Therefore, in order to insulate, a part of the metal pattern 39 is partially thinned compared to the periphery in the region facing the outer peripheral breakdown voltage holding structure 22, and the distance between the two is widened.

[0043] Embodiment 4. FIG. 18 is a cross-sectional view showing a semiconductor device according to Embodiment 4. A large opening 51 is formed directly below the semiconductor chip 1 in the insulating layer 37b closer to the chip. The metal layer 50 is connected to the metal pattern 39 through the opening 51.

[0044] Even if the metal patterns 39 and 40 joined to the semiconductor chip 1 are as thin as 0.2 mm or less, current flows through the thick metal layer 50 through the opening 51, so the loss (resistance) is small. Also, since heat is dissipated through the metal layer 50 of the opening 51, the thermal resistance does not increase.

[0045] FIG. 19 is a plan view showing the positional relationship between the metal pattern of the insulating substrate and the semiconductor chip according to Embodiment 4. The opening 51 is circular and is arranged so as to overlap the semiconductor chip 1 in plan view. Small-diameter vias 52 are formed to draw up from the inner metal layer 50 to the front-side metal pattern 39.

[0046] FIG. 20 is a cross-sectional view showing a modification 1 of the semiconductor device according to Embodiment 4. The metal pattern 39 has its joint portion with the semiconductor chip 1 and its bonding portion with the wire 44 separated. Since the two are electrically connected by the inner metal layer 50, there is no problem in this form either. However, it is preferable from the viewpoints of heat dissipation and low loss that the two are not separated.

[0047] FIG. 21 is a cross-sectional view showing a modification 2 of the semiconductor device according to Embodiment 4. Forming an opening 51 with a large diameter as shown in FIGS. 18-19 requires a special processing technique. Therefore, a plurality of openings 51 with a small diameter are formed instead of the opening 51 with a large diameter. Thereby, the cost is reduced and the productivity is improved without increasing the loss and the thermal resistance.

[0048] Also, the insulating layer 37a and the insulating layer 37b are made of the same material. Therefore, it is easy to integrally form the insulating layer 37a and the insulating layer 37b. Further, since the thermal expansion coefficients of the insulating layer 37a and the insulating layer 37b are the same, the reliability is high.

[0049] Embodiment 5. FIG. 22 is a cross-sectional view showing a semiconductor device according to Embodiment 5. An insulating substrate 36b is laminated on the insulating substrate 36a. In the insulating substrate 36a, a metal layer 38 is formed on the lower surface of the insulating layer 37a, and a metal layer 53 is formed on the upper surface. In the insulating substrate 36b, a metal layer 54 is formed on the lower surface of the insulating layer 37b, and metal patterns 39, 40 are formed on the upper surface. The metal layer 53 of the insulating substrate 36a is joined to the metal layer 54 of the insulating substrate 36b with solder 41. Note that other bonding materials such as silver nanopaste or copper nanopaste may be used instead of the solder 41. Further, the insulating layer 37a and the insulating layer 37b may be integrally formed so that there is only one metal layer between them.

[0050] For the insulating layer 37b close to the semiconductor chip 1, processability such as miniaturization of patterns, accuracy, ease of processing of the openings 51, and crack resistance is required. On the other hand, for the insulating layer 37a far from the semiconductor chip 1, heat dissipation, that is, low thermal resistance is required. For this reason, the insulating layer 37a and the insulating layer 37b are made of different materials, and the most suitable insulating materials are selected respectively. Specifically, the insulating layer 37a is a ceramic substrate such as aluminum nitride, silicon nitride, or alumina with low thermal resistance. The insulating layer 37b is a glass epoxy substrate or a resin sheet. The ceramic substrate is prone to cracking, and since a brazing material is used for bonding the insulating substrate and the metal pattern, the pattern system is poor and the minimum dimension and error are large. On the other hand, the glass epoxy substrate or the resin sheet is difficult to crack, and since the bonding of the insulating substrate and the metal sheet is by thermal pressing, the pattern accuracy is high.

[0051] FIG. 23 is a cross-sectional view showing a modified example of the semiconductor device according to Embodiment 5. In FIG. 22, the wire 44 is bonded to the metal pattern 39 of the insulating substrate 36b, but in FIG. 23, it is bonded to the metal layer 53 of the insulating substrate 36a. As a result, the loss is reduced.

[0052] Note that the semiconductor chip 1 is not limited to being formed of silicon, and may be formed of a wide-bandgap semiconductor having a larger bandgap than silicon. The wide-bandgap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. A semiconductor chip formed of such a wide-bandgap semiconductor has high breakdown voltage and allowable current density, so it can be miniaturized. By using this miniaturized semiconductor chip, a semiconductor device incorporating this semiconductor chip can also be miniaturized and highly integrated. In addition, since the semiconductor chip has high heat resistance, the heat dissipation fins of the heat sink can be miniaturized and the water-cooling part can be air-cooled, so the semiconductor device can be further miniaturized. Also, since the power loss of the semiconductor chip is low and it is highly efficient, the semiconductor device can be made highly efficient.

Explanation of Reference Numerals

[0053] 1 semiconductor chip, 8, 28 gate insulating film, 10 emitter electrode, 15 first gate electrode pad, 22 outer peripheral breakdown voltage holding structure, 29 collector electrode, 31 second gate electrode pad, 36, 36a, 36b insulating substrate, 37a, 37b, 37b insulating layer, 39, 40 metal pattern, 42, 43 wire, 47 slit, 48 insulating film, 50 metal layer, 51 opening, 52 via

Claims

1. A semiconductor chip having a first main surface and a second main surface on opposite sides of each other, A first main electrode formed on the first main surface and electrically connected to the semiconductor chip, A first control electrode pad formed on the first main surface with a first insulating film interposed between the semiconductor chip, A second main electrode formed on the second main surface and electrically connected to the semiconductor chip, A second control electrode pad formed on the second main surface with a second insulating film interposed between the semiconductor chip, A first wire bonded to the first main electrode, A second wire bonded to the first control electrode pad, An insulating substrate having first and second metal patterns separated from each other, The second main electrode and the second control electrode pad are respectively joined to the first and second metal patterns, The bonding portions of the first and second wires overlap the bonding portions of the second main electrode or the second control electrode pad in plan view, The second control electrode pad is formed at the central portion of the second main surface of the semiconductor chip, A slit is formed from the central portion to the outer peripheral portion of the second main surface where the second main electrode does not exist, The second metal pattern is drawn out from the central portion of the semiconductor chip through the slit to the outside of the semiconductor chip in plan view. A semiconductor device characterized by that.

2. A semiconductor chip having a first main surface and a second main surface on opposite sides of each other, A first main electrode formed on the first main surface and electrically connected to the semiconductor chip, A first control electrode pad formed on the first main surface with a first insulating film interposed between the semiconductor chip, A second main electrode formed on the second main surface and electrically connected to the semiconductor chip, A second control electrode pad formed on the second main surface with a second insulating film interposed between the semiconductor chip, A first wire bonded to the first main electrode, A second wire bonded to the first control electrode pad, An insulating substrate having first and second metal patterns separated from each other, The second main electrode and the second control electrode pad are respectively joined to the first and second metal patterns, The bonding portions of the first and second wires overlap the bonding portions of the second main electrode or the second control electrode pad in plan view, The second control electrode pad is formed at the central portion of the second main surface of the semiconductor chip. An insulating film is formed so as to cover a part of the second main electrode from the central portion to the outer peripheral portion of the second main surface. The semiconductor device is characterized in that the second metal pattern is drawn out to the outside of the semiconductor chip through a region where the insulating film is formed from the central portion of the semiconductor chip in plan view. **Claim 3** The semiconductor device according to claim 1 or 2, wherein a distance between the second main electrode and the second control electrode pad is 0.5 mm or less. **Claim 4** The insulating substrate includes a first insulating layer, a metal layer formed on the first insulating layer, and a second insulating layer formed on the metal layer. The first and second metal patterns are formed on the second insulating layer. An opening is formed in the second insulating layer. The semiconductor device according to any one of claims 1 to 3, wherein the metal layer is connected to the first metal pattern or the second metal pattern through the opening. **Claim 5** A third metal pattern formed on the second insulating layer and separated from the first and second metal patterns, and a via formed in the second insulating layer and connecting the metal layer and the third metal pattern. The semiconductor device according to claim 4, wherein the metal layer is connected to the second metal pattern through the opening. **Claim 6** The opening is formed directly below the semiconductor chip. The semiconductor device according to claim 4, wherein the metal layer is connected to the first metal pattern through the opening. **Claim 7** The semiconductor device according to any one of claims 4 to 6, wherein the first insulating layer and the second insulating layer are made of the same material. **Claim 8** The semiconductor device according to any one of claims 4 to 6, wherein the first insulating layer and the second insulating layer are made of different materials. **Claim 9** The first insulating layer is a ceramic substrate. The semiconductor device according to claim 8, wherein the second insulating layer is a glass epoxy substrate or a resin sheet. **Claim 10** The semiconductor device according to any one of claims 1 to 9, wherein the semiconductor chip is an IGBT or an RC-IGBT. **Claim 11** The semiconductor device according to any one of claims 1 to 10, wherein the semiconductor chip is formed of a wide bandgap semiconductor.

12. The semiconductor device according to any one of claims 1 to 11, wherein the thicknesses of the first and second metal patterns are 0.2 mm or less.

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