Wiring Substrate and Semiconductor Device

Abstract

To provide a wiring structure that is less likely to cause peel-off and cracks even in a case where an adhesion layer and a stress buffer layer do not affect electrical characteristics.SOLUTION: A wiring board includes: a substrate 11 that contains an inorganic insulation material on its surface; a first conductive layer 12 arranged on the inorganic insulation material so as to have a first region As1 and a second region As2 surrounding the first region; a second conductive layer 14 arranged on the first region of the first conductive layer, being thicker than the first conductive layer; and an organic insulation layer 22 arranged on the second region of the first conductive layer and on the inorganic insulation material.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a wiring board.

Background Art

[0002] In a wiring board having wirings disposed on a substrate, various problems may occur depending on the relationship between an insulating material and a metallic material forming the wirings disposed on this insulating material. For example, due to the adhesion and the difference in thermal stress between the insulating material and the metallic material, the wirings may peel off from the insulating material, or cracks may occur in the insulating material. If peeling or cracking occurs during manufacturing, it results in a manufacturing defect and lowers the yield, and if it occurs after the product is completed, it leads to a decrease in reliability. In order to suppress such a decrease in yield or reliability, techniques such as disposing an adhesion layer or disposing a stress buffer layer are disclosed, for example, in Patent Documents 1 and 2.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] By disposing the adhesion layer or the stress buffer layer as described above, various manufacturing defects can be eliminated. On the other hand, when trying to improve peeling and cracking only with such a layer, the presence of this layer may affect the electrical characteristics. In that case, the design of the wiring board may become complicated to reduce the influence. When the wiring is viewed in plan from the surface of the substrate, stress concentrates at the boundary between the wiring and the adhesion layer or the stress buffer layer. In such a stress-concentrating portion, peeling and cracking are likely to occur. Therefore, even when the adhesion layer and the stress buffer layer do not affect the electrical characteristics, it is more preferable to devise and adopt a wiring structure in which peeling and cracking are less likely to occur in order to suppress product defects.

[0005] One of the objects of the present disclosure is to suppress manufacturing defects occurring in a wiring board by a method different from the conventional method.

Means for Solving the Problems

[0006] According to the present disclosure, there is provided a wiring board including a substrate containing an inorganic insulating material on the surface, a first conductive layer disposed on the inorganic insulating material and having a first region and a second region surrounding the first region, a second conductive layer disposed on the first region of the first conductive layer and thicker than the first conductive layer, and an organic insulating layer disposed on the second region of the first conductive layer and on the inorganic insulating material.

[0007] The wiring board further includes a third conductive layer connected to the second conductive layer, the third conductive layer including a contact portion with the second conductive layer and an extended portion extending outside the contact portion, and the distance from the outer edge of the first region to the outer edge of the second region may be less than or equal to the distance from the outer edge of the contact portion to the outer edge of the extended portion.

[0008] The thickness of the first conductive layer may be smaller than the distance from the outer edge of the first region to the outer edge of the second region.

[0009] A through hole penetrating the first surface and the second surface is formed in the substrate, and on the inner surface of the through hole The first conductive layer is disposed on the first surface and the second surface, and the second region may be present on the first surface and the second surface.

[0010] A through hole penetrating the first surface and the second surface is formed in the substrate, the first conductive layer is disposed on the inner surface of the through hole, and the second region may be present on the inner surface of the through hole.

[0011] The first conductive layer and the second conductive layer may have different physical properties from each other.

[0012] The first conductive layer and the second conductive layer may be made of different materials from each other.

[0013] Further, according to the present disclosure, there is provided a semiconductor device including the above wiring substrate and a semiconductor chip electrically connected to the wiring substrate.

Advantages of the Invention

[0014] According to the present disclosure, manufacturing defects occurring in the wiring substrate can be suppressed by a method different from the conventional method.

Brief Description of the Drawings

[0015]

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Embodiments for Carrying Out the Invention

[0016] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. It should be noted that each of the embodiments shown below is an example, and the present disclosure is not construed as being limited to these embodiments. In the drawings referred to in this embodiment, the same parts or parts having the same functions are denoted by the same reference numerals or similar reference numerals (reference numerals with only A, B, etc. appended after the numbers), and the repeated description thereof may be omitted. In addition, the dimensional ratios in the drawings may be different from the actual ratios for convenience of explanation, or a part of the configuration may be omitted from the drawings. In the drawings attached to this specification, for convenience of illustration and easy understanding, the scale, the vertical and horizontal dimensional ratios, etc. may be changed or exaggerated from those of the actual object, or a part of the configuration may be omitted from the drawings.

[0017] <First Embodiment> [1. Overall Structure] A wiring board according to an embodiment of the present disclosure includes through holes and wiring. The wiring is formed of a metal material and is disposed on an inorganic insulating material. Hereinafter, such a wiring board having wiring will be specifically described. In this example, the wiring board is an interposer having through holes. Note that the wiring board may be a board without through holes.

[0018] FIG. 1 is a schematic plan view showing a wiring board 10 according to the first embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view (a cross-sectional view taken along line A-A in FIG. 1) showing the wiring board 10 in the first embodiment of the present disclosure. In FIG. 1, some configurations are omitted so that the positional relationship among the substrate 11, the first conductive layer 12, and the second conductive layer 14 can be easily understood.

[0019] The wiring board 10 includes a substrate 11, a first conductive layer 12, and a second conductive layer 14. The substrate 11 has a first surface 11a and a second surface 11b opposite to the first surface 11a. The substrate 11 is a substrate having an insulating surface, and in this example, it is an alkali-free glass. The thickness of the substrate 11 may be appropriately designed according to the use of the wiring board 10. For example, increasing the thickness of the substrate 11 can prevent it from bending against an external force, and decreasing the thickness of the substrate 11 allows it to bend following an external force. However, it is necessary to set the thickness of the substrate 11 to such an extent that a through hole 15 with a target opening width can be formed. Specifically, it is easier to form a through hole 15 with a small opening width when the substrate 11 is thinner. Therefore, the thickness of the substrate 11 is preferably 30 μm or more and 1000 μm or less, and in this example, it is 400 μm.

[0020] Note that the substrate 11 may be an inorganic insulating material other than glass, an organic material, or a semiconductor substrate. For example, when a silicon substrate is used for an interposer, a case where the substrate surface is coated with an inorganic insulating material such as a silicon oxide film or a silicon nitride film can be considered. This is because silicon is a material with excellent rigidity but has conductivity. Note that by forming an inorganic insulating material such as a silicon oxide film or a silicon nitride film on the side wall of the through hole, the diameter of the through hole can be reduced, and a through electrode with a high aspect ratio can be formed. On the other hand, since glass, particularly alkali-free glass and quartz, are insulating, there is no need to coat the surface with another material to obtain insulation unless there is a particular reason. Therefore, when considering electrical characteristics, it can be regarded as a uniform substance, which facilitates the simulation of characteristics and the design of the wiring structure. For materials such as alkali glass, which have higher insulation than silicon but lower insulation than alkali-free glass, they may be coated with an inorganic insulating material as in the case of a silicon substrate if necessary.

[0021] The wiring 100 has a structure in which a plurality of conductive layers (two conductive layers in this example) are laminated, and includes a first conductive layer 12 disposed on the surface of the substrate 11 and a second conductive layer 14 laminated on a part of the first conductive layer 12. There is a region near the edge of the first conductive layer 12 where the second conductive layer 14 is not disposed. According to the plan view shown in FIG. 1, the edge of the first conductive layer 12 is disposed outside the edge of the second conductive layer 14. Among the first conductive layer 12, the region where the second conductive layer 14 is disposed is referred to as a first region As1, and the other region, that is, the region where the second conductive layer 14 is not disposed is referred to as a second region As2 (see FIG. 3). According to this definition, it can be said that the first region As1 is surrounded by the second region As2. Note that the first conductive layer 12 may be directly disposed on the surface (the first surface 11a or the second surface 11b) of the substrate 11, or may be disposed on an inorganic insulating material different from the inorganic insulating material on the surface of the substrate 11 via at least one conductive or insulating layer.

[0022]

[0023] The first conductive layer 12 corresponds to a part of the seed layer. The seed layer is a conductive layer that functions as an electrode when forming the second conductive layer 14 by electrolytic plating. In this example, the first conductive layer 12 is a copper (Cu) film, but it may be other films such as chromium (Cr), titanium (Ti), nickel (Ni), tantalum (Ta), molybdenum (Mo), or may be formed of a plurality of films. The thickness of the first conductive layer 12 is preferably 0.05 μm or more and 2 μm or less, more preferably 0.05 μm or more and 1 μm or less, and is 0.2 μm in this example.

[0024] In this example, the first conductive layer 12 is formed by electroless plating, but may be formed by another method such as sputtering. When the electroless plating method is used, even if the aspect ratio of the through hole 15 is large, it is easy to form the first conductive layer 12 on the inner surface 15a of the through hole 15. On the other hand, the first conductive layer 12 formed by the electroless plating method tends to have a smaller adhesion to the substrate 11 than when formed by the sputtering method. Even in such a case, by adopting the structure of the wiring 100 according to the present disclosure, the stress concentrated at the end of the second conductive layer 14 when the wiring is viewed in plan from the substrate surface can be dispersed by the first conductive layer 12, and since the contact area of the first conductive layer 12 with the substrate 11 increases, peeling of the wiring 100 from the substrate 11 can be suppressed. Further, when further suppressing peeling, an adhesion layer may be used in combination. Conversely, when suppressing cracks, a stress buffer layer may be used in combination.

[0025] The second conductive layer 14 is formed by electrolytic plating using the first conductive layer 12 as a seed layer. In this example, the second conductive layer 14 is a Cu film, but it may be a film of other conductive materials or may be formed of a plurality of films. As the thickness of the second conductive layer 14 increases, the stress caused by thermal changes increases. Therefore, it is preferably thin to prevent peeling and cracking. However, it is preferably thick to reduce wiring resistance. For this reason, the thickness of the second conductive layer 14 is designed to balance these, and in this example, it is preferably 0.5 μm or more and 40 μm or less, more preferably 5 μm or more and 30 μm or less, and is 20 μm in this example. Note that the first conductive layer 12 and the second conductive layer 14 may be formed of different materials from each other, or may be formed of the same material as each other. Even when the first conductive layer 12 and the second conductive layer 14 are formed of the same material as each other, they may have different physical properties such as different film qualities.

[0026] The substrate 11 has a through hole 15 that penetrates the first surface 11a and the second surface 11b. Also inside the through hole 15, the first conductive layer 12 and the second conductive layer 14 are disposed. The first conductive layer 12 and the second conductive layer 14 disposed inside the through hole 15 constitute a through electrode by reaching the first surface 11a side and the second surface 11b side of the substrate 11. In this example, inside the through hole 15, a conductive layer is disposed along the inner surface 15a of the through hole 15, and an insulating layer 22 is disposed in the central axis portion, but it may be blocked by the conductive layer.

[0027] In order to suppress transmission loss, it is necessary to reduce the wiring resistance including the through electrode. Also, if the through hole 15 is enlarged, the wiring pitch cannot be reduced, making integration difficult. Therefore, the opening width of the through hole 15 must be at least larger than twice the thickness of the second conductive layer 14. Considering the necessity and machining accuracy, it is preferably 150 μm or less, and in this example, it is 80 μm. Here, the opening width of the through hole 15 defines a figure formed by the cross section of the through hole 15 along these surfaces between the first surface 11a and the second surface 11b, and refers to the maximum value of the values that can be obtained as the distance between any two points on the outer edge of the figure. When the figure formed by the outer edge is circular, the above-mentioned width refers to the diameter of the circle. As will be described later, since the through hole 15 does not have to be cylindrical, the opening width may differ between the first surface 11a and the second surface 11b. The opening width specified as 150 μm or less here indicates the narrower opening width among the opening width on the first surface 11a side and the opening width on the second surface 11b side of the through hole 15.

[0028] For example, when the thickness of the second conductive layer 14 is 20 μm, in order to provide an opening between the first surface 11a and the second surface 11b in the through hole 15 even after the second conductive layer 14 is formed, the lower limit of the opening width needs to be twice the thickness of the second conductive layer 14, that is, 40 μm or more. By providing such an opening, the flow of gas and liquid can be generated between the first surface 11a and the second surface 11b through the through hole 15.

[0029] On the other hand, it is also possible to block the through hole 15 simultaneously with the formation of the second conductive layer 14. In that case, the opening width needs to be less than twice the thickness of the second conductive layer 14, that is, less than 40 μm. At this time, in order to block the through hole 15 and prevent a cavity from occurring inside the through hole 15, it is preferable to make only one of the first surface 11a or the second surface 11b of the through hole 15 less than 40 μm. By closing the through hole 15 in this way, it becomes possible to provide, for example, a via and laminate wiring at the closed portion, and it is possible to prevent the flow of gas and liquid between the first surface 11a and the second surface 11b.

[0030] However, as described above, for example, when the thickness of the substrate 11 is 1000 μm, since the substrate 11 is sufficiently thick, it is difficult to reduce the opening width of the through hole 15. That is, the opening width needs to be appropriately adjusted according to the processing method and the thickness of the substrate 11. In this embodiment, since the substrate 11 with a thickness of 400 μm is used, the opening width of the through hole 15 is set to 40 μm or more in consideration of processability. When the opening width of the through hole 15 is small, it is also necessary to consider the method of forming the seed layer. For example, when using physical film formation methods such as sputtering and evaporation, there may be cases where the seed layer cannot be formed up to the depth of the through hole 15 (the central portion between the first surface 11a and the second surface 11b), but by using electroless plating, it becomes easier to form the seed layer up to the depth of the through hole 15. On the other hand, the adhesion to the substrate 11 is lower for electroless plating and higher for physical film formation.

[0031] As shown in the figure, the through hole 15 has the same opening width between the first surface 11a and the second surface 11b, that is, it has a cylindrical shape, but it may have other shapes. For example, the opening width may vary between the first surface 11a and the second surface 11b, and may have, for example, a minimum value, a maximum value, or both a minimum value and a maximum value. Also, the opening width may gradually increase or gradually decrease from the first surface 11a to the second surface 11b.

[0032] Insulating layers 22 are formed on the first surface 11a side and the second surface 11b side of the substrate 11. In this example, the insulating layer 22 is a layer containing a resin which is an organic material. This organic resin is, for example, polyimide or acrylic. In the insulating layer 22, via holes 23 are formed. A third conductive layer 24 is disposed in each of the via holes 23. The third conductive layer 24 is electrically connected to the second conductive layer 14 disposed at the bottom of the via hole 23. Note that a multilayer wiring structure having more layers may be realized by repeatedly laminating insulating layers and conductive layers.

[0033] The wiring substrate 10 is electrically connected to the semiconductor chip 90 via the third conductive layer 24. In addition, the wiring board 10 is connected to the circuit board 80 via the solder balls 25 and the third conductive layer 24. The semiconductor chip 90 may also be connected to the third conductive layer 24 via the solder balls 25. According to this configuration, there is provided a semiconductor device having the wiring board 10, the semiconductor chip 90 disposed on the first surface 11a side of the substrate 11 and electrically connected to the second conductive layer 14, and the circuit board 80 disposed on the second surface 11b side of the substrate 11 and electrically connected to the second conductive layer 14. According to the wiring board 10 of the present embodiment, mounting a semiconductor chip 90 with a narrow terminal pitch on a large circuit board 80 is simplified. The circuit board 80 is, for example, a motherboard.

[0034] In this way, by electrically connecting a wiring board such as the wiring board 10 to other elements such as the semiconductor chip 90, a semiconductor device is realized as a whole. The semiconductor chip 90 may include functions such as, for example, a memory, a processor, an acceleration sensor, a magnetic sensor, a filter, and an amplifier. The semiconductor device is mounted on various electronic devices such as, for example, a mobile terminal, an information processing device, and a household appliance.

[0035] [2. Wiring Structure] Subsequently, the detailed structure of the wiring 100 will be described with reference to the enlarged view of the vicinity of the region AX in FIG. 2.

[0036] FIG. 3 is an enlarged view of the wiring according to the first embodiment of the present disclosure (an enlarged view of the vicinity of the region AX in FIG. 2). FIG. 4 is a diagram showing the relationship between the first conductive layer and the second conductive layer according to the first embodiment of the present disclosure. The thickness of the first conductive layer 12 is referred to as thickness t1, and the thickness of the second conductive layer 14 is referred to as thickness t2. As described above, in the first conductive layer 12, the region where the second conductive layer 14 is disposed is referred to as the first region As1, and the remaining region is referred to as the second region As2. In addition, when the side surface of the second conductive layer 14 is inclined and the width of the second conductive layer 14 expands or contracts as it moves away from the first conductive layer 12, the first region As1 is defined as the region where the second conductive layer 14 is in contact with the first conductive layer 12.

[0037] The distance from the outer edge of the first region As1 to the outer edge of the second region As2 is referred to as distance d1. Also, the portion where the second conductive layer 14 and the third conductive layer 24 are in contact is referred to as the contact portion CA. Among the third conductive layer 24, the portion that extends outward from the contact portion CA is referred to as the extended portion EA. The distance from the outer edge of the contact portion CA to the outer edge of the extended portion EA is referred to as distance d2.

[0038] As shown in FIG. 3, in the first conductive layer 12, the second region As2 is sandwiched between the substrate 11 and the insulating layer 22. The substrate 11 and the insulating layer 22 are in contact with each other in the region adjacent to the outside of the second region As2. Generally, in order to enhance the adhesion to the organic insulating material, it is advisable to increase the surface roughness of the underlying layer on which the organic insulating material is formed. However, it is not preferable to increase the surface area of the first conductive layer 12 and the second conductive layer 14. This is because when the signal transmitted through the wiring is a high-frequency signal, the signal travels along the surface of the wiring, so transmission loss is likely to occur when the surface area increases. Therefore, it is easier to increase the roughness of the inorganic insulating material in order to improve the adhesion to the organic insulating material. In addition, since the inorganic insulating material has little surface change and is easy to maintain its state, it is also characterized by being able to easily ensure the stability of the chemical bond with the organic insulating material. On the other hand, for a metal which is a conductive layer, there are concerns about changes in the surface state even during the process, such as the formation of a natural oxide film on the surface, so consideration is required in the process. That is, it is preferable to realize keeping the surface clean, controlling the oxide film, or providing an adhesion layer with the organic insulating material to coat the surface. Also, the end portion of a certain wiring 100 is constituted by the first conductive layer 12 where the second conductive layer 14 is not arranged. By adopting such a structure for the wiring 100, the stress of the second conductive layer 14 is dispersed in the second region As2 of the first conductive layer 12, and furthermore, the second region As2 is covered by the insulating layer 22 and is fixed to the substrate 11 from the outside of the second region As2. With such a configuration, the separation between the substrate 11 and the wiring 100 can be suppressed, and the occurrence of cracks in the substrate 11 can also be suppressed.

[0039] At this time, by adopting a structure that satisfies at least one of the following conditions for the wiring 100, it is possible to suppress the occurrence of peeling or cracking while further improving the electrical characteristics of the entire wiring board 10. For example, if the distance d1 is too large, it may be necessary to narrow the second conductive layer 14 due to the distance relationship between adjacent wirings, or it may act as a stub structure, making electrical design difficult. Note that the structure of the wiring 100 may satisfy these conditions in an overlapping manner, or may not satisfy some of the conditions. (Condition 1) The distance d1 is less than or equal to the distance d2. (Condition 2) The thickness t1 is smaller than the distance d1. (Condition 3) The thickness t2 is larger than the distance d1.

[0040] Note that the above-described wiring 100 is not limited to being applied only to the wiring 100 disposed only on the first surface 11a or the second surface 11b, and the same applies to the first conductive layer 12 and the second conductive layer 14 including through electrodes in the configuration.

[0041] [3. Method for manufacturing a wiring board] Next, a method for manufacturing the wiring board 10 will be described.

[0042] FIGS. 5 to 9 are diagrams for explaining a method for manufacturing a wiring board according to the first embodiment of the present disclosure. FIGS. 5 to 9 all show the cross-sectional shape (cross-sectional view taken along line A1 - A2 in FIG. 1) of the corresponding part in FIG. 2. First, a substrate 11 having a first surface 11a and a second surface 11b and having a through hole 15 penetrating the first surface 11a and the second surface 11b is prepared. The through hole 15 is formed in the substrate 11 by performing processing such as etching, laser processing, a combination of laser processing and etching, sandblasting, electrical discharge machining, or drilling. As shown in FIG. 5, a seed layer 1210 is formed on the first surface 11a, the second surface 11b, and the inner surface 15a of the through hole 15 of the substrate 11 by electroless plating.

[0043] As shown in FIG. 6, a resist mask RM is formed on a part of the seed layer 1210. By an electrolytic plating method, a conductive layer is formed on the part of the seed layer 1210 that is exposed from the resist mask RM. Thereby, the second conductive layer 14 is formed. Thereafter, the resist mask RM is removed.

[0044] As shown in FIG. 7, on the first surface 11a side and the second surface 11b side of the substrate 11, a resist mask RM is formed so as to cover the second conductive layer 14. At this time, the edge of the resist mask RM is disposed outside the second conductive layer 14. The distance from the edge of the second conductive layer 14 to the edge of the resist mask RM generally corresponds to the above-described distance d1.

[0045] As shown in FIG. 8, the seed layer 1210 exposed from the resist mask RM is etched, and then the resist mask RM is removed. Thereby, each conductive layer is separated, and a wiring 100 having a laminated structure of the first conductive layer 12 and the second conductive layer 14 is formed on the substrate 11. Subsequently, as shown in FIG. 9, an insulating layer 22 is formed from the first surface 11a side and the second surface 11b side. At this time, via holes 23 are formed in the insulating layer 22. Further, by forming a third conductive layer 24 so as to fill the via holes 23, the configuration shown in FIG. 2 is realized.

[0046] <Second Embodiment> The method for manufacturing the wiring 100 is not limited to the above-described method. Another method for manufacturing the wiring 100 will be described.

[0047] FIG. 10 and FIG. 11 are diagrams showing a method for manufacturing wiring according to the second embodiment of the present disclosure. FIG. 10 is a diagram in the vicinity of wiring 100 when the resist mask RM is removed in the structure shown in FIG. 6 in the first embodiment, and then the seed layer 1210 exposed from the plating layer 1410 (corresponding to the second conductive layer 14 shown in FIG. 6) is etched. The seed layers 1210, which are etched and separated from each other, are formed as the first conductive layer 12 on the substrate 11. In this example, the first conductive layer 12 (seed layer 1210) and the plating layer 1410 are formed of different materials. The combination of materials is adopted from a combination of materials in which the etching rate of the plating layer 1410 is higher than the etching rate of the first conductive layer 12 with respect to a predetermined etching solution.

[0048] Subsequently, as shown in FIG. 11, a part of the exposed portion of the plating layer 1410 is etched by wet etching of the plating layer 1410 with the above-described etching solution. Here, the upper surface and side surfaces of the plating layer 1410 that are not in contact with the first conductive layer 12 are exposed. Therefore, the second conductive layer 14, which is etched from the upper surface and side surfaces of the plating layer 1410 and becomes smaller as a whole, is formed. At this time, the first conductive layer 12 is hardly etched, and as shown in FIG. 11, a part of the first conductive layer 12 is exposed from the second conductive layer 14, and a structure similar to the second region As2 of the wiring 100 in the first embodiment can be formed. According to this example, unlike the first embodiment, the film thickness of the second conductive layer 14 slightly decreases. On the other hand, the size of the second region As2 can be controlled by the wet etching time regardless of the alignment accuracy during the formation of the resist mask RM as in the first embodiment. As a result, the size of the second region As2 can also be controlled with high precision.

[0049] <Third Embodiment> In the third embodiment, while adopting the same structure as in the first embodiment in the through electrode portion, an example in which wiring is arranged not on the substrate 11 but on a structure corresponding to the insulating layer 22 will be described.

[0050] FIG. 12 is a schematic cross-sectional view showing details of the wiring structure according to the third embodiment of the present disclosure. Among the first conductive layers 12A constituting the through electrodes, the first region As1 is disposed across the inner surface 15a of the through hole 15, the first surface 11a, and the second surface 11b, and the second region As2 is disposed on the first surface 11a and the second surface 11b. This configuration is the same as that of the first embodiment. The insulating layer 22A covering the second region As2 is an organic insulating material and includes an opening 225A having a diameter larger than that of the through hole 15. The first conductive layer 12A is exposed at the portion where the opening 225A is disposed. Since the second conductive layer 14A is formed on the exposed portion of the first conductive layer 12A, that portion corresponds to the first region As1.

[0051] A fourth conductive layer 16A is disposed between the second conductive layer 14A and the insulating layer 22A. The fourth conductive layer 16A corresponds to a seed layer when the second conductive layer 14A is formed by electrolytic plating. In this example, the fourth conductive layer 16A is not disposed in the portion between the first conductive layer 12A and the second conductive layer 14A, but it may be disposed.

[0052] Similar to the first embodiment, a third conductive layer 24 connected to the second conductive layer 14A through the insulating layer 22 and the via hole 23 formed in the insulating layer 22 in the first embodiment is further disposed on the second conductive layer 14A.

[0053] With such a structure, in the through electrode portion, the positional relationship among the substrate 11, the first conductive layer 12A, the second conductive layer 14A, and the insulating layer 22A is the same as that in the first embodiment, and the other wirings are disposed on the insulating layer 22A. When a pattern with a short wiring interval is adopted, it is not desirable to provide the second region As2. Therefore, such an insulating layer 22A is used for stress relaxation. By also using it as a buffer layer, it is also possible to use wiring that does not provide the second region As2. For example, when providing wiring connected to the through electrode on the substrate surface, and when a pattern is adopted in which the distance between adjacent wirings where the second regions As2 of the adjacent wirings are connected and there is a risk of short circuit is short, it is not desirable to provide the second region As2. Therefore, by forming wiring on the insulating layer 22A and also using it as a stress buffer layer, it is also possible to use wiring that does not provide the second region As2.

[0054] Also, in the through electrode portion, since the expansion or contraction of the substrate 11 due to the difference in the coefficient of thermal expansion occurs not only in the plane direction of the substrate 11 but also in the thickness direction, stress is also likely to occur. Therefore, peeling and cracking are likely to occur in the through electrode, but by adopting such a structure, it is also possible to suppress the occurrence of peeling and cracking.

[0055] Figures 13 to 15 are diagrams showing a method of manufacturing a wiring substrate according to the third embodiment of the present disclosure. Figures 13 to 15 all show the cross-sectional shape of the corresponding part with respect to Figure 12. First, a substrate 11 having a first surface 11a and a second surface 11b and having a through hole 15 penetrating the first surface 11a and the second surface 11b is prepared. As shown in Figure 13, a seed layer is formed on the first surface 11a, the second surface 11b, and the inner surface 15a of the through hole 15 of the substrate 11 by electroless plating, and by processing it into a desired pattern, the first conductive layer 12A is formed.

[0056] Subsequently, as shown in Figure 14, on the first surface 11a side and the second surface 11b side of the substrate 11, an insulating layer 22A, which is an organic insulating material, is formed so as to cover the end portions of the first conductive layer 12A (corresponding to the second region As2). At this time, an opening 225A having a diameter larger than that of the through hole 15 is formed in the insulating layer 22A.

[0057] Subsequently, as shown in FIG. 15, a seed layer 1610A is formed by a film formation method such as sputtering, vapor deposition, electroless plating, etc., and a resist mask RM is further formed. As a result, the seed layer 1610A is formed on the surface of the insulating layer 22A. Thereafter, in the same manner as in the first embodiment, the second conductive layer 14A is formed by an electrolytic plating process, and through the removal of the resist mask RM, the removal of the exposed seed layer 1610A, the formation of the insulating layer 22, and the formation of the third conductive layer 24, the configuration shown in FIG. 12 is realized.

[0058] <Fourth Embodiment> In the fourth embodiment, an example in which the second region As2 in the third embodiment is disposed on the inner surface 15a of the through hole 15 will be described.

[0059] FIG. 16 is a schematic cross-sectional view showing details of the wiring structure according to the fourth embodiment of the present disclosure. The first conductive layer 12B constituting the through electrode is disposed in a strip shape so as to go around the inside of the through hole 15. Among the first conductive layer 12B, the first region As1 and the second region As2 are disposed on the inner surface 15a of the through hole 15 and do not extend up to the first surface 11a and the second surface 11b. The insulating layer 22B covering the second region As2 is an organic insulating material and is disposed so as to cover the end portion of the second region As2 of the first conductive layer 12B inside the through hole 15, and a strip-shaped opening 225B is disposed so as to go around the inside of the through hole 15 between the two second regions As2. The first conductive layer 12B is exposed at the portion where the opening 225B is disposed. Since the second conductive layer 14B is formed on the exposed portion of the first conductive layer 12B, that portion corresponds to the first region As1. Even with such a configuration, the first region As1 is surrounded by the second region As2. In other words, the first region As1 is not disposed at the end of the first conductive layer 12B as in other embodiments.

[0060] A fourth conductive layer 16B is disposed between the second conductive layer 14B and the insulating layer 22B. The fourth conductive layer 16B corresponds to a seed layer when the second conductive layer 14B is formed by electrolytic plating. In this example, the fourth conductive layer 16B is not disposed in the portion between the first conductive layer 12B and the second conductive layer 14B, but it may be disposed.

[0061] Similar to the first embodiment, a third conductive layer 24 connected to the second conductive layer 14B is disposed on the second conductive layer 14B via the insulating layer 22 and the via hole 23 formed in the insulating layer 22 in the first embodiment.

[0062] With such a structure, in the through electrode portion, the positional relationship among the substrate 11, the first conductive layer 12B, the second conductive layer 14B, and the insulating layer 22B is the same as that in the first embodiment even inside the through hole 15, and the other wirings are disposed on the insulating layer 22B. When a pattern with a short wiring pitch is adopted, it is not desirable to provide the second region As2. Therefore, by adopting such an insulating layer 22B as a stress buffer layer, it is also possible to use wirings without providing the second region As2. For example, when providing a wiring connected to the through electrode on the substrate surface and a pattern with a short distance between adjacent wirings where the second regions As2 of the adjacent wirings are connected and there is a risk of short circuit is adopted, it is not desirable to provide the second region As2. Therefore, by forming a wiring on the insulating layer 22B and also using it as a stress buffer layer, it is also possible to use wirings without providing the second region As2.

[0063] Also, in the through electrode portion, expansion or contraction of the substrate 11 due to the difference in the coefficient of thermal expansion occurs not only in the plane direction of the substrate 11 but also in the thickness direction, so stress is also likely to occur. Therefore, peeling and cracking are likely to occur in the through electrode, but by adopting such a structure, the occurrence of peeling and cracking can also be suppressed.

[0064] Figs. 17 to 19 are diagrams showing a method of manufacturing a wiring board according to the fourth embodiment of the present disclosure. Figs. 17 to 19 all show the cross-sectional shapes of the corresponding parts with respect to Fig. 16. First, a substrate 11 having a first surface 11a and a second surface 11b and having a through hole 15 penetrating the first surface 11a and the second surface 11b is prepared. As shown in Fig. 17, a resist mask RM is formed from the first surface 11a side and the second surface 11b side of the substrate 11. At this time, it is formed so that the resist mask RM penetrates into a part inside the through hole 15. The penetration amount of the resist mask RM is adjusted by the size of the opening diameter of the portion of the resist mask RM corresponding to the through hole 15, the viscosity of the resist mask RM, and the like. The central portion of the inner surface 15a of the through hole 15 is not covered by the resist mask RM.

[0065] Subsequently, a first conductive layer 12B serving as a seed layer is formed by electroless plating. In this example, the electroless plating treatment uses conditions under which it is easier to form on an inorganic material than on an organic material. As a result, as shown in Fig. 18, the first conductive layer 12B is formed on the portion of the inner surface 15a exposed from the resist mask RM. Thereafter, the resist mask RM is removed, and as shown in Fig. 19, an insulating layer 22B, which is an organic insulating material, is formed so as to cover the end portion (corresponding to the second region As2) of the first conductive layer 12B inside the through hole 15. Such a structure is realized by setting the processing conditions so that the penetration amount of the insulating layer 22B into the through hole 15 becomes larger than when the resist mask RM is formed.

[0066] Regarding the subsequent steps, they are the same as the content described with reference to Fig. 15 in the third embodiment. That is, a seed layer is formed on the insulating layer 22B by electroless plating under conditions under which it is easier to form on an organic material than on an inorganic material, and a resist mask RM is further formed. Thereafter, a second conductive layer 14B is formed by electrolytic plating, and through the removal of the resist mask RM, the removal of the exposed seed layer, the formation of the insulating layer 22, and the formation of the third conductive layer 24, the configuration shown in Fig. 16 is realized.

[0067] <Fifth Embodiment> In the fifth embodiment, an example of manufacturing a structure similar to that of the fourth embodiment by a different method will be described.

[0068] Figures 20 to 23 are diagrams showing a method of manufacturing a wiring board according to the fifth embodiment of the present disclosure. Figures 20 to 23 all show the cross-sectional shape of the corresponding part with respect to Figure 16. First, a substrate 11 having a first surface 11a and a second surface 11b and a through hole 15 penetrating the first surface 11a and the second surface 11b is prepared. As shown in Figure 20, a seed layer 1210B is formed by electroless plating, and a resist mask RM is formed from the first surface 11a side and the second surface 11b side of the substrate 11. The formation of the resist mask RM is the same as in the fourth embodiment, but the fifth embodiment is different from the fourth embodiment in that the seed layer 1210B is formed before that.

[0069] Subsequently, as shown in Figure 21, a plating layer 1215B is formed on the portion of the seed layer 1210B exposed from the resist mask RM by an electrolytic plating process. Then, as shown in Figure 22, the resist mask RM is removed, and the seed layer 1210B is etched using the plating layer 1215B as a mask, whereby, as shown in Figure 23, a first conductive layer 12B having a structure in which the seed layer 1210B and the plating layer 1215B are laminated is formed. The subsequent steps are the same as the steps from Figure 19 in the fourth embodiment.

[0070] <Sixth Embodiment> In the above-described embodiments, the wiring 100 has a configuration in which the first conductive layer 12 and the second conductive layer 14 are laminated. However, in the sixth embodiment, an example in which a structure similar to that of the wiring 100 is realized using an integral layer will be described.

[0071] FIG. 24 and FIG. 25 are diagrams showing a method for manufacturing wiring according to the sixth embodiment of the present disclosure. First, as shown in FIG. 24, a conductive layer 1010C is formed on a substrate 11, and a resist mask RM is further formed so as to cover a part of the conductive layer 1010C. The portion covered by the resist mask RM corresponds to the first region As1, and the other portion corresponds to the second region As2. Subsequently, the portion of the conductive layer 1010C that is exposed from the resist mask RM is etched. At this time, it is preferable to use highly anisotropic etching. Then, as shown in FIG. 25, a wiring 100C having portions corresponding to the first region As1 and the second region As2 that is thinner than the first region As1 is formed. At this time, the length relationships as shown in FIGS. 3 and 4 may be similarly applied. In this way, even if the wiring is formed in one layer, by adopting a structure similar to that in the case of forming it in two layers, an effect similar to the wiring structure in the first embodiment can be obtained.

[0072] <Modification example> The present disclosure is not limited to the above-described embodiments, and includes various other modification examples. For example, the above-described embodiments have been described in detail for easy understanding of the present disclosure, and are not necessarily limited to those having all the configurations described. Also, a part of the configuration of one embodiment may be replaced with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, for a part of the configuration of each embodiment, addition, deletion, or replacement with other configurations is possible. Hereinafter, some modification examples will be described. Note that examples obtained by modifying the first embodiment can also be applied as examples of modifying other embodiments.

[0073] (1) The material of the second conductive layer 14 is not limited to Cu, and may include conductive materials such as gold (Au), silver (Ag), copper (Cu), iron (Fe), nickel (Ni), platinum (Pt), palladium (Pd), ruthenium (Ru), and tungsten (W).

[0074] (2) The method for forming the pattern of the conductive layer such as the third conductive layer 24 can take various methods. For example 、The forming method may employ a semi-additive method, a full-additive method, a subtractive method, a damascene method, a dual damascene method, or the like.

[0075] (3) The above-described substrate 11 had a structure in which at least an inorganic insulating material was exposed on the surface, but it may have a structure in which an organic insulating material is exposed on the surface. In the wiring disposed on the inorganic insulating material as described above, adopting the structure in the first embodiment is effective for improving adhesion and the like. On the other hand, in the wiring disposed on the organic insulating material, problems such as adhesion are less likely to occur than in the wiring disposed on the inorganic insulating material, but adopting the same structure as in the first embodiment increases the contact area. Therefore, the adhesion is improved compared to the case where the structure is not adopted.

[0076] [Examples (Simulation Results)] In order to verify the effect of the structure of the wiring 100 of the present disclosure, the transmission characteristics were confirmed by simulation. The wiring structure adopted a microstrip structure, the wiring length was 1.0 mm, and the wiring width corresponding to the first region As1 was 20 μm.

[0077] Considering the characteristics of the wiring 100 of the present disclosure, since the thickness t1 needs to be smaller than the distance d1, the thickness of the wiring was set to 0.5 μm for the first layer (corresponding to the first conductive layer 12) and 4.5 μm for the second layer (corresponding to the second conductive layer 14). Also, four numerical values were substituted with the distance d1 as a variable, and the obtained S parameters (S11, S21) were compared with the distance d1 (four numerical values). The numerical values substituted for the distance d1 were 0.0 μm, 1.0 μm, 2.0 μm, and 5.0 μm. 1.0 μm, 2.0 μm, and 5.0 μm correspond to the results of the present invention, and 0.0 μm corresponds to the results of the prior art.

[0078] The transmission characteristics for simulation are S parameters. Here, S11 (reflection loss at terminal 1: reflection characteristics) and S21 (insertion loss from terminal 1 to terminal 2: passing characteristics) were targeted. Here, these characteristics were compared with the variable being the operating frequency. When giving representative examples in the following description, comparison was made based on the characteristics at an operating frequency of 20 GHz.

[0079] That is, to put it simply, the embodiments disclosed here assume a microstrip structure, applied distance d1 and operating frequency as two variables, and are the results of comparing the S parameters S11 and S21 at this time. The analysis results based on the above are shown.

[0080] FIG. 26 is a diagram showing the simulation results of the operating frequency dependence of the reflection characteristics (S11). As shown in FIG. 26, S11 generally coincides regardless of the value of distance d1. That is, S11 hardly depends on distance d1.

[0081] FIG. 27 is a diagram showing the simulation results of the operating frequency dependence of the passing characteristics (S21). In S21, compared with S11, it seems that there is a difference depending on the value of distance d1. Therefore, the results of the prior art and the present invention were compared more precisely. First, the characteristic values (dB) at an operating frequency of 20 GHz were converted into gain, which is the ratio of input to output. Next, among the obtained gains, the ratios at distances d1 of 0.1 μm, 0.2 μm, and 0.5 μm were obtained so that the gain when distance d1 was 0.0 μm became 1.00. As a result, for distances d1 of 0.1 μm, 0.2 μm, and 0.5 μm, the ratios were 0.995, 0.990, and 0.988, respectively. In this way, it was confirmed that there is no significant difference in gain even due to the structure of the wiring 100 according to the present disclosure. As described above, it can be seen that even when adopting the structure of the wiring 100 described in the present disclosure, the influence on the transmission characteristics at high frequencies is slight compared to the conventional structure with distance d1 = 0.0 μm.

Description of Reference Numerals

[0082] 10... Wiring board, 11... Board, 11a... First surface, 11b... Second surface, 12, 12A, 12B ... the first conductive layer, 14, 14A, 14B... the second conductive layer, 15... through hole, 15a... inner surface, 16, 16A, 16B... the fourth conductive layer, 22, 22A, 22B... insulating layer, 23... via hole, 24... the third conductive layer, 25... solder ball, 80... circuit board, 90... semiconductor chip, 100, 100C... wiring, 225, 225A, 225B... opening, 1010C... conductive layer, 1210... seed layer, 1215B... plating layer, 1410... plating layer, 1610A... seed layer

Claims

1. A substrate including an inorganic insulating material on its surface, a first conductive layer disposed on the inorganic insulating material, a second conductive layer disposed above the first conductive layer and having a portion directly connected to the first conductive layer, an insulating layer disposed between the first conductive layer and the second conductive layer, and a third conductive layer connected to the second conductive layer and the insulating layer between the second conductive layer and the insulating layer, wherein a through hole penetrating a first surface and a second surface is formed in the substrate, the insulating layer is disposed on the first surface and the second surface, A wiring substrate.

2. The first conductive layer includes a first region where the second conductive layer is disposed and a remaining second region, the insulating layer covers the first conductive layer in the second region, The wiring substrate according to claim 1.

3. A substrate including an inorganic insulating material on its surface, a first conductive layer disposed on the inorganic insulating material, a second conductive layer disposed above the first conductive layer and having a portion directly connected to the first conductive layer, an insulating layer disposed between the first conductive layer and the second conductive layer, and a third conductive layer connected to the second conductive layer and the insulating layer between the second conductive layer and the insulating layer, the first conductive layer includes a first region where the second conductive layer is disposed and a remaining second region, the insulating layer covers the first conductive layer in the second region, wherein a through hole penetrating a first surface and a second surface is formed in the substrate, the first conductive layer is disposed on an inner surface of the through hole, on the first surface, and on the second surface, the second region exists on the first surface and the second surface, A wiring substrate.

4. A substrate including an inorganic insulating material on its surface, a first conductive layer disposed on the inorganic insulating material, a second conductive layer disposed above the first conductive layer and having a portion directly connected to the first conductive layer, an insulating layer disposed between the first conductive layer and the second conductive layer, and a third conductive layer connected to the second conductive layer and the insulating layer between the second conductive layer and the insulating layer, the first conductive layer includes a first region where the second conductive layer is disposed and a remaining second region, the insulating layer covers the first conductive layer in the second region, wherein a through hole penetrating a first surface and a second surface is formed in the substrate, the first conductive layer is disposed on an inner surface of the through hole, the second region exists on the inner surface of the through hole, A wiring substrate.

5. The first region is surrounded by the second region. The wiring board according to any one of claims 2 to 4.

6. The insulating layer covers an end portion of the first conductive layer. The wiring board according to any one of claims 1 to 5.

7. The insulating layer is an organic insulating material. The wiring board according to any one of claims 1 to 6.

8. The insulating layer is disposed on the first surface and the second surface. The wiring board according to claim 3 or claim 4.

9. The first conductive layer is connected to the third conductive layer. The wiring board according to any one of claims 1 to 8.

10. The second conductive layer is thicker than the first conductive layer. The wiring board according to any one of claims 1 to 9.

11. The first conductive layer and the second conductive layer have different physical properties. The wiring board according to any one of claims 1 to 10.

12. The first conductive layer and the second conductive layer are made of different materials. The wiring board according to any one of claims 1 to 11.

13. The wiring board according to any one of claims 1 to 12, a semiconductor chip electrically connected to the wiring board, and a semiconductor device including the same.

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