Image sensor

Abstract

To provide an image sensor that can simplify the manufacturing process and simplify a wiring structure.SOLUTION: An image sensor of the present invention includes a first chip that includes a pixel area and a pad area, and a second chip that is in contact with one side of the first chip and includes circuitry for driving the first chip. The first chip includes a first substrate, an interlayer insulating film between the first substrate and the second chip, a first wiring within the interlayer insulating film, a conductive pad located between the first wiring and the second chip and provided in the pad region, and a recess region that penetrates the first substrate and interlayer insulating film to expose the conductive pads in the pad region.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an image sensor.

Background Art

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal. Image sensors can be classified into CCD (Charge coupled device) type and CMOS (Complementary metal oxide semiconductor) type. The CMOS type image sensor is abbreviated as CIS (CMOS image sensor). The CIS includes a plurality of pixels arranged two-dimensionally. Each of the pixels includes a photodiode PD (photodiode). The photodiode serves to convert the incident light into an electrical signal.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide an image sensor that can simplify the manufacturing process and the wiring structure.

[0005] The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned should be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0006] An image sensor according to an embodiment of the present invention includes a first chip including a pixel region and a pad region, and a second chip in contact with one surface of the first chip and including a circuit for driving the first chip. The first chip may include a first substrate, an interlayer insulating film between the first substrate and the second chip, a first wiring in the interlayer insulating film, a conductive pad disposed between the first wiring and the second chip and provided in the pad region, and a recess region that penetrates the first substrate and the interlayer insulating film and exposes the conductive pad in the pad region.

[0007] An image sensor according to an embodiment of the present invention includes a first chip including a pixel region and a pad region, and a second chip in contact with one surface of the first chip and including a circuit for driving the first chip. The first chip includes a first substrate, an interlayer insulating film between the first substrate and the second chip, a first wiring in the interlayer insulating film, a metal pattern disposed between the first wiring and the second chip, the metal pattern including a conductive pad in the pad region and a first metal pattern in the pixel region, an upper connection pad between the first metal pattern and the second chip, and a recess region that penetrates the first substrate and the interlayer insulating film and exposes the conductive pad in the pad region. The first metal pattern includes an opening, and the upper connection pad can cover the opening.

[0008] The image sensor according to an embodiment of the present invention includes a first chip including a pixel region and a pad region, and a second chip in contact with one surface of the first chip and including a circuit for driving the first chip. The first chip includes a first substrate, a deep element isolation part that separates unit pixels in the pixel region of the first substrate, a photoelectric conversion part disposed in the first substrate in each of the unit pixels, a transfer gate disposed on one surface of the first substrate, an interlayer insulating film between the first substrate and the second chip, a first wiring in the interlayer insulating film, and a metal pattern disposed between the first wiring and the second chip. The metal pattern includes a conductive pad in the pad region and a first metal pattern in the pixel region, an upper connection pad between the first metal pattern and the second chip, and a recess region that penetrates the first substrate and the interlayer insulating film to expose the conductive pad in the pad region. The second chip includes a second substrate, a second wiring on the second substrate, and a lower connection pad connected to the upper connection pad. The first metal pattern includes an opening, and the upper connection pad can cover the opening.

Advantages of the Invention

[0009] The image sensor of the present invention can simplify the wiring structure between the conductive pad and the first chip. In addition, since the image sensor of the present invention can form a shielding structure that covers the pixel region together with the formation of the conductive pad and the connection pad, the manufacturing process can be simplified.

Brief Description of the Drawings

[0010]

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Mode for Carrying Out the Invention

[0011] Hereinafter, in order to describe the present invention more specifically, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

[0012] FIG. 1 is a plan view of an image sensor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1 according to an embodiment of the present invention.

[0013] Referring to FIGS. 1 and 2, the image sensor 1000 according to the present embodiment can have a structure in which a first chip CH1 and a second chip CH2 are bonded. The first chip CH1 can perform an image sensing function. The second chip CH2 can include a circuit for driving the first chip CH1 or for processing and storing an electrical signal generated by the first chip CH1.

[0014] The first chip CH1 includes a first substrate 1 including a pad region PAD, an optical black region OB, and a pixel region APS. The optical black region OB and the pad region PAD can be disposed on at least one side of the pixel region APS. As an example, the optical black region OB and the pad region PAD can each surround the pixel region APS. The first substrate 1 includes a first surface 1a and a second surface 1b on opposite sides of each other. The first substrate 1 can be, for example, a single crystal silicon wafer, a silicon epitaxial layer, or an SOI (silicon on insulator) substrate. The first substrate 1 can be doped with an impurity of a first conductivity type. For example, the first conductivity type can be a P type.

[0015] The pixel region APS can include a plurality of unit pixels UP two-dimensionally arranged along a first direction X and a second direction Y. A deep element isolation portion 13d is disposed in the first substrate 1 in the pixel region APS to separate the unit pixels UP. A shallow element isolation portion 5 can be disposed adjacent to the first surface 1a on the first substrate 1. The deep element isolation portion 13d can penetrate the shallow element isolation portion 5.

[0016] The deep device isolation portion 13d can include a conductive pattern 9 disposed in the deep trench 3, a separation insulating film 7 surrounding the side surfaces of the conductive pattern 9, and an embedded insulating pattern 11 interposed between the conductive pattern 9 and the first surface 1a of the first substrate 1. The conductive pattern 9 can include a conductive material, such as metal or polysilicon doped with impurities. The separation insulating film 7 can include, for example, a silicon oxide film. The embedded insulating pattern 11 can include, for example, a silicon oxide film. As illustrated in FIGS. 1 and 2, the conductive pattern 9 of the deep device isolation portion 13d can have a lattice shape and can be connected to a bias contact plug 29c described below.

[0017] A photoelectric conversion portion PD can be disposed in the first substrate 1 in each of the unit pixels UP. A photoelectric conversion portion PD can also be disposed in the first substrate 1 in the optical black region OB. The photoelectric conversion portion PD can be doped, for example, with impurities of a second conductivity type opposite to the first conductivity type. The second conductivity type can be, for example, N-type. The N-type impurities doped in the photoelectric conversion portion PD can form a PN junction with the P-type impurities doped in the adjacent region of the substrate 1 to provide a photodiode.

[0018] A transfer gate TG can be disposed on the first surface 1a of the first substrate 1 in each unit pixel UP. A part of the transfer gate TG can extend into the first substrate 1. A gate insulating film Gox can be interposed between the transfer gate TG and the first substrate 1. A floating diffusion (floating diffusion) region FD can be disposed in the first substrate 1 on one side of the transfer gate TG. The floating diffusion region FD can be, for example, a region doped with impurities of the second conductivity type.

[0019] Light can be incident into the first substrate 1 through the second surface 1b of the first substrate 1. Electron-hole pairs can be generated at the PN junction by the incident light. The electrons thus generated can be moved to the photoelectric conversion portion PD. If a voltage is applied to the transfer gate TG, the electrons can be moved to the floating diffusion region FD.

[0020] The first surface 1a can be covered with the upper interlayer insulating film IL. The upper interlayer insulating film IL can be formed of a multilayer film including at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a porous low dielectric film. The first wiring 15 can be disposed between or within the interlayer insulating films IL. As an example, the first wiring 15 can include a metal such as copper. The floating diffusion region FD can be connected to the first wiring 15 by the first contact plug 17. The first contact plug 17 can penetrate the first interlayer insulating film IL1 closest to the first surface 1a among the upper interlayer insulating films IL in the pixel region APS.

[0021] The upper connection pad 21 can be disposed within the second interlayer insulating film IL2 farthest from the first surface 1a among the upper interlayer insulating films IL. The upper connection pad 21 is exposed on one surface of the first chip CH1 and can be in direct contact with the lower connection pad 114 of the second chip CH2. The upper connection pad 21 can include, for example, copper. A metal pattern MP can be provided between the upper connection pad 21 and the first wiring 15. The metal pattern MP can be provided within the second interlayer insulating film IL2. The metal pattern MP can include a conductive pad 34 provided in the pad region PAD. The conductive pad 34 can be directly connected to the upper connection pad 21. The conductive pad 34 can be connected to a circuit outside the chip by wire bonding or the like. Although only one conductive pad 34 is shown, a plurality of conductive pads 34 can be arranged along the outside of the pixel region APS.

[0022] In the present embodiment, the metal pattern MP can include a first metal pattern 31 provided in the pixel region APS and a second metal pattern 32 provided in the optical black region OB. The metal pattern MP can include a metal material different from that of the upper connection pad 21. As an example, the metal pattern MP can include aluminum. The first metal pattern 31 and the second metal pattern 32 can be arranged at the same level as the conductive pad 34.

[0023] In the optical black region OB, light may not be incident on the inside of the substrate 1. The deep element isolation portion 13d extends also to the optical black region OB and can separate the first black pixel UPO1 and the second black pixel UPO2. In the first black pixel UPO1, the photoelectric conversion portion PD can be disposed within the first substrate 1. In the second black pixel UPO2, it is possible that the photoelectric conversion portion PD does not exist within the first substrate 1. Transfer gates TG and floating diffusion regions FD can be disposed in both the first black pixel UPO1 and the second black pixel UPO2. The first black pixel UPO1 can sense the amount of charge generated from the photoelectric conversion portion PD where light is blocked and provide a first reference charge amount. The first reference charge amount can be a relative reference value when calculating the amount of charge generated from the unit pixel UP. The second black pixel UPO2 can sense the amount of charge that can be generated in a state where the photoelectric conversion portion PD is absent and provide a second reference charge amount. The second reference charge amount can be used as information for removing process noise.

[0024] Although not shown, a reset transistor, a selection transistor, and a source follower transistor can be disposed on the first surface 1a of the first substrate 1. The image sensor 1000 can be a back-illuminated image sensor. The second surface 1b of the first substrate 1 can be covered with a back insulating film 23. The back insulating film 23 can be provided in the pixel region APS, the optical black region OB, and the pad region PAD.

[0025] The back insulating film 23 can include, for example, at least one of a bottom antireflective coating (hereinafter referred to as BARC) layer, a fixed charge layer, an adhesive layer, and a protective layer. The fixed charge layer can be composed of a metal oxide film or a metal fluoride film containing an amount of oxygen or fluorine less than the stoichiometric ratio. Therefore, the fixed charge layer can have a negative fixed charge. The fixed charge layer can be composed of a metal oxide or a metal fluoride containing at least one metal among hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanoids. Hole accumulation can occur around the fixed charge layer. Therefore, the generation of dark current and white spots can be effectively reduced.

[0026] The antireflection layer can prevent light reflection so that the light incident on the second surface 1b of the first substrate 1 can smoothly reach the photoelectric conversion unit PD. As an example, the antireflection layer can include a metal oxide (e.g., aluminum oxide or hafnium oxide) or a silicon-based insulating material (e.g., silicon oxide or silicon nitride).

[0027] A first recess region 25t1 that penetrates a part of the back insulating film 23 and the first substrate 1 can be provided between the optical black region OB and the pad region PAD. The side wall of the first recess region 25t1 can be aligned with the side wall of the back insulating film 23. The first recess 25t1 can expose the outermost deep element isolation part 13e among the deep element isolation parts 13d.

[0028] In the pad region PAD, a second recess region 25t2 can be provided that penetrates the back insulating film 23 and the first substrate 1 and also penetrates a part of the upper interlayer insulating film IL1. The second recess region 25t2 can expose the conductive pad 34. The sidewalls of the second recess region 25t2 can be aligned with the sidewalls of the back insulating film 23. The second recess region 25t2 can be spaced apart from the first recess region 25t1. The width of the second recess region 25t2 can increase as it gets farther from the conductive pad 34.

[0029] In the pad region PAD, the first substrate 1 can be penetrated by the pad isolation part 13g. The pad isolation part 13g can be spaced apart from the second recess region 25t2. In a plan view, the pad isolation part 13g can surround the conductive pad 34. The pad isolation part 13g can include a conductive pattern 9 disposed in a deep trench 3 similar to the deep element isolation part 13d, a separation insulating film 7 surrounding the side surfaces of the conductive pattern 9, and an embedded insulating pattern 11 interposed between the conductive pattern 9 and the upper interlayer insulating film IL1. A voltage can not be applied to the conductive pattern 9c of the pad isolation part 13g and it can be electrically insulated. In contrast, a bias contact plug connected to the conductive pattern 9 of the pad isolation part 13g can be provided.

[0030] On the back insulating film 23 in the optical black region OB and the pad region PAD, an anti-reflection pattern 27p and a first optical black pattern 29p can be arranged. The anti-reflection pattern 27p can conformally cover the first recess region 25t1. The anti-reflection pattern 27p can be formed of a metal nitride film such as TiN, TaN, or WN. The first optical black pattern 29p can be formed of, for example, tungsten. The first optical black pattern 29p can fill the first recess 25t1 to form a bias contact plug 29c. The bias contact plug 29c can be connected to the outermost deep element isolation portion 13e. For example, a negative voltage can be applied to the conductive pattern 9 in the deep element isolation portion 13d through the bias contact plug 29c. Therefore, holes that can exist on the surface of the deep element isolation portion 13d can be captured to improve the dark current characteristics.

[0031] In the pixel region APS, a light-shielding grid pattern 27g can be arranged on the back charge film 23. The light-shielding grid pattern 27g can be overlapped with the deep element isolation portion 13d and can have a planar grid structure. A low refractive index pattern 71 can be arranged on the light-shielding grid pattern 27g. The low refractive index pattern 71 can contain an organic substance. The low refractive index pattern 71 can have a refractive index smaller than that of the color filters CF1 and CF2. For example, the low refractive index pattern 71 can have a refractive index of about 1.3 or less. The low refractive index pattern 71 can be overlapped with the light-shielding grid pattern 27g and can have the same planar shape.

[0032] In the pixel region APS, color filters CF1 and CF2 can be arranged between the low refractive index patterns 71. The color filters CF1 and CF2 can each have a different one of the colors blue, green, and red. On the back insulating film 23 in the optical black region OB, a second optical black pattern CFB can be arranged. The second optical black pattern CFB can contain, for example, the same substance as the blue color filter.

[0033] The pixel region APS and the optical black region OB can be covered with the microlens layer ML. Different from what is shown, the microlens layer ML can also be provided in the pad region PAD. The microlens layer ML can have a convex lens shape on each unit pixel UP of the pixel region APS. The microlens layer ML can have a flat upper surface on the optical black region OB.

[0034] The second chip CH2 can include a second substrate 100, a plurality of transistors TR arranged on the second substrate 100, a lower interlayer insulating film 110 covering the second substrate 100, a second wiring 112 arranged in the lower interlayer insulating film 110, and a lower connection pad 114 connected to the top one among the second wirings 112. The lower interlayer insulating film 110 can have a single film or a multi-film structure of at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a porous insulating film. The lower connection pad 114 can include the same material as the upper connection pad 21, for example, copper. The lower connection pad 114 is exposed on one surface of the second chip CH2 and can be in direct contact with the upper connection pad 21 of the first chip CH1. The upper interlayer insulating film IL and the lower interlayer insulating film 110 can be in contact. Hereinafter, the surface where the first chip CH1 and the second chip CH2 are in contact can be referred to as the connection interface CI.

[0035] Figure 3 is an enlarged view of the P1 portion of Figure 2. Figure 4 is an enlarged view of the P2 portion of Figure 2. Figure 5 is an enlarged view of the P3 portion of Figure 3. Hereinafter, the shapes and arrangements of the metal pattern MP and the connection pads 21 and 114 will be described in more detail.

[0036] Referring to FIGS. 2 to 5, a second contact plug 18 can be provided that connects the first wiring 15 and the second metal pattern 32 in the optical black region OB and connects the first wiring 15 and the conductive pad 34 in the pad region PAD. The second contact plug 18 can include a metal material different from that of the first wiring 15. As an example, the second contact plug 18 can include at least one of tungsten, titanium, tantalum, and their conductive nitrides. The second contact plug 18 is not provided in the pixel region APS, and the first metal pattern 31 may not be electrically connected to the first wiring 15.

[0037] The metal pattern MP can include a first barrier layer BL1 on its lower surface MP_B and upper surface. The first barrier layer BL1 may not be provided on the side wall MP_S of the metal pattern MP. The first barrier layer BL1 can include at least one of titanium, tantalum, tungsten, and their conductive metal nitrides. The width of the metal pattern MP can decrease as it approaches the second chip CH2.

[0038] The connection pads 21, 114 can include a second barrier layer BL2. The second barrier layer BL2 can include at least one of titanium, tantalum, tungsten, and their conductive metal nitrides. As an example, the second barrier layer BL2 can be provided on the upper surface and side wall of the upper connection pad 21, but may not be provided on the lower surface in contact with the lower connection pad 114. Similarly, the second barrier layer BL2 can be provided on the lower surface and side wall of the lower connection pad 114, but may not be provided on the upper surface in contact with the upper connection pad 21. That is, the second barrier layer BL2 may not be provided at the connection interface CI. The width of the upper connection pad 21 can increase as it approaches the second chip CH2, contrary to the metal pattern MP. The width of the lower connection pad 114 can increase as it approaches the first chip CH1.

[0039] The upper connection pad 21 can include a first upper connection pad 21a provided in the pixel region APS, a second upper connection pad 21b provided in the optical black region OB, and a third upper connection pad 21c provided in the pad region PAD. The lower connection pad 114 can include a first lower connection pad 114a connected to the first upper connection pad 21a, a second lower connection pad 114b connected to the second upper connection pad 21b, and a third lower connection pad 114c connected to the third upper connection pad 21c.

[0040] As illustrated in FIG. 5, the upper connection pad 21 can penetrate through the first barrier layer BL1 on the lower surface MP_B of the metal pattern MP. At the connection portion between the upper connection pad 21 and the metal pattern MP, a step structure ST can be provided on at least one of the upper connection pad 21 and the metal pattern MP. As illustrated in FIG. 4, the second recess region 25t2 can penetrate through the first barrier layer BL1 on the upper surface of the metal pattern MP.

[0041] The first lower connection pad 114a may not be electrically connected to the second wiring 112. In contrast, the second and third lower connection pads 114b, 114c can be electrically connected to the second wiring 112. As an example, the second and third lower connection pads 114b, 114c can include vias VI (see FIG. 4) at their lower portions and can be connected to the second wiring 112 through the vias VI. The first lower connection pad 114a may not include a via connected to the second wiring 112.

[0042] The second interlayer insulating film IL2 can include a first connection insulating film CL1 at the connection interface CI. The lower interlayer insulating film 110 can include a second connection insulating film CL2 at the connection interface CI. The first connection insulating film CL1 and the second connection insulating film CL2 can be in direct contact. As an example, the first connection insulating film CL1 and the second connection insulating film CL2 can include at least one of SiCN, SiOCN, and SiC.

[0043] The thickness t1 of the metal pattern MP can be greater than the thickness t2 of the upper connection pad 21. The thickness t1 of the metal pattern MP can be greater than the thickness t3 of the first lower connection pad 114a. In contrast, the thickness t1 of the metal pattern MP can be less than the thickness t4 of the second and third lower connection pads 114b, 114c. The thickness t1 of the metal pattern MP can be greater than the thickness t5 of the second contact plug 18. As an example, the thickness t1 of the metal pattern MP can be from about 6000 Å to about 12000 Å. The thickness of the first barrier layer BL1 can be from about 100 Å to about 600 Å. The thickness t2 of the upper connection pad 21 and the thickness t3 of the first lower connection pad 114a can be from about 5000 Å to about 10000 Å. The thickness t4 of the second and third lower connection pads 114b, 114c can be from about 11000 Å to about 15000 Å.

[0044] Figures 6 and 7 are plan views illustrating the arrangement of the metal pattern MP and the connection pads 21, 114. Referring to FIG. 6, the first metal pattern 31 can have a lattice shape including a plurality of openings OP arranged two-dimensionally along the first direction X and the second direction Y. That is, the first metal pattern 31 can have a mesh shape in which a line portion extending in the first direction X and a line portion extending in the second direction Y intersect each other. The first upper connection pad 21a and the first lower connection pad 114a (hereinafter, the first connection pads 21a, 114a) can be coupled to the first metal pattern 31 as shown in the cross-sectional view of FIG. 3 and cover the opening OP. The first connection pads 21a, 114a can have a width larger than that of the opening OP in the first direction X and the second direction Y. As a result, the first metal pattern 31 and the first connection pads 21a, 114a can form a shielding structure SS that covers the pixel region APS. As an example, the shielding structure SS can completely cover the pixel region APS, more specifically, the unit pixel UP within the pixel region APS, and shield noise caused by an electromagnetic field induced by the operation of a circuit within the second chip CH2. The shielding structure SS can also cover a part of the optical black region OB together. When the image sensor operates, a ground voltage can be applied to the shielding structure SS.

[0045] The width w1 of the first upper connection pad 21a can be greater than the width w2 of the second upper connection pad 21b and the width w3 of the third upper connection pad 21c. Hereinafter, the width is described based on the width in the first direction X, but is not limited thereto. The width w4 of the first metal pattern 31 between a pair of adjacent openings OP can be smaller than the width w6 of the conductive pad 34. The width w5 of the second metal pattern 32 can be smaller than the width w6 of the conductive pad 34. Referring to FIG. 7, the first metal pattern 31 may not include the opening OP described with reference to FIG. 6. The width of the lower connection pad 114 can correspond to the width of the upper connection pad 21 connected thereto. As an example, the width of the first lower connection pad 114a can be substantially the same as the width w1 of the first upper connection pad 21a, the width of the second lower connection pad 114b can be substantially the same as the width w2 of the second upper connection pad 21b, and the width of the third lower connection pad 114c can be substantially the same as the width w3 of the third upper connection pad 21c.

[0046] According to an embodiment of the present invention, since the conductive pad 34 is provided adjacent to the first chip CH1, the wiring structure between the conductive pad 34 and the first chip CH1 can be simplified.

[0047] FIGS. 8 to 15 are drawings sequentially showing a method of manufacturing an image sensor according to an embodiment of the present invention, and are cross-sectional views taken along line A-A' of FIG. 1.

[0048] Referring to FIG. 8, the first chip CH1 is manufactured. For this purpose, an ion implantation process or the like is advanced on the first substrate 1 including the pixel region APS, the optical black region OB, and the pad region PAD to form the photoelectric conversion unit PD. A shallow element isolation portion 5 is formed on the first surface 1a of the first substrate 1 to define the active region. The shallow element isolation portion 5 can be formed by a STI (Shallow Trench Isolation) process. A deep trench 3 is formed by etching a part of the shallow element isolation portion 5 and the first substrate 1. In the pixel region APS and the optical black region OB, the deep trench 3 can limit the unit pixel UP and the black pixels UPO1, UPO2. In the pad region PAD, the deep trench 3 can limit the position of the pad isolation portion 13g. A separation insulating film 7 is conformally formed on the entire surface of the first surface 1a of the first substrate 1. After filling the deep trench 3 with a conductive material, an etch-back process is advanced to form conductive patterns 9 in the deep trench 3 respectively. Then, an embedded insulating pattern 11 is formed on the conductive pattern 9, and the separation insulating film 7 on the first surface 1a can be removed to expose the first surface 1a. Accordingly, the deep element isolation portion 13d, the outermost deep element isolation portion 13e, and the pad isolation portion 13g can be formed simultaneously.

[0049] A gate insulating film Gox, a transfer gate TG, a floating diffusion region FD, and an upper interlayer insulating film IL1 can be formed on the first surface 1a of the first substrate 1. A first contact plug 17 in contact with the floating diffusion region FD is formed through the first interlayer insulating film IL1. A first wiring 15 and an upper interlayer insulating film IL can be formed on the upper interlayer insulating film IL1. As an example, the first wiring 15 can include copper.

[0050] A second contact plug 18 connected to the first wiring 15 can be formed within the upper interlayer insulating film IL. The second contact plug 18 can be formed of a metal material different from that of the first wiring 15. As an example, the second contact plug 18 can contain tungsten. The second contact plug 18 can further include a barrier layer containing a conductive metal nitride such as titanium nitride, tantalum nitride, and tungsten nitride. The second contact plug 18 can be formed by a damascene process. As an example, forming the second contact plug 18 can include forming a via hole that penetrates the uppermost upper interlayer insulating film IL to expose the first wiring 15, sequentially forming a metal nitride layer and a metal layer within the via hole, and performing a planarization process.

[0051] Referring to FIG. 9, a metal pattern MP can be formed on the second contact plug 18. The metal pattern MP can include a conductive pad 34 provided in the pad region PAD, a first metal pattern 31 provided in the pixel region APS, and a second metal pattern 32 provided in the optical black region OB. As an example, the metal pattern MP can be formed of aluminum. Forming the metal pattern MP can include forming a conductive layer covering the upper interlayer insulating film IL and etching the same to form the conductive pad 34, the first metal pattern 31, and the second metal pattern 32 separated from each other. In this case, the conductive layer can include a first barrier layer BL1 on its upper and lower surfaces as described with reference to FIGS. 3 to 5. As an example, forming the metal pattern MP can include sequentially forming a first titanium nitride layer, an aluminum layer, and a second titanium nitride layer and then patterning them. Since the metal pattern MP is patterned by an etching process, the upper width can be smaller than the lower width, and the first barrier layer BL1 may not be provided on its sidewalls.

[0052] Referring to FIG. 10, after forming the second interlayer insulating film IL2 covering the metal pattern MP, an upper connection pad 21 connected to the metal pattern MP can be formed within the second interlayer insulating film IL2. The upper portion of the second interlayer insulating film IL2 can include the first connection insulating film CL1 as described with reference to FIGS. 3 and 4. As an example, the first connection insulating film CL1 can include at least one of SiCN, SiOCN, and SiC.

[0053] The upper connection pad 21 can be formed by a damascene process. As an example, the upper connection pad 21 can include copper. The upper connection pad 21 can include the second barrier layer BL2 as described with reference to FIGS. 3 to 5. The second barrier layer BL2 can include at least one of titanium, tantalum, tungsten, and conductive metal nitrides thereof. As an example, forming the upper connection pad 21 can include forming a recess region on the upper portion of the second interlayer insulating film IL2, then forming the second barrier layer BL2 and a copper layer within the recess region, and thereafter performing a planarization process until the second interlayer insulating film IL2 is exposed. As an example, the copper layer can be formed by electroplating using a metal seed layer. When the recess region is formed, the upper portion of the metal pattern MP (as an example, the first barrier layer BL1) can be etched together. The upper connection pad 21 can include a first upper connection pad 21a connected to the first metal pattern 31, a second upper connection pad 21b connected to the second metal pattern 32, and a third upper connection pad 21c connected to the conductive pad 34.

[0054] Referring to FIG. 11, a second chip CH2 having the structure described with reference to FIG. 2 is prepared. The first chip CH1 is covered. After positioning such that the upper interlayer insulating film IL contacts the lower interlayer insulating film 110 and the upper connection pad 21 contacts the lower connection pad 114, a thermal compression bonding process or the like can be carried out to bond the first chip CH1 onto the second chip CH2.

[0055] Referring to FIG. 12, in the state of FIG. 11, a grinding process can be performed on the second surface 1b of the first substrate 1 to reduce the thickness of the first substrate 1. At this time, the conductive patterns 9 of the deep element isolation portion 13d, the outermost deep element isolation portion 13e, and the pad isolation portion 13g can be exposed. A back insulating film 23 can be deposited on the second surface 1b of the first substrate 1. The back insulating film 23, a part of the first substrate 1, and a part of the outermost deep element isolation portion 13e can be etched to form a first recess region 25t1.

[0056] Referring to FIG. 13, after a diffusion prevention film and a first optical black film are conformally formed on the second surface 1b of the first substrate 1, a patterning process of the first optical black film can be performed. As a result, a first optical black pattern 29p can be formed in the optical black region OB and the pad region PAD. The first recess region 25t1 can be filled with the first optical black film to form a via contact plug 29c. By this patterning process, the diffusion prevention film can be exposed in the pixel region APS. After forming a low refractive index film covering the diffusion prevention film exposed in the pixel region APS, a patterning process is performed to form a low refractive index pattern 71 and a light shielding grid pattern 27g in the pixel region APS, and a diffusion prevention pattern 27p can be formed in the optical black region OB and the pad region PAD. The low refractive index film can be formed, for example, by spin coating.

[0057] Referring to FIG. 14, a passivation film 33 is conformally formed on the entire second surface 1b of the first substrate 1. Thereafter, color filters CF1, CF2 and a second optical black pattern CFB can be formed. The second optical black pattern CFB can be formed simultaneously when forming a blue color filter. Then, a microlens layer ML can be formed on the color filters CF1, CF2 and the second optical black pattern CFB. The microlens layer ML can be formed in the pixel region APS and the optical black region OB.

[0058] Referring to FIG. 15, a second recess region 25t2 that exposes the conductive pad 34 in the pad region PAD can be formed. Forming the second recess region 25t2 can include forming a mask pattern 39 and etching the first substrate 1 and the upper interlayer insulating film IL using this as an etching mask. The mask pattern 39 can include at least one of a silicon nitride film, a silicon oxide film, and a silicon oxynitride film. Thereafter, the mask pattern 39 can be removed and the manufacturing of the image sensor 1000 described with reference to FIG. 2 can be completed.

[0059] According to an embodiment of the present invention, since a shielding structure covering the pixel region can be formed using the steps for forming the conductive pad and the connection pad, the manufacturing process can be simplified. Further, since the recess region exposing the conductive pad is formed in the final stage, it is possible to mitigate the remaining of unnecessary substances such as a color filter on the conductive pad.

[0060] FIG. 16 is a plan view of an image sensor according to an embodiment of the present invention. FIG. 17 is a cross-sectional view taken along line A-A' of FIG. 16 according to an embodiment of the present invention. For simplicity of explanation, the description of overlapping configurations can be omitted.

[0061] Referring to FIGS. 16 and 17, the image sensor 1003 according to this embodiment can be an example of an Organic CMOS Image sensor. In a plan view, the through-structure 43 can be arranged between unit pixels UP. The through-structure 43 can penetrate the deep element isolation portion 13d between adjacent unit pixels UP and divide the deep element isolation portion 13d into two parts. The through-structure 43 can include a through-conductive pattern 49, a through-embedded insulating pattern 41, and a through-isolation insulating film 47. The through-isolation insulating film 47 can insulate the through-conductive pattern 49 from the conductive pattern 9 of the deep element isolation portion 13d. The through-conductive pattern 49 can include substances such as the conductive pattern 9 of the deep element isolation portion 13d, the outermost deep element isolation portion 13e, and the pad isolation portion 13g. The third contact plug 19 can penetrate the first interlayer insulating film IL1 and the through-embedded insulating pattern 41 to connect the through-conductive pattern 49 to a part of the first wiring 15. It can be assumed that the first optical black pattern 29p described with reference to FIG. 2 is not provided. Color filters CF1 and CF2 can be arranged on the back insulating film 23 in the pixel region APS. In this example, the color filters CF1 and CF2 can each have a different one of blue or red colors. The color filters CF1 and CF2 can be covered with a planarization film 51. Pixel electrodes PE can be arranged on the planarization film 51 in the pixel region APS and the optical black region OB so as to be separated from each other. The fourth contact plug 53 can penetrate the planarization film 51 to connect the pixel electrode PE and the through-conductive pattern 49. The planarization film 51 can include at least one of a silicon oxide film and a silicon nitride film. The pixel electrode PE can be covered with an organic photoelectric conversion film OPD. The organic photoelectric conversion film OPD can include a p-type organic semiconductor material and an n-type organic semiconductor material, and the p-type organic semiconductor material and the n-type organic semiconductor material can form a pn junction. Alternatively, the organic photoelectric conversion film OPD can include a quantum dot or a chalcogenide material. The organic photoelectric conversion film OPD can perform photoelectric conversion for light of a specific color (for example, green).A common electrode CE can be disposed on the organic optoelectronic conversion film OPD. The pixel electrode PE and the common electrode CE can include ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ZnO (Zinc Oxide), and / or an organic transparent conductive material.

[0062] A microlens layer ML can be disposed on the common electrode CE. A second optical black pattern OBP can be disposed in the microlens layer ML in the optical black region OB. The second optical black pattern OBP can include, for example, an opaque metal (such as aluminum). By including the organic optoelectronic conversion film OPD, the image sensor 1003 according to this embodiment can simultaneously detect light of two colors with one unit pixel UP.

[0063] As described above, embodiments of the present invention have been described with reference to the accompanying drawings. Those having ordinary knowledge in the technical field to which the present invention pertains can understand that the present invention can be implemented in other specific forms without changing its technical idea or essential features. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and not restrictive. In addition to the individual embodiments described, the embodiments of the present invention can include embodiments in which the configurations of the individual embodiments are combined, exchanged, and modified with each other.

Explanation of Reference Numerals

[0064] 1 First substrate 17 First contact plug 21 Upper connection pad 23 Back insulating film 34 Conductive pad 110 Lower interlayer insulating film 114 Lower connection pad 1000 Image sensor APS Pixel region CH1 First chip FD Floating diffusion region IL Upper interlayer insulating film OB Optical black area PAD Pad area PD Photoelectric conversion section TG Transfer gate UP Unit pixel

Claims

1. A first chip including a pixel region and a pad region, and a second chip in contact with one surface of the first chip and including a circuit for driving the first chip. The first chip includes: a first substrate, an interlayer insulating film between the first substrate and the second chip, a first wiring in the interlayer insulating film, a conductive pad disposed between the first wiring and the second chip and provided in the pad region, a recess region penetrating the first substrate and the interlayer insulating film to expose the conductive pad in the pad region, a first upper connection pad between the conductive pad and the second chip, a metal pattern disposed between the first wiring and the second chip and provided in the pixel region, and a second upper connection pad between the metal pattern and the second chip. The second chip includes a first lower connection pad directly connected to the first upper connection pad. The metal pattern includes the same material as the conductive pad and is disposed at the same level. The metal pattern and the second upper connection pad are directly connected. The metal pattern has a lattice shape including openings, and the second upper connection pad covers each of the openings. An image sensor.

2. The first upper connection pad and the first lower connection pad include the same metal material. The image sensor according to claim 1, wherein the conductive pad includes a metal material different from the first upper connection pad and the first lower connection pad.

3. The conductive pad includes aluminum. The image sensor according to claim 2, wherein the first upper connection pad and the first lower connection pad include copper.

4. The image sensor according to claim 1, wherein the conductive pad is thicker than the first upper connection pad.

5. The image sensor according to claim 1, wherein the width of each of the second upper connection pads is larger than the width of the first upper connection pad.

6. The first chip further includes a contact plug connecting the first wiring and the conductive pad. The image sensor according to claim 1, wherein the contact plug is not provided between the metal pattern provided in the pixel region and the first wiring.

7. The conductive pad includes barrier layers on its upper and lower surfaces. The image sensor according to claim 1, wherein the recess region penetrates the barrier layer on the upper surface of the conductive pad.

8. The image sensor according to claim 7, wherein the barrier layer is not provided on the sidewall of the conductive pad.

9. A first chip including a pixel region and a pad region, A second chip in contact with one surface of the first chip and including a circuit for driving the first chip, The first chip includes A first substrate, An interlayer insulating film between the first substrate and the second chip, A first wiring in the interlayer insulating film, A metal pattern disposed between the first wiring and the second chip, the metal pattern including a conductive pad in the pad region and a first metal pattern in the pixel region, An upper connection pad between the first metal pattern and the second chip, The first metal pattern includes an opening, and the upper connection pad is an image sensor covering the opening.

10. The image sensor according to claim 9, wherein the pixel region is completely covered by the first metal pattern and the upper connection pad.

11. The second chip includes a lower connection pad directly connected to the upper connection pad, The image sensor according to claim 9, wherein the width of the lower connection pad in the pixel region is larger than the width of the lower connection pad in the pad region.

12. The image sensor according to claim 9, wherein the first chip further includes a recess region that penetrates the first substrate and the interlayer insulating film to expose the conductive pad in the pad region.

13. The first chip further includes an optical black region, The metal pattern further includes a second metal pattern in the optical black region, The image sensor according to claim 9, wherein the width of the second metal pattern is smaller than the width of the conductive pad.

14. The image sensor according to claim 9, wherein the conductive pad is thicker than the upper connection pad.

15. A first chip including a pixel region and a pad region, A second chip in contact with one surface of the first chip and including a circuit for driving the first chip, The first chip includes A first substrate, A deep device isolation portion that separates unit pixels in the pixel region of the first substrate, A photoelectric conversion portion disposed in the first substrate for each of the unit pixels, A transfer gate disposed on one surface of the first substrate, An interlayer insulating film between the first substrate and the second chip, A first wiring in the interlayer insulating film, A metal pattern disposed between the first wiring and the second chip, the metal pattern including a conductive pad within the pad region and a first metal pattern within the pixel region. An upper connection pad between the first metal pattern and the second chip. The second chip includes a second substrate, second wiring on the second substrate, and a lower connection pad connected to the upper connection pad. The first metal pattern includes an opening, and the upper connection pad is an image sensor covering the opening. **Claim 16** The image sensor according to claim 15, wherein the first chip further includes a recess region that penetrates the first substrate and the interlayer insulating film to expose the conductive pad in the pad region.

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