Semiconductor module

Abstract

To provide semiconductor modules with a module structure that is desirable for performance improvement and miniaturization.SOLUTION: A semiconductor module A1 has a conductive substrate 2, a semiconductor element 10, control terminals 46A-46E, 47A-47E, and encapsulating resin. The conductive substrate has a main surface and a back surface spaced apart from each other in the thickness direction z. The semiconductor element is electrically bonded to the main surface and has a switching function. Control terminals control the semiconductor element. The encapsulating resin has a resin main surface and a resin back surface, and covers the conductive substrate, the semiconductor element, and part of the control terminals. The control terminals protrude from the resin main surface and extend along the thickness direction.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor module.

Background Art

[0002] Conventionally, semiconductor modules including power switching elements such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and IGBTs (Insulated Gate Bipolar Transistors) are known. Such semiconductor modules are mounted on all kinds of electronic devices from industrial equipment to home appliances, information terminals, and automotive equipment. Patent Document 1 discloses a conventional semiconductor module (power module). The semiconductor module described in Patent Document 1 includes a semiconductor element and a support substrate (ceramic substrate). The semiconductor element is, for example, an IGBT made of Si (silicon). The support substrate supports the semiconductor element. The support substrate includes an insulating base material and conductor layers laminated on both surfaces of the base material. The base material is made of, for example, ceramic. Each conductor layer is made of, for example, Cu (copper), and a semiconductor element is joined to one of the conductor layers.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In recent years, energy saving, high performance, and miniaturization of electronic devices have been demanded. For this purpose, improvement in performance and miniaturization of semiconductor modules mounted on electronic devices are required.

[0005] The present disclosure has been conceived in view of the above circumstances, and an object thereof is to provide a semiconductor module having a preferable module structure for improving performance and miniaturization and the like.

Means for Solving the Problems

[0006] The semiconductor module of the present disclosure includes a conductive substrate having a main surface facing one side in the thickness direction and a back surface facing the opposite side of the main surface, a semiconductor element electrically joined to the main surface and having a switching function, a control terminal for controlling the semiconductor element, and a sealing resin having a resin main surface facing the same side as the main surface and a resin back surface facing the opposite side of the resin main surface, and covering the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin main surface and extends along the thickness direction.

Effects of the Invention

[0007] According to the above configuration, for example, a preferable semiconductor module structure for improving performance and miniaturization and the like can be provided.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] Preferred embodiments of the semiconductor module of the present disclosure will be described below with reference to the drawings. In the following description, the same or similar components are denoted by the same reference numerals, and redundant descriptions are omitted.

[0010] FIGS. 1 to 20 show a semiconductor module A1 according to the first embodiment. The semiconductor module A1 includes a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3, a plurality of input terminals 41 to 43, a plurality of output terminals 44, a plurality of control terminals 45, a control terminal support 5, a conductive member 6, a first conductive bonding material 71, a second conductive bonding material 72, a plurality of wires 731 to 735, an encapsulating resin 8, a resin portion 87, and a resin filling portion 88.

[0011] FIG. 1 is a perspective view showing a semiconductor module A1. FIG. 2 is a view of the perspective view of FIG. 1 with the encapsulating resin 8, resin portion 87, and resin filling portion 88 omitted. FIG. 3 is a view of the perspective view of FIG. 2 with the conduction member 6 omitted. FIG. 4 is a plan view showing the semiconductor module A1. FIG. 5 is a view of the plan view of FIG. 4 with the encapsulating resin 8, resin portion 87, and resin filling portion 88 shown by imaginary lines. FIG. 6 is a partial enlarged view of a part of FIG. 5. In FIG. 6, the imaginary lines of the encapsulating resin 8, resin portion 87, and resin filling portion 88 are omitted. FIG. 7 is a partial enlarged view of a part of FIG. 6. FIG. 8 is a view of the plan view of FIG. 5 with a part of the conduction member 6 (a second conduction member 62 described later) shown by imaginary lines. FIG. 9 is a front view showing the semiconductor module A1. FIG. 10 is a bottom view showing the semiconductor module A1. FIG. 11 is a left side view showing the semiconductor module A1. FIG. 12 is a right side view showing the semiconductor module A1. FIG. 13 is a cross-sectional view taken along line XIII-XIII of FIG. 5. FIG. 14 is a cross-sectional view taken along line XIV-XIV of FIG. 5. FIG. 15 is a partial enlarged view of a part of FIG. 14. FIG. 16 is a cross-sectional view taken along line XVI-XVI of FIG. 5. FIG. 17 is a cross-sectional view taken along line XVII-XVII of FIG. 5. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII of FIG. 5. FIG. 19 is a cross-sectional view taken along line XIX-XIX of FIG. 5. Note that in FIGS. 2, 3, 7, 14, and 18, a plurality of wires 731 to 735 are omitted. FIG. 20 is an example of a circuit configuration of the semiconductor module A1. In the circuit diagram of FIG. 20, only one each of a plurality of first semiconductor elements 10A (described later) and a plurality of second semiconductor elements 10B (described later) are shown, and the other first semiconductor elements 10A and the other second semiconductor elements 10B are omitted.

[0012] For the sake of convenience of explanation, three mutually perpendicular directions, namely, the x-direction, the y-direction, and the z-direction, are referred to. As an example, the z-direction is the thickness direction of the semiconductor module A1. The x-direction is the left-right direction in the plan view of the semiconductor module A1 (see FIG. 4). The y-direction is the up-down direction in the plan view of the semiconductor module A1 (see FIG. 4). One of the x-directions is the x1-direction, and the other of the x-directions is the x2-direction. Similarly, one of the y-directions is the y1-direction, the other of the y-directions is the y2-direction, one of the z-directions is the z1-direction, and the other of the z-directions is the z2-direction. In the following description, "plan view" means when viewed in the z-direction. The z-direction is an example of the "thickness direction", the x-direction is an example of the "first direction", and the y-direction is an example of the "second direction".

[0013] The plurality of semiconductor elements 10 are each the functional center of the semiconductor module A1. The constituent material of each semiconductor element 10 is, for example, a semiconductor material mainly composed of SiC (silicon carbide). This semiconductor material is not limited to SiC, and may be Si (silicon), GaAs (gallium arsenide), GaN (gallium nitride), or the like. Each semiconductor element 10 has, for example, a switching function unit Q1 (see FIG. 20) composed of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The switching function unit Q1 is not limited to a MOSFET, and may be other transistors such as a field-effect transistor including a MISFET (Metal-Insulator-Semiconductor FET) or a bipolar transistor such as an IGBT. Each semiconductor element 10 is the same element. Each semiconductor element 10 is, for example, an n-channel type MOSFET, but may be a p-channel type MOSFET.

[0014] As shown in FIG. 15, each semiconductor element 10 has an element main surface 101 and an element back surface 102. In each semiconductor element 10, the element main surface 101 and the element back surface 102 are separated in the z-direction. The element main surface 101 faces the z2-direction, and the element back surface 102 faces the z1-direction.

[0015] The plurality of semiconductor elements 10 includes a plurality of first semiconductor elements 10A and a plurality of second semiconductor elements 10B. In the present embodiment, the semiconductor module A1 includes three first semiconductor elements 10A and three second semiconductor elements 10B. However, the number of the first semiconductor elements 10A and the number of the second semiconductor elements 10B are not limited to this configuration and can be appropriately changed according to the performance required for the semiconductor module A1. In the example of FIG. 8, three first semiconductor elements 10A and three second semiconductor elements 10B are arranged respectively. The number of the first semiconductor elements 10A and the number of the second semiconductor elements 10B may be one or two respectively, or may be four or more respectively. The number of the first semiconductor elements 10A and the number of the second semiconductor elements 10B may be equal or different. The number of the first semiconductor elements 10A and the number of the second semiconductor elements 10B is determined by the current capacity handled by the semiconductor module A1.

[0016] As shown in FIG. 20, the semiconductor module A1 is configured as, for example, a half-bridge type switching circuit. In this case, the plurality of first semiconductor elements 10A constitute the upper arm circuit of the semiconductor module A1, and the plurality of second semiconductor elements 10B constitute the lower arm circuit. In the upper arm circuit, the plurality of first semiconductor elements 10A are connected in parallel to each other, and in the lower arm circuit, the plurality of second semiconductor elements 10B are connected in parallel to each other. Each first semiconductor element 10A and each second semiconductor element 10B are connected in series to form a bridge layer.

[0017] As shown in FIGS. 8 and 16, etc., the plurality of first semiconductor elements 10A are each mounted on the conductive substrate 2. In the example shown in FIG. 8, the plurality of first semiconductor elements 10A are arranged, for example, in the y direction and are spaced apart from each other. Each first semiconductor element 10A is conductively joined to the conductive substrate 2 (the first conductive portion 2A described later) via the second conductive joining material 72. When each first semiconductor element 10A is joined to the first conductive portion 2A, the back surface 102 of the element faces the first conductive portion 2A.

[0018] As shown in FIGS. 8 and 17, etc., the plurality of second semiconductor elements 10B are each mounted on the conductive substrate 2. In the example shown in FIG. 8, the plurality of second semiconductor elements 10B are arranged side by side in the y direction, for example, and are spaced apart from each other. Each second semiconductor element 10B is conductively joined to the conductive substrate 2 (second conductive portion 2B described later) via the second conductive joining material 72. When each second semiconductor element 10B is joined to the second conductive portion 2B, the element back surface 102 faces the second conductive portion 2B. As understood from FIG. 8, when viewed in the x direction, the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B may or may not overlap.

[0019] The plurality of semiconductor elements 10 (the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B) each have a first main surface electrode 11, a second main surface electrode 12, and a back surface electrode 15. The configurations of the first main surface electrode 11, the second main surface electrode 12, and the back surface electrode 15 described below are common to each semiconductor element 10. The first main surface electrode 11 and the second main surface electrode 12 are provided on the element main surface 101. The first main surface electrode 11 and the second main surface electrode 12 are insulated by an insulating film (not shown). The back surface electrode 15 is provided on the element back surface 102.

[0020] The first main surface electrode 11 is, for example, a gate electrode, and a drive signal (for example, a gate voltage) for driving the semiconductor element 10 is input thereto. In each semiconductor element 10, the second main surface electrode 12 is, for example, a source electrode, and a source current flows therethrough. The back surface electrode 15 is, for example, a drain electrode, and a drain current flows therethrough. The back surface electrode 15 covers substantially the entire area of the element back surface 102. The back surface electrode 15 is formed, for example, by Ag plating.

[0021] When a drive signal (gate voltage) is input to the first main surface electrode 11 (gate electrode) of each semiconductor element 10 by the switching function unit Q1, the conduction state and the cutoff state are switched according to this drive signal. This operation of switching between the conduction state and the cutoff state is called a switching operation. In the conduction state, current flows from the back surface electrode 15 (drain electrode) to the second main surface electrode 12 (source electrode), and in the cutoff state, this current does not flow. That is, each semiconductor element 10 performs a switching operation by the switching function unit Q1. The semiconductor module A1 converts the first power supply voltage (DC voltage) input between one input terminal 41 and two input terminals 42 and 43 into, for example, a second power supply voltage (AC voltage) by the switching function units Q1 of a plurality of semiconductor elements 10, and outputs the second power supply voltage from the output terminal 44. The input terminals 41 to 43 and the output terminal 44 are all power supply terminals that handle power supply voltages. The input terminals 41 to 43 are the first power supply terminals to which the first power supply voltage is input. The output terminal 44 is the second power supply terminal that outputs the second power supply voltage.

[0022] Some of the plurality of semiconductor elements 10 (two in the example shown in FIG. 8) further have a diode function unit D1 (see FIG. 20) in addition to the switching function unit Q1. In the semiconductor module A1, one of the plurality of first semiconductor elements 10A (the first semiconductor element 10A arranged on the most y2 direction side in FIG. 8) and one of the plurality of second semiconductor elements 10B (the second semiconductor element 10B arranged on the most y1 direction side in FIG. 8) include a diode function unit D1 in addition to the switching function unit Q1. Regarding the diode function unit D1, its function and role are not particularly limited, and for example, a temperature detection diode can be mentioned. Note that the diode D2 shown in FIG. 20 is, for example, a parasitic diode component of the switching function unit Q1.

[0023] As shown in FIG. 8, the semiconductor element 10 having the diode functional section D1 further includes a third main surface electrode 13, a fourth main surface electrode 14, and a fifth main surface electrode 16 in addition to the first main surface electrode 11, the second main surface electrode 12, and the back surface electrode 15. The configurations of the third main surface electrode 13, the fourth main surface electrode 14, and the fifth main surface electrode 16, which will be described below, are common to each semiconductor element 10 having the diode functional section D1. The third main surface electrode 13, the fourth main surface electrode 14, and the fifth main surface electrode 16 are formed on the element main surface 101. The third main surface electrode 13 and the fourth main surface electrode 14 are electrically connected to the diode functional section D1 in the semiconductor element 10 having the diode functional section D1. The fifth main surface electrode 16 is, for example, a source sense electrode, and a source current in the switching functional section Q1 flows therethrough.

[0024] As shown in FIG. 7, each first semiconductor element 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 in plan view. FIG. 7 shows a first semiconductor element 10A disposed at the center in the y direction among a plurality of first semiconductor elements 10A arranged in the y direction, but other first semiconductor elements 10A also have the first side 191, the second side 192, the third side 193, and the fourth side 194 in the same manner. The first side 191 and the second side 192 each extend in the y direction. The first side 191 is an edge on the x2 direction side in plan view, and the second side 192 is an edge on the x1 direction side in plan view. The third side 193 and the fourth side 194 each extend in the x direction. The third side 193 is an edge on the y2 direction side in plan view, and the fourth side 194 is an edge on the y1 direction side in plan view. Since each first semiconductor element 10A is rectangular in plan view, the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 are substantially right angles in plan view. As shown in FIG. 7, these four corners do not overlap with the conduction members 6 (the first conduction member 61 and the second conduction member 62 described later) in plan view. The lengths of the third side 193 and the fourth side 194 are greater than the lengths of the first side 191 and the second side 192.

[0025] The conductive substrate 2 is also called a lead frame. The conductive substrate 2 supports a plurality of semiconductor elements 10. The conductive substrate 2 is joined to the support substrate 3 via a first conductive bonding material 71. The conductive substrate 2 is, for example, rectangular in plan view. The conductive substrate 2, together with the conduction member 6, constitutes a path for the main circuit current switched by the plurality of semiconductor elements 10.

[0026] The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B are each a plate-like member made of metal. This metal is, for example, Cu (copper) or a Cu alloy. The first conductive portion 2A and the second conductive portion 2B, together with a plurality of input terminals 41 to 43 and a plurality of output terminals 44, constitute conduction paths to the plurality of semiconductor elements 10. As shown in FIGS. 13 to 18, the first conductive portion 2A and the second conductive portion 2B are each joined to the support substrate 3 via a first conductive bonding material 71. A plurality of first semiconductor elements 10A are each joined to the first conductive portion 2A via a second conductive bonding material 72. A plurality of second semiconductor elements 10B are each joined to the second conductive portion 2B via a second conductive bonding material 72. The first conductive portion 2A and the second conductive portion 2B are spaced apart in the x direction as shown in FIGS. 3, 8, 13, and 14. In the examples shown in these figures, the first conductive portion 2A is located in the x2 direction relative to the second conductive portion 2B. The first conductive portion 2A and the second conductive portion 2B are each, for example, rectangular in plan view. The first conductive portion 2A and the second conductive portion 2B overlap when viewed in the x direction. The first conductive portion 2A and the second conductive portion 2B each have, for example, a dimension in the x direction of 15 mm to 25 mm (preferably about 20 mm), a dimension in the y direction of 30 mm to 40 mm (preferably about 35 mm), and a dimension in the z direction of 1.5 mm to 3.0 mm (preferably about 2.0 mm).

[0027] The conductive substrate 2 has a main surface 201 and a back surface 202. As shown in FIGS. 13, 14, and 16 to 18, the main surface 201 and the back surface 202 are spaced apart in the z direction. The main surface 201 faces the z2 direction, and the back surface 202 faces the z1 direction. The main surface 201 is the combination of the upper surfaces of the first conductive portion 2A and the second conductive portion 2B. The back surface 202 is the combination of the lower surfaces of the first conductive portion 2A and the second conductive portion 2B. The back surface 202 is joined to the support substrate 3 so as to face the support substrate 3. As shown in FIGS. 5, 8, and 13, a plurality of recesses 201a are formed in the main surface 201. Each recess 201a is a portion that is recessed in the z direction from the main surface 201. The degree of depression (depth) of each recess 201a is, for example, more than 0 μm and 100 μm or less. Each recess 201a is formed, for example, during the mold forming described later. The plurality of recesses 201a include those formed in the main surface 201 of the first conductive portion 2A and those formed in the main surface 201 of the second conductive portion 2B. The two recesses 201a formed in the main surface 201 of the first conductive portion 2A are spaced apart in the y direction and overlap when viewed in the y direction. The two recesses 201a formed in the main surface 201 of the second conductive portion 2B are spaced apart in the y direction and overlap when viewed in the y direction.

[0028] The conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B) includes a base material 21, a main surface bonding layer 22, and a back surface bonding layer 23 laminated on each other. The base material 21 is a plate-shaped member made of metal. This metal is Cu or a Cu alloy. The main surface bonding layer 22 is formed on the upper surface of the base material 21. The main surface bonding layer 22 is the surface layer on the z2 direction side of the conductive substrate 2. The upper surface of the main surface bonding layer 22 corresponds to the main surface 201 of the conductive substrate 2. The main surface bonding layer 22 is, for example, Ag plating. The back surface bonding layer 23 is formed on the lower surface of the base material 21. The back surface bonding layer 23 is the surface layer on the z1 direction side of the conductive substrate 2. The lower surface of the back surface bonding layer 23 corresponds to the back surface 202 of the conductive substrate 2. The back surface bonding layer 23 is, for example, Ag plating similar to the main surface bonding layer 22.

[0029] The support substrate 3 supports the conductive substrate 2. The support substrate 3 is composed of, for example, a DBC (Direct Bonded Copper) substrate. The support substrate 3 includes an insulating layer 31, a first metal layer 32, a first bonding layer 321, and a second metal layer 33.

[0030] The insulating layer 31 is, for example, a ceramic with excellent thermal conductivity. Such a ceramic includes, for example, AlN (aluminum nitride). The insulating layer 31 is not limited to ceramics and may be an insulating resin sheet or the like. The insulating layer 31 is, for example, rectangular in plan view.

[0031] The first metal layer 32 is formed on the upper surface (the surface facing the z2 direction) of the insulating layer 31. The constituent material of the first metal layer 32 includes, for example, Cu. The constituent material may include Al instead of Cu. The first metal layer 32 includes a first part 32A and a second part 32B. The first part 32A and the second part 32B are spaced apart in the x direction. The first part 32A is located on the x2 direction side of the second part 32B. The first part 32A is joined to the first conductive part 2A and supports the first conductive part 2A. The second part 32B is joined to the second conductive part 2B and supports the second conductive part 2B. The first part 32A and the second part 32B are each, for example, rectangular in plan view.

[0032] The first bonding layer 321 is formed on the upper surface of the first metal layer 32 (each of the first part 32A and the second part 32B). The first bonding layer 321 is, for example, an Ag plating. The first bonding layer 321 is provided to facilitate bonding by solid-phase diffusion with the first conductive bonding material 71.

[0033] The second metal layer 33 is formed on the lower surface (the surface facing the z1 direction) of the insulating layer 31. The constituent material of the second metal layer 33 is the same as the constituent material of the first metal layer 32. The lower surface (the bottom surface 302 described later) of the second metal layer 33 is exposed from the encapsulating resin 8 in the example shown in FIG. 10. The lower surface may not be exposed from the encapsulating resin 8 and may be covered with the encapsulating resin 8. The second metal layer 33 overlaps both the first part 32A and the second part 32B in plan view.

[0034] As shown in FIGS. 13 to 18, the support substrate 3 has a support surface 301 and a bottom surface 302. The support surface 301 and the bottom surface 302 are spaced apart in the z direction. The support surface 301 faces the z2 direction, and the bottom surface 302 faces the z1 direction. As shown in FIG. 10, the bottom surface 302 is exposed from the sealing resin 8. The support surface 301 is the upper surface of the first bonding layer 321 and is the combined upper surface of the upper surface of the first portion 32A and the upper surface of the second portion 32B. The support surface 301 faces the conductive substrate 2 and the conductive substrate 2 is bonded thereto. The bottom surface 302 is the lower surface of the second metal layer 33. A heat dissipation member (for example, a heat sink) (not shown) or the like can be attached to the bottom surface 302. The dimension of the support substrate 3 in the z direction (the distance along the z direction from the support surface 301 to the bottom surface 302) is, for example, 0.7 mm to 2.0 mm.

[0035] The plurality of input terminals 41 to 43 and the plurality of output terminals 44 are each made of a plate-shaped metal plate. The constituent material of this metal plate is, for example, Cu or a Cu alloy. In the examples shown in FIGS. 1 to 5, FIG. 8, and FIG. 10, the semiconductor module A1 includes three input terminals 41 to 43 and two output terminals 44.

[0036] A power supply voltage is applied between the three input terminals 41 to 43. In the present embodiment, the input terminal 41 is the positive electrode (P terminal), and the two input terminals 42 and 43 are each the negative electrode (N terminal). Alternatively, the input terminal 41 may be the negative electrode (N terminal) and the two input terminals 42 and 43 may each be the positive electrode (P terminal). In this case, the wiring inside the package may be appropriately changed in accordance with the change in the polarity of the terminals. The three input terminals 41 to 43 and the two output terminals 44 each include a portion covered with the sealing resin 8 and a portion exposed from the resin side surface of the sealing resin 8.

[0037] As shown in FIG. 14, the input terminal 41 is integrally formed with the first conductive portion 2A. Different from this configuration, the input terminal 41 may be separated from the first conductive portion 2A and conductively joined to the first conductive portion 2A. As shown in FIG. 8 and the like, the input terminal 41 is located on the x2 direction side with respect to the plurality of first semiconductor elements 10A and the first conductive portion 2A (conductive substrate 2). The input terminal 41 is electrically connected to the first conductive portion 2A and, via the first conductive portion 2A, is electrically connected to the back surface electrode 15 (drain electrode) of each first semiconductor element 10A. The input terminal 41 is an example of a "first input terminal".

[0038] The input terminal 41 has an input-side bonding surface 411 and an input-side side surface 412. The input-side bonding surface 411 faces the z2 direction and extends in the x2 direction side. The input-side side surface 412 is located at the periphery of the input-side bonding surface 411 when viewed in the z direction and faces a direction intersecting the input-side bonding surface 411. In the present embodiment, the input-side side surface 412 includes a tip surface 413 and a pair of side surfaces 414. The tip surface 413 is located at the x2 direction end of the input terminal 41 and faces the x2 direction. The pair of side surfaces 414 are located at both ends of the input terminal 41 in the y direction and face the y1 direction and the y2 direction. On the input-side side surface 412, at least one of the tip surface 413 and the pair of side surfaces 414 has an input-side processing mark. The input-side processing mark is formed by a cutting process of a lead frame described later.

[0039] As shown in FIG. 8, the two input terminals 42 and 43 are each separated from the first conductive portion 2A. The two input terminals 42 and 43 are each joined with a second conductive member 62. As shown in FIG. 8 and the like, the two input terminals 42 and 43 are each located on the x2 direction side with respect to the plurality of first semiconductor elements 10A and the first conductive portion 2A (conductive substrate 2). The two input terminals 42 and 43 are each electrically connected to the second conductive member 62 and, via the second conductive member 62, are electrically connected to the second main surface electrode 12 (source electrode) of each second semiconductor element 10B. The input terminal 42 is an example of a "second input terminal", and the input terminal 43 is an example of a "third input terminal".

[0040] The input terminals 42 and 43 have input-side joint surfaces 421 and 431 and input-side side surfaces 422 and 432. The input-side joint surfaces 421 and 431 face in the z2 direction and extend in the x2 direction side. The input-side side surfaces 422 and 432 are located at the peripheries of the input-side joint surfaces 421 and 431 when viewed in the z direction and face a direction intersecting the input-side joint surfaces 421 and 431. In the present embodiment, the input-side side surface 422 includes a tip surface 423 and a pair of side surfaces 424. The tip surface 423 is located at the x2 direction side end of the input terminal 42 and faces in the x2 direction. The pair of side surfaces 424 are located at both ends of the input terminal 42 in the y direction and face in the y1 direction and the y2 direction. On the input-side side surface 422, at least one of the tip surface 423 and the pair of side surfaces 424 has an input-side processing mark. The input-side processing mark is formed by a cutting process of a lead frame described later. The input-side side surface 432 includes a tip surface 433 and a pair of side surfaces 434. The tip surface 433 is located at the x2 direction side end of the input terminal 43 and faces in the x2 direction. The pair of side surfaces 434 are located at both ends of the input terminal 43 in the y direction and face in the y1 direction and the y2 direction. On the input-side side surface 432, at least one of the tip surface 433 and the pair of side surfaces 434 has an input-side processing mark. The input-side processing mark is formed by a cutting process of a lead frame described later.

[0041] As shown in FIGS. 1 to 5, FIG. 8, and FIG. 10, etc., the three input terminals 41 to 43 each protrude from the sealing resin 8 in the x2 direction in the semiconductor module A1. The three input terminals 41 to 43 are spaced apart from each other. The two input terminals 42 and 43 are located on opposite sides of each other with the input terminal 41 interposed therebetween in the y direction. The input terminal 42 is located on the y2 direction side of the input terminal 41, and the input terminal 43 is located on the y1 direction side of the input terminal 41. The three input terminals 41 to 43 overlap each other when viewed in the y direction.

[0042] As can be understood from FIGS. 8 and 14, the two output terminals 44 are integrally formed with the second conductive portion 2B. Different from this configuration, the output terminals 44 may be separated from the second conductive portion 2B and conductively joined to the second conductive portion 2B. As shown in FIG. 8 and the like, the two output terminals 44 are each located on the x1 direction side with respect to the plurality of second semiconductor elements 10B and the second conductive portion 2B (conductive substrate 2). Each output terminal 44 is electrically connected to the second conductive portion 2B and, via the second conductive portion 2B, is electrically connected to the back surface electrode 15 (drain electrode) of each second semiconductor element 10B. The two output terminals 44 are each an example of a "first output terminal" and a "second output terminal".

[0043] The output terminal 44 has an output-side joint surface 441 and an output-side side surface 442. The output-side joint surface 441 faces the z2 direction and extends in the x1 direction side. The output-side side surface 442 is located at the periphery of the output-side joint surface 441 when viewed in the z direction and faces a direction intersecting the output-side joint surface 441. In the present embodiment, the output-side side surface 442 includes a tip surface 443 and a pair of side surfaces 444. The tip surface 443 is located at the x1 direction end of the output terminal 44 and faces the x1 direction. The pair of side surfaces 444 are located at both ends of the output terminal 44 in the y direction and face the y1 direction and the y2 direction. On the output-side side surface 442, at least one of the tip surface 443 and the pair of side surfaces 444 has an output-side processing mark. The output-side processing mark is formed by a cutting process of a lead frame described later. Note that the number of output terminals 44 is not limited to two, and may be, for example, one or three or more. For example, when there is one output terminal 44, it is desirable that it is connected to the central portion of the second conductive portion 2B in the y direction.

[0044] The plurality of control terminals 45 are each pin-shaped terminals for controlling each semiconductor element 10. The plurality of control terminals 45 include a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D. The plurality of first control terminals 46A to 46E are used for controlling each first semiconductor element 10A. The plurality of second control terminals 47A to 47D are used for controlling each second semiconductor element 10B.

[0045] The plurality of first control terminals 46A to 46E are arranged at intervals in the y direction. As shown in FIGS. 8 and 14, etc., each of the first control terminals 46A to 46E is supported by the first conductive portion 2A via a control terminal support 5 (a first support portion 5A described later). As shown in FIGS. 5 and 8, each of the first control terminals 46A to 46E is located between the plurality of first semiconductor elements 10A and the three input terminals 41 to 43 in the x direction.

[0046] The first control terminal 46A is a terminal (gate terminal) for inputting a drive signal to the plurality of first semiconductor elements 10A. A drive signal for driving the plurality of first semiconductor elements 10A is input to the first control terminal 46A (for example, a gate voltage is applied).

[0047] The first control terminal 46B is a terminal (source sense terminal) for detecting a source signal of the plurality of first semiconductor elements 10A. A voltage (a voltage corresponding to the source current) applied to each of the second main surface electrodes 12 (source electrodes) of the plurality of first semiconductor elements 10A is detected from the first control terminal 46B.

[0048] The first control terminal 46C and the first control terminal 46D are terminals that conduct to the diode function portion D1. The first control terminal 46C conducts to the third main surface electrode 13 of the first semiconductor element 10A having the diode function portion D1, and the first control terminal 46D conducts to the fourth main surface electrode 14 of the first semiconductor element 10A having the diode function portion D1.

[0049] The first control terminal 46E is a terminal (drain sense terminal) for detecting a drain signal of the plurality of first semiconductor elements 10A. A voltage (a voltage corresponding to the drain current) applied to each of the back surface electrodes 15 (drain electrodes) of the plurality of first semiconductor elements 10A is detected from the first control terminal 46E.

[0050] The plurality of second control terminals 47A to 47D are arranged at intervals in the y direction. As shown in FIGS. 5 and 18 etc., each of the second control terminals 47A to 47D is supported by the second conductive portion 2B via a control terminal support 5 (a second support portion 5B described later). As shown in FIGS. 5 and 8, each of the second control terminals 47A to 47D is located between the plurality of second semiconductor elements 10B and the two output terminals 44 in the x direction.

[0051] The plurality of control terminals 45 (the plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D) each include a holder 451 and a metal pin 452.

[0052] The holder 451 is made of a conductive material. As shown in FIG. 15, the holder 451 is joined to the control terminal support 5 (a first metal layer 52 described later) via a conductive bonding material 459. The holder 451 includes a cylindrical portion, an upper flange portion, and a lower flange portion. The upper flange portion is connected above the cylindrical portion, and the lower flange portion is connected below the cylindrical portion. The metal pin 452 is inserted through at least the upper flange portion and the cylindrical portion of the holder 451. The upper surface of the upper flange portion is exposed from the sealing resin 8 (a second protruding portion 852 described later) and is covered with the resin portion 87.

[0053] The metal pin 452 is a rod-shaped member extending in the z direction. The metal pin 452 is supported by being press-fitted into the holder 451. The metal pin 452 is electrically connected to the control terminal support 5 (a first metal layer 52 described later) at least via the holder 451. As in the example shown in FIG. 15, when the lower end (the end portion on the z1 direction side) of the metal pin 452 is in contact with the conductive bonding material 459 within the insertion hole of the holder 451, the metal pin 452 is electrically connected to the control terminal support 5 via the conductive bonding material 459.

[0054] The control terminal support 5 supports the plurality of control terminals 45. The control terminal support 5 is interposed between the main surface 201 (the conductive substrate 2) and the plurality of control terminals 45.

[0055] The control terminal support 5 includes a first support portion 5A and a second support portion 5B. The first support portion 5A is disposed on the first conductive portion 2A of the conductive substrate 2 and supports a plurality of first control terminals 46A to 46E among the plurality of control terminals 45. As shown in FIG. 15, the first support portion 5A is joined to the first conductive portion 2A via a joining material 59. The joining material 59 may be conductive or insulating, and for example, solder is used. The second support portion 5B is disposed on the second conductive portion 2B of the conductive substrate 2 and supports a plurality of second control terminals 47A to 47D among the plurality of control terminals 45. The second support portion 5B is joined to the second conductive portion 2B via the joining material 59.

[0056] The control terminal support 5 (each of the first support portion 5A and the second support portion 5B) is composed of, for example, a DBC substrate. The control terminal support 5 has an insulating layer 51, a first metal layer 52, and a second metal layer 53 laminated on each other.

[0057] The insulating layer 51 is made of, for example, ceramics. The insulating layer 51 is, for example, rectangular in plan view.

[0058] As shown in FIG. 15 and the like, the first metal layer 52 is formed on the upper surface of the insulating layer 51. Each control terminal 45 stands on the first metal layer 52. The first metal layer 52 is, for example, Cu or a Cu alloy. As shown in FIG. 8 and the like, the first metal layer 52 includes a first portion 521, a second portion 522, a third portion 523, a fourth portion 524, and a fifth portion 525. The first portion 521, the second portion 522, the third portion 523, the fourth portion 524, and the fifth portion 525 are spaced apart from each other and insulated.

[0059] The first portion 521 is joined with a plurality of wires 731, and is electrically connected to the first main surface electrode 11 (gate electrode) of each semiconductor element 10 via each wire 731. As shown in FIG. 8, the first control terminal 46A is joined to the first portion 521 of the first support portion 5A, and the second control terminal 47A is joined to the first portion 521 of the second support portion 5B.

[0060] The second part 522 has a plurality of wires 732 joined thereto, and is electrically connected to the second main surface electrode 12 (source electrode) of each semiconductor element 10 via each wire 732. As shown in FIG. 8, a first control terminal 46B is joined to the second part 522 of the first support part 5A, and a second control terminal 47B is joined to the second part 522 of the second support part 5B.

[0061] The third part 523 has a wire 733 joined thereto, and is electrically connected to the third main surface electrode 13 of the semiconductor element 10 having the diode function part D1 via the wire 733. As shown in FIG. 8, a first control terminal 46C is joined to the third part 523 of the first support part 5A, and a second control terminal 47C is joined to the third part 523 of the second support part 5B.

[0062] The fourth part 524 has a wire 734 joined thereto, and is electrically connected to the fourth main surface electrode 14 of the semiconductor element 10 having the diode function part D1 via the wire 734. As shown in FIG. 8, a first control terminal 46D is joined to the fourth part 524 of the first support part 5A, and a second control terminal 47D is joined to the fourth part 524 of the second support part 5B.

[0063] The fifth part 525 of the first support part 5A has a wire 735 joined thereto, and is electrically connected to the first conductive part 2A via the wire 735. The fifth part 525 of the second support part 5B is not electrically connected to other component parts. As shown in FIG. 8, a first control terminal 46E is joined to the fifth part 525 of the first support part 5A.

[0064] The second metal layer 53 is formed on the lower surface of the insulating layer 51 as shown in FIG. 15 and the like. The second metal layer 53 of the first support part 5A is joined to the first conductive part 2A via a bonding material 59 as shown in FIG. 15. The second metal layer 53 of the second support part 5B is joined to the second conductive part 2B via the bonding material 59.

[0065] The conduction member 6, together with the conductive substrate 2, constitutes a path for the main circuit current switched by the plurality of semiconductor elements 10. The conduction member 6 is spaced apart from the main surface 201 (conductive substrate 2) in the z2 direction and overlaps the main surface 201 in plan view. In the present embodiment, the conduction member 6 is constituted by a metal plate material. The metal is, for example, Cu or a Cu alloy. Specifically, the conduction member 6 is a bent metal plate material. However, the conduction member 6 may be constituted by a metal foil material. In the present embodiment, the conduction member 6 includes a plurality of first conduction members 61 and second conduction members 62. The main circuit current includes a first main circuit current and a second main circuit current. The first main circuit current is a current that passes between the input terminal 41 and the output terminal 44. The second main circuit current is a current that passes between the output terminal 44 and the input terminals 42 and 43.

[0066] Each of the plurality of first conduction members 61 is joined to the second main surface electrode 12 (source electrode) of each first semiconductor element 10A and the second conductive portion 2B to conduct the second main surface electrode 12 of each first semiconductor element 10A and the second conductive portion 2B. Each first conduction member 61, the second main surface electrode 12 (see FIG. 8) of each first semiconductor element 10A, and each first conduction member 61 and the second conductive portion 2B are joined via a conductive bonding material 69, respectively. The conductive bonding material 69 is, for example, solder, a metal paste material, or a sintered metal. As shown in FIG. 8, each first conduction member 61 is in a strip shape extending along the x direction in plan view.

[0067] In the present embodiment, as shown in FIG. 6 and the like, in each first conduction member 61, an opening 61h is formed in a rectangular portion connecting each first semiconductor element 10A and the second conductive portion 2B. The opening 61h is preferably formed at the center of the rectangle in a plan view, and is, for example, a through hole penetrating in the z direction. The opening 61h is formed to facilitate the flow of the resin material between the upper side (z2 direction side) and the lower side (z1 direction side) in the vicinity of each first conduction member 61 when injecting a resin material having fluidity to form the sealing resin. The planar shape of the opening 61h may be a perfect circle, or may be other shapes such as an ellipse or a rectangle. The shape of the first conduction member 61 is not limited to this configuration, and for example, the opening 61h may not be formed.

[0068] In the present embodiment, three first conduction members 61 are provided corresponding to the number of the first semiconductor elements 10A. As a modification, one first conduction member 61 common to the plurality of first semiconductor elements 10A may be used regardless of the number of the plurality of first semiconductor elements 10A.

[0069] The second conduction member 62 electrically connects the second main surface electrodes 12 of each second semiconductor element 10B and the input terminals 42 and 43. The second conduction member 62 has a maximum dimension in the x direction of, for example, 25 mm to 40 mm (preferably about 32 mm), and a maximum dimension in the y direction of, for example, 30 mm to 45 mm (preferably about 38 mm). As shown in FIG. 6, the second conduction member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624.

[0070] The first wiring portion 621 is connected to the input terminal 42. The first wiring portion 621 and the input terminal 42 are joined by a conductive bonding material 69. The first wiring portion 621 is a strip-shaped portion extending in the x direction in a plan view.

[0071] The second wiring portion 622 is connected to the input terminal 43. The second wiring portion 622 and the input terminal 43 are joined by a conductive bonding material 69. The second wiring portion 622 is a strip-shaped portion extending in the x direction in plan view. The first wiring portion 621 and the second wiring portion 622 are spaced apart in the y direction and are arranged substantially parallel to each other. The second wiring portion 622 is located in the y1 direction with respect to the first wiring portion 621.

[0072] The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622. The third wiring portion 623 is a strip-shaped portion extending in the y direction in plan view. As can be understood from FIG. 6, the third wiring portion 623 overlaps a plurality of second semiconductor elements 10B in plan view. As shown in FIG. 17, the third wiring portion 623 is connected to each second semiconductor element 10B. The third wiring portion 623 has a plurality of concave regions 623a. As shown in FIG. 17, each concave region 623a of the third wiring portion 623 protrudes in the z1 direction more than other portions of the third wiring portion 623. Each concave region 623a of the third wiring portion 623 is joined to each second semiconductor element 10B. Each concave region 623a of the third wiring portion 623 and the second main surface electrode 12 (see FIG. 8) of each second semiconductor element 10B are joined via a conductive bonding material 69.

[0073] The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622. Further, the fourth wiring portion 624 is connected to the third wiring portion 623. The fourth wiring portion 624 is located on the x2 direction side of the third wiring portion 623. As can be understood from FIG. 6, the fourth wiring portion 624 overlaps a plurality of first semiconductor elements 10A in plan view. The fourth wiring portion 624 includes a first strip portion 625 and a plurality of second strip portions 626.

[0074] The first strip portion 625 is spaced apart from the third wiring portion 623 in the x direction and is a strip-shaped portion in the fourth wiring portion 624 in a plan view. The first strip portion 625 is connected to both the first wiring portion 621 and the second wiring portion 622. The first strip portion 625 overlaps a plurality of first semiconductor elements 10A in a plan view. The first strip portion 625 has a plurality of convex regions 625a. As shown in FIG. 16, each convex region 625a protrudes in the z2 direction more than other portions of the first strip portion 625. As shown in FIG. 6, each convex region 625a overlaps each first semiconductor element 10A in a plan view. Since the first strip portion 625 has a plurality of convex regions 625a, as shown in FIG. 16, a region for bonding each first conduction member 61 is provided on each first semiconductor element 10A. Thereby, contact between the first strip portion 625 and each first conduction member 61 is suppressed.

[0075] Each of the plurality of second strip portions 626 is connected to the first strip portion 625 and the third wiring portion 623. Each second strip portion 626 is strip-shaped and extends in the x direction in a plan view. The plurality of second strip portions 626 are spaced apart in the y direction and are arranged substantially parallel to each other. Each of the plurality of second strip portions 626 has one end connected between two first semiconductor elements 10A adjacent to each other in the y direction of the first strip portion 625 and the other end connected between two second semiconductor elements 10B adjacent to each other in the y direction of the third wiring portion 623 in a plan view.

[0076] The first strip portion 625 has a first edge 627 and a second edge 628. As shown in FIG. 7, the first edge 627 is located in the x1 direction with respect to the first side 191 in a plan view, and extends at least from the third side 193 to the fourth side 194 in the y direction. Thereby, in a plan view, the two corners 171, 172 on the x2-direction side of each first semiconductor element 10A do not overlap with the second conduction member 62, respectively. The two corners are the corner 171 formed by the first side 191 and the third side 193, and the corner 172 formed by the first side 191 and the fourth side 194. Therefore, in each first semiconductor element 10A, in a plan view (specifically, when viewed as shown in FIG. 7. The same applies hereinafter.), a part of each of the two sides sandwiching the corners 171, 172 is visible. The second edge 628 is located in the x2 direction with respect to the second side 192 in a plan view, and extends at least from the third side 193 to 194 in the y direction as shown in FIG. 7. Thereby, in a plan view, the two corners 173, 174 on the x1-direction side of each first semiconductor element 10A do not overlap with the second conduction member 62, respectively. The two corners are the corner 173 formed by the second side 192 and the third side 193, and the corner 174 formed by the second side 192 and the fourth side 194. Therefore, in each first semiconductor element 10A, in a plan view, a part of each of the two sides sandwiching the corners 173, 174 is visible.

[0077] At each of the above-described corners 171, 172, 173, and 174, with respect to the two sides sandwiching each of the corners 171, 172, 173, and 174, it is sufficient that they appear to have a length exceeding 0 μm and equal to or less than 200 μm in a plan view. Further, in a plan view, the length of the visible portion on the two sides sandwiching each of the corners 171, 172, 173, and 174 is preferably 5 μm or more and 150 μm or less respectively. When the length of the visible portion on the two sides sandwiching each of the corners 171, 172, 173, and 174 is 2 μm or more, the corners of the first semiconductor element 10A can be detected. When the length of the visible portion on the two sides is 5 μm or more, the corners of the first semiconductor element 10A can be surely detected. Incidentally, when the length of the visible portion on the two sides exceeds 200 μm, the bonding area between the first conduction member 61 and the first semiconductor element 10A becomes undesirably small. If the upper limit of the length of the visible portion on the two sides is 150 μm or less, it is preferable because it is possible to avoid the bonding area between the first conduction member 61 and the first semiconductor element 10A from becoming too small.

[0078] As shown in FIG. 6, the conduction member 6 (the first conduction member 61 and the second conduction member 62) has a first portion 601. The first portion 601 is a region that overlaps with the semiconductor element 10 (either a plurality of first semiconductor elements 10A or a plurality of second semiconductor elements 10B) in a plan view. In the second conduction member 62, a part of the fourth wiring portion 624 (a region that overlaps with a plurality of first semiconductor elements 10A in a plan view) and a part of the third wiring portion 623 (a region that overlaps with a plurality of second semiconductor elements 10B in a plan view) constitute the first portion 601.

[0079] As shown in FIGS. 6 and 8, the main surface electrodes 11, 13, 14, 16 of the first semiconductor element 10A (the first semiconductor element 10A having the diode function section D1) are arranged side by side along the y direction at the end on the x2 direction side of the first semiconductor element 10A. In a plan view, the first conduction member 61 and the second conduction member 62 do not overlap with any of the main surface electrodes 11, 13, 14, 16 and the corners 171, 172 on the x2 direction side of the first semiconductor element 10A. Also, in a plan view, the first conduction member 61 and the second conduction member 62 do not overlap with at least one of the corners 173, 174 on the x1 direction side (the side opposite to the side where the main surface electrodes are arranged) of the first semiconductor element 10A. Due to these, in a plan view, at least three of the four corners 171, 172, 173, 174 of the semiconductor element 10A are visible. Thus, in a state where the semiconductor element 10A, the first conduction member 61, and the second conduction member 62 are mounted on the conductive substrate 2, it is possible to inspect whether the semiconductor element 10A is correctly mounted by automatic appearance inspection. In a plan view, all of the four corners 171, 172, 173, 174 of the semiconductor element 10A may be visible. Note that the main surface electrodes 11, 13, 14, 16 of the first semiconductor element 10A described above are an example of the "one-side main surface electrodes".

[0080] Note that, as shown in FIG. 6, each of the second semiconductor elements 10B is also rectangular in a plan view, similar to the first semiconductor element 10A, and has four corners 181, 182, 183, 184 corresponding to the four corners 171, 172, 173, 174 of the first semiconductor element 10A. The relationship in a plan view between the four corners 171, 172, 173, 174 of each of the first semiconductor elements 10A described above and the first conduction member 61 and the second conduction member 62 is the same as the relationship in a plan view between the four corners 181, 182, 183, 184 of each of the second semiconductor elements 10B and the second conduction member 62.

[0081] As shown in FIG. 5, the second conduction member 62 includes a first portion 62A and a second portion 62B. The first portion 62A overlaps the main surface 201 of the conductive substrate 2 (the main surface 201 of the first conductive portion 2A or the second conductive portion 2B) in a plan view and does not overlap any of the plurality of semiconductor elements 10 in the plan view. The second portion 62B overlaps the main surface 201 in a plan view and overlaps one of the plurality of semiconductor elements 10 in the plan view. In FIG. 5, the first portion 62A is hatched diagonally upward to the right, and the second portion 62B is hatched diagonally downward to the right. The first portion 62A has an opening 63. The opening 63 is a partially cut-away portion as viewed in a plan view, as shown in FIGS. 5 and 13. In the present embodiment, the opening 63 is located at a position that overlaps the main surface 201 of the first conductive portion 2A (conductive substrate 2) in a plan view and does not overlap the plurality of semiconductor elements 10. The opening 63 is, for example, a through hole penetrating in the z direction. The opening 63 includes one formed in the first wiring portion 621 and one formed in the second wiring portion 622. The opening 63 is provided near at least two of the four corners of the conductive substrate 2 in a plan view. For example, in each of the first wiring portion 621 and the second wiring portion 622, it is provided closer to the x2 direction side. Note that the planar shape of the opening 63 is not limited, and it may be a hole as in the present embodiment, or may be a notch different from the present embodiment. The opening 63 may be formed by, for example, electroforming. In this case, the second conduction member 62 has the opening 63 formed of a portion where metal was not electrodeposited, rather than the opening 63 formed of the removed portion.

[0082] In the second conduction member 62, an opening 625h is formed in a rectangular portion that overlaps each first semiconductor element 10A in a plan view. In the present embodiment, the opening 625h is preferably formed to overlap the central portion of each first semiconductor element 10A in a plan view. The opening 625h is, for example, a through hole formed in each convex region 625a of the first strip portion 625 (fourth wiring portion 624) (see FIG. 6). The opening 625h is used to optically confirm the bonding situation from above when bonding the first conduction member 61 and the first semiconductor element 10A.

[0083] In the second conduction member 62, an opening 623h is formed in a rectangular portion that overlaps each second semiconductor element 10B in a plan view. In the present embodiment, the opening 623h is preferably formed to overlap the central portion of the second semiconductor element 10B in a plan view. The opening 623h is, for example, a through hole formed in each concave region 623a of the third wiring portion 623. The opening 623h is used when positioning the second conduction member 62 with respect to the conductive substrate 2. The planar shapes of the two types of openings 623h and 625h may be a perfect circle, or may be other shapes such as an ellipse or a rectangle.

[0084] The shape of the second conduction member 62 is not limited to this configuration. For example, it may not include the fourth wiring portion 624. However, in order to reduce the inductance value due to the current flowing through the second conduction member 62, it is preferable to provide the fourth wiring portion 624 in the second conduction member 62.

[0085] The first conductive bonding material 71 is interposed between the conductive substrate 2 and the support substrate 3, and electrically connects the conductive substrate 2 and the support substrate 3. The first conductive bonding material 71 includes one that electrically connects the first conductive portion 2A to the first portion 32A and one that electrically connects the second conductive portion 2B to the second portion 32B. As shown in FIG. 15, the first conductive bonding material 71 has a first base layer 711, a first layer 712, and a second layer 713 that are laminated on each other.

[0086] As shown in FIG. 15, it is most preferable that the side surface of the first conductive bonding material 71 and the side surface of the first metal layer 32, which is the uppermost layer of the support substrate 3, are flush. In a plan view, it is preferable that the side surface of the first metal layer 32 is slightly positioned inside the side surface of the first conductive bonding material 71. That is, in a plan view, the side surface of the first metal layer 32 is joined so as not to protrude outside the side surface of the first conductive bonding material 71. When the side surface of the first metal layer 32 protrudes outside the side surface of the first conductive bonding material 71 in a plan view, the creepage distance between the first metal layer 32 and the second metal layer 33 becomes small, which is not preferable. In addition, in a plan view, the side surface of the first metal layer 32 is disposed outside the side surface of the base material 21 included in the conductive substrate 2.

[0087] The first base layer 711 is made of metal, and the metal is, for example, Al or an Al alloy. The first base layer 711 is a sheet material. The Young's modulus of Al (aluminum), which is the constituent material of the first base layer 711, is 70.3 GPa.

[0088] The first layer 712 is formed on the upper surface of the first base layer 711. The first layer 712 is interposed between the first base layer 711 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B). The first layer 712 is, for example, Ag plating. The first layer 712 is joined to each back surface bonding layer 23 of the first conductive portion 2A and the second conductive portion 2B, for example, by solid-phase diffusion of the metal. That is, the first layer 712 and each back surface bonding layer 23 of the first conductive portion 2A and the second conductive portion 2B are joined by solid-phase diffusion bonding. As a result, the first layer 712 and each back surface bonding layer 23 are joined in a state of being in direct contact with each other at the bonding interface. In the present disclosure, "A and B are joined by solid-phase diffusion bonding" means a mode in which, as a result of performing solid-phase diffusion bonding, A and B are fixed to each other in a state of being in direct contact at the bonding interface, and it can be said that a solid-phase diffusion bonding layer is formed by A and B. When solid-phase diffusion bonding is performed under ideal conditions, the bonding interface may not clearly exist due to diffusion of metal elements. On the other hand, when inclusions such as oxide films exist on the surfaces of A and B, or when voids exist between A and B, these inclusions or voids may exist at the bonding interface.

[0089] The second layer 713 is formed on the lower surface of the first base layer 711. The second layer 713 is interposed between the first base layer 711 and the support substrate 3 (each of the first portion 32A and the second portion 32B). The second layer 713 is, for example, Ag plating. The second layer 713 is joined to the first bonding layer 321 formed on each of the first portion 32A and the second portion 32B, for example, by solid-phase diffusion of the metal. That is, the second layer 713 and the first bonding layer 321 are joined by solid-phase diffusion bonding, and are joined in a state of being in direct contact with each other at the bonding interface. The Young's modulus of Ag (silver), which is the constituent material of the first layer 712 and the second layer 713, is 82.7 GPa.

[0090] In the first conductive bonding material 71, since the constituent material of the first base layer 711 and the constituent materials of the first layer 712 and the second layer 713 are as described above, the Young's modulus of the first base layer 711 is smaller than the Young's moduli of the first layer 712 and the second layer 713. The thickness (dimension in the z direction) of the first base layer 711 is larger than the respective thicknesses of the first layer 712 and the second layer 713.

[0091] In the first conductive bonding material 71, no Ag plating is formed on the end face of the first base layer 711 which is Al or an Al alloy, and the end face of the first base layer 711 is exposed. However, Ag plating may be formed on the end face of the first base layer 711. From the viewpoint of reducing the manufacturing cost of the first conductive bonding material 71, it is preferable to manufacture the first conductive bonding material 71 by cutting the Ag-plated sheet material after forming Ag plating on both sides of a large-area sheet material. From this viewpoint, it is preferable that no Ag plating is formed on the end face of the first base layer 711.

[0092] The second conductive bonding material 72 is interposed between the conductive substrate 2 and each semiconductor element 10, and conducts and joins the conductive substrate 2 and each semiconductor element 10. The second conductive bonding material 72 includes those for conductively joining each first semiconductor element 10A to the first conductive portion 2A and those for conductively joining each second semiconductor element 10B to the second conductive portion 2B. As shown in FIG. 15, the second conductive bonding material 72 includes a second base layer 721, a third layer 722, and a fourth layer 723 which are laminated on each other.

[0093] The second base layer 721 is made of metal, and the metal is, for example, Al or an Al alloy. The second base layer 721 is a sheet material.

[0094] The third layer 722 is formed on the upper surface of the second base layer 721. The third layer 722 is interposed between the second base layer 721 and each semiconductor element 10. The third layer 722 is, for example, Ag plating. The third layer 722 is joined to the back electrode 15 of each semiconductor element 10, for example, by solid-phase diffusion of a metal. That is, the third layer 722 and the back electrode 15 are joined by solid-phase diffusion bonding and are joined in a state of being in direct contact with each other at the bonding interface.

[0095] The fourth layer 723 is formed on the lower surface of the second base layer 721. The fourth layer 723 is interposed between the second base layer 721 and the conductive substrate 2 (each of the first conductive portion 2A and the second conductive portion 2B). The fourth layer 723 is, for example, Ag plating. The fourth layer 723 is joined to each main surface bonding layer 22 of the first conductive portion 2A and the second conductive portion 2B, for example, by solid-phase diffusion of a metal. That is, the fourth layer 723 and each main surface bonding layer 22 are joined by solid-phase diffusion bonding and are joined in a state of being in direct contact with each other at the bonding interface.

[0096] In the second conductive bonding material 72, since the constituent material of the second base layer 721 and the constituent materials of the third layer 722 and the fourth layer 723 are as described above, the Young's modulus of the second base layer 721 is smaller than the Young's moduli of the third layer 722 and the fourth layer 723. The thickness (dimension in the z direction) of the second base layer 721 is larger than the respective thicknesses of the third layer 722 and the fourth layer 723.

[0097] In the second conductive bonding material 72, Ag plating is not formed on the end face of the second base layer 721 which is Al or an Al alloy, and the end face of the second base layer 721 is exposed. However, Ag plating may be formed on the end face of the second base layer 721. From the viewpoint of reducing the manufacturing cost of the second conductive bonding material 72, it is preferable to manufacture the second conductive bonding material 72 by forming Ag plating on both sides of a large-area sheet material and then cutting the Ag-plated sheet material. From this viewpoint, it is preferable that Ag plating is not formed on the end face of the second base layer 721.

[0098] The plurality of wires 731 to 735 each conduct between two spaced-apart parts. The plurality of wires 731 to 735 are each, for example, bonding wires. Each constituent material of the plurality of wires 731 to 735 contains, for example, any one of Au (gold), Al, or Cu.

[0099] As shown in FIG. 8, each of the plurality of wires 731 is joined to the first main surface electrode 11 (gate electrode) of each semiconductor element 10 and the first part 521 (first metal layer 52) of each control terminal support 5 to conduct between them. As shown in FIG. 8, the plurality of wires 731 include a plurality of first wires 731a and a plurality of second wires 731b. Each of the plurality of first wires 731a is connected to the first main surface electrode 11 (gate electrode) of each first semiconductor element 10A and the first part 521 (first metal layer 52) of the first support part 5A. Thereby, the first control terminal 46A is conducted to the first main surface electrode 11 (gate electrode) of each first semiconductor element 10A via each first wire 731a. Each of the plurality of second wires 731b is connected to the first main surface electrode 11 (gate electrode) of each second semiconductor element 10B and the first part 521 (first metal layer 52) of the second support part 5B. Thereby, the second control terminal 47A is conducted to the first main surface electrode 11 (gate electrode) of each second semiconductor element 10B via each second wire 731b.

[0100] As shown in FIG. 8, each of the plurality of wires 732 is joined to the second main surface electrode 12 (source electrode) of each semiconductor element 10 and the second part 522 (first metal layer 52) of each control terminal support 5 to conduct between them. However, in each semiconductor element 10 having the diode function part D1, each wire 732 is joined to the fifth main surface electrode 16 (source sense electrode) instead of the second main surface electrode 12 (source electrode).

[0101] As shown in FIG. 8, each of the plurality of wires 733 is joined to the third main surface electrode 13 of each semiconductor element 10 having the diode function part D1 and the third part 523 (first metal layer 52) of each control terminal support 5 to conduct between them.

[0102] As shown in FIG. 8, each of the plurality of wires 734 is joined to the fourth main surface electrode 14 of each semiconductor element 10 having a diode function section D1 and the fourth section 524 (first metal layer 52) of each control terminal support 5 to electrically connect them.

[0103] As shown in FIG. 8, the wire 735 is joined to the main surface 201 of the first conductive section 2A (conductive substrate 2) and the fifth section 525 (first metal layer 52) of the first support section 5A (control terminal support 5) to electrically connect them.

[0104] The encapsulating resin 8 covers the plurality of semiconductor elements 10, the conductive substrate 2, the support substrate 3 (excluding the bottom surface 302), parts of the plurality of input terminals 41 to 43, parts of the plurality of output terminals 44, parts of the plurality of control terminals 45, the control terminal support 5, the conductive member 6, and the plurality of wires 731 to 735, respectively. The encapsulating resin 8 is made of, for example, a black epoxy resin. The encapsulating resin 8 is formed, for example, by the molding process described later. The encapsulating resin 8 has, for example, a dimension in the x direction of about 35 mm to 60 mm, a dimension in the y direction of about 35 mm to 50 mm, and a dimension in the z direction of about 4 mm to 15 mm. These dimensions are the sizes of the largest portions along each direction. The encapsulating resin 8 has a resin main surface 81, a resin back surface 82, and a plurality of resin side surfaces 831 to 834.

[0105] The resin front surface 81 and the resin back surface 82 are spaced apart in the z direction as shown in FIGS. 9, 11, and 12. The resin front surface 81 faces the z2 direction, and the resin back surface 82 faces the z1 direction. A plurality of control terminals 45 (a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D) protrude from the resin front surface 81. The resin back surface 82 is in a frame shape surrounding the bottom surface 302 (the lower surface of the second metal layer 33) of the support substrate 3 in a plan view as shown in FIG. 10. The bottom surface 302 of the support substrate 3 is exposed from the resin back surface 82 and is flush with the resin back surface 82, for example. The plurality of resin side surfaces 831 to 834 are each connected to both the resin front surface 81 and the resin back surface 82 and are sandwiched therebetween in the z direction. As shown in FIG. 4, etc., the resin side surface 831 and the resin side surface 832 are spaced apart in the x direction. The resin side surface 831 faces the x1 direction, and the resin side surface 832 faces the x2 direction. Two output terminals 44 protrude from the resin side surface 831, and three input terminals 41 to 43 protrude from the resin side surface 832. As shown in FIG. 4, etc., the resin side surface 833 and the resin side surface 834 are spaced apart in the y direction. The resin side surface 833 faces the y1 direction, and the resin side surface 834 faces the y2 direction.

[0106] As shown in FIG. 4, a plurality of recesses 832a are formed in the resin side surface 832. Each recess 832a is a portion recessed in the x direction in a plan view. The plurality of recesses 832a include those formed between the input terminal 41 and the input terminal 42 and those formed between the input terminal 41 and the input terminal 43 in a plan view. The plurality of recesses 832a are provided to increase the creepage distance along the resin side surface 832 between the input terminal 41 and the input terminal 42 and the creepage distance along the resin side surface 832 between the input terminal 41 and the input terminal 43.

[0107] As shown in FIGS. 13 and 14, etc., the encapsulating resin 8 has a plurality of first protrusions 851, a plurality of second protrusions 852, and a resin void portion 86.

[0108] The plurality of first protrusions 851 each protrude in the z direction from the resin main surface 81. The plurality of first protrusions 851 are arranged near the four corners of the sealing resin 8 in a plan view. At the tip (end portion in the z2 direction) of each first protrusion 851, a first protrusion end surface 851a is formed. Each first protrusion end surface 851a among the plurality of first protrusions 851 is substantially parallel to the resin main surface 81 and lies on the same plane (x-y plane). Each first protrusion 851 is, for example, in the shape of a frustum of a cone with a bottom. The plurality of first protrusions 851 are used as spacers when the semiconductor module A1 is mounted on a control circuit board or the like of a device that utilizes the power generated by the semiconductor module A1. The plurality of first protrusions 851 each have a recess 851b and an inner wall surface 851c formed in the recess 851b. The shape of each first protrusion 851 may be columnar, and preferably cylindrical. The shape of the recess 851b is cylindrical, and in a plan view, the inner wall surface 851c is preferably a single perfect circle. Each first protrusion 851 is an example of a "protrusion", and each first protrusion end surface 851a is an example of a "protrusion end surface".

[0109] The semiconductor module A1 may be mechanically fixed to a control circuit board or the like by a method such as screwing. In this case, screw threads of a screw can be formed on the inner wall surface 851c of the recess 851b in the plurality of first protrusions 851. An insert nut may be embedded in the recess 851b in the plurality of first protrusions 851.

[0110] As shown in FIG. 14 and the like, the plurality of second protrusions 852 protrude in the z direction from the resin main surface 81. The plurality of second protrusions 852 overlap the plurality of control terminals 45 in a plan view. Each metal pin 452 of the plurality of control terminals 45 protrudes from each second protrusion 852. A part of the holder 451 (the upper surface of the upper flange portion) is exposed from the upper end surface of each second protrusion 852. Each second protrusion 852 is in the shape of a frustum of a cone. A resin portion 87 is arranged on each second protrusion 852.

[0111] As shown in FIG. 13, the resin void portion 86 communicates with the recess 201a formed on the main surface 201 of the conductive substrate 2 from the resin main surface 81 in the z direction. The resin void portion 86 is formed in a tapered shape with a decreasing cross-sectional area in the z direction from the resin main surface 81 toward the recess 201a. The resin void portion edge 861 in contact with the main surface 201 in the resin void portion 86 and the recess edge 201b in contact with the main surface 201 in the recess 201a coincide with each other. The resin void portion 86 is formed during the mold forming process described later and is a portion where the sealing resin 8 is not formed during the mold forming process.

[0112] The resin portion 87 is provided on the second protruding portion 852 of the sealing resin 8. The resin portion 87 covers a part (the upper surface of the upper flange portion) of the holder 451 exposed from the sealing resin 8 and a part of the metal pin 452 at each control terminal 45. The resin portion 87 is made of, for example, an epoxy resin like the sealing resin 8, but may be made of a material different from the sealing resin 8.

[0113] The resin filling portion 88 is filled in the resin void portion 86 so as to fill the resin void portion 86. The resin filling portion 88 is made of, for example, an epoxy resin like the sealing resin 8, but may be made of a material different from the sealing resin 8.

[0114] Next, a method for manufacturing the semiconductor module A1 will be described with reference to FIGS. 21 to 29. FIG. 21 is a plan view showing a step of the method for manufacturing the semiconductor module A1. FIG. 22 is a schematic cross-sectional view showing a step of the method for manufacturing the semiconductor module A1. FIG. 23 is a plan view showing a step of the method for manufacturing the semiconductor module A1. FIG. 24 is an end face view of a cut portion showing a step of the method for manufacturing the semiconductor module A1. FIG. 24 corresponds to the cross section shown in FIG. 13. FIGS. 25 and 28 are enlarged cross-sectional views of main parts showing a step of the method for manufacturing the semiconductor module A1, and correspond to enlarged views of a part of the cross section shown in FIG. 13. FIGS. 26, 27, and 29 are enlarged cross-sectional views of main parts showing a step of the method for manufacturing the semiconductor module A1, and correspond to enlarged views of a part of the cross section shown in FIG. 14.

[0115] First, prepare a plurality of semiconductor elements 10, a conductive substrate 2, a support substrate 3, a plurality of input terminals 41 to 43, and a plurality of output terminals 44. The configurations of the plurality of semiconductor elements 10, the conductive substrate 2, and the support substrate 3 are as described above. At the stage of preparing these, the plurality of semiconductor elements 10, the conductive substrate 2, and the support substrate 3 are each prepared individually and not joined to each other. Also, as shown in FIG. 21, the conductive substrate 2, the plurality of input terminals 41 to 43, and the plurality of output terminals 44 are connected to each other and are, for example, composed of the same lead frame. Further, as shown in FIG. 21, no recess 201a is formed on the main surface 201 of the conductive substrate 2.

[0116] Next, as shown in FIG. 22, place the conductive substrate 2 on the support substrate 3 with the first conductive bonding material 71 interposed therebetween, and place each semiconductor element 10 on the conductive substrate 2 with the second conductive bonding material 72 interposed therebetween. Then, while sandwiching the lower surface of the support substrate 3 and the upper surface of each semiconductor element 10 (refer to the thick arrow in FIG. 22), heat is applied to join each semiconductor element 10 and the conductive substrate 2 by solid-phase diffusion and to join the conductive substrate 2 and the support substrate 3 by solid-phase diffusion. Specifically, the first bonding layer 321 (support substrate 3) on the first metal layer 32 and the second layer 713 (first conductive bonding material 71), the first layer 712 (first conductive bonding material 71) and the back surface bonding layer 23 (conductive substrate 2), the fourth layer 723 (second conductive bonding material 72) and the main surface bonding layer 22 (conductive substrate 2), and the third layer 722 (second conductive bonding material 72) and the back surface electrode 15 of each semiconductor element 10 are joined to each other by solid-phase diffusion all at once. In the conditions of solid-phase diffusion, the heating temperature during bonding may be in the range of 200°C or higher and 350°C or lower, and the pressure applied during bonding (the clamping force) may be in the range of 1 MPa or higher and 100 MPa or lower. Solid-phase diffusion is assumed to be performed in the atmosphere, but it may also be performed in a vacuum. As a result, the conductive substrate 2 is joined to the support substrate 3 via the first conductive bonding material 71, and each semiconductor element 10 is joined to the conductive substrate 2 via the second conductive bonding material 72. Note that the joining of the conductive substrate 2 and the support substrate 3 and the joining of the conductive substrate 2 and each semiconductor element 10 may be processed separately instead of all at once. However, processing all at once is preferable in terms of improving manufacturing efficiency.

[0117] When placing each semiconductor element 10 on the conductive substrate 2 with the second conductive bonding material 72 interposed therebetween, as shown in FIGS. 16 and 17, individual second conductive bonding materials 72 corresponding to each semiconductor element 10 are arranged. Not limited thereto, one second conductive bonding material 72 corresponding in common to the three semiconductor elements 10 shown in FIG. 16 may be arranged.

[0118] Next, as shown in FIG. 23, the bonding of the control terminal support 5, the bonding of each holder 451 of the plurality of control terminals 45, the wire bonding of the plurality of wires 731 to 735, the bonding of the plurality of first conduction members 61, and the bonding of the second conduction member 62 are performed. Note that the order of these processes is not limited.

[0119] Next, the encapsulation resin 8 is formed. The formation of the encapsulation resin 8 is, for example, by mold molding. As shown in FIG. 24, the mold 91 used in the mold molding is provided with a pressing pin 911 as a pressing member. The tip of the pressing pin 911 is in contact with the main surface 201 of the conductive substrate 2. At this time, a recess 201a is formed in the main surface 201 due to the pressing force applied to the main surface 201 by the pressing pin 911. The degree of depression (depth) of the recess 201a varies depending on the magnitude of the pressing force and the like. Further, the pressing pin 911 in contact with the main surface 201 in the first conductive portion 2A is inserted through the opening 63 of the second conductive member 62. Then, a fluid resin material is injected into the cavity space 919 of the mold 91 sequentially via a resin flow path and a resin injection port (both not shown). The encapsulation resin 8 is formed by the solidification of the injected fluid resin material. The formed encapsulation resin 8 has the first protrusion 851, the second protrusion 852, and the resin void portion 86 as shown in FIGS. 25 and 26. As shown in FIG. 25, the resin void portion edge 861 in contact with the main surface 201 in the resin void portion 86 and the recess edge 201b in contact with the main surface 201 in the recess 201a coincide with each other. As shown in FIG. 26, the upper surface of the holder 451 is exposed from the second protrusion 852 and is flush with the upper surface of the second protrusion 852. Further, as understood from FIGS. 24 and 25, the resin void portion 86 is formed because the fluid resin material was not filled by the pressing pin 911. Note that the pressing pin 911 may be a movable pin. In this case, the pressing pin 911 is preferably provided in a hole formed in the mold 91 and is elastically supported. Not limited to a pin-shaped pressing member, a block-shaped pressing member may be used.

[0120] Next, the mold 91 is opened, and a molded body including a lead frame containing the conductive substrate 2 and the sealing resin 8 is taken out. Thereafter, the sealing resin 8 is separated from the resin solidified at the resin flow path and the resin injection port. In this step, resin separation marks are formed at any of the following positions on the resin side surface 831 on the x1-direction side of the sealing resin 8. The first position is at least one of two positions close to both ends in the y direction on the resin side surface 831 shown in FIG. 1, or at least one of the corner portions at both ends. When resin separation marks are formed at the corner portions at both ends, resin separation marks are formed on the surface formed at the corner portion (the chamfered portion in a plan view, the C surface). The inclined surface described above is included in the resin side surface 831 on the x1-direction side of the sealing resin 8. The second position is between the two output terminals 44 on the resin side surface 831 shown in FIG. 1. These resin separation marks correspond to the position of the resin injection port of the mold 91 and are formed by separating the sealing resin 8 from the resin solidified at the resin injection port. In order to suppress the bias of the resin intrusion, it is preferable to inject the resin from the central position in the y direction. In this case, resin separation marks are formed between the two output terminals 44.

[0121] Next, as shown in FIG. 27, each metal pin 452 of the plurality of control terminals 45 is press-fitted into each holder 451. Specifically, each metal pin 452 having a cross-sectional dimension slightly larger than the inner diameter of the cylindrical portion (see FIG. 26) of each holder 451 is inserted while applying an insertion pressure. Thereby, each holder 451 and each metal pin 452 are mechanically fixed and electrically connected. Each holder 451 and each metal pin 452 may be electrically connected using, for example, solder. Thereafter, as shown in FIGS. 28 and 29, a resin portion 87 and a resin filling portion 88 are formed. The formation of the resin portion 87 and the resin filling portion 88 is performed, for example, by potting.

[0122] Next, by appropriately cutting the lead frame, a plurality of input terminals 41 to 43 and output terminal 44 are separated. In the input terminals 41 to 43 and output terminal 44 shown in FIG. 21, the vicinity of the connection portion between each terminal and the outer frame portion of the lead frame (the portion indicated by the broken line in FIG. 21) may be cut using a mold or the like. Here, tip surfaces 413, 423, and 433 as input-side processing marks are respectively formed on the input terminals 41 to 43. A tip surface 443 as an output-side processing mark is formed on the output terminal 44. When the lead frame has tie bars connecting adjacent terminals in the y direction in the y direction, the tie bars may be cut using a mold or the like. In this case, processing marks are formed on two side surfaces facing the y direction at each terminal. Through the above steps, the semiconductor module A1 shown in FIGS. 1 to 20 is manufactured.

[0123] The semiconductor module A1 is mounted on a control circuit board or the like. Here, each metal pin 452 is inserted into a pin hole of the circuit board on which the semiconductor module A1 is mounted and connected to a terminal around the pin hole. The input terminals 41, 42, and 43 each have input-side bonding surfaces 411, 421, and 431 facing one side in the z direction (z2 direction). Each output terminal 44 has an output-side bonding surface 441 facing one side in the z direction (z2 direction side). The input-side bonding surfaces 411, 421, and 431 and the output-side bonding surface 441 are connected to the terminals of the circuit board on which the semiconductor module A1 is mounted using, for example, solder.

[0124] In the semiconductor module A1 of the present embodiment, the current path from the input terminal 41 to the output terminal 44 will be described below. A first main circuit current flows through the path of the input terminal 41, the first conductive portion 2A, each first semiconductor element 10A, the first conduction member 61, the second conductive portion 2B, and each output terminal 44. A first main circuit current flows along the x direction via each first conduction member 61 between the second main surface electrode 12 of each first semiconductor element 10A and the second conductive portion 2B. In the second conductive portion 2B, a first main circuit current flows along the x direction and a direction slightly inclined from the x direction between the portion where each first conduction member 61 is joined and each output terminal 44.

[0125] The current path from the output terminal 44 to the input terminal 42 and the input terminal 43 will be described below. The second main circuit current flows through the path of the output terminal 44, the second conductive part 2B, each second semiconductor element 10B, the second conduction member 62, the input terminal 42, and the input terminal 43. The path of the second main circuit current is provided by the second conduction member 62, and the second main circuit current flows through both the third wiring part 623 extending in the y direction and the first wiring part 621 and the second wiring part 622 connected to both ends of the third wiring part 623 and extending in the x2 direction. Further, the second main circuit current flows through the two second strip parts 626 arranged between the first wiring part 621 and the second wiring part 622 and extending in the x direction, and the first strip part 625 arranged between the first wiring part 621 and the second wiring part 622 and extending in the y direction, and then flows into the first wiring part 621 and the second wiring part 622.

[0126] Between the input terminal 42 and the input terminal 43 and the second main surface electrode 12 of each second semiconductor element 10B, the second main circuit current flows through the first wiring part 621, the second wiring part 622, the third wiring part 623, the two second strip parts 626, and the first strip part 625 included in each second conduction member 62. In the first wiring part 621, the second wiring part 622, and the two second strip parts 626, the second main circuit current flows along the x direction. The direction in which the first main circuit current flows is opposite to the direction in which the second main circuit current flows.

[0127] The direction in which the first main circuit current flows in the first conduction member 61 and the direction in which the second main circuit current flows in the first wiring part 621, the second wiring part 622, and the two second strip parts 626 included in the second conduction member 62 are both in the x direction.

[0128] The operation and effects of the semiconductor module A1 are as follows.

[0129] The semiconductor module A1 includes a conductive substrate 2, a plurality of input terminals 41 to 43, an output terminal 44, and a conduction member 6. The conductive substrate 2 includes a first conductive portion 2A to which a plurality of first semiconductor elements 10A are joined and a second conductive portion 2B to which a plurality of second semiconductor elements 10B are joined. The input terminal 41 is connected to the first conductive portion 2A and is electrically connected to the plurality of first semiconductor elements 10A through the first conductive portion 2A. The input terminal 42 and the input terminal 43 are electrically connected to the plurality of second semiconductor elements 10B through a second conduction member 62 (conduction member 6). The output terminal 44 is connected to the second conductive portion 2B and is electrically connected to the plurality of second semiconductor elements 10B through the second conductive portion 2B. The conduction member 6 includes a first conduction member 61 that conducts each first semiconductor element 10A and the second conductive portion 2B, and a second conduction member 62 that conducts each second semiconductor element 10B and each input terminal 42, 43. The plurality of input terminals 41 to 43 are arranged on the x2 direction side with respect to the conductive substrate 2, and the output terminal 44 is arranged in the x1 direction with respect to the conductive substrate 2. And the two input terminals 42, 43 are arranged on opposite sides in the y direction with the input terminal 41 interposed therebetween. In a semiconductor module having a configuration different from that of the semiconductor module A1, when the input terminal 43 is not provided and the input terminal 41 and the input terminal 42 are arranged side by side in the y direction, variations occur in the current path flowing from the input terminal 41 to the output terminal 44 through each first semiconductor element 10A, and variations may occur in the current path flowing from the output terminal 44 to each input terminal 42 through each second semiconductor element 10B. Therefore, the semiconductor module A1 is provided with two input terminals 42, 43, and by sandwiching the input terminal 41 with the two input terminals 42, 43, it is possible to reduce variations in the current path flowing from the input terminal 41 to the output terminal 44 through each first semiconductor element 10A, and to reduce variations in the current path flowing from the output terminal 44 to each of the input terminals 42, 43 through each second semiconductor element 10B. Thereby, the parasitic inductance component of the semiconductor module A1 can be reduced. That is, the semiconductor module A1 has a preferable package structure in reducing the parasitic inductance component.

[0130] In the semiconductor module A1, the upper arm current path and the lower arm current path overlap in a plan view. The upper arm current path is the path of the current flowing from the input terminal 41 through the first conductive part 2A, each first semiconductor element 10A, each first conduction member 61, and the second conductive part 2B to each output terminal 44. In the present embodiment, as understood from FIG. 5, it extends along the x1 direction side from the x2 direction side. The lower arm current path is the path of the current flowing from the output terminal 44 through each second semiconductor element 10B and the second conduction member 62 to the input terminal 42. In the present embodiment, as understood from FIG. 5, it extends along the x2 direction side from the x1 direction side. According to this configuration, since the magnetic field generated by the current along the upper arm current path and the magnetic field generated by the current along the lower arm current path cancel each other out, the parasitic inductance component can be reduced. In particular, in the semiconductor module A1, by forming the conduction member 6 (each of the plurality of first conduction members 61 and the second conduction member 62) of a metal plate material, an appropriate region where the upper arm current path and the lower arm current path overlap in a plan view can be ensured. That is, the semiconductor module A1 has a preferable package structure for reducing the parasitic inductance component.

[0131] In the semiconductor module A1, the second conduction member 62 that constitutes the lower arm current path includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to input terminals 42 and 43 that are arranged on opposite sides in the y direction with the input terminal 41 interposed therebetween, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622 and extends in the y direction, and is connected to each of the plurality of second semiconductor elements 10B. The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622, and overlaps the plurality of first semiconductor elements 10A in a plan view. The second conduction member 62 configured to include the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624 is arranged to be spaced apart from the main surface 201 (conductive substrate 2) in the z direction, and overlaps a wide range of the main surface 201 in a plan view. According to such a configuration, the variation in the current path flowing from the output terminal 44 to the input terminals 42 and 43 via each second semiconductor element 10B is appropriately reduced, which is suitable for reducing the parasitic inductance component.

[0132] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B overlap each other when viewed in the x direction. According to such a configuration, it is possible to suppress an increase in the dimension of the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B) in the y direction in which the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are arranged, and it is possible to reduce the size of the semiconductor module A1.

[0133] The fourth wiring portion 624 of the second conduction member 62 has a first strip portion 625 and a plurality of second strip portions 626. The first strip portion 625 is connected to both the first wiring portion 621 and the second wiring portion 622 and extends in the y direction, and is a portion that overlaps with a plurality of first semiconductor elements 10A in a plan view. Each of the plurality of second strip portions 626 is connected to the first strip portion 625 and the third wiring portion 623, and is strip-shaped and extends in the x direction in a plan view. The plurality of second strip portions 626 are spaced apart in the y direction and are arranged substantially parallel to each other. Each of the plurality of second strip portions 626 has one end connected between two adjacent first semiconductor elements 10A in the y direction of the first strip portion 625 and the other end connected between two adjacent second semiconductor elements 10B in the y direction of the third wiring portion 623 in a plan view. According to such a configuration, it is possible to ensure a larger size of the fourth wiring portion 624 (second conduction member 62) in a plan view. This is more preferable for reducing the parasitic inductance component.

[0134] The first strip portion 625 has a plurality of convex regions 625a that protrude in the z2 direction more than other portions. Each convex region 625a overlaps with each first semiconductor element 10A in a plan view. According to the configuration in which the first strip portion 625 has a plurality of convex regions 625a, it is possible to avoid the first strip portion 625 from improperly contacting the first conduction member 61 joined on the first semiconductor element 10A.

[0135] The third wiring portion 623 has a plurality of concave regions 623a that protrude in the z1 direction more than other portions. Each concave region 623a is joined to any one of the plurality of second semiconductor elements 10B. According to such a configuration, it is possible to ensure a larger size of the third wiring portion 623 (second conduction member 62) in a plan view while appropriately conducting the third wiring portion 623 (second conduction member 62) and the plurality of second semiconductor elements 10B.

[0136] In the semiconductor module A1, in addition to including the conduction member 6 (the first conduction member 61 and the second conduction member 62) having the above configuration, a plurality of first control terminals 46A to 46E and a plurality of second control terminals 47A to 47D for controlling the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are provided. The plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D are each arranged to extend along the z direction on the main surface 201 of the conductive substrate 2. The semiconductor module A1 having such a configuration is suitable for achieving miniaturization in a plan view while reducing the parasitic inductance component because it can be miniaturized in a plan view.

[0137] The plurality of first control terminals 46A to 46E are supported by the first conductive portion 2A and are arranged on the x2 direction side of the plurality of first semiconductor elements 10A. The plurality of second control terminals 47A to 47D are supported by the second conductive portion 2B and are arranged on the x1 direction side of the plurality of second semiconductor elements 10B. The plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D are each arranged at intervals in the y direction. Thereby, the plurality of first control terminals 46A to 46E and the plurality of second control terminals 47A to 47D are appropriately arranged in regions corresponding to the plurality of first semiconductor elements 10A constituting the upper arm circuit and the plurality of second semiconductor elements 10B constituting the lower arm circuit, respectively. The semiconductor module A1 having such a configuration is more preferable in achieving miniaturization while reducing the parasitic inductance component.

[0138] The first semiconductor element 10A and the second semiconductor element 10B each have a first main surface electrode 11 (gate electrode) facing in the z2 direction. The first control terminal 46A is connected to the first main surface electrode 11 (gate electrode) of each first semiconductor element 10A via each first wire 731a. The second control terminal 47A is connected to the first main surface electrode 11 (gate electrode) of each second semiconductor element 10B via each second wire 731b. Thus, a drive signal for driving the first semiconductor element 10A (second semiconductor element 10B) having a switching function can be appropriately input to the first main surface electrode 11 via the first control terminal 46A (second control terminal 47A) and the first wire 731a (second wire 731b).

[0139] When the semiconductor module A1 is mounted on the circuit board, each metal pin 452 is inserted into a pin hole of the circuit board on which the semiconductor module A1 is mounted and connected to a terminal around the pin hole. The input terminals 41, 42, 43 each have input-side bonding surfaces 411, 421, 431 facing one side in the z direction (z2 direction). Each output terminal 44 has an output-side bonding surface 441 facing one side in the z direction (z2 direction side). The input-side bonding surfaces 411, 421, 431 and the output-side bonding surface 441 are connected to the terminals of the circuit board on which the semiconductor module A1 is mounted, for example, using solder. With the above-described configuration, the power system circuit board to which the input terminals 41 to 43 and the output terminal 44 are connected and the control system circuit board to which each metal pin 452 is connected can be arranged separately in the z direction. As a result, first, the degree of freedom regarding the arrangement of the signal terminals in the semiconductor module A1 is improved. Second, the degree of freedom regarding the routing and the length of the signal wiring in the semiconductor module A1 is improved. Third, when using the semiconductor module A1, the degree of freedom regarding the arrangement of the circuit board by the user is improved.

[0140] In the semiconductor module A1, each control terminal 45 protrudes from the resin main surface 81 and extends along the z direction. In a configuration different from that of the semiconductor module A1, each control terminal 45 may be arranged to extend along a plane (x-y plane) orthogonal to the z direction. In this configuration, there is a limit to miniaturization in plan view. Therefore, by arranging each control terminal 45 to extend along the z direction as in the semiconductor module A1, miniaturization of the semiconductor module A1 in plan view is possible. That is, the semiconductor module A1 has a preferable package structure for achieving miniaturization in plan view.

[0141] In the semiconductor module A1 of the present embodiment, a control terminal support 5 is interposed between each control terminal 45 and the main surface 201 (conductive substrate 2). The control terminal support 5 has an insulating layer 51, and each control terminal 45 is supported by the conductive substrate 2 via the control terminal support 5. According to such a configuration including the control terminal support 5, it is possible to appropriately support the control terminal 45 on the conductive substrate 2 while ensuring insulation from the conductive substrate 2.

[0142] The control terminal support 5 is a laminated structure having an insulating layer 51, a first metal layer 52, and a second metal layer 53 laminated on each other. The control terminal 45 is joined to the first metal layer 52 formed on the upper surface of the control terminal support 5 via a conductive bonding material 459. According to such a configuration, while using a ready-made laminated structure (such as a DBC substrate, etc.) as the control terminal support 5, it is possible to conductively join the control terminal 45 to the control terminal support 5 (first metal layer 52).

[0143] The semiconductor element 10 has an element main surface 101 facing the z2 direction and an element back surface 102 facing the z1 direction. A first main surface electrode 11 (gate electrode) is arranged on the element main surface 101. The first main surface electrode 11 of each semiconductor element 10 and the first metal layer 52 (first part 521) are connected by a conductive wire 731. Thereby, a drive signal for driving the semiconductor element 10 having a switching function can be appropriately input to the first main surface electrode 11 via the control terminal 45, the first metal layer 52, and the wire 731.

[0144] Each control terminal 45 includes a holder 451 and a metal pin 452. The holder 451 is made of a conductive material and includes a cylindrical portion. The metal pin 452 is a rod-shaped member extending in the z direction and is press-fitted into the holder 451. Also, a part of the holder 451 (the upper surface of the upper flange portion) is exposed from the sealing resin 8. According to such a configuration, by forming the sealing resin 8 (mold molding), the holder 451 is covered with the sealing resin 8 except for a part thereof (the upper end surface), and the upper end surface of the holder 451 is exposed from the sealing resin 8. Thereby, it is possible to insert the metal pin 452 into the holder 451 after forming the sealing resin 8. Therefore, according to the configuration in which the control terminal 45 includes the above-described holder 451 and metal pin 452, it is possible to avoid the mold 91 used in mold molding from becoming complicated, and it is suitable for efficiently manufacturing the semiconductor module A1.

[0145] The semiconductor module A1 of the present embodiment includes a resin portion 87 joined to the sealing resin 8. The resin portion 87 covers a part of the holder 451 exposed from the sealing resin 8 (the upper surface of the upper flange portion) and a part of the metal pin 452. According to such a configuration, it is possible to prevent foreign matter from entering the connection portion between the holder 451 and the metal pin 452. The semiconductor module A1 having the above configuration is preferable in terms of durability and reliability.

[0146] The sealing resin 8 has a plurality of second protruding portions 852 protruding from the resin main surface 81. The plurality of second protruding portions 852 surround the plurality of control terminals 45 in a plan view. Each metal pin 452 of the plurality of control terminals 45 protrudes from each second protruding portion 852. The resin portion 87 is disposed on each second protruding portion 852. According to such a configuration, it is possible to increase the creepage distance along the resin main surface 81 between adjacent control terminals 45. This is preferable for increasing the withstand voltage between adjacent control terminals 45.

[0147] The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B that are spaced apart from each other in the x direction. The first conductive portion 2A is located in the x2 direction with respect to the second conductive portion 2B. The plurality of semiconductor elements 10 include a first semiconductor element 10A joined to the first conductive portion 2A and a second semiconductor element 10B joined to the second conductive portion 2B. The plurality of control terminals 45 include first control terminals 46A to 46E and second control terminals 47A to 47D. The first control terminals 46A to 46E are supported by the first conductive portion 2A and are located between the first semiconductor element 10A and the input terminals 41, 42, etc. in the x direction. The second control terminals 47A to 47D are located between the second semiconductor element 10B and the output terminal 44 in the x direction. According to such a configuration, the plurality of control terminals 45 (the first control terminals 46A to 46E and the second control terminals 47A to 47D) are appropriately arranged in regions corresponding to the first semiconductor element 10A constituting the upper arm circuit and the second semiconductor element 10B constituting the lower arm circuit, respectively. Such a configuration is more preferable for miniaturizing the semiconductor module A1.

[0148] The encapsulating resin 8 has a plurality of first protruding portions 851 protruding from the resin main surface 81. A first protruding end surface 851a is formed at the tip of each first protruding portion 851. Each first protruding end surface 851a of the plurality of first protruding portions 851 is substantially parallel to the resin main surface 81 and lies on the same plane (x-y plane). According to such a configuration, in a device that uses the power generated by the semiconductor module A1, a predetermined gap can be ensured between the surface of the control circuit board on which the semiconductor module A1 is mounted and the resin main surface 81. Thereby, even when various functional components are mounted on the surface of the control circuit board facing the semiconductor module A1, the functional components are prevented from coming into improper contact with the encapsulating resin 8.

[0149] In semiconductor module A1, a conductive substrate 2 to which each semiconductor element 10 is joined is provided. According to this configuration, heat generated by energizing each semiconductor element 10 is transmitted to the conductive substrate 2, and the heat transmitted from each semiconductor element 10 in the conductive substrate 2 is diffused. Therefore, the semiconductor module A1 forms a preferable package structure for improving the heat dissipation property of each semiconductor element 10.

[0150] In semiconductor module A1, the conductive substrate 2 and the support substrate 3 are joined via a first conductive joining material 71. The first conductive joining material 71 includes a first layer 712 and a second layer 713. The first layer 712 is joined to the conductive substrate 2 by solid-phase diffusion of a metal and is joined in a state of being in direct contact with each other at the joining interface. The second layer 713 is joined to the support substrate 3 by solid-phase diffusion of a metal and is joined in a state of being in direct contact with each other at the joining interface. According to this configuration, the joining strength between the conductive substrate 2 and the support substrate 3 can be increased as compared with the case where they are joined by a joining material such as solder. Therefore, the semiconductor module A1 forms a preferable package structure for suppressing the peeling between the conductive substrate 2 and the support substrate 3.

[0151] In semiconductor module A1, each semiconductor element 10 and the conductive substrate 2 are joined via a second conductive joining material 72. The second conductive joining material 72 includes a third layer 722 and a fourth layer 723. The third layer 722 is joined to each semiconductor element 10 (back surface electrode 15) by solid-phase diffusion of a metal and is joined in a state of being in direct contact with each other at the joining interface. The fourth layer 723 is joined to the conductive substrate 2 by solid-phase diffusion of a metal and is joined in a state of being in direct contact with each other at the joining interface. According to this configuration, the joining strength between each semiconductor element 10 and the conductive substrate 2 can be increased as compared with the case where they are joined by a joining material such as solder. Therefore, the semiconductor module A1 forms a preferable package structure for suppressing the peeling between each semiconductor element 10 and the conductive substrate 2.

[0152] In the semiconductor module A1 of the present embodiment, the Young's modulus of the first base layer 711 in the first conductive bonding material 71 is smaller than the Young's modulus of the constituent materials of each of the first layer 712 and the second layer 713. According to such a configuration, when the first conductive bonding material 71 is joined to the conductive substrate 2 and the support substrate 3 by solid-phase diffusion, the stress is relaxed by the relatively soft first base layer 711, and the smoothing of the bonding boundary portion can be achieved. As a result, the first layer 712 and the conductive substrate 2, and the second layer 713 and the support substrate 3 are more firmly joined by solid-phase diffusion.

[0153] Further, in the present embodiment, the thickness of the first base layer 711 is larger than the thickness of each of the first layer 712 and the second layer 713. Thereby, when joining by solid-phase diffusion, the pressing forces acting on the boundary portions between the first layer 712 and the conductive substrate 2 (back surface bonding layer 23), and between the second layer 713 and the support substrate 3 (first bonding layer 321) become more uniform. Therefore, the first layer 712 and the conductive substrate 2, and the second layer 713 and the support substrate 3 can each be in a more firmly electrically conductive joined state.

[0154] The constituent materials of each of the first layer 712 and the second layer 713 contain silver. According to such a configuration, when joining by solid-phase diffusion using the first conductive bonding material 71, oxidation of the first layer 712 and the second layer 713 is suppressed, and good solid-phase diffusion bonding becomes possible. Further, since each of the back surface bonding layer 23 and the first bonding layer 321 joined to the first layer 712 and the second layer 713 also contains silver, better solid-phase diffusion bonding becomes possible.

[0155] In the present embodiment, the Young's modulus of the second base layer 721 in the second conductive bonding material 72 is smaller than the Young's modulus of the constituent materials of each of the third layer 722 and the fourth layer 723. According to such a configuration, when the second conductive bonding material 72 is joined to the semiconductor element 10 (back surface electrode 15) and the conductive substrate 2 by solid-phase diffusion, the stress is relaxed by the relatively soft second base layer 721, and the smoothing of the bonding boundary portion can be achieved. As a result, the third layer 722 and the semiconductor element 10 (back surface electrode 15), and the fourth layer 723 and the conductive substrate 2 are more firmly joined by solid-phase diffusion.

[0156] In addition, in the present embodiment, the thickness of the second base layer 721 is greater than the thickness of each of the third layer 722 and the fourth layer 723. Thereby, when joining by solid-phase diffusion, the pressing forces acting on the boundary between the third layer 722 and the semiconductor element 10 (back surface electrode 15) and on the boundary between the fourth layer 723 and the conductive substrate 2 (main surface joining layer 22) become more uniform. Therefore, the third layer 722 and the semiconductor element 10 (back surface electrode 15), and the fourth layer 723 and the conductive substrate 2 can each be in a more firmly electrically connected joined state.

[0157] The constituent materials of each of the third layer 722 and the fourth layer 723 contain silver. According to such a configuration, during joining by solid-phase diffusion using the second conductive joining material 72, oxidation of the third layer 722 and the fourth layer 723 is suppressed, and good solid-phase diffusion joining becomes possible. Further, since each of the back surface electrode 15 and the main surface joining layer 22 joined to the third layer 722 and the fourth layer 723 also contains silver, better solid-phase diffusion joining becomes possible.

[0158] The first conductive joining material 71 has a structure in which a first layer 712 and a second layer 713, which are Ag plating layers, are laminated on the surface (both sides) of a first base layer 711 made of a sheet material containing Al. Also, the second conductive joining material 72 has a structure in which a third layer 722 and a fourth layer 723, which are Ag plating layers, are laminated on the surface (both sides) of a second base layer 721 made of a sheet material containing Al. According to such a configuration, the first conductive joining material 71 and the second conductive joining material 72 can be easily prepared.

[0159] In the semiconductor module A1, an opening 63 is formed in the second conductive member 62. The opening 63 overlaps the main surface 201 (conductive substrate 2) in a plan view and does not overlap each semiconductor element 10 in a plan view. According to this configuration, in the molding process (the process of forming the sealing resin 8) of the manufacturing process of the semiconductor module A1, the pressing pin 911 provided on the mold 91 can be inserted into the opening 63. Thereby, since the conductive substrate 2 can be pressed by the pressing pin 911 without interfering with the second conductive member 62, warping of the support substrate 3 to which the conductive substrate 2 is joined can be suppressed. The warping occurs, for example, such that both outer sides of the support substrate 3 in the y direction are positioned above the center side in the y direction. If warping occurs in the support substrate 3, there is a risk that the bonding strength between the conductive substrate 2 and the support substrate 3 will decrease. Further, during the molding process, a part of the sealing resin 8 may be formed on the bottom surface 302 due to resin leakage, which is a cause of poor bonding of a heat radiating member (for example, a heat sink) that can be joined to the bottom surface 302. Therefore, the semiconductor module A1 is a preferable package structure for improving the bonding strength between the conductive substrate 2 and the support substrate 3 by suppressing warping of the support substrate 3, and also forms a preferable package structure for suppressing resin leakage to an unintended position of the sealing resin 8.

[0160] The conductive substrate 2 includes a first conductive portion 2A to which a plurality of first semiconductor elements 10A are joined and a second conductive portion 2B to which a plurality of second semiconductor elements 10B are joined. The first conductive portion 2A and the second conductive portion 2B are spaced apart in the x direction, and the first conductive portion 2A is located in the x2 direction with respect to the second conductive portion 2B. The second conduction member 62 is connected to the plurality of second semiconductor elements 10B and the input terminals 42 and 43, and an opening 63 provided in the second conduction member 62 overlaps the main surface 201 of the first conductive portion 2A in plan view. According to such a configuration, even when ensuring a large size of the second conduction member 62 in plan view, at the time of forming the sealing resin 8 (at the time of mold molding), the conductive substrate 2 can be pressed by a pressing pin 911 provided on the mold 91 while avoiding interference with the second conduction member 62. Note that by increasing the size of the second conduction member 62 in plan view, it is possible to suppress the parasitic resistance component of the second conduction member 62 (conduction member 6) that constitutes the path of the main circuit current.

[0161] The second conduction member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to input terminals 42 and 43 arranged on opposite sides in the y direction with the input terminal 41 interposed therebetween, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622 and extends in the y direction, and is connected to each of the plurality of second semiconductor elements 10B. The opening 63 is formed closer to the x2 direction in each of the first wiring portion 621 and the second wiring portion 622. Thereby, the opening 63 is provided in the vicinity of two corner portions on both outer sides in the y direction of the conductive substrate 2 (first conductive portion 2A) in a plan view. Therefore, the opening 63 is provided in the vicinity of two corner portions on both outer sides in the y direction of the support substrate 3 that supports the conductive substrate 2 (first conductive portion 2A) in a plan view. According to such a configuration, while ensuring a relatively large size of the second conduction member 62 in a plan view, when the sealing resin 8 is formed (at the time of mold molding), the pressing pin 911 provided on the mold 91 is inserted through the opening 63, and the vicinity of the corner portions on both outer sides in the y direction of the conductive substrate 2 (first conductive portion 2A) can be pressed. As described above, the warp of the support substrate 3 to which the conductive substrate 2 is joined occurs such that both outer sides in the y direction of the support substrate 3 are located above the central side in the y direction. According to the above configuration, the warp of the support substrate 3 during mold molding can be effectively suppressed.

[0162] In the present embodiment, the conduction members 6 (the first conduction member 61 and the second conduction member 62) are formed of a metal plate material. Thereby, the opening 63 can be easily formed in the second conduction member 62. Further, for the conduction members 6 (the first conduction member 61 and the second conduction member 62) made of a metal plate material, it is easy to cope with various shapes and sizes, and the reliability of the joint portion with other parts can be enhanced by ensuring a sufficient joint area with other parts.

[0163] In a portion of the main surface 201 of the conductive substrate 2 (first conductive portion 2A) that overlaps with each opening 63 in a plan view, a recess 201a is formed. Each recess 201a is a trace of the pressing force applied to the main surface 201 by the pressing pin 911 during the mold forming process. In the present embodiment, by devising the arrangement of the second conduction member 62 and the openings 63 formed therein, during the mold forming process, the appropriate position of the conductive substrate 2 (first conductive portion 2A) can be held by the pressing pin 911 while avoiding interference with functional elements such as the semiconductor element 10.

[0164] In the sealing resin 8, a resin void portion 86 that communicates with the recess 201a from the resin main surface 81 is formed. The resin void portion 86 is tapered, and the cross-sectional area becomes smaller as it goes from the resin main surface 81 toward the recess 201a. Such a resin void portion 86 is formed during the mold forming process (when the sealing resin 8 is formed). After the mold forming, the surface of the recess 201a in the main surface 201 of the conductive substrate 2 is exposed from the sealing resin 8. Also, in the present embodiment, the resin void portion 86 is filled with a resin filling portion 88 so as to fill the resin void portion 86. According to such a configuration, it is possible to prevent the intrusion of foreign substances (including moisture) into the recess 201a exposed from the sealing resin 8. The semiconductor module A1 having the above configuration is preferable in terms of durability and reliability.

[0165] In the present embodiment, each opening 63 formed in the second conduction member 62 (conduction member 6) is a through hole that penetrates in the z direction. According to such a configuration, in the second conduction member 62 (conduction member 6) that constitutes the path of the main circuit current, the bias of the current path due to the formation of the opening 63 is suppressed.

[0166] The semiconductor module A1 includes a conduction member 6. The conduction member 6 constitutes a path for the main circuit current that is switched by each semiconductor element 10. The conduction member 6 includes each first conduction member 61 connected to each first semiconductor element 10A and a second conduction member 62 connected to each second semiconductor element 10B. The conduction member 6 (each of the first conduction members 61 and the second conduction member 62) is formed of a metal plate material. The main circuit current may be a relatively large value. In this case, suppressing the parasitic resistance component in the conduction member 6, which is the path of the main circuit current, is preferable for reducing the power consumption of the semiconductor module A1. Therefore, in the semiconductor module A1, as described above, by forming the conduction member 6 of a metal plate material instead of a bonding wire, the parasitic resistance component in the conduction member 6 is suppressed. That is, the semiconductor module A1 has a preferable package structure for suppressing the parasitic resistance component.

[0167] In the semiconductor module A1, each first semiconductor element 10A is rectangular in plan view, and the four corners of the first semiconductor element 10A in plan view do not overlap with the second conduction member 62. According to this configuration, in the manufacturing process of the semiconductor module A1, before the step of forming the sealing resin 8, an appearance inspection can be performed to determine whether each first semiconductor element 10A is properly bonded. That is, since the semiconductor module A1 can perform an appearance inspection of the bonding state of each first semiconductor element 10A during the manufacturing process (for example, the state shown in FIG. 23), it is possible to determine whether each first semiconductor element 10A is properly bonded. For example, by the laser ranging method, the distances at the four corners of the first semiconductor element 10A are measured. If the distance differences at the four measured corners are small, it can be determined that the first semiconductor element 10A is properly bonded. Therefore, since the semiconductor module A1 can perform an appearance inspection during the manufacturing process, it has a preferable package structure for improving reliability. When performing the appearance inspection, it is sufficient if at least three of the four corners of the first semiconductor element 10A in plan view can be confirmed. Therefore, it is only necessary that the three corners are configured not to overlap with the second conduction member 62. Also, as shown in FIG. 5, similarly in each second semiconductor element 10B, since the four corners of each second semiconductor element 10B in plan view do not overlap with the second conduction member 62, in the manufacturing process of the semiconductor module A1, before the step of forming the sealing resin 8, an appearance inspection can be performed to determine whether each second semiconductor element 10B is properly bonded. The appearance inspection may be an automatic appearance inspection using imaging and image processing.

[0168] The second conduction member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to input terminals 42 and 43 disposed on opposite sides in the y direction with the input terminal 41 interposed therebetween, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622 and extends in the y direction, and is connected to each of the plurality of second semiconductor elements 10B. The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622. The fourth wiring portion 624 is located on the x2 direction side with respect to the third wiring portion 623 and overlaps the plurality of first semiconductor elements 10A in a plan view. The second conduction member 62 configured to include the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624 overlaps a wide range of the main surface 201 in a plan view, and has a relatively large size in a plan view. Increasing the size of the second conduction member 62 in a plan view in this way is more preferable for suppressing the parasitic resistance component of the second conduction member 62 (conduction member 6) that constitutes the path of the main circuit current.

[0169] Each first semiconductor element 10A has a first side 191, a second side 192, a third side 193, and a fourth side 194 in a plan view. The first side 191 and the second side 192 each extend in the y direction. The first side 191 is an edge on the x2 direction side in the plan view, and the second side 192 is an edge on the x1 direction side in the plan view. The third side 193 and the fourth side 194 each extend in the x direction. The third side 193 is an edge on the y2 direction side in the plan view, and the fourth side 194 is an edge on the y1 direction side in the plan view. Since each first semiconductor element 10A is rectangular in the plan view, the four corners formed by the first side 191, the second side 192, the third side 193, and the fourth side 194 are substantially right angles in the plan view. On the other hand, the fourth wiring portion 624 (first strip portion 625) of the second conduction member 62 has a first edge 627 and a second edge 628. The first edge 627 is an edge located in the x2 direction in the fourth wiring portion 624 and is located in the x1 direction from the first side 191 in the plan view. The first edge 627 also extends at least from the third side 193 to the fourth side 194 in the y direction. Thereby, in the plan view, the two corners 171 and 172 on the x2 direction side of each first semiconductor element 10A do not overlap the second conduction member 62, respectively. The second edge 628 is an edge located in the x1 direction in the fourth wiring portion 624 (first strip portion 625) and is located in the x2 direction from the second side 192 in the plan view. The second edge 628 also extends at least from the third side 193 to the fourth side 194 in the y direction. Thereby, in the plan view, the two corners 173 and 174 on the x1 direction side of each first semiconductor element 10A do not overlap the second conduction member 62, respectively. In such a configuration, by securing a region of the fourth wiring portion 624 that overlaps each first semiconductor element 10A in the plan view, the size of the second conduction member 62 in the plan view is increased, and the four corners of the first semiconductor element 10A in the plan view do not overlap the second conduction member 62. Therefore, the parasitic resistance component of the second conduction member 62 (conduction member 6) can be effectively suppressed, and the appearance inspection of the bonding state of each first semiconductor element 10A can be performed during the manufacturing process of the semiconductor module A1.

[0170] The fourth wiring portion 624 (the first strip portion 625) has a plurality of convex regions 625a protruding in the z2 direction more than other portions. Each convex region 625a overlaps each first semiconductor element 10A in a plan view. According to the configuration in which the fourth wiring portion 624 has the plurality of convex regions 625a, it is possible to avoid the fourth wiring portion 624 from improperly contacting the first conduction member 61 joined on the first semiconductor element 10A.

[0171] The third wiring portion 623 has a plurality of concave regions 623a protruding in the z1 direction more than other portions. Each concave region 623a is joined to any one of the plurality of second semiconductor elements 10B. According to such a configuration, while appropriately conducting the third wiring portion 623 (the second conduction member 62) and the plurality of second semiconductor elements 10B, it is possible to ensure a large size of the third wiring portion 623 (the second conduction member 62) in a plan view.

[0172] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B overlap each other when viewed in the x direction. According to such a configuration, it is possible to suppress an increase in the dimension in the y direction of the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B) on which the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are arranged, and to reduce the size of the semiconductor module A1.

[0173] The semiconductor module A1 includes a conductive substrate 2, two input terminals 41, 42 (or two input terminals 41, 43), an output terminal 44, and a conduction member 6. The conductive substrate 2 includes a first conductive portion 2A and a second conductive portion 2B arranged in the x direction in a plan view. A plurality of first semiconductor elements 10A are electrically joined to the first conductive portion 2A. Also, a plurality of second semiconductor elements 10B are electrically joined to the second conductive portion 2B. The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are each arranged at intervals along the y direction. The two input terminals 41, 42 (or two input terminals 41, 43) are located in the x2 direction with respect to the first conductive portion 2A. The input terminal 41 is the positive electrode and is connected to the first conductive portion 2A. The input terminal 42 (or input terminal 43) is the negative electrode. The output terminal 44 is located in the x1 direction with respect to the second conductive portion 2B. The conduction member 6 includes a first conduction member 61 connected to the plurality of first semiconductor elements 10A and the second conductive portion 2B, and a second conduction member 62 connected to the plurality of second semiconductor elements 10B and the input terminal 42 (or input terminal 43). According to this configuration, the path of the main circuit current switched by the plurality of semiconductor elements 10 (the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B) is configured to extend along the x direction in a plan view, and the symmetry axis (see the auxiliary line L1 in FIG. 5) in the planar structure of the semiconductor module A1 is configured to extend along the y direction in a plan view. That is, the symmetry axis and the path of the main circuit current are orthogonal. Thereby, in the main circuit current input from the two input terminals 41, 42 (or two input terminals 41, 43) and output from the output terminal 44, the difference in the current paths to the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B can be reduced. That is, variations in the parasitic inductance components and current variations in the semiconductor module A1 can be suppressed. Therefore, the semiconductor module A1 has a preferable package structure in terms of equalizing the parasitic inductance components in the path of the main circuit current and equalizing the amount of current flowing to each semiconductor element 10.

[0174] Each first semiconductor element 10A and each second semiconductor element 10B are spaced apart in the x direction. Each first semiconductor element 10A and each second semiconductor element 10B are arranged along the y direction. Therefore, the direction in which each semiconductor element 10 is arranged and the direction in which the first main circuit current or the second main circuit current flows are orthogonal. Thereby, when a plurality of switching elements are connected in parallel and used as in the present embodiment, it is possible to suppress the occurrence of a difference in the length of the current path of the first main circuit current among the three first semiconductor elements 10A. Thereby, the parasitic resistance component in the conduction member 6 which is the path of the main circuit current can be suppressed.

[0175] The region where the first main circuit current flows and the region where the second main circuit current flows are configured to overlap in a plan view. That is, the second conduction member 62 that connects the output terminal 44 and the first input terminal 42 and the second input terminal 43 which are negative terminals is disposed above the region (the first conductive portion 2A, the first conduction member 61, the second conductive portion 2B) where the first main circuit current flows. The direction in which the first main circuit current flows and the direction in which the second main circuit current flows are opposite. Therefore, with the above-described arrangement, the magnetic field generated by the first main circuit current and the magnetic field generated by the second main circuit current can cancel each other out, so that the inductance can be reduced.

[0176] The semiconductor module A1 of the present embodiment includes two input terminals 42 and 43. These input terminals 42 and 43 are both negative electrodes and sandwich the input terminal 41 in the y direction. Further, the second conduction member 62 is connected to the two input terminals 42 and 43. According to such a configuration, it is possible to further reduce the variation in the current path flowing from the output terminal 44 to each input terminal 42 and 43 through each second semiconductor element 10B and the second conduction member 62.

[0177] In the semiconductor module A1, the second conduction member 62 includes a first wiring portion 621, a second wiring portion 622, a third wiring portion 623, and a fourth wiring portion 624. The first wiring portion 621 and the second wiring portion 622 are respectively connected to input terminals 42 and 43 which are arranged on opposite sides in the y direction with the input terminal 41 interposed therebetween, and extend in the x direction. The third wiring portion 623 is connected to both the first wiring portion 621 and the second wiring portion 622 and extends in the y direction, and is connected to each of the plurality of second semiconductor elements 10B. The fourth wiring portion 624 is located on the x2 direction side with respect to the third wiring portion 623 and is connected to any of the first wiring portion 621, the second wiring portion 622, and the third wiring portion 623. The second conduction member 62 configured to include the first wiring portion 621, the second wiring portion 622, the third wiring portion 623, and the fourth wiring portion 624 overlaps a wide range of the main surface 201 in a plan view, and a large size in the plan view can be ensured. According to such a configuration, variations in the current path flowing from the output terminal 44 to each input terminal 42, 43 through each second semiconductor element 10B and the second conduction member 62 are appropriately reduced. Therefore, the semiconductor module A1 of the present embodiment is more preferable in achieving equalization of the parasitic inductance component in the main circuit current path (second conduction member 62) and equalization of the amount of current flowing to each second semiconductor element 10B.

[0178] The fourth wiring portion 624 is connected to both the first wiring portion 621 and the second wiring portion 622 and overlaps a plurality of first semiconductor elements 10A in a plan view. Further, the fourth wiring portion 624 (first strip portion 625) has a plurality of convex regions 625a protruding in the z2 direction more than other portions. Each convex region 625a overlaps each first semiconductor element 10A in a plan view. According to such a configuration, while ensuring a large size of the fourth wiring portion 624 (second conduction member 62) in a plan view, it is possible to avoid the fourth wiring portion 624 from improperly contacting the first conduction member 61 joined on the first semiconductor element 10A.

[0179] The plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B overlap each other when viewed in the x direction. According to such a configuration, it is possible to suppress an increase in the dimension in the y direction of the conductive substrate 2 (the first conductive portion 2A and the second conductive portion 2B) on which the plurality of first semiconductor elements 10A and the plurality of second semiconductor elements 10B are arranged, and the semiconductor module A1 can be miniaturized.

[0180] Figs. 30 to 32 show a semiconductor module according to the second embodiment. In the semiconductor module A2 of the present embodiment, the configuration of the sealing resin 8 is different from that of the semiconductor module A1 of the above embodiment.

[0181] In the present embodiment, the sealing resin 8 does not include the second protruding portion 852. As shown in Fig. 32, the resin main surface 81 of the sealing resin 8 is flush with the upper surface of the upper flange portion of the holder 451. Thereby, a part (the upper surface of the upper flange portion) of each holder 451 is exposed from the sealing resin 8. The resin portion 87 is disposed on the upper surface of the upper flange portion of each holder 451 and on the resin main surface 81 surrounding this. The resin portion 87 covers a part (the upper surface of the upper flange portion) of the holder 451 exposed from the sealing resin 8 and a part of the metal pin 452 at each control terminal 45.

[0182] Also in the semiconductor module A2 of the present embodiment, the same operational effects as those of the semiconductor module A1 of the above embodiment are achieved.

[0183] Figs. 33 to 35 show a semiconductor module according to the third embodiment. In the semiconductor module A3 of the present embodiment, the configuration of the resin portion 87 is different from that of the semiconductor module A2 of the above embodiment.

[0184] In this embodiment, the encapsulating resin 8 does not have the second protruding portion 852. As shown in FIG. 35, the resin main surface 81 of the encapsulating resin 8 is flush with the upper surface of the upper flange portion of the holder 451. Thus, similar to the semiconductor module A2 shown in FIG. 32, a part (the upper surface of the upper flange portion) of each holder 451 is exposed from the encapsulating resin 8. On the other hand, in this embodiment, the resin portion 87 is disposed on the upper surface of the upper flange portion of the holder 451 at each of the plurality of second control terminals 47A to 47D and on the resin main surface 81 continuous therewith. Further, the resin portion 87 is disposed on the upper surface of the upper flange portion of the holder 451 at each of the plurality of first control terminals 46A to 46E and on the resin main surface 81 continuous therewith. In the above-described semiconductor module A2 (see FIG. 32), a plurality of resin portions 87 were disposed corresponding to each holder 451 of the plurality of control terminals 45, but in this embodiment, one resin portion 87 corresponding to the plurality of first control terminals 46A to 46E and another one resin portion 87 corresponding to the plurality of second control terminals 47A to 47D are provided. One resin portion 87 covers a part (the upper surface of the upper flange portion) of each holder 451 exposed from the encapsulating resin 8 and a part of each metal pin 452 at the plurality of first control terminals 46A to 46E. The other resin portion 87 covers a part (the upper surface of the upper flange portion) of each holder 451 exposed from the encapsulating resin 8 and a part of each metal pin 452 at the plurality of second control terminals 47A to 47D.

[0185] Also in the semiconductor module A3 of this embodiment, the same operational effects as those of the semiconductor module A1 of the above embodiment are achieved.

[0186] FIGS. 36 and 37 show a semiconductor module according to the fourth embodiment. In the semiconductor module A4 of this embodiment, the configuration of the metal pins 452 at each of the plurality of control terminals 45 is different from that of the semiconductor module A1 of the above embodiment.

[0187] In the present embodiment, at each control terminal 45 (each first control terminal 46A to 46E and each second control terminal 47A to 47D), the metal pin 452 has a cushion portion 452a. The cushion portion 452a absorbs the impact caused by vibration and is exposed from the sealing resin 8. In the examples shown in FIGS. 36 and 37, the cushion portion 452a is provided at a position closer to the resin portion 87 in the longitudinal direction of the metal pin 452 and is configured as a portion that bends substantially in a U shape within a plane including the z direction.

[0188] Also in the semiconductor module A4 of the present embodiment, the same operational effects as those of the semiconductor module A1 of the above embodiment are achieved. Further, in the semiconductor module A4, each metal pin 452 (each control terminal 45) has a cushion portion 452a. According to such a configuration, for example, even when the semiconductor module A4 is mounted on an electronic device (for example, an automotive device) that may generate relatively large vibrations, the cushion portion 452a can absorb the impact caused by the vibrations, so that damage to the metal pin 452 (control terminal 45) can be prevented. Note that the specific configuration of the cushion portion 452a is not limited to the illustrated example, and for example, the cushion portion 452a may be configured by providing an L-shaped bent portion in the middle of the metal pin 452.

[0189] FIGS. 38 to 40 show a semiconductor module according to the fifth embodiment. In the semiconductor module A5 of the present embodiment, the configuration of the second conduction member 62 is different from that of the semiconductor module A1 of the above embodiment.

[0190] In this embodiment, the area occupied by the fourth wiring portion 624 of the second conduction member 62 is different from that of the above embodiment. Specifically, the dimension of the first strip portion 625 in the x direction is made larger than that of the semiconductor module A1 of the above embodiment. As shown in FIGS. 39 and 40, the position of the second edge 628 of the first strip portion 625 is located on the x1 direction side compared to the semiconductor module A1 of the above embodiment. As shown in FIG. 40, the second edge 628 is located in the x1 direction from the second side 192 of the first semiconductor element 10A in a plan view. As a result, in a plan view, two corners on the x1 direction side of each first semiconductor element 10A overlap with the second conduction member 62 (first strip portion 625), respectively.

[0191] Also in the semiconductor module A5 of this embodiment, the same operational effects as those of the semiconductor module A1 of the above embodiment are achieved. Further, in the semiconductor module A5, the size of the first strip portion 625 (second conduction member 62) of the fourth wiring portion 624 in a plan view can be ensured to be larger. This is more preferable in reducing the parasitic inductance component.

[0192] FIGS. 41 and 42 show a semiconductor module according to the sixth embodiment. In the semiconductor module A6 of this embodiment, mainly the configuration of the second conduction member 62 is different from that of the semiconductor module A1 of the above embodiment.

[0193] In the semiconductor module A6, unlike the above embodiment, the second conduction member 62 does not have an opening 63. When manufacturing the semiconductor module A6, the mold 91 used for forming the encapsulation resin 8 (mold molding) does not include a pressing pin 911. As a result, as shown in FIG. 42, no resin void portion 86 is formed in the encapsulation resin 8, and no recess 201a is formed on the main surface 201 of the conductive substrate 2 (first conductive portion 2A and second conductive portion 2B). Further, since no resin void portion 86 is formed in the encapsulation resin 8, the semiconductor module A6 of this embodiment does not include the resin filling portion 88 used to fill the resin void portion 86 in the above embodiment.

[0194] Also in the semiconductor module A6 of the present embodiment, the same operational effects as those of the semiconductor module A1 of the above embodiment are achieved.

[0195] The semiconductor module according to the present disclosure is not limited to the above-described embodiments. The specific configuration of each part of the semiconductor module of the present disclosure can be freely designed in various ways.

[0196] The present disclosure includes the configurations described in the following supplementary notes.

[0197] Supplementary Note 1. A conductive substrate having a main surface facing one side in the thickness direction and a back surface facing the side opposite to the main surface, A semiconductor element that is electrically joined to the main surface and has a switching function, A control terminal for controlling the semiconductor element, A sealing resin having a resin main surface facing the same side as the main surface and a resin back surface facing the side opposite to the resin main surface, and covering the conductive substrate, the semiconductor element, and a part of the control terminal, The control terminal protrudes from the resin main surface and extends along the thickness direction, a semiconductor module. Supplementary Note 2. The sealing resin has a resin side surface that is connected to both the resin main surface and the resin back surface and is sandwiched between the resin main surface and the resin back surface in the thickness direction, A power supply terminal that protrudes from the resin side surface, is electrically connected to the semiconductor element, and handles a power supply voltage, The power supply terminal includes a bonding surface facing one side in the thickness direction, the semiconductor module according to Supplementary Note 1. Supplementary Note 3. The power supply terminal includes a first power supply terminal to which a first power supply voltage is input and a second power supply terminal that outputs a second power supply voltage, the semiconductor module according to Supplementary Note 2. Supplementary Note 4. A control terminal support having an insulating layer and interposed between the main surface and the control terminal is provided, the semiconductor module according to any one of Supplementary Notes 1 to 3. Supplementary Note 5. The control terminal support includes the insulating layer, a first metal layer laminated on one side in the thickness direction of the insulating layer, and a second metal layer laminated on the other side in the thickness direction of the insulating layer and joined to the conductive substrate so as to face the main surface, and is the semiconductor module according to Supplementary Note 4. Supplementary Note 6. The control terminal is joined to the first metal layer via a conductive bonding material, and is the semiconductor module according to Supplementary Note 5. Supplementary Note 7. It further includes a conductive wire, The semiconductor element has an element main surface facing the same side as the main surface, an element back surface facing the side opposite to the element main surface, and a gate electrode disposed on the element main surface, The conductive wire is connected to the gate electrode and the first metal layer, and is the semiconductor module according to Supplementary Note 6. Supplementary Note 8. The control terminal is joined to the first metal layer and includes a cylindrical holder having conductivity and a metal pin press-fitted into the holder and extending in the thickness direction, and is the semiconductor module according to Supplementary Note 6 or 7. Supplementary Note 9. A part of the holder is exposed from the sealing resin on one side in the thickness direction, and is the semiconductor module according to Supplementary Note 8. Supplementary Note 10. It further includes a resin part joined to the sealing resin, The resin part covers a part of the holder exposed from the sealing resin and a part of the metal pin, and is the semiconductor module according to Supplementary Note 9. Supplementary Note 11. The conductive substrate includes a first conductive part and a second conductive part which are spaced apart from each other on one side and the other side in a first direction perpendicular to the thickness direction, The first power terminal includes a first input terminal located on one side in the first direction with respect to the first semiconductor element and connected to the first conductive part, and a second input terminal located on one side in the first direction with respect to the first semiconductor element and connected to the second semiconductor element, The second power terminal is an output terminal that is located on the other side of the second semiconductor element in the first direction and is connected to the second conductive portion. The control terminal includes a first control terminal that controls the first semiconductor element and a second control terminal that controls the second semiconductor element. The first control terminal is supported by the first conductive portion and is disposed between the first semiconductor element and the first input terminal and the second input terminal in the first direction. The semiconductor module according to appended note 3, wherein the second control terminal is supported by the second conductive portion and is disposed between the second semiconductor element and the output terminal in the first direction. Appended note 12. A plurality of the first semiconductor elements arranged at intervals in a second direction that is perpendicular to both the thickness direction and the first direction; A plurality of the first control terminals arranged at intervals in the second direction; A plurality of the second semiconductor elements arranged at intervals in the second direction; The semiconductor module according to appended note 11, further comprising a plurality of the second control terminals arranged at intervals in the second direction. Appended note 13. The encapsulating resin has a plurality of protruding portions that protrude from the resin main surface and have protruding end surfaces formed at respective tips. The semiconductor module according to any one of appended notes 1 to 12, wherein the protruding end surfaces of the plurality of protruding portions are each parallel to the resin main surface and are on the same plane. Appended note 14. The semiconductor module according to any one of appended notes 1 to 13, wherein the control terminal has a cushion portion for absorbing impact due to vibration. Appended note 15. The semiconductor module according to appended note 14, wherein the cushion portion is exposed from the encapsulating resin. Appended note 16. A conductive substrate having a main surface facing one side in the thickness direction and a back surface facing the side opposite to the main surface; A semiconductor element having a switching function and electrically joined to the main surface; A control terminal for controlling the semiconductor element, A sealing resin having a resin main surface facing the same side as the main surface and a resin back surface facing the opposite side of the resin main surface, covering the conductive substrate, the semiconductor element, and a part of the control terminal, The control terminal protrudes from the resin main surface and extends along the thickness direction, a semiconductor module. Supplementary Note 17. The semiconductor module according to Supplementary Note 16, further comprising a control terminal support having an insulating layer interposed between the main surface and the control terminal. Supplementary Note 18. The control terminal support has the insulating layer, a first metal layer laminated on one side in the thickness direction of the insulating layer, and a second metal layer laminated on the other side in the thickness direction of the insulating layer and joined to the conductive substrate so as to face the main surface, the semiconductor module according to Supplementary Note 17. Supplementary Note 19. The control terminal is joined to the first metal layer via a conductive bonding material, the semiconductor module according to Supplementary Note 18. Supplementary Note 20. The semiconductor element has an element main surface facing the same side as the main surface, an element back surface facing the opposite side of the element main surface, and a gate electrode disposed on the element main surface, A conductive wire is connected to the gate electrode and the first metal layer, the semiconductor module according to Supplementary Note 19. Supplementary Note 21. The control terminal includes a cylindrical holder joined to the first metal layer and having conductivity, and a metal pin press-fitted into the holder and extending in the thickness direction, the semiconductor module according to Supplementary Note 19 or 20. Supplementary Note 22. A part of the holder is exposed from the sealing resin on one side in the thickness direction, the semiconductor module according to Supplementary Note 21. Supplementary Note 23. Further comprising a resin portion joined to the sealing resin, The semiconductor module according to appended note 22, wherein the resin portion covers a portion exposed from the sealing resin in the holder and a part of the metal pin. Appended note 24. The conductive substrate includes a first conductive portion and a second conductive portion that are spaced apart from each other when viewed in the thickness direction and are disposed on one side and the other side in a first direction perpendicular to the thickness direction. The semiconductor element includes a first semiconductor element electrically joined to the first conductive portion and a second semiconductor element electrically joined to the second conductive portion. A first input terminal that is located on one side in the first direction with respect to the first semiconductor element and is connected to the first conductive portion. A second input terminal that is located on one side in the first direction with respect to the first semiconductor element and is connected to the second semiconductor element. The semiconductor module according to any one of appended notes 16 to 23, further comprising an output terminal that is located on the other side in the first direction with respect to the second semiconductor element and is connected to the second conductive portion. The control terminal includes a first control terminal for controlling the first semiconductor element and a second control terminal for controlling the second semiconductor element. The first control terminal is supported by the first conductive portion and is disposed between the first semiconductor element and the first input terminal and the second input terminal in the first direction. The second control terminal is supported by the second conductive portion and is disposed between the second semiconductor element and the output terminal in the first direction. Appended note 25. A plurality of the first semiconductor elements arranged at intervals in a second direction perpendicular to both the thickness direction and the first direction. A plurality of the first control terminals arranged at intervals in the second direction. A plurality of the second semiconductor elements arranged at intervals in the second direction. The semiconductor module according to appended note 24, further comprising a plurality of the second control terminals arranged at intervals in the second direction. Appended note 26. The sealing resin has a plurality of protruding portions that protrude from the main surface of the resin and have protruding end surfaces formed at their respective tips. The protruding end surfaces of the plurality of protruding portions are each parallel to the main surface of the resin and are on the same plane. The semiconductor module according to any one of Appendices 16 to 25. Appendix 27. The control terminal has a cushion portion for absorbing impact caused by vibration. The semiconductor module according to any one of Appendices 16 to 26. Appendix 28. The cushion portion is exposed from the sealing resin. The semiconductor module according to Appendix 27.

Explanation of Reference Numerals

[0198] A1, A2, A3, A4, A5, A6: Semiconductor module 10: Semiconductor element 10A: First semiconductor element 10B: Second semiconductor element 101: Element main surface 102: Element back surface 11: First main surface electrode (gate electrode) 12: Second main surface electrode (source electrode) 13: Third main surface electrode 14: Fourth main surface electrode 15: Back surface electrode (drain electrode) 16: Fifth main surface electrode 171, 172, 173, 174: Corners 181, 182, 183, 184: Corners 191: First side 192: Second side 193: Third side 194: Fourth side 2: Conductive substrate 2A: First conductive portion 2B: Second conductive portion 201: Main surface 201a: Recess 201b: Recess edge 202: Back surface 21: Substrate 22: Main surface bonding layer 23: Back surface bonding layer 3: Support substrate 301: Support surface 302: Bottom surface 31: Insulating layer 32: First metal layer 32A: First part 32B: Second part 321: First bonding layer 33: Second metal layer 41: First input terminal 411: Input side bonding surface 412: Input side surface 413: Front end surface 414: Side surface 42: Second input terminal 421: Input side bonding surface 422: Input side surface 423: Front end surface 424: Side surface 43: Third input terminal 431: Input side bonding surface 432: Input side surface 433: Front end surface 434: Side surface 44: Output terminal 441: Output side bonding surface 442: Output side surface 443: Front end surface 444: Side surface 45: Control terminal 451: Holder 452: Metal pin 452a: Cushion part 459: Conductive bonding material 46A, 46B, 46C, 46D, 46E: First control terminal 47A, 47B, 47C, 47D: Second control terminal 5: Control terminal support 51: Insulating layer 52: First metal layer 521: First part 522: Second part 523: Third part 524: Fourth part 525: Fifth part 53: Second metal layer 59: Bonding material 6: Conductive member 601: First part 61: First conductive member 61h: Opening 62: Second conductive member 62A: First part 62B: Second part 621: First wiring part 622: Second wiring part 623: Third wiring part 623a: Concave region 623h: Opening 624: Fourth wiring part 625: First strip part 625a: Convex region 625h: Opening 626: Second strip part 627: First edge 628: Second edge 63: Opening 69: Conductive bonding material 71: First conductive bonding material 711: First base layer 712: First layer 713: Second layer 72: Second conductive bonding material 721: Second base layer 722: Third layer 723: Layer 4 731: Wire 731a: First Wire 731b: Second Wire 732, 733, 734, 735: Wires 8: Encapsulating Resin 81: Main Resin Surface 82: Back Resin Surface 831, 832: Resin Side Surfaces 832a: Concave Portion 833, 834: Resin Side Surfaces 851: First Protrusion 851a: First Protrusion End Surface 851b: Concave Portion 851c: Inner Wall Surface 852: Second Protrusion 86: Resin Void Portion 861: Edge of Resin Void Portion 87: Resin Portion 88: Resin Filling Portion 91: Mold 911: Pressing Pin

Claims

1. A semiconductor module configured with a half-bridge type circuit, including a first conductive part and a second conductive part, a conductive substrate having a main surface facing one side in the thickness direction and a back surface facing the side opposite to the main surface, a first semiconductor element and a second semiconductor element that are electrically joined to the respective main surfaces of the first conductive part and the second conductive part and have a switching function, a first control terminal and a second control terminal for controlling the first semiconductor element and the second semiconductor element respectively, including a metal layer insulated from the conductive substrate, a first control terminal support for supporting the first control terminal, and a second control terminal support for supporting the second control terminal, a first input terminal disposed on one side in a first direction orthogonal to the thickness direction with respect to the conductive substrate, a second input terminal and a third input terminal that are disposed on one side in the first direction with respect to the conductive substrate and are disposed on opposite sides of each other across the first input terminal in a second direction orthogonal to the thickness direction and the first direction, at least one output terminal disposed on the other side in the first direction with respect to the conductive substrate, a conduction member that is electrically connected to the first conductive part, the second conductive part, the first semiconductor element, the second semiconductor element, the first input terminal, the second input terminal, and the third input terminal and constitutes the half-bridge type circuit, having a resin main surface facing the same side as the main surface and a resin back surface facing the side opposite to the resin main surface, and a sealing resin covering the conductive substrate, the first semiconductor element, the second semiconductor element, a part of the first input terminal, a part of the second input terminal, a part of the third input terminal, a part of the output terminal, and the conduction member, the first control terminal and the second control terminal are exposed from the resin main surface, a first main circuit current path, which is a path of a first main circuit current, is formed between the first input terminal and the output terminal via the first semiconductor element, a second main circuit current path, which is a path of a second main circuit current, is formed between the output terminal and the second input terminal and the third input terminal via the second semiconductor element, the first main circuit current path and the second main circuit current path are symmetrically disposed with respect to a center line passing through the center of the first input terminal and extending in the first direction when viewed in the thickness direction. A semiconductor module.

2. The semiconductor module according to claim 1, wherein the conduction member is composed of a plate-like member made of metal.

3. The semiconductor module according to claim 2, wherein the conduction member is symmetrically arranged with respect to a center line passing through the center of the first input terminal and extending in the first direction when viewed in the thickness direction.

4. The semiconductor module according to claim 3, wherein a region through which the first main circuit current flows and a region through which the second main circuit current flows are configured to overlap in a plan view.

5. The semiconductor module according to claim 1, wherein the first control terminal support and the second control terminal support include an insulating layer, a first metal layer laminated on one side in the thickness direction of the insulating layer, and a second metal layer laminated on the other side in the thickness direction of the insulating layer and joined to the conductive substrate so as to face the main surface.

6. The semiconductor module according to claim 5, wherein the first control terminal and the second control terminal are joined to the first metal layer.

7. The first semiconductor element has a first element main surface facing the same side as the main surface, a first element back surface facing the side opposite to the first element main surface, and a first gate electrode disposed on the first element main surface. The second semiconductor element has a second element main surface facing the same side as the main surface, a second element back surface facing the side opposite to the second element main surface, and a second gate electrode disposed on the second element main surface. The semiconductor module according to claim 6, wherein a conductive wire is connected to the first gate electrode, the second gate electrode, and the first metal layer.

8. The semiconductor module according to claim 5, wherein the first control terminal support and the second control terminal support are constituted by a DBC substrate.

9. The semiconductor module according to claim 5, wherein the insulating layer is made of ceramics.

10. The semiconductor module according to claim 1, comprising a plurality of the first semiconductor elements arranged at intervals in the second direction and a plurality of the second semiconductor elements arranged at intervals in the second direction.

11. The semiconductor module according to claim 1, wherein the first control terminal support and the second control terminal support respectively support a plurality of the first control terminals and a plurality of the second control terminals.

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