Leakage Current Detection Circuit for Semiconductor Element

Abstract

To provide a semiconductor element leakage current detection circuit capable of separating and reliably detecting a leakage current even during a period in which conduction control of a semiconductor element is performed.SOLUTION: When a power element 1 is turned on, a mask circuit 10S sets a period during which a charging current flows into a gate as a mask period. A current sense amplifier 7S and a comparator 8S output a detection signal when a leakage current flowing from the gate to the source of the power element 1 is detected after the mask period has elapsed.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a circuit for detecting a leakage current generated between a control terminal and a conduction terminal in a semiconductor element.

Background Art

[0002] For example, regarding circuits for detecting leakage currents generated between the drain and gate or between the gate and source in power elements such as power MOSFETs, various conventional circuits have been proposed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, when turning on an N-channel MOSFET, a charging current flows into the gate, and when turning off, a discharging current flows out from the gate. Therefore, in order to detect the leakage current, it is necessary to separate it from the period during which the charging current or discharging current flows as described above. However, none of the above-mentioned conventional techniques specifically disclose how to separate the period during which the charging and discharging currents flow when detecting the leakage current.

[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide a leakage current detection circuit for a semiconductor element that can reliably detect the leakage current by separating it even during the period when the conduction control of the semiconductor element is performed.

Means for Solving the Problems

[0006] According to the leakage current detection circuit of the semiconductor device described in claim 1, when turning on the semiconductor device, the low potential side setting circuit sets the period during which the charging current flows into the control terminal as a non-detectable period, and after the non-detectable period has elapsed, the low potential side detection unit outputs a detection signal when detecting the leakage current flowing from the control terminal to the low potential side conduction terminal. With this configuration, the low potential side detection unit can surely exclude the period during which the charging current flows into the control terminal and detect the leakage current.

[0007] Also, Claim 1 According to the leakage current detection circuit of the semiconductor device described in, when turning off the semiconductor device, the high potential side setting circuit sets the period during which the discharge current flows out from the control terminal as a non-detectable period, and after the non-detectable period has elapsed, the high potential side detection unit outputs a detection signal when detecting the leakage current flowing from the high potential side conduction terminal to the control terminal. With this configuration, the high potential side detection unit can surely exclude the period during which the discharge current flows out from the control terminal and detect the leakage current. Furthermore, the low-potential side detection unit is connected to a charging-side resistance element disposed in the charging path to the control terminal, and the high-potential side detection unit is connected to a discharging-side resistance element disposed in the discharging path from the control terminal. The charging-side resistance element is a shunt resistor having one end connected to a power source and provided in a drive circuit for turning on a semiconductor element by a constant current drive method, and the discharging-side resistance element is a shunt resistor having one end connected to a ground and provided in a drive circuit for turning off a semiconductor element by a constant current drive method. BRIEF DESCRIPTION OF THE DRAWINGS

[0008]

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Modes for Carrying Out the Invention

[0009] (First Embodiment) As shown in FIG. 1, in this embodiment, in a drive circuit 2 that drives a power element 1 on the lower arm side that constitutes an inverter, a leakage current generated between the gate and source of the power element 1 is detected. The power element 1, which is an example of a semiconductor element, is, for example, an N-channel MOSFET. The drive circuit 2 includes a series circuit of an on-side drive element 3 and an off-side drive element 4 connected between a power supply and a ground, and a common connection point of these elements 3 and 4 is connected to the gate of the power element 1 via a gate resistor 5. The on-side drive element 3 and the off-side drive element 4 are, for example, a P-channel MOSFET and an N-channel MOSFET, respectively.

[0010] The gates of the on-side drive element 3 and the off-side drive element 4 are connected to the output terminals of the control block 6, and their drive control is performed by the control block 6. The non-inverting input terminal of the current sense amplifier 7S is connected to the common connection point of the elements 3 and 4, and the inverting input terminal is connected to the gate of the power element 1. The output terminal of the current sense amplifier 7S is connected to the non-inverting input terminal of the comparator 8S, and a voltage source 9S for applying a threshold voltage is connected to the inverting input terminal of the comparator 8S.

[0011] The output terminal of the comparator 8S is connected to the input terminal of the control block 6 via the mask circuit 10S. Also, the gate drive signal output by the control block 6 to the on-side drive element 3 is input to the mask circuit 10S. The mask circuit 10S operates to mask the output signal of the comparator 8S for a certain period of time from the time when the control block 6 outputs the gate drive signal to the on-side drive element 3. This "masking for a certain period of time" period is the mask period and corresponds to the non-detectable period.

[0012] As described above, the gate, drain, and source of the power element 1 are examples of the control terminal, high-potential side Conduction terminal, and low-potential side Conduction terminal, respectively. The current sense amplifier 7S and the comparator 8S correspond to the low-potential side detection unit, and the mask circuit 10S corresponds to the low-potential side setting unit. Also, the components 7S to 10S constitute the leakage current detection circuit 11S.

[0013] Next, the operation of this embodiment will be described. When the control block 6 turns on the power element 1, the on-side drive element 3 is turned on and the off-side drive element 4 is turned off. At this time, as shown in FIG. 2, a high-level gate voltage is applied to the gate of the power element 1 via the on-side drive element 3. However, when the gate voltage rises to the high level, a current for charging the gate of the power element 1 flows instantaneously. The mask circuit 10S performs masking to prevent the output signal of the comparator 8S from being input to the control block 6 during this period.

[0014] If a leakage current flows between the gate and source of the power element 1, a current flows through the gate resistor 5 even after the current for charging the gate has flowed. Therefore, a potential difference corresponding to the terminal voltage of the gate resistor 5 is generated between the input terminals of the current sense amplifier 7S. As a result, the output signal of the comparator 8S becomes high level, and this signal is input to the control block 6 after the mask period has elapsed. Thus, the control block 6 can detect that a leakage failure has occurred between the gate and source of the power element 1.

[0015] As described above, according to the present embodiment, when the mask circuit 10S turns on the power element 1, the period during which the charging current flows into the gate is set as the mask period. After the mask period has elapsed, when the current sense amplifier 7S and the comparator 8S detect a leakage current flowing from the gate to the source of the power element 1, they output a detection signal. With this configuration, the mask circuit 10S can surely exclude the period during which the charging current flows into the gate and detect the leakage current.

[0016] (Second Embodiment) Hereinafter, the same parts as those in the first embodiment will be denoted by the same reference numerals and the description thereof will be omitted, and the different parts will be described. As shown in FIG. 3, in the second embodiment, instead of the leakage current detection circuit 11S, a leakage current detection circuit 11D for detecting a leakage current flowing from the drain to the gate of the power element 1 is shown. The leakage current detection circuit 11D includes a current sense amplifier 7D, a comparator 8D, a voltage source 9D, and a mask circuit 10D corresponding to the configuration of the leakage current detection circuit 11S.

[0017] The non-inverting input terminal of the current sense amplifier 7D is connected to the gate of the power element 1, and the inverting input terminal is connected to the common connection point of the elements 3 and 4. A gate drive signal output from the control block 6 to the off-side drive element 4 is input to the mask circuit 10D. The mask circuit 10D is configured as shown in FIGS. 5 and 6, for example.

[0018] In the mask circuit 10D(1) shown in FIG. 5, in the RC filter composed of the resistor element 12 and the capacitor 13, an N-channel MOSFET 14 is connected in parallel to the capacitor 13, and the gate drive signal of the off-drive element 4 is applied to the gate of the FET 14 via the NOT gate 15. During the period when the off-drive element 4 is off, the FET 14 is on, so the capacitor 13 is short-circuited. During the period when the off-drive element 4 is on, the FET 14 is off, and the output signal is delayed and masked by the action of the RC filter.

[0019] Also, the mask circuit 10D(2) shown in FIG. 6 is a combination of the AND gate 16 and the timer 17. One of the input terminals of the AND gate 16 is supplied with the output signal of the comparator 8D, and the other input terminal is supplied with the gate drive signal of the off-drive element 4 via the timer 17. The timer 17 starts counting the clock when the gate drive signal becomes high level, and when the set mask time elapses, it sets the input terminal of the AND gate 16 to high level and outputs the output signal of the comparator 8D. Note that the mask circuit 10S can also be configured on the same principle as the mask circuits 10D(1) and 10D(2). In the above, the current sense amplifier 7D and the comparator 8D correspond to the high-potential side detection unit, and the mask circuit 10D corresponds to the high-potential side setting unit. Also, the configurations 7S to 10S constitute the leakage current detection circuit 11S.

[0020] Next, the operation of the second embodiment will be described. When the control block 6 turns off the power element 1, the on-side drive element 3 is turned off and the off-side drive element 4 is turned on. At this time, as shown in FIG. 4, a low-level gate voltage is applied to the gate of the power element 1 via the off-side drive element 4. When the gate voltage falls to the low level, a discharge current instantaneously flows from the gate of the power element 1. The mask circuit 10D masks so as to prevent the output signal of the comparator 8D from being input to the control block 6 during this period.

[0021] If a leakage current flows between the drain and gate of the power element 1, even after a discharge current flows from the gate, a current flows through the gate resistor 5. Therefore, a potential difference corresponding to the terminal voltage of the gate resistor 5 is generated between the input terminals of the current sense amplifier 7D. As a result, the output signal of the comparator 8D becomes high level, and this signal is input to the control block 6 after the mask period has elapsed. Therefore, the control block 6 can detect that a leakage failure has occurred between the drain and gate of the power element 1.

[0022] As described above, according to the second embodiment, when the mask circuit 10D turns off the power element 1, the period during which the discharge current flows out from the gate is set as the mask period. After the mask period has elapsed, when the current sense amplifier 7D and the comparator 8D detect a leakage current flowing from the drain to the gate of the power element 1, they output a detection signal. With this configuration, the mask circuit 10D can surely exclude the period during which the charging current flows into the gate and detect the leakage current.

[0023] (Third Embodiment) As shown in FIGS. 7 and 8, the third embodiment has a configuration including both the leakage current detection circuit 11S of the first embodiment and the leakage current detection circuit 11D of the second embodiment.

[0024] (Fourth Embodiment) As shown in FIG. 9, in the fourth embodiment, instead of the gate resistor 5 in the configuration of the third embodiment, a gate resistor 5H connected between the source of the on-driving element 3 and the gate of the power element 1, and a gate resistor 5L connected between the drain of the off-driving element 4 and the gate of the power element 1 are connected. At this time, the gate resistor 5H is connected between the input terminals of the current sense amplifier 7S, and the gate resistor 5L is connected between the input terminals of the current sense amplifier 7D.

[0025] According to the fourth embodiment configured as described above, in order to individually adjust the turn-on time and turn-off time of the power element 1, even when the resistance values of the gate resistors 5H and 5L are set to different values, it is possible to detect that a leak failure has occurred between the gate-source and drain-gate of the power element 1.

[0026] (Fifth Embodiment) As shown in FIG. 10, the fifth embodiment is a case where the drive circuit 21 replacing the drive circuit 2 is a constant current drive method. In FIG. 10, only the on-drive element 3 side is shown. A shunt resistor 22H is connected between the power supply and the drain of the on-drive element 3. The non-inverting input terminal of the drive amplifier 23H is connected to the negative terminal of a voltage source 24 whose positive terminal is connected to the power supply, and the inverting input terminal is connected to the source of the on-drive element 3. The output terminal of the drive amplifier 23H is connected to the gate of the on-drive element 3. The enable control of the drive amplifier 23H is performed by a control logic (not shown). The drive amplifier 23H controls the gate potential of the on-drive element 3 so that the terminal voltage of the shunt resistor 22H becomes equal to the potential applied to the non-inverting input terminal.

[0027] FIG. 11 shows the leak current detection circuit with the off-drive element 4 side added, but the illustration of the drive amplifier 23 is omitted. A shunt resistor 22L is connected between the source of the off-drive element 4 and the ground. The non-inverting input terminal of the current sense amplifier 7S is connected to the power supply, and the inverting input terminal is connected to the source of the on-drive element 3. The non-inverting input terminal of the current sense amplifier 7D is connected to the source of the off-drive element 4, and the inverting input terminal is connected to the ground.

[0028] According to the fifth embodiment configured as described above, even in a configuration where no gate resistor is used when driving the power element 1, it is possible to detect that a leak failure has occurred between the gate-source and drain-gate of the power element 1.

[0029] (Sixth Embodiment) As shown in FIG. 12, in the driving circuit 2 of the voltage driving method as in the first embodiment, in the sixth embodiment, the shunt resistors 22H and 22L of the fifth embodiment are replaced with the gate resistors 5 and used for detecting the leakage current. That is, the input terminals of the current sense amplifier 7S are connected to both ends of the shunt resistor 22H, and the input terminals of the current sense amplifier 7D are connected to both ends of the shunt resistor 22L. Further, the control block 6 controls the gate potentials of the on-driving element 3 and the off-driving element 4 via the driving amplifiers 26H and 26L.

[0030] (Seventh Embodiment) The leakage current detection circuit 31S of the seventh embodiment shown in FIG. 13 arranges a low-pass filter 32S between the mask circuit 10 and the control block 6 in the leakage current detection circuit 11S of the first embodiment. The gate wiring of the power element 1 is a terminal where noise is very likely to be superimposed, and the leakage current is a signal with a level smaller than the current flowing at the time of turn-on and turn-off. If the threshold voltage of the comparator 8 is set to detect such a minute-level signal, there is a risk of detecting noise as well. Therefore, in the seventh embodiment, the low-pass filter 32S is arranged to remove the noise that occurs irregularly as shown in FIG. 14.

[0031] (Eighth Embodiment) The leakage current detection circuit 33S of the eighth embodiment shown in FIG. 15 includes a counter 34 inside the control block 6A, and counts the number of times the output signal of the comparator 8S input via the mask circuit 10S and the filter 32S continuously changes to the high level. A binary-level signal, that is, a gate voltage, which the gate driving unit 35 outputs to the gate of the on-driving element 3, is input to the counter 34. The low-potential side detection unit is configured to include the counter 34.

[0032] For example, as shown in FIG. 16, when the gate drive unit 35 changes the gate voltage so as to alternately turn on and off the on-drive element 3, if the output signal of the filter 32S exceeds the threshold value for three consecutive on-off cycles, when the count value of the counter 34 reaches "3", the counter 34 outputs a detection signal for the leakage current. If the output signal of the comparator 8S does not continuously change to the high level, the counter 34 is reset.

[0033] (Embodiment 9) The leakage current detection circuit 36S of the ninth embodiment shown in FIG. 17 includes a control logic 6B in which an on-period determination unit 37 is added to the control logic 6A of the eighth embodiment. As shown in FIG. 18, when the on-pulse width of the gate voltage is longer than the sum of the mask period set by the mask circuit 10S and the time constant time of the filter 32S, the leakage current can be detected.

[0034] On the other hand, as shown in FIG. 19, when the above on-pulse width becomes shorter than the sum of the mask period and the time constant time, the leakage current cannot be detected. Therefore, in the ninth embodiment, the on-period determination unit 37 compares the length of the on-pulse width with (mask period + time constant time) as a threshold value, and as shown in FIG. 20, when the on-pulse width is shorter than the threshold value, the reset of the counter 34 is prevented. Thereby, it is possible to prevent the counter 34 from being reset due to the short on-period of the on-drive element 3 even though the leakage current is actually flowing, resulting in the inability to detect the leakage current or a delay.

[0035] (Embodiment 10) The leakage current detection circuit 38S of the tenth embodiment shown in FIG. 21 has a configuration in which the control block 6A in the leakage current detection circuit 33S of the eighth embodiment is replaced with a control block 6C. The control block 6C is obtained by adding an on-time measurement unit 39, on-time registers 40(n) and 40(n + 1), and a leakage determination unit 41 to the control block 6A. These also constitute a low-potential side detection unit.

[0036] As shown in FIG. 22, in the tenth embodiment, it is assumed that the on / off control pattern of the power element 1 is repeated for each electrical angle period according to a predetermined waveform such as a sine wave. The on-time measurement unit 39 measures the on-time width of the gate drive signal output by the gate drive unit 35 and sequentially stores it in the on-time register 40(n + 1). The on-time register 40(n) stores the previous measurement result. The leak determination unit 41 compares the register values of the on-time registers 40(n) and 40(n + 1). When the value of the former is smaller than the value of the latter, the value of the on-time register 40(n) at that time is determined as the minimum value. The period from this minimum value to the determination of the next minimum value is one cycle of the electrical angle, which is the gate-source leak determination period shown in FIG. 22.

[0037] During the above determination period, when the count value of the counter 34 becomes "4" or more as shown in FIG. 24, for example, the leak determination unit 41 determines that there is a "leak" between the gate and the source. Regarding the gate-source leak determination period shown in FIG. 22, the maximum value may be determined by comparing the register values of the on-time registers 40(n) and 40(n + 1) in the same manner as above, and the period until the next maximum value is determined may be used as the determination period.

[0038] (Eleventh Embodiment) The leak current detection circuit 42S of the eleventh embodiment shown in FIG. 25 has a configuration in which the control block 6C in the leak current detection circuit 38S of the tenth embodiment is replaced with a control block 6D. The control block 6D uses the leak determination unit 41 of the control block 6C as a sub-leak determination unit 41, and a counter 43 and a leak determination unit 44 are connected in series to the output terminal of the sub-leak determination unit 41. These also constitute a low-potential side detection unit.

[0039] The counter 43 counts the number of times the sub - leak determination unit 41 determines that there is a leak. Also, when the count value of the counter 34 does not reach "4" within the leak determination period, the counter 43 is reset. Then, as shown in FIG. 26, when the counter 43 is incremented over three determination periods and its count value reaches "3", the leak determination unit 44 determines that there is a leak.

[0040] In addition, although the 7th to 11th embodiments show circuits for detecting the source - side leak current, the circuits for detecting the drain - side leak current can be configured in the same manner as each embodiment. When applying the 9th embodiment to a circuit for detecting the drain - side leak current, the component corresponding to the on - period determination unit 37 becomes an off - period determination unit that determines the off - period of the power element 1.

[0041] (12th - 14th Embodiments) The 12th to 14th embodiments show specific circuit examples of the current sense amplifier 7. The 12th embodiment shown in FIG. 27 shows the case where the current sense amplifier 7A is configured as a single - stage amplifier circuit. The 13th embodiment shown in FIG. 28 shows the case where the current sense amplifier 7B is configured as an instrumentation amplifier. The 14th embodiment shown in FIG. 29 shows the case where the current sense amplifier 7C is configured as a switched - capacitor circuit.

[0042] (15th Embodiment) In the 1st to 11th embodiments, in the inverter circuit 51 shown in FIG. 30, a circuit 53D for detecting the leak current of the lower - arm - side power element 52D is shown. However, as shown in the same figure, a similar leak current detection circuit 53U can also be applied to the upper - arm - side power element 52U. If the power element 52U is an IGBT, the high - potential - side conduction terminal is the collector and the low - potential - side conduction terminal is the emitter. Also, if the power element 52U is a P - channel MOSFET, the high - potential - side conduction terminal is the source and the low - potential - side conduction terminal is the drain.

[0043] (16th Embodiment) The leakage current detection circuit 61S of the 16th embodiment shown in FIG. 31 has a configuration in which, in the configuration of the 1st embodiment, the non-inverting input terminal and the inverting input terminal of the current sense amplifier 7S are connected to the drain and the source of the on-driving element 3, respectively. That is, instead of the gate resistor 5, the on-resistance of the on-driving element 3 is used to detect the leakage current. When configuring the leakage current detection circuit 61D, the on-resistance of the off-driving element 4 may be used.

[0044] (17th embodiment) The leakage current detection circuit 62S of the 17th embodiment shown in FIGS. 32 and 33 has a configuration in which the control block 6C in the leakage current detection circuit 38S of the 10th embodiment is replaced with a control block 6E. Similar to the 10th embodiment, when repeating the on / off control pattern of the power element 1 for each electrical angle period according to a predetermined waveform, the electrical angle period as the leakage determination period is detected by detecting the zero-crossing point of the waveform.

[0045] The control block 6E includes an on / off time measurement unit 63, an on-time register 64, an off-time register 65, and a leakage determination unit 66 instead of the on-time measurement unit 39, the on-time registers 40(n) and 40(n + 1), and the leakage determination unit 41. These constitute the low-potential side detection unit. The high-potential side detection unit can be configured in the same manner. The same applies to other embodiments.

[0046] Next, the operation of the 17th embodiment will be described. At the zero-crossing point, the duty ratio of the PWM signal becomes 50%, so the magnitude relationship between the on-time and off-time of the power element 1 is reversed before and after that. The on / off time measurement unit 63 measures the pulse widths and times of the on-pulse signal and the off-pulse signal input from the gate drive unit 35. The measurement results are stored in the on-time register 64 and the off-time register 65, respectively. The leakage determination unit 66 compares the magnitudes of the register values stored in the registers 64 and 65.

[0047] In the leakage determination unit 66, (on-time register value) < (off-time register value), then The timing when the (on-time register value) changes to be greater than the (off-time register value), or from when the (on-time register value) is greater than the (off-time register value) detect the timing when the (on-time register value) changes to be less than the (off-time register value). Since the interval between each timing corresponds to one cycle of the electrical angle, this is used as the determination period.

[0048] The leakage determination unit 66 determines that there is "leakage" between the gate and source when the count value of the counter 34 becomes "4" or more within the above determination period, for example, in the same manner as in the tenth embodiment.

[0049] When determining the zero-crossing point, a margin may be provided for the determination of a duty ratio of 50%. For example, a value obtained by adding or subtracting a margin value to the on-time register value may be compared with the off-time register value, or a value obtained by adding or subtracting a margin value to the off-time register value may be compared with the on-time register value. Also, in order to prevent a short circuit between the upper and lower arms, a dead time, which is a period when both are off simultaneously, is given, so that it can be similarly applied even when the duty ratio deviates from 50%.

[0050] (The 18th embodiment) The leakage current detection circuit 67S of the 18th embodiment shown in FIG. 34 has a configuration in which the control block 6E in the leakage current detection circuit 62S of the 17th embodiment is replaced with a control block 6F. In the control block 6F, the on / off time measurement unit 63, the on-time register 64, the off-time register 65, and the leakage determination unit 66 of the control block 6E are replaced with a clock generation circuit 68, a counter 69, and a leakage determination unit 70.

[0051] The counter 69 counts the number of clock pulses output by the clock generation circuit 68, notifies the leakage determination circuit 70 when the count value reaches a predetermined value, and resets the count value. For example, if the rotation speed of a two-pole motor is 3000 rpm and the carrier frequency of PWM control is 10 kHz, the predetermined value may be set to 200 or more. The leakage determination circuit 70 uses the interval of the notification from the counter 69 as the determination period. The determination period is, for example, a time sufficiently longer than one cycle of the electrical angle described above.

[0052] (Embodiment 19) The leakage current detection circuit 71S of the 19th embodiment shown in FIG. 35 has a configuration in which the control block 6F in the leakage current detection circuit 67S of the 18th embodiment is replaced with a control block 6G. In the control block 6G, the clock generation circuit 68 is deleted, and the counter 69 counts the number of pulse outputs of the on signal or off signal output from the gate drive unit 35, and notifies the leakage determination unit 70 in the same manner as in the 18th embodiment. That is, the predetermined value of the counted value of the number of pulse outputs becomes the determination period.

[0053] (Embodiment 20) The leakage current detection circuit 72S of the 20th embodiment shown in FIG. 36 has a configuration in which the control block 6G in the leakage current detection circuit 71S of the 19th embodiment is replaced with a control block 6H. The control block 6G is composed of a counter 34, a gate drive unit 35, and a leakage determination unit 73. The PWM signal generation circuit 74 generates a PWM signal based on the AC voltage command Vx and the electrical angle information θ generated by the internal carrier counter, and outputs it to the gate drive unit 35. The electrical angle information θ is input to the leakage determination unit 73, and based on the electrical angle information θ, one cycle of the electrical angle is detected in the same manner as in the 17th embodiment and used as the determination period.

[0054] (Embodiment 21) The leakage current detection circuit 75S of the 21st embodiment shown in FIG. 37 detects the terminal voltage of the gate resistor 5H by A / D conversion using A / D converters 76H and 76L in a configuration having gate resistors 5H and 5L as in the 4th embodiment. The input terminal of the A / D converter 76H is connected to the drain of the on-side drive element 3, and the input terminal of the A / D converter 76L is connected to the common connection point of the gate resistors 5H and 5L. The reference potential of each of the A / D converters 76H and 76L is ground.

[0055] The A / D-converted data is stored in registers 77H and 77L respectively, and these register values are input to the subtraction circuit 78. If the subtraction circuit 78 subtracts the register value of the register 77L from the register value of the register 77H, the terminal voltage of the gate resistor 5H can be detected, and the current flowing through the gate resistor 5H can be detected from that terminal voltage.

[0056] (Other Embodiments) The power element is not limited to MOSFETs or IGBTs. The counter value etc. of the counter for determining the leakage current may be changed as appropriate. Although the present disclosure has been described based on the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and further other combinations and forms including only one element, more than one element, or less than one element thereof, fall within the scope and spirit of the present disclosure.

Description of Reference Numerals

[0057] In the drawings, 1 is a power element, 2 is a drive circuit, 3 is an on-side drive element, 4 is an off-side drive element, 7 is a current sense amplifier, 8 is a comparator, 10 is a mask circuit, and 11 is a leakage current detection circuit.

Claims

1. Regarding a semiconductor element (1, 52) including a high-potential-side conduction terminal, a low-potential-side conduction terminal, and a control terminal that is arranged in an insulated state from these terminals and to which a signal for controlling the conduction state between both terminals is input, a low-potential-side setting circuit (10S) that sets a period during which a charging current flows into the control terminal as a non-detectable period when turning on the semiconductor element; a low-potential-side detection unit (6A to 6H, 7S, 8S) that outputs a detection signal when detecting a leakage current flowing from the control terminal to the low-potential-side conduction terminal after the non-detectable period has elapsed; 、 a high-potential-side setting circuit (10D) that sets a period during which a discharge current flows out from the control terminal as a non-detectable period when turning off the semiconductor element; a high-potential-side detection unit (7D, 8D) that outputs a detection signal when detecting a leakage current flowing from the high-potential-side conduction terminal to the control terminal after the non-detectable period has elapsed, and comprising: the low-potential-side detection unit is connected to a charging-side resistance element (5H) arranged in a charging path to the control terminal; the high-potential-side detection unit is connected to a discharging-side resistance element (5L) arranged in a discharging path from the control terminal; the charging-side resistance element is a shunt resistance (22H) having one end connected to a power supply, which is included in a drive circuit for turning on the semiconductor element by a constant current drive method; the discharging-side resistance element is a leakage current detection circuit for a semiconductor element, which is a shunt resistance (22L) having one end connected to a ground, which is included in a drive circuit for turning off the semiconductor element by a constant current drive method.

2. The leakage current detection circuit for a semiconductor element according to claim 1, wherein both the low-potential-side detection unit and the high-potential-side detection unit are connected to a common resistance element (5) connected in series to the control terminal.

3. The leakage current detection circuit for a semiconductor element according to claim 1 or 2, comprising a filter circuit (32) for low-pass filtering the detection signal.

4. The low-potential-side detection unit (6A to 6H) includes a counter (34) that counts the number of times the leakage current is detected, and the leakage current detection circuit for a semiconductor element according to any one of claims 1 to 3, wherein when the count value of the counter reaches a predetermined value while continuously increasing each time the semiconductor element is turned on, the detection signal is output.

5. The high-potential-side detection unit (6A to 6H) includes a counter (34) that counts the number of times the leakage current is detected, The leak current detection circuit for a semiconductor device according to any one of claims 1 to 4, wherein when the count value of the counter continuously increases and reaches a predetermined value each time the semiconductor device is turned off, the detection signal is output.

6. The leak current detection circuit for a semiconductor device according to claim 4 or 5, wherein when the count value of the counter reaches the predetermined value within a predetermined time, the detection signal is output.

7. The leak current detection circuit for a semiconductor device according to claim 4 or 5, wherein when the count value of the counter reaches the predetermined value within the period during which the signal for turning the semiconductor device on and off is output a predetermined number of times, the detection signal is output.

8. The low-potential-side detection unit includes a counter (34) that counts the number of times the leak current is detected. When the count value of the counter continuously increases and reaches a predetermined value each time the semiconductor device is turned on, the detection signal is output. The leak current detection circuit for a semiconductor device according to claim 3, further comprising an on-period determination unit (37) that excludes the on period from the continuous requirement if the output period of the signal for turning on the semiconductor device is shorter than the sum of the detection-inability period and the time-constant period of the filter circuit.

9. The high-potential-side detection unit includes a counter (34) that counts the number of times the leak current is detected. When the count value of the counter continuously increases and reaches a predetermined value each time the semiconductor device is turned off, the detection signal is output. The leak current detection circuit for a semiconductor device according to claim 3, further comprising an off-period determination unit that excludes the off period from the continuous requirement if the output period of the signal for turning off the semiconductor device is shorter than the sum of the detection-inability period and the time-constant period of the filter circuit.

10. When the semiconductor device is being on-off controlled according to a predetermined waveform for each electrical angle period. The leak current detection circuit for a semiconductor device according to any one of claims 4, 5, 8, or 9, wherein the low-potential-side detection unit (6C, 6E, 6H) includes a leak determination unit (41) that outputs the detection signal when the count value of the counter reaches the predetermined value within one electrical angle period.

11. When the semiconductor device is being on-off controlled according to a predetermined waveform for each electrical angle period. The low potential side detection unit (6C, 6E, 6H) is provided with a leak determination unit (44) that outputs the detection signal when a state where the count value of the counter reaches the predetermined value within one electrical angle cycle continues over a plurality of electrical angle cycles. The leak current detection circuit for a semiconductor element according to any one of claims 4, 5, 8, or 9.

12. The low potential side detection unit (6E, 6H) determines the one electrical angle cycle based on a zero cross point at which the polarity of the signal for on-off control changes. The leak current detection circuit for a semiconductor element according to claim 10 or 11.

13. It includes a signal output unit (74) that outputs the signal for on-off control. The low potential side detection unit (6H) determines the one electrical angle cycle based on the information of the electrical angle cycle input from the signal output unit. The leak current detection circuit for a semiconductor element according to any one of claims 10 to 12.

14. The low potential side detection unit is on-driven when turning on the semiconductor element, and detects a leak current using the on-resistance of an on-drive element (3) that allows a charging current to flow into the control terminal. The leak current detection circuit for a semiconductor element according to claim 1.

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