Semiconductor device

Abstract

A semiconductor device is provided with an insulation layer, a semiconductor element, a wiring layer, and a sealing resin. The insulation layer has a main surface and a reverse surface set away from each other in the thickness direction, and has formed therein a penetration part extending in the thickness direction. The semiconductor element has an electrode corresponding to the penetration part and is in contact with the main surface. The wiring part includes a linking part that is housed in the penetration part and is in contact with the electrode, and a main part that is continuous from the linking part and that is positioned on the reverse surface. The sealing resin is in contact with the main surface and covers the semiconductor element. The electrode has a connection surface facing the linking part. The connection surface includes a first region that is exposed from the insulation layer by the penetration part, and a second region in contact with the insulation layer. The surface roughness of the first region is higher than the surface roughness of the second region.

Description

Technical Field

[0001] The present disclosure relates to Semiconductor device this.

Background Art

[0002] With the recent miniaturization of electronic devices, the miniaturization of semiconductor devices used in such electronic devices has been progressing. In response to such trends, there is known a semiconductor device including a sealing resin, an insulating layer laminated on the sealing resin, an electrode exposed from the insulating layer, a semiconductor element covered with the sealing resin and the insulating layer, and a wiring layer connected to the electrode and disposed in the insulating layer. By having such a configuration for the semiconductor device, miniaturization of the device can be achieved. Further, since the wiring layer of the semiconductor device can be freely provided, the device has an advantage that it can flexibly respond to the wiring pattern of a wiring board to be mounted.

[0003] Patent Document 1 discloses an example of a method for manufacturing such a semiconductor device. The manufacturing method includes a step of embedding a semiconductor element having an electrode in a sealing resin (a cured body in Patent Document 1), a step of forming an insulating layer (a buffer coat film in Patent Document 1) in contact with the semiconductor element and the sealing resin, and a step of forming a wiring layer connected to the electrode. In the step of embedding the semiconductor element in the sealing resin, the electrode is made to be exposed from the sealing resin. In the step of forming the insulating layer, an opening is formed in the insulating layer by photolithography patterning. The electrode is exposed from the opening formed in the insulating layer. In the step of forming the wiring layer, a plating layer including a portion connected to the electrode and accommodated in the opening is formed. The plating layer is an element constituting the wiring layer.

[0004] In the process of forming a wiring layer, voids may occur between the electrode of a semiconductor element and the wiring layer connected to the electrode. If the scale of void generation becomes relatively large, there is a risk of inhibiting the electrical connection between the semiconductor element and the wiring layer. Therefore, it is desirable to suppress the scale of void generation by further improving the adhesion of the wiring layer to the electrode.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In view of the above circumstances, an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the same that can further improve the adhesion of a wiring layer to an electrode of a semiconductor element.

Means for Solving the Problems

[0007] According to a first aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first insulating layer having a first main surface and a first back surface spaced apart from each other in a thickness direction, and a first through-hole extending in the thickness direction; a semiconductor element having an electrode corresponding to the first through-hole and in contact with the first main surface; and a first wiring layer including a first connecting portion accommodated in the first through-hole and in contact with the electrode, a first main portion connected to the first connecting portion and disposed on the first back surface. The electrode has a connection surface facing the first connecting portion, and the connection surface includes a first region exposed from the first insulating layer by the first through-hole and a second region in contact with the first insulating layer. The surface roughness of the first region is greater than the surface roughness of the second region.

[0008] Preferably, the first wiring layer has a first base layer in contact with the first insulating layer and a first plating layer covering the first base layer, and the first plating layer is in contact with the first region.

[0009] Preferably, the first insulating layer is made of a material containing a thermosetting synthetic resin and an additive containing a metal element constituting the first base layer.

[0010] Preferably, the first insulating layer has a groove portion recessed from the first back surface and connected to the first through portion, and the first main portion is disposed in the groove portion.

[0011] Preferably, the first main portion has a recessed portion recessed in the thickness direction, and the recessed portion extends along the direction in which the groove portion extends.

[0012] Preferably, the first insulating layer has a first inner peripheral surface defining the first through portion, and the first inner peripheral surface is covered by the first base layer and is inclined with respect to the first main surface.

[0013] Preferably, the first through portion has a first cross section orthogonal to the thickness direction, and the area of the first cross section increases from the first main surface toward the first back surface.

[0014] Preferably, the semiconductor device further includes a protective layer covering the first back surface and the first main portion. The protective layer has an opening penetrating in the thickness direction, and a part of the first main portion is exposed from the protective layer through the opening.

[0015] Preferably, the semiconductor device further includes a terminal, and the terminal is joined to a part of the first main portion exposed from the protective layer through the opening. Also, the terminal protrudes from the protective layer in the thickness direction.

[0016] Preferably, the terminal is made of a material containing tin.

[0017] Preferably, the semiconductor device has a second front surface and a second back surface that are spaced apart from each other in the thickness direction, a second through-hole extending in the thickness direction is formed, and the second front surface is in contact with the first back surface; a second insulating layer; a second connecting portion housed in the second through-hole and connected to the first main portion; and a second main portion connected to the second connecting portion and disposed on the second back surface. The first main portion is covered by the second insulating layer. When viewed along the thickness direction, at least a part of the second through-hole overlaps the first main portion.

[0018] Preferably, when viewed along the thickness direction, the second main portion includes a portion overlapping the first main portion and extends along a direction different from the direction in which the first main portion extends.

[0019] Preferably, the second wiring layer has a second base layer in contact with the second insulating layer and a second plating layer covering the second base layer. At the second connecting portion, the second plating layer is in contact with the first main portion.

[0020] Preferably, the second insulating layer is made of a material including a thermosetting synthetic resin and an additive containing a metal element constituting the second base layer.

[0021] Preferably, the second insulating layer has a second inner peripheral surface defining the second through-hole, and the second inner peripheral surface is covered by the second base layer and is inclined with respect to the second front surface.

[0022] Preferably, the second through-hole has a second cross-section orthogonal to the thickness direction, and the area of the second cross-section increases from the second front surface toward the second back surface.

[0023] According to a second aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The manufacturing method includes: embedding a semiconductor element having an electrode in a sealing resin so that the electrode is exposed; forming an insulating layer laminated on the sealing resin and covering the electrode; and forming a wiring layer having a connection portion embedded in the insulating layer and connected to the electrode, and a main portion connected to the connection portion. The insulating layer is made of a material including a thermosetting synthetic resin and an additive containing a metal element that constitutes a part of the wiring layer. The step of forming the wiring layer includes: (a) forming, by laser irradiation, a through-hole that exposes a part of the surface of the electrode from the insulating layer, and a groove that is recessed from the surface of the insulating layer and connected to the through-hole, in the insulating layer; (b) depositing, on the insulating layer, an underlayer that covers an inner peripheral surface of the insulating layer defining the through-hole and the groove and contains the metal element; and (c) forming a plating layer that covers the underlayer. The step of depositing the underlayer includes forming irregularities on a part of the surface of the electrode exposed from the insulating layer at the through-hole by the laser irradiation.

[0024] Preferably, the step of forming the plating layer includes forming the plating layer by at least one of electroless plating or electrolytic plating.

Advantages of the Invention

[0025] According to the semiconductor device and the method of manufacturing the same according to the present disclosure, it is possible to further improve the adhesion of the wiring layer to the electrode of the semiconductor element.

[0026] Other features and advantages of the present disclosure will become more apparent from the following detailed description based on the accompanying drawings.

Brief Description of the Drawings

[0027]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Embodiments for Carrying Out the Invention

[0028] Embodiments according to the present disclosure will be described based on the accompanying drawings.

[0029] Based on FIGS. 1 to 10, a semiconductor device A10 according to the first embodiment will be described. The semiconductor device A10 includes a first insulating layer 11, a plurality of first wiring layers 21, a semiconductor element 30, a sealing resin 41, a protective layer 42, and a plurality of terminals 50. The semiconductor device A10 is surface-mounted on a wiring board. The semiconductor device A10 includes a single semiconductor element 30. Alternatively, the semiconductor device A10 may include a plurality of semiconductor elements 30. As an example, the plurality of semiconductor elements 30 include a laser diode and a switching element such as a MOSFET. In this configuration, when the switching element is driven, the laser diode emits light in pulses at intervals of several ns. By using such a semiconductor device A10, it is possible to explore an object located at a relatively long distance, similar to a radar. Such a exploration technique is called LIDAR (Laser Imaging Detection and Ranging). For convenience of understanding, in FIG. 1, the sealing resin 41 is transparent, and in FIG. 2, the semiconductor element 30 is further transparent with respect to FIG. 1. In FIG. 4, the protective layer 42 and a plurality of terminals 50 are transparent. In FIG. 2, the outer shape of the semiconductor element 30 is indicated by an imaginary line (two-dot chain line).

[0030] For the sake of convenience in explaining the semiconductor device A10, three directions orthogonal to each other are appropriately referred to. In the illustrated example, these are the first direction x, the second direction y, and the thickness direction z, but the present disclosure is not limited thereto. As shown in FIG. 5 and the like, the thickness direction z corresponds to, for example, the direction penetrating the thickness of the first insulating layer 11. As shown in FIG. 1, the outer shape of the semiconductor device A10 is rectangular when viewed along the thickness direction z. The first direction x is parallel to one side (the first side) of the semiconductor device A10, and the second direction y is parallel to another side (the second side orthogonal to the first side) of the semiconductor device A10. In the illustrated example, the first side is longer than the second side, but the present disclosure is not limited thereto.

[0031] As shown in FIGS. 5 and 6, the first insulating layer 11 faces the semiconductor element 30 in the thickness direction z. The first insulating layer 11 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element constituting a part (a first underlying layer 21A described later) of each of the plurality of first wiring layers 21. The synthetic resin is, for example, an epoxy resin or a polyimide. The first insulating layer 11 has a first main surface 11A, a first back surface 11B, and a plurality of end surfaces 11C. The first main surface 11A and the first back surface 11B face opposite sides in the thickness direction z. Among these, the first main surface 11A faces the semiconductor element 30. The plurality of end surfaces 11C are connected to the first main surface 11A and the first back surface 11B. Each of the plurality of end surfaces 11C faces either the first direction x or the second direction y.

[0032] As shown in FIGS. 2, 4, and 7, the first insulating layer 11 has a plurality of first through-holes 111. Each of the plurality of first through-holes 111 extends from the side where the first main surface 11A is located to the side where the first back surface 11B is located in the thickness direction z and penetrates the first insulating layer 11 in the thickness direction z. Each of the plurality of first through-holes 111 is defined by any one of a plurality of first inner peripheral surfaces 111A of the first insulating layer 11. Each of the plurality of first inner peripheral surfaces 111A is inclined with respect to the first main surface 11A. Each of the plurality of first inner peripheral surfaces 111A takes a posture of falling toward any one of the plurality of first through-holes 111 defined by the first inner peripheral surface 111A from the side where the first back surface 11B is located to the side where the first main surface 11A is located in the thickness direction z. Therefore, the cross-sectional area of each of the plurality of first through-holes 111 with respect to the thickness direction z gradually increases from the side where the first main surface 11A is located to the side where the first back surface 11B is located.

[0033] As shown in FIGS. 7 to 9, the first insulating layer 11 has a plurality of first groove portions 112. Each of the plurality of first groove portions 112 is recessed from the first back surface 11B in the thickness direction z. Each of the plurality of first groove portions 112 is connected to any one of the plurality of first through-holes 111. As shown in FIG. 4, each of the plurality of first groove portions 112 extends along a direction orthogonal to the thickness direction z. As shown in FIG. 9, a pair of side surfaces of each of the plurality of first groove portions 112 are inclined with respect to the first back surface 11B. In each of the plurality of first groove portions 112, the width b1 of the first groove portion 112 at the boundary between the pair of side surfaces and the bottom surface of the first groove portion 112 is smaller than the width b2 of the first groove portion 112 at the boundary between the pair of side surfaces and the first back surface 11B.

[0034] As shown in FIGS. 5 and 6, a plurality of first wiring layers 21 are disposed on the first insulating layer 11. The plurality of first wiring layers 21 form part of a conductive path between the wiring substrate on which the semiconductor device A10 is mounted and the semiconductor element 30. Each of the plurality of first wiring layers 21 includes a first connection portion 211 and a first main portion 212. As shown in FIGS. 2, 4, and 7, the first connection portion 211 is housed in any one of a plurality of first through portions 111 of the first insulating layer 11. The first connection portion 211 is in contact with any one of a plurality of first inner peripheral surfaces 111A that define the first through portion 111. The first connection portion 211 is connected to any one of a plurality of electrodes 31 (details will be described later) of the semiconductor element 30. As shown in FIGS. 4 to 6, the first main portion 212 is connected to the first connection portion 211 of any one of the plurality of first wiring layers 21 and is disposed on the side where the first back surface 11B is located in the first insulating layer 11. More specifically, the first main portion 212 is disposed in any one of a plurality of first groove portions 112 of the first insulating layer 11. The first main portion 212 is in contact with the first groove portion 112. As shown in FIGS. 7 to 9, in the semiconductor device A10, a part of the first main portion 212 of each of the plurality of first wiring layers 21 protrudes from any one of the plurality of first groove portions 112.

[0035] As shown in FIGS. 7 to 9, each of the first connection portion 211 and the first main portion 212 of each of the plurality of first wiring layers 21 has a first base layer 21A and a first plating layer 21B. The first base layer 21A is composed of a metal element contained in an additive included in the first insulating layer 11. The first base layer 21A is in contact with the first insulating layer 11. Each of the plurality of first inner peripheral surfaces 111A of the first insulating layer 11 is covered with the first base layer 21A that forms the first connection portion 211 of any one of the plurality of first wiring layers 21. The first plating layer 21B covers the first base layer 21A of any one of the plurality of first wiring layers 21. The first plating layer 21B is made of a material containing, for example, copper (Cu). As shown in FIG. 9, the first plating layer 21B of the first main portion 212 of each of the plurality of first wiring layers 21 has a recess 212A that is recessed in the thickness direction z. The recess 212A extends along the direction in which any one of the plurality of first groove portions 112 of the first insulating layer 11 extends.

[0036] As shown in FIGS. 5 and 6, the semiconductor element 30 is disposed in contact with the first main surface 11A of the first insulating layer 11. In the semiconductor device A10, the semiconductor element 30 is of the flip chip mounting type. The semiconductor element 30 has a plurality of electrodes 31. The plurality of electrodes 31 are provided on either side in the thickness direction z of the semiconductor element 30. The plurality of electrodes 31 are provided on the side closer to the first main surface 11A in the thickness direction z. Each of the plurality of electrodes 31 is electrically connected to a circuit formed in the semiconductor element 30. Each of the plurality of electrodes 31 is composed of a single metal layer or a plurality of metal layers stacked in the thickness direction z. As shown in FIG. 7, each of the plurality of electrodes 31 has a connection surface 311. The connection surface 311 faces the same side as the first back surface 11B of the first insulating layer 11 in the thickness direction z. The first connection portion 211 of each of the plurality of first wiring layers 21 is connected to the connection surface 311 of any one of the plurality of electrodes 31. Thereby, the semiconductor element 30 is electrically connected to the plurality of first wiring layers 21. As shown in FIG. 7, the semiconductor element 30 has a passivation film 32. The passivation film 32 is in contact with the first main surface 11A of the semiconductor element 30. The passivation film 32 is in contact with each of the plurality of electrodes 31. The passivation film 32 is made of a material containing, for example, polyimide.

[0037] As shown in FIG. 7, the connection surface 311 of each of the plurality of electrodes 31 has a first region 311A and a second region 311B. The first region 311A is exposed from the first insulating layer 11 through any one of the plurality of first through holes 111 of the first insulating layer 11. In the first connection portion 211 of each of the plurality of first wiring layers 21, the first plating layer 21B of the first connection portion 211 is in contact with the first region 311A of any one of the plurality of electrodes 31. The second region 311B is covered by the first insulating layer 11. As shown in FIG. 10, on the connection surface 311 of each of the plurality of electrodes 31, the surface roughness sr1 of the first region 311A is larger than the surface roughness sr2 of the second region 311B. Here, the surface roughnesses sr1 and sr2 are the distances in the thickness direction z between the bottommost portion located most inward in the thickness direction z of the connection surface 311 of each of the plurality of electrodes 31 and the topmost portion located farthest from the bottommost portion in the thickness direction z.

[0038] As shown in FIGS. 5 and 6, the sealing resin 41 is disposed in contact with the first main surface 11A of the first insulating layer 11 and covers a part of the semiconductor element 30. The sealing resin 41 is made of a material containing, for example, a black epoxy resin. The sealing resin 41 has a plurality of side surfaces 41A. Each of the plurality of side surfaces 41A faces either the first direction x or the second direction y. Each of the plurality of side surfaces 41A is flush with one of the plurality of end surfaces 11C of the first insulating layer 11.

[0039] As shown in FIGS. 5 and 6, the protective layer 42 covers the first back surface 11B of the first insulating layer 11 and the first main portions 212 of the plurality of first wiring layers 21. When the semiconductor device A10 is mounted on a wiring board, the protective layer 42 faces the wiring board. The protective layer 42 has electrical insulation properties. The protective layer 42 is made of a material containing, for example, polyimide. As shown in FIGS. 3 and 8, the protective layer 42 has a plurality of openings 421. The plurality of openings 421 penetrate the protective layer 42 in the thickness direction z. A part of the first main portion 212 of each of the plurality of first wiring layers 21 is exposed from the protective layer 42 through one of the plurality of openings 421.

[0040] As shown in FIGS. 3 and 8, the plurality of terminals 50 are individually joined to a part of the first main part 212 of the plurality of first wiring layers 21 exposed from the plurality of openings 421 of the protective layer 42. The plurality of terminals 50 are used for mounting the semiconductor device A10 on a wiring substrate. The plurality of terminals 50 protrude from the protective layer 42 in the thickness direction z. As shown in FIG. 8, in the example shown by the semiconductor device A10, each of the plurality of terminals 50 has a base portion 51 and a bump portion 52. The base portion 51 is in contact with a part of any one of the first main parts 212 of the plurality of first wiring layers 21. The base portion 51 is composed of a plurality of metal layers laminated in the order of a nickel (Ni) layer, a palladium layer (Pd), and a gold (Au) layer in a direction away from the first back surface 11B of the first insulating layer 11 in the thickness direction z. Here, among these metal layers, the palladium layer may not be provided. The bump portion 52 is in contact with both the base portion 51 and the protective layer 42. The bump portion 52 includes a portion protruding from the protective layer 42 in the thickness direction z. The bump portion 52 is made of a material containing tin (Sn). The bump portion 52 is made of, for example, lead-free solder.

[0041] Based on FIGS. 11 to 20, an example of a manufacturing method of the semiconductor device A10 will be described. The cross-sectional positions in FIGS. 11 to 20 (excluding FIGS. 14, 15, and 17) are the same as the cross-sectional position in FIG. 5.

[0042] First, as shown in FIG. 11, the semiconductor element 30 is embedded in the encapsulating resin 81. The encapsulating resin 81 is made of a material containing a black epoxy resin. In this step, after arranging the material of the encapsulating resin 81 and the semiconductor element 30 in a mold, compression molding is performed. Thereby, the semiconductor element 30 is embedded in the encapsulating resin 81. At this time, the plurality of electrodes 31 are made to be exposed from the encapsulating resin 81.

[0043] Next, as shown in FIG. 12, an insulating layer 82 is formed on the sealing resin 81 and covers a plurality of electrodes 31 of the semiconductor element 30. The insulating layer 82 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that composes a part of a plurality of wiring layers 83 (details will be described later). The synthetic resin is an epoxy resin or a polyimide. The insulating layer 82 is formed by compression molding.

[0044] Next, as shown in FIGS. 13 to 17, a plurality of wiring layers 83 connected to the plurality of electrodes 31 of the semiconductor element 30 are formed. The plurality of wiring layers 83 correspond to the plurality of first wiring layers 21 of the semiconductor device A10. Therefore, each of the plurality of wiring layers 83 includes a first connection portion 211 and a first main portion 212. The step of forming the plurality of wiring layers 83 includes a step of depositing an underlayer 83A on the insulating layer 82 and a step of forming a plating layer 83B covering the underlayer 83A.

[0045] First, as shown in FIG. 14, an underlying layer 83A is deposited on the insulating layer 82. The underlying layer 83A is composed of a metal element contained in an additive included in the insulating layer 82. In this step, as shown in FIG. 13, a plurality of through-holes 821 and a plurality of grooves 822 are formed in the insulating layer 82. The plurality of through-holes 821 penetrate the insulating layer 82 in the thickness direction z. Each of the plurality of through-holes 821 exposes a part of the surface (connection surface 311) of any one of the plurality of electrodes 31 of the semiconductor element 30 from the insulating layer 82. Each of the plurality of grooves 822 is recessed from the surface 82A of the insulating layer 82 and is connected to any one of the plurality of through-holes 821. The surface 82A corresponds to the first back surface 11B of the first insulating layer 11. The plurality of through-holes 821 and the plurality of grooves 822 are formed by performing laser irradiation on the insulating layer 82 while performing image recognition of the positions of the plurality of electrodes 31 with an infrared camera. The laser irradiation position in the insulating layer 82 is corrected one by one based on the position information of the plurality of electrodes 31 obtained by image recognition. The laser is an ultraviolet laser having a wavelength of 355 nm and a beam diameter of 17 μm. As shown in FIG. 15, when forming the plurality of through-holes 821, irregularities 31A are formed by laser irradiation on a part of the surface (the first region 311A of the connection surface 311) of any one of the plurality of electrodes 31 exposed from the insulating layer 82 in each of the plurality of through-holes 821. By performing laser irradiation on the insulating layer 82, the metal element contained in the additive included in the insulating layer 82 is excited. As a result, an underlying layer 83A is formed that covers the inner peripheral surface 821A of the insulating layer 82 that individually defines the plurality of through-holes 821 and the plurality of grooves 822.

[0046] Next, as shown in FIG. 17, a plating layer 83B is formed to cover the underlying layer 83A. The plating layer 83B is made of a material containing copper. The plating layer 83B is formed by electroless plating, electrolytic plating, or a combination thereof. As a result, as shown in FIG. 16, a first connection portion 211 of any one of the plurality of wiring layers 83 is formed in each of the plurality of through-holes 821. At the same time, a first main portion 212 of any one of the plurality of wiring layers 83 is formed in each of the plurality of grooves 822. Thus, the plurality of wiring layers 83 are formed.

[0047] Next, as shown in FIG. 18, a protective layer 84 is formed on the insulating layer 82 and covers the first main portions 212 of the plurality of wiring layers 83. The protective layer 84 has a plurality of openings 841 penetrating in the thickness direction z. First, photosensitive polyimide is applied to the surface of the insulating layer 82 and the surfaces of the plurality of wiring layers 83 using a spin coater. Next, a plurality of openings 841 are formed in the photosensitive polyimide by photolithographic patterning. As a result, a part of the first main portion 212 of each of the plurality of wiring layers 83 is exposed from the protective layer 84 through one of the plurality of openings 841.

[0048] Next, as shown in FIG. 19, a plurality of terminals 50 individually joined to a part of the first main portions 212 of the plurality of wiring layers 83 exposed through the plurality of openings 841 of the protective layer 84 are formed. First, the bases 51 of the plurality of terminals 50 shown in FIG. 8 are formed. The bases 51 are formed by electroless plating. Next, the bump portions 52 of the plurality of terminals 50 shown in FIG. 8 are formed. The bump portions 52 are formed by melting a conductive material containing tin such as lead-free solder by reflow and then solidifying it by cooling. Thus, the plurality of terminals 50 are formed.

[0049] Finally, as shown in FIG. 20, the encapsulating resin 81, the insulating layer 82, and the protective layer 84 are cut along the cutting line CL with a dicing blade or the like to be divided into a plurality of individual pieces. Each of the individual pieces includes one semiconductor element 30 and a plurality of wiring layers 83 connected thereto. The encapsulating resin 81, the insulating layer 82, and the protective layer 84 that have become individual pieces in this step correspond to the encapsulating resin 41, the first insulating layer 11, and the protective layer 42 of the semiconductor device A10. Through the above steps, the semiconductor device A10 is manufactured.

[0050] Next, the operation and effect of the semiconductor device A10 will be described.

[0051] The first connection part 211 of the first wiring layer 21 of the semiconductor device A10 is accommodated in the first through part 111 of the first insulating layer 11 and is connected to the electrode 31 of the semiconductor element 30. The electrode 31 has a connection surface 311 including a first region 311A and a second region 311B. The first region 311A is exposed from the first insulating layer 11 at the first through part 111. The second region 311B is covered by the first insulating layer 11. The first connection part 211 is in contact with the first region 311A. As shown in FIG. 10, the surface roughness sr1 of the first region 311A is larger than the surface roughness sr2 of the second region 311B. Thereby, the surface area per unit area of the first region 311A becomes larger than the surface area per unit area of the second region 311B. For this reason, the contact area of the first connection part 211 with respect to the first region 311A increases. Furthermore, the anchoring effect of the first connection part 211 with respect to the first region 311A appears. Therefore, according to the semiconductor device A10, it is possible to further improve the adhesion of the wiring layer (first wiring layer 21) to the electrode 31 of the semiconductor element 30.

[0052] In the step of forming the wiring layer 83 according to the manufacturing method of the semiconductor device A10, the step of depositing the underlying layer 83A on the insulating layer 82 is included. In this step, by forming the through part 821 for exposing a part of the surface (connection surface 311) of the electrode 31 of the semiconductor element 30 from the insulating layer 82 by laser irradiation, the underlying layer 83A covering the inner peripheral surface 821A of the insulating layer 82 defining the through part 821 is deposited. At this time, as shown in FIG. 15, irregularities 31A are formed on a part of the surface of the electrode 31 exposed from the insulating layer 82 at the through part 821 by the laser. Thereby, the surface of the electrode 31, that is, the connection surface 311 of the electrode 31 can be configured to include the first region 311A and the second region 311B.

[0053] Furthermore, when forming the through part 821 in the insulating layer 82, while recognizing the position of the electrode 31, the insulating layer 82 is irradiated with laser. Thereby, the first region 311A and the second region 311B are configured to be accurately divided on the surface (connection surface 311) of the electrode 31.

[0054] In the method for manufacturing the semiconductor device A10, by including the step of depositing the underlying layer 83A on the insulating layer 82, the first inner peripheral surface 111A that defines the first through-hole 111 of the first insulating layer 11 is covered by the first underlying layer 21A. The first inner peripheral surface 111A is inclined with respect to the first main surface 11A of the first insulating layer 11. Further, the cross-sectional area of the first through-hole 111 in the thickness direction z gradually increases from the side where the first main surface 11A is located toward the side where the first back surface 11B is located. This is a configuration obtained by performing laser irradiation from the surface 82A of the insulating layer 82 toward the surface (connection surface 311) of the electrode 31 when forming the through-hole 821 in the insulating layer 82.

[0055] In the step of depositing the underlying layer 83A on the insulating layer 82, in addition to the through-hole 821, a groove portion 822 that is recessed from the surface 82A of the insulating layer 82 and is connected to the through-hole 821 is formed in the insulating layer 82 by laser irradiation. As a result, the underlying layer 83A that covers the groove portion 822 is deposited. Therefore, patterning of the wiring layer 83 can be freely performed by laser irradiation.

[0056] In the step of forming the wiring layer 83 according to the method for manufacturing the semiconductor device A10, the step of forming a plating layer 83B that covers the underlying layer 83A is included. In this step, the plating layer 83B is formed by electroless plating, electrolytic plating, or a combination thereof. Among these formation methods for the plating layer 83B, the formation method by electroless plating does not require providing a conductive path necessary for performing the electrolytic plating on the surface 82A of the insulating layer 82 as compared with the formation method by electrolytic plating. Therefore, the wiring layer 83 can be formed more efficiently.

[0057] In the semiconductor device A10, a protective layer 42 and terminals 50 are provided. The protective layer 42 covers the first back surface 11B of the first insulating layer 11 and the first main portion 212 of the first wiring layer 21. The protective layer 42 has an opening 421 through which a part of the first main portion 212 is exposed from the protective layer 42. The terminal 50 is joined to a part of the first main portion 212 exposed from the protective layer 42 at the opening 421 and protrudes in the thickness direction from the protective layer 42. Thereby, when the semiconductor device A10 is mounted on a wiring board, the positioning accuracy of the semiconductor device A10 with respect to the wiring board can be improved.

[0058] Furthermore, by adopting the terminal 50 made of a material containing tin, when the semiconductor device A10 is mounted on a wiring board, at least a part of the terminal 50 is melted by reflow. Thereby, an effect (self-alignment effect) can be obtained in which the misalignment of the semiconductor device A10 with respect to the wiring board is self-repaired.

[0059] Based on FIGS. 21 to 28, the semiconductor device A20 according to the second embodiment will be described. In these figures, the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant descriptions are omitted.

[0060] In the semiconductor device A20, the configuration of the second insulating layer 12 and the plurality of second wiring layers 22, and the configuration of the protective layer 42 and the plurality of terminals 50 are different from those of the semiconductor device A10. For convenience of understanding, in FIG. 21, it penetrates through the sealing resin 41, and in FIG. 22, it further penetrates through the first insulating layer 11 and the semiconductor element 30 with respect to FIG. 21. In FIG. 24, it penetrates through the protective layer 42 and the plurality of terminals 50. In FIG. 24, the outer shape of the penetrated semiconductor element 30 is indicated by an imaginary line.

[0061] As shown in FIGS. 25 and 26, the second insulating layer 12 is disposed in contact with the first back surface 11B of the first insulating layer 11. The first insulating layer 11 is sandwiched between the second insulating layer 12 and the encapsulating resin 41 in the thickness direction z. The second insulating layer 12 is made of a material containing a thermosetting synthetic resin and an additive containing a metal element that composes a part (a second base layer 22A described later) of each of the plurality of second wiring layers 22. The synthetic resin is, for example, an epoxy resin or a polyimide. The second insulating layer 12 has a second front surface 12A, a second back surface 12B, and a plurality of end surfaces 12C. The second front surface 12A and the second back surface 12B face opposite sides in the thickness direction z. Among these, the second front surface 12A is in contact with the first back surface 11B. The plurality of end surfaces 12C are connected to the second front surface 12A and the second back surface 12B. Each of the plurality of end surfaces 12C faces either the first direction x or the second direction y. Each of the plurality of end surfaces 12C is flush with both one of the plurality of end surfaces 11C of the first insulating layer 11 and one of the plurality of side surfaces 41A of the encapsulating resin 41.

[0062] As shown in FIGS. 22, 24, and 27, the second insulating layer 12 has a plurality of second through-holes 121. Each of the plurality of second through-holes 121 extends from the side where the second front surface 12A is located to the side where the second back surface 12B is located in the thickness direction z and penetrates the second insulating layer 12 in the thickness direction z. Each of the plurality of second through-holes 121 is defined by one of the plurality of second inner peripheral surfaces 121A of the second insulating layer 12. Each of the plurality of second inner peripheral surfaces 121A is inclined with respect to the second front surface 12A. Each of the plurality of second inner peripheral surfaces 121A takes a posture of falling toward one of the plurality of second through-holes 121 defined by the second inner peripheral surface 121A from the side where the second back surface 12B is located to the side where the second front surface 12A is located in the thickness direction z. Therefore, the cross-sectional area of each of the plurality of second through-holes 121 in the thickness direction z gradually increases from the side where the second front surface 12A is located to the side where the second back surface 12B is located.

[0063] As shown in FIGS. 27 and 28, the second insulating layer 12 has a plurality of second groove portions 122. Each of the plurality of second groove portions 122 is recessed from the second back surface 12B in the thickness direction z. Each of the plurality of second groove portions 122 is connected to any one of the plurality of second through portions 121. As shown in FIG. 24, each of the plurality of second groove portions 122 extends along a direction orthogonal to the thickness direction z. As shown in FIG. 28, a pair of side surfaces of each of the plurality of second groove portions 122 is inclined with respect to the second back surface 12B. In each of the plurality of second groove portions 122, the width b3 of the second groove portion 122 at the boundary between the pair of side surfaces and the bottom surface of the second groove portion 122 is smaller than the width b4 of the second groove portion 122 at the boundary between the pair of side surfaces and the second back surface 12B.

[0064] As shown in FIGS. 25 and 26, the plurality of second wiring layers 22 are disposed in the second insulating layer 12. The plurality of second wiring layers 22, together with the plurality of first wiring layers 21, form a part of the conductive path between the wiring substrate on which the semiconductor device A10 is mounted and the semiconductor element 30. Each of the plurality of second wiring layers 22 includes a second connecting portion 221 and a second main portion 222. As shown in FIGS. 22, 24, and 27, the second connecting portion 221 is accommodated in any one of the plurality of second through portions 121 of the second insulating layer 12. The second connecting portion 221 is in contact with any one of the plurality of second inner peripheral surfaces 121A that define the second through portion 121. The second connecting portion 221 is connected to the second main portion 212 of any one of the plurality of first wiring layers 21. As shown in FIGS. 24 to 26, the second main portion 222 is connected to the second connecting portion 221 of any one of the plurality of second wiring layers 22 and is disposed on the side where the second back surface 12B is located in the second insulating layer 12. More specifically, the second main portion 222 is disposed in any one of the plurality of second groove portions 122 of the second insulating layer 12. The second main portion 222 is in contact with the second groove portion 122. As shown in FIGS. 27 and 28, in the semiconductor device A20, a part of the second main portion 222 of each of the plurality of second wiring layers 22 protrudes from any one of the plurality of second groove portions 122.

[0065] As shown in FIGS. 22 and 24, when viewed along the thickness direction z, at least a part of each of the plurality of second through-holes 121 of the second insulating layer 12 overlaps with any one of the first main portions 212 of the plurality of first wiring layers 21. As shown in FIG. 24, when viewed along the thickness direction z, each of the second main portions 222 of the plurality of second wiring layers 22 includes a portion overlapping with any one of the first main portions 212 of the plurality of first wiring layers 21 and extends along a direction different from the direction in which the first main portion 212 extends.

[0066] As shown in FIG. 27, each of the second connection portions 221 and the second main portions 222 of the plurality of second wiring layers 22 has a second base layer 22A and a second plating layer 22B. The second base layer 22A is composed of a metal element contained in an additive included in the second insulating layer 12. The second base layer 22A is in contact with the second insulating layer 12. Each of the plurality of second inner peripheral surfaces 121A of the second insulating layer 12 is covered with the second base layer 22A forming any one of the second connection portions 221 of the plurality of second wiring layers 22. The second plating layer 22B covers any one of the second base layers 22A of the plurality of second wiring layers 22. The second plating layer 22B is made of a material containing, for example, copper. At each of the second connection portions 221 of the plurality of second wiring layers 22, the second plating layer 22B is in contact with any one of the first main portions 212 of the plurality of first wiring layers 21. As shown in FIG. 28, the second plating layer 22B of each of the second main portions 222 of the plurality of second wiring layers 22 has a recess 222A that is recessed in the thickness direction z. The recess 222A extends along the direction in which any one of the plurality of second groove portions 122 of the second insulating layer 12 extends.

[0067] As shown in FIGS. 25 and 26, the protective layer 42 covers the second back surface 12B of the second insulating layer 12 and the second main portions 222 of the plurality of second wiring layers 22. When the semiconductor device A20 is mounted on a wiring board, the protective layer 42 faces the wiring board. A part of each of the second main portions 222 of the plurality of second wiring layers 22 is exposed from the protective layer 42 through any one of the plurality of openings 421. As shown in FIG. 23, the plurality of terminals 50 are individually joined to a part of the second main portions 222 of the plurality of second wiring layers 22 exposed through the plurality of openings 421.

[0068] Next, the operation and effect of the semiconductor device A20 will be described.

[0069] The first connection portion 211 of the first wiring layer 21 of the semiconductor device A20 is accommodated in the first through portion 111 of the first insulating layer 11 and is connected to the electrode 31 of the semiconductor element 30. The electrode 31 has a connection surface 311 including a first region 311A and a second region 311B. The first region 311A is exposed from the first insulating layer 11 at the first through portion 111. The second region 311B is covered by the first insulating layer 11. The first connection portion 211 is in contact with the first region 311A. As shown in FIG. 10, the surface roughness sr1 of the first region 311A is larger than the surface roughness sr2 of the second region 311B. Therefore, also with the semiconductor device A20, it is possible to further improve the adhesion of the wiring layer (first wiring layer 21) to the electrode 31 of the semiconductor element 30.

[0070] The semiconductor device A20 further includes a second insulating layer 12 having a second main surface 12A, a second back surface 12B, and a second through portion 121, and a second wiring layer 22 having a second connection portion 221 and a second main portion 222. The second main surface 12A is in contact with the first back surface 11B of the first insulating layer 11. The second connection portion 221 is accommodated in the second through portion 121 and is connected to the first main portion 212 of the first wiring layer 21. The second main portion 222 is connected to the second connection portion 221 and is disposed on the side where the second back surface 12B is located in the second insulating layer 12. The first main portion 212 is covered by the second insulating layer 12. When viewed along the thickness direction z, at least a part of the second through portion 121 overlaps the first main portion 212. Thereby, in the semiconductor device A20, without causing a short circuit in the conduction path between the first wiring layer 21 and the second wiring layer 22, when viewed along the thickness direction z, the second main portion 222 can take an arrangement form that overlaps the first main portion 212. Therefore, according to the semiconductor device A20, a conduction path more complex than that of the semiconductor device A10 can be configured.

[0071] The present disclosure is not limited to the above-described embodiments, and the specific configurations of the respective parts in the semiconductor device can be freely designed in various ways. For example, in each embodiment, a configuration including a plurality of semiconductor elements 30 may be adopted. The type of each semiconductor element 30 can be selected according to the required application and function. Further, in the above-described embodiments, components having a rectangular outer shape when viewed along the thickness direction z are variously used, but the present disclosure is not limited thereto, and the outer shape may be, for example, circular or hexagonal.

Description of Reference Numerals

[0072] A10, A20: Semiconductor device 11: First insulating layer 11A: First main surface 11B: First back surface 11C: End face 111: First through hole 111A: First inner peripheral surface 112: First groove 12: Second insulating layer 12A: Second main surface 12B: Second back surface 12C: End face 121: Second through hole 121A: Second inner peripheral surface 122: Second groove 21: First wiring layer 21A: First underlayer 21B: First plating layer 211: First connection portion 212: First main portion 212A: Concave portion 22: Second wiring layer 22A: Second underlayer 22B: Second plating layer 221: Second connection portion 222: Second main portion 222A: Concave portion 30: Semiconductor element 31: Electrode 311: Connection surface 311A: First region 311B: Second region 32: Passivation film 41: Encapsulation resin 41A: Side surface 42: Protection layer 421: Opening 50: Terminal 51: Base portion 52: Bump portion 81: Encapsulation resin 82: Insulating layer 82A: Surface 821: Through hole 821A: Inner peripheral surface 822: Groove 83: Wiring layer 83A: Underlayer 83B: plating layer 84: protective layer 841: opening b1, b2, b3, b4: width z: thickness direction x: first direction y: second direction

Claims

1. A first insulating layer having a first main surface and a first back surface facing opposite sides in the thickness direction, and having a first through-hole extending in the thickness direction; A semiconductor element having an electrode corresponding to the first through-hole and contacting the first main surface; A first wiring layer including a first connecting portion accommodated in the first through-hole and contacting the electrode, and a first main portion connected to the first connecting portion and disposed on the first back surface; A sealing resin contacting the first main surface and covering the semiconductor element; The electrode has a connection surface facing the first connecting portion; The connection surface includes a first region exposed from the first insulating layer by the first through-hole and a second region contacting the first insulating layer; The surface roughness of the first region is greater than the surface roughness of the second region; The first insulating layer has a groove portion recessed from the first back surface and connected to the first through-hole; The first main portion is disposed in the groove portion; The first main portion has a recess recessed in the thickness direction; The semiconductor device, wherein the recess extends along the direction in which the groove portion extends.

2. The first wiring layer has a first base layer contacting the first insulating layer and a first plating layer covering the first base layer; The semiconductor device according to claim 1, wherein the first plating layer contacts the first region.

3. The semiconductor device according to claim 2, wherein the first insulating layer is made of a material including a thermosetting synthetic resin and an additive containing a metal element constituting the first base layer.

4. The first insulating layer has a first inner peripheral surface defining the first through-hole; The semiconductor device according to claim 2 or 3, wherein the first inner peripheral surface is covered by the first base layer and is inclined with respect to the first main surface.

5. The first through-hole has a first cross-section orthogonal to the thickness direction; The semiconductor device according to claim 4, wherein the area of the first cross-section increases from the first main surface toward the first back surface.

6. Further comprising a protective layer covering the first back surface and the first main portion; The protective layer has an opening penetrating in the thickness direction; The semiconductor device according to any one of claims 1 to 5, wherein a part of the first main portion is exposed from the protective layer through the opening.

7. Further comprising a terminal; The terminal is joined to a part of the first main portion exposed from the protective layer through the opening. The semiconductor device according to claim 6, wherein the terminal protrudes from the protective layer in the thickness direction.

8. The semiconductor device according to claim 7, wherein the terminal is made of a material containing tin.

9. A second insulating layer having a second main surface and a second back surface facing opposite sides in the thickness direction, a second through portion extending in the thickness direction being formed, and the second main surface being in contact with the first back surface; A second wiring layer including a second connecting portion accommodated in the second through portion and connected to the first main portion, and a second main portion connected to the second connecting portion and disposed on the second back surface; and further comprising: The first main portion is covered by the second insulating layer. The semiconductor device according to any one of claims 1 to 5, wherein at least a part of the second through portion overlaps the first main portion when viewed in the thickness direction.

10. The semiconductor device according to claim 9, wherein when viewed in the thickness direction, the second main portion includes a portion overlapping the first main portion and extends along a direction different from the direction in which the first main portion extends.

11. The second wiring layer has a second base layer in contact with the second insulating layer and a second plating layer covering the second base layer. The semiconductor device according to claim 10, wherein the second plating layer is in contact with the first main portion at the second connecting portion.

12. The semiconductor device according to claim 11, wherein the second insulating layer is made of a material including a thermosetting synthetic resin and an additive containing a metal element constituting the second base layer.

13. The second insulating layer has a second inner peripheral surface defining the second through portion. The semiconductor device according to claim 11 or 12, wherein the second inner peripheral surface is covered by the second base layer and is inclined with respect to the second main surface.

14. The second through portion has a second cross section orthogonal to the thickness direction. The semiconductor device according to claim 13, wherein the area of the second cross section increases from the second main surface toward the second back surface.

Images