Semiconductor device test board

Abstract

To provide a test board that accommodates a semiconductor device in a singulation die state and is carried to an inside of a testing apparatus, with which it is possible to adjust and uniformize test temperatures of a plurality of semiconductor devices accommodated in the inside.SOLUTION: The present invention relates to a semiconductor device test board that accommodates a plurality of semiconductor devices and is carried to an inside of a testing apparatus. Specifically, the present invention provides a semiconductor device test board comprising: an accommodation unit in which is formed a plurality of semiconductor device accommodation grooves that accommodate a plurality of semiconductor devices, respectively; and a lead unit that is removably joined to the accommodation unit, the lead unit including a heat transfer part including: a first heat transfer edge that is exposed to an outside of the lead unit while being joined to the accommodation unit, and a second heat transfer edge that extends from the first heat transfer edge and is exposed to a temperature adjustment region that is partitioned so as to be provided with at least one of the plurality of semiconductor device accommodation grooves.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a test board for accommodating and testing semiconductor devices, and more particularly, to a test board that is carried into a test apparatus including a temperature control device.

Background Art

[0002] In recent years, as the required capacity and speed in the field of semiconductor devices have increased, various attempts have been made to mount more capacious memories within a narrow area and drive them efficiently. Along with this, semiconductor devices having a three-dimensional structure have been researched and developed for improving the integration degree of semiconductor devices. Among them, semiconductor devices applying the TSV (Through Silicon Via) method have attracted attention. Such semiconductor devices having a three-dimensional structure enable ultra-high density design, and by utilizing TSVs as connection line paths, the connection line length between circuits can be reduced, and various advantages such as an increase in signal speed and a decrease in power consumption can be obtained.

[0003] Conventional test apparatuses for testing semiconductor devices used a method of directly or indirectly applying pressure to the device during test execution in order to contact the semiconductor device with a tester. Therefore, when testing a device without packaging, damage may occur to the device. In order to prevent this, a test board capable of minimizing the impact applied to the semiconductor device during the test process has been proposed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention provides a test board for a semiconductor device in a test board that houses a semiconductor device in a singulation die state and is carried into a test apparatus, and can uniformly adjust the test temperature of a plurality of semiconductor devices housed therein.

Means for Solving the Problems

[0006] In order to achieve the above object, a semiconductor device test board according to an embodiment disclosed in the present invention includes a plurality of semiconductor device accommodation grooves that respectively accommodate a plurality of semiconductor devices, and a heat transfer unit that is detachably coupled to the accommodation unit. Cover It includes a part.

[0007] The heat transfer unit is Cover In a state where the part is coupled to the accommodation part, Cover A first heat transfer end portion that is exposed outside the part, and a second heat transfer end portion that extends from the first heat transfer end portion and is exposed to a temperature adjustment region partitioned so as to include at least one of the plurality of semiconductor device accommodation grooves.

[0008] The plurality of semiconductor device accommodation grooves formed in the accommodation part are partitioned by a plurality of temperature adjustment regions, and the heat transfer unit may be formed in a plurality and respectively correspond to the plurality of temperature adjustment regions. Desirably, each temperature adjustment region may be partitioned so as to include one semiconductor device accommodation groove.

[0009] The plurality of heat transfer units may include a heat conductor that extends from the first heat transfer end portion to the second heat transfer end portion. Cover In a state where the part is coupled to the accommodation part, at least a part of the second heat transfer end portion may contact a semiconductor device accommodated in the temperature adjustment region, and the temperature of the semiconductor device may be adjusted by a heat conduction method.

[0010] A plurality of temperature adjustment regions may be formed, and may include a plurality of outer peripheral temperature adjustment regions partitioned so as to include at least one outer peripheral semiconductor device accommodation groove formed in the outer peripheral portion of the accommodation part, and a plurality of inner peripheral temperature adjustment regions partitioned so as not to include the outer peripheral semiconductor device accommodation groove.

[0011] In order to uniformly adjust a plurality of semiconductor devices in both the outer peripheral temperature adjustment region and the inner peripheral temperature adjustment region, heat conductors corresponding to the outer peripheral temperature adjustment region and the inner peripheral temperature adjustment region may be formed differently. As an example, the heat conductor in the outer peripheral temperature adjustment region may have a length up to a first heat transfer end portion shorter than that of the heat conductor in the inner peripheral temperature adjustment region. As another example, the heat conductor in the outer peripheral temperature adjustment region may have an average cross-sectional area from a first heat transfer end portion wider than that of the heat conductor in the inner peripheral temperature adjustment region to a second heat transfer end portion. As another example, the heat conductor in the outer peripheral temperature adjustment region may have a higher thermal conductivity than that of the heat conductor in the inner peripheral temperature adjustment region.

[0012] The heat conductor may have a cross-sectional area at the second heat transfer end portion wider than that at the first heat transfer end portion.

[0013] The semiconductor test board may preferably further include a plurality of temperature sensors for measuring the temperatures of the semiconductor devices respectively inside the semiconductor device accommodation grooves. The board temperature adjustment unit may individually control the temperatures of the plurality of semiconductor devices based on the temperatures measured by the temperature sensors.

[0014] The semiconductor test board may further include a circuit portion that forms a circuit for electrically connecting the semiconductor device and the tester. Cover The portion selectively pressurizes at least a part of the accommodation portion, Cover In the pressurized state by the portion, the circuit portion may be selectively connected to the semiconductor device in the accommodation portion.

[0015] The accommodation portion may be configured to include a pocket unit in which a semiconductor device accommodation groove is formed, and a socket base on which the pocket unit is provided to be relatively movable. The lead portion pressurizes the pocket unit when coupled to the upper side of the accommodation portion, the position of the pocket unit is changed, and the semiconductor device accommodated in the pocket unit can be connected to the circuit portion.

[0016] The circuit portion may include device contact terminals that are selectively connected to semiconductor devices housed in the housing portion. Cover If the position of the pocket unit is changed by pressurizing the portion, the device contact terminals can be exposed inside the pocket unit and electrically connected to the semiconductor device. An elastic member may be provided between the socket base and the pocket unit, and the pocket unit may be elastically supported on the socket base.

[0017] In other embodiments disclosed in the present invention, the housing portion Cover At least a part of the second heat transfer end portion is in contact with the portion in a state where the portion is coupled to the housing portion Cover It may further include a plurality of housing portion heat conductors having a portion contact portion that contacts the portion and a semiconductor device contact portion that contacts the semiconductor device. This can adjust the temperature of the semiconductor device by a heat conduction method together with heat conductors included in each of the plurality of heat transfer portions and extending from the first heat transfer end portion to the second heat transfer end portion.

[0018] Alternatively, in other embodiments disclosed in the present invention, the plurality of heat transfer portions may each include a heat transfer flow path extending from the first heat transfer end portion to the second heat transfer end portion. In this embodiment, Cover The heat transfer medium is supplied to the semiconductor device groove in the temperature adjustment region through the heat transfer flow path in a state where the portion is coupled to the housing portion, and the temperature of the semiconductor device can be adjusted by a heat convection method.

Advantages of the Invention

[0019] According to the embodiments disclosed in the present invention, since the test board includes a plurality of heat transfer portions corresponding to a plurality of temperature adjustment regions, it can be controlled at a uniform temperature without being affected by the positions where a plurality of semiconductor devices are housed.

[0020] Also, by forming the heat transfer path length, cross-sectional area, and thermal conductivity to be different depending on the position of the heat transfer portion, a plurality of semiconductor devices can be heated / cooled at a uniform speed.

Brief Description of the Drawings

[0021]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Mode for Carrying Out the Invention

[0022] Hereinafter, embodiments of a test board for a semiconductor device according to the present invention will be described with reference to the drawings. In the following description, the positional relationship of each component is described based on the drawings in principle. And, the drawings may be shown with the structure of the invention simplified or exaggerated, if necessary, for the convenience of explanation. Therefore, the present invention is not limited to the content shown in the drawings, and of course, various devices can be added, changed, or omitted and implemented.

[0023] In the following embodiments, the "semiconductor device" may mean various semiconductor device elements. In this embodiment, as an example, a high-bandwidth memory element (HBM, High Bandwidth Memory) configured by the TSV (Through Silicon Via) method will be described as an example, but the present invention is not limited thereto. Semiconductor devices manufactured by other methods may also be included, or it may mean including non-memory elements that are not memory elements.

[0024] And "electrically connected" does not only mean a state where electricity is substantially conducted, but may also be interpreted to include a state where a connection path is formed so that an electrical signal can be transmitted when the electrical signal is applied.

[0025] And when a specific configuration is "connected", "coupled", or "pressurized" to another configuration, it may be interpreted to include not only the case where the said configuration actively "connects", "couples", or "pressurizes", but also the case where it is "connected", "coupled", or "pressurized" manually or by reaction due to the action of another configuration.

[0026] Furthermore, when two different configurations are "connected", "coupled", or "pressurized" in an "electrical" or "mechanical" manner, it may be interpreted to include not only the case where the two configurations are directly connected, coupled, or pressurized, but also the case where they are indirectly connected, coupled, or pressurized through another configuration.

[0027] Hereinafter, with reference to FIGS. 1 to 6, the structure of a test board according to an embodiment of the present invention will be specifically described.

[0028] FIG. 1 is a perspective view showing a test board according to an embodiment of the present invention. The test board 10 according to this embodiment is configured to be used in the process of testing a plurality of semiconductor devices 20. Here, the plurality of semiconductor devices 20 may be singulation dies obtained by dicing a stacked wafer structure, and may be elements in a stage prior to the packaging process. As an example, the device may be a high bandwidth memory element configured by a TSV method.

[0029] In a conventional test apparatus, when a test board is carried into a test chamber, the temperature in the test chamber is adjusted to a test temperature via a heater and / or a blower provided on the inner wall of the chamber. However, since such a temperature adjustment method is to heat / cool the space itself in the test chamber, the test temperature may vary depending on the position where the semiconductor device 20 is accommodated in the test board. The test board 10 according to the embodiment of the present invention is configured such that a plurality of semiconductor devices 20 can be controlled at a uniform temperature.

[0030] Specifically, as shown in FIG. 1, the test board 10 according to this embodiment includes a housing portion 100 that houses a plurality of semiconductor devices 20, and a Cover portion 300 that is detachably provided above the housing portion 100.

[0031] The housing part 100 houses a plurality of semiconductor devices 20 in a plurality of semiconductor device housing grooves 121 formed in an N×M array structure. The plurality of semiconductor device housing grooves 121 formed in the housing part 100 are partitioned into a plurality of temperature control regions 150 each including at least one semiconductor device housing groove 121. The plurality of temperature control regions 150 include a plurality of outer peripheral temperature control regions 151 partitioned to include at least one outer peripheral semiconductor device housing groove formed in the outer peripheral part of the housing part 100 and a plurality of inner peripheral temperature control regions 152 partitioned not to include an outer peripheral semiconductor device housing groove. As shown in FIG. 1, the plurality of temperature control regions 150 may be partitioned to each include one semiconductor device housing groove 121.

[0032] Cover The part 300 may be configured as a plate-like structure coupled to the upper side of the housing part 100. Cover During the test process, the part 300 is coupled to the upper side of the housing part 100 to protect the housed semiconductor devices 20 during the transfer and test of the test board 10 and prevent the semiconductor devices 20 from being removed. Cover A clamping structure 301 to be clamped with the housing part 100 is formed at the edge of the part 300 and can be selectively detachably coupled according to the process stage. In the embodiment shown in FIG. 1 Cover The part 300 is configured using a plate-shaped member in which no other opening is formed, but it is also possible to configure it such that a plurality of openings are formed so that a part of the housed semiconductor device 20 is exposed.

[0033] Cover The part 300 includes a heat transfer part 330. The heat transfer part 330 is CoverIt includes a first heat transfer end 331 that is exposed outside the part 300 and a second heat transfer end 332 that extends from the first heat transfer end 331 and is exposed to the semiconductor device accommodation groove 121. The heat transfer parts 330 are formed in plural and respectively correspond to a plurality of temperature adjustment regions 150 partitioned on the accommodation part. Referring to the embodiment shown in FIG. 1, the temperature adjustment regions 150 are partitioned so as to each include one semiconductor device accommodation groove 121, and the heat transfer parts 330 are provided to correspond to the number of the semiconductor device accommodation grooves 121, that is, the number of the semiconductor devices 20, and the second heat transfer ends 332 of the heat transfer parts 330 can be respectively exposed to the corresponding temperature adjustment regions 150. The test board 10 provided with the plurality of heat transfer parts 330 exerts an effect of heating / cooling the plurality of semiconductor devices 20 more uniformly as compared with a test board provided with a single heat transfer part. When the test board has only a single heat transfer part, the plurality of semiconductor devices have to be heated / cooled collectively by the single heat transfer part having a large cross-sectional area. At this time, the larger the cross-sectional area of the heat transfer part is, the more the temperature of the inner peripheral part and the outer peripheral part may become different, and thus, a deviation in the heating / cooling rate due to the accommodation position of the semiconductor device may occur.

[0034] On the other hand, the test board 10 according to the present embodiment may further include a socket board 200. The socket board 200 forms the main body of the test board 10, and the accommodation part 100 may be fixedly provided on the upper surface of the socket board 200. As shown in FIG. 1, the socket board 200 may be composed of a plate-shaped member having an area wider than the accommodation part 100 and the Cover part 300. Cover The fastening structure 301 of the part 300 may be formed to be fastened to the socket board 200. Among the socket board 200, a portion where the accommodation part 100 is not provided can form a portion where a pushing unit pressurizes for being electrically connected to a tester terminal at a test site (see FIG. 4). Such a socket board 200 includes, as an example, a printed circuit board (PCB), and a part of the circuit part 400 described later may be formed on the socket board 200.

[0035] FIG. 2 is a cross-sectional view showing a cross-section of a partial area in which the semiconductor device 20 is housed in the test board 10 shown in FIG. 1, and FIG. 3 is a view in FIG. 2 where Cover FIG. 3 is a cross-sectional view showing a cross-section in a state where the portion 300 is coupled to the housing portion 100. Hereinafter, with reference to FIGS. 2 and 3, the housing portion 100 and Cover the structure of the portion 300 will be specifically described.

[0036] Specifically, the housing portion 100 may include a socket base 110 and a plurality of pocket units 120. The socket base 110 may be fixedly provided on the socket board 200 and may include a plurality of recess portions 111 for providing the pocket units 120. And the plurality of pocket units 120 are each provided so as to be relatively movable with respect to the socket base 110 while at least a part of each is housed in the recess portion 111, and each can form a semiconductor device housing groove 121 for housing the semiconductor device 20.

[0037] The semiconductor device accommodation groove 121 may be configured in a form with an upper opening and surrounded by the partition wall 122 of the pocket unit 120. Therefore, the semiconductor device 20 can be supported by the bottom surface of the pocket unit 120 while being accommodated in the semiconductor device accommodation groove 121. The semiconductor device accommodation groove 121 may be formed at a predetermined interval from each partition wall 122 in a state where the semiconductor device 20 is fixed. Thereby, the operation of loading or unloading the semiconductor device 20 onto the semiconductor device accommodation groove 121 can be performed. Specifically, the semiconductor device accommodation groove 121 of the pocket unit 120 may be configured to have a taper structure in which the cross-sectional area of the space gradually narrows along the direction in which the semiconductor device 20 is drawn in. In this case, the semiconductor device 20 can easily enter the upper opening of the accommodation space, the entered semiconductor device 20 can be easily guided to the fixing position on the bottom surface of the pocket unit 120, and the horizontal movement of the fixed semiconductor device 20 can be minimized. Therefore, the lower side of the semiconductor device accommodation groove 121 of the pocket unit 120 may be configured to have a tolerance of 5 to 15 μm along the outside in a state where the semiconductor device 20 is accommodated, and the upper side may be configured to have a tolerance of 20 to 50 μm.

[0038] The accommodating portion 100 is provided on the upper side Cover In a state where the portion 300 is coupled, Cover It may be configured such that at least a part thereof is pressurized by the portion 300. As shown in FIGS. 2 and 3, the accommodating portion 100 Cover In a coupled state with the portion 300 Cover The portion 300 may be configured to pressurize the pocket unit 120. The pocket unit 120 may be configured to be able to move up and down in the recess portion 111 of the socket base 110 in the vertical direction, CoverWhen the pressure member 300 presses the pocket unit 120, the position of the pocket unit 120 may be changed. At this time, the pocket unit 120 may be elastically supported on the socket base 110. For example, at least one elastic member 130 may be provided between the recessed portion 111 of the socket base 110 and the bottom surface of the pocket unit 120. Therefore, the semiconductor device 20 may be accommodated in the pocket unit 120 or may be elastically supported on the socket base 110. Cover The pressure applied to the pocket unit 120 by the pressure applying portion 300 can reduce the impact caused by the pressure applied to the pocket unit 120 when the pressure is applied to the pocket unit 120 .

[0039] Cover Specifically, the heat transfer portion 330 of the receiving portion 300 may include a heat conductor 335 extending from a first heat transfer end 331 to a second heat transfer end 332. Referring to the embodiment shown in FIG. 2 and FIG. 3, the heat transfer portion 330 may be entirely one heat conductor 335. Alternatively, the heat transfer portion 330 may be at least partially formed of the heat conductor 335. As shown in FIG. 3, the receiving portion 100 may include a heat conductor 335 extending from a first heat transfer end 331 to a second heat transfer end 332. Cover When the test board 10 is connected to the board 300, at least a portion of the second heat transfer end 332 may be in contact with the semiconductor device 20 accommodated in the semiconductor device accommodation groove 121. Cover The board temperature adjusting unit 1425 contacts the outside of the thermal conductor 335 to adjust the temperature of the semiconductor device 20 accommodated therein (see FIG. 4). At this time, the temperature of the semiconductor device 20 is adjusted by a heat conduction method using the thermal conductor 335. The board temperature adjusting unit 1425 and the semiconductor device 20 are in contact with the first heat transfer end 331 and the second heat transfer end 332 of the thermal conductor 335, respectively, so that the semiconductor device 20 is heated / cooled via the heat conduction path from the first heat transfer end 331 to the second heat transfer end 332.

[0040] In the embodiment shown in FIG. 1, since the semiconductor device accommodation grooves 121 are arranged in an N×M array structure in the accommodation portion 100, the temperature adjustment regions 150 partitioned to each include one semiconductor device accommodation groove 121 are also arranged in an N×M array structure. At this time, the inner peripheral temperature adjustment region 152 has all four sides, i.e., both sides in the row direction and the column direction, surrounded by one other temperature adjustment region 150, while the outer peripheral temperature adjustment region 151 has at least one side adjacent to the edge of the accommodation portion, so that heat can be released to the outside during the temperature adjustment process. As a result, a deviation in the heating / cooling rate may occur between the outer peripheral temperature adjustment region 151 and the inner peripheral temperature adjustment region 152. Therefore, by making the shapes or materials of the heat conductors 335 corresponding to the outer peripheral temperature adjustment region 151 and the inner peripheral temperature adjustment region 152 different, the plurality of semiconductor devices 20 can be uniformly heated / cooled regardless of the positions where they are accommodated.

[0041] For example, in the heat conduction method, the heat transfer rate is inversely proportional to the length of the heat conduction path. In this embodiment, the length of the heat conduction path corresponds to the length L from the first heat transfer end 331 to the second heat transfer end 332. Therefore, by forming the heat conductor 335 corresponding to the outer peripheral temperature adjustment region 151 such that the length L from the first heat transfer end 331 to the second heat transfer end 332 is shorter than that of the heat conductor 335 corresponding to the inner peripheral temperature adjustment region 152, the plurality of semiconductor devices 20 can be heated / cooled at a uniform rate regardless of the positions where they are accommodated.

[0042] Alternatively, for example, the heat transfer rate is proportional to the cross-sectional area of the heat conduction path. In this embodiment, the cross-sectional area of the heat conduction path corresponds to the average value of the cross-sectional areas A in the path direction from the first heat transfer end 331 to the second heat transfer end 332. Therefore, by forming the heat conductor 335 corresponding to the outer peripheral temperature adjustment region 151 such that the average value of the cross-sectional areas A from the first heat transfer end 331 to the second heat transfer end 332 is larger than that of the heat conductor 335 corresponding to the inner peripheral temperature adjustment region 152, the plurality of semiconductor devices 20 can be heated / cooled at a uniform rate regardless of the positions where they are accommodated.

[0043] Alternatively, for example, the heat transfer rate is proportional to the thermal conductivity inherent in the material forming the heat conductor 335. Therefore, by forming the heat conductor 335 corresponding to the outer peripheral temperature adjustment region 151 with a material having a higher thermal conductivity than the heat conductor 335 corresponding to the inner peripheral temperature adjustment region 152, the plurality of semiconductor devices 20 can be heated / cooled at a uniform rate regardless of the accommodated position.

[0044] The heat conductor 335 may be formed such that the cross-sectional area at the second heat transfer end 332 is larger than the cross-sectional area of the first heat transfer end 331. The heat conductor 335 having such a shape allows the second heat transfer end 332 to make a wider area contact with the semiconductor device 20, so that the heat transferred from the first heat transfer end 331 can be transferred to the semiconductor device 20 more uniformly via the second heat transfer end 332. The shape of the heat conductor 335 is not limited to the embodiments shown in FIGS. 2 and 3. For example, it may be formed to have a rounded shape from the first heat transfer end 331 to the second heat transfer end 332.

[0045] The test board 10 may include a circuit portion 400 that forms a path for electrically connecting the semiconductor device 20 and the tester. The circuit portion 400 may include a plurality of semiconductor device contact terminals 410, a plurality of tester contact terminals 430, and a device contact circuit 420 that forms a path through which the semiconductor device contact terminals 410 and the tester contact terminals 430 are electrically connected. Specifically, the semiconductor device contact terminals 410 are each configured to contact and be electrically connected to the respective semiconductor device 20, and a plurality of them may be provided corresponding to the number of semiconductor devices 20 to be accommodated. Each device contact terminal 410 is the above-mentioned CoverThe section 300 is provided, and by changing the position of the pocket unit 120, it can be electrically connected to the housed semiconductor device 20 respectively. On the other hand, the tester contact terminal 430 is configured to be electrically connected to the tester terminal 1422 during testing, and is formed on the outer surface of the test board 10 so that it can be directly accessed from the outside. Therefore, after a plurality of semiconductor devices 20 are housed in the test board 10, Cover if the section 300 is coupled, the test board 10 and the tester 1421 can be connected to perform testing without applying additional external force to the semiconductor device 20.

[0046] Also, the housing portion 100 may include a temperature sensor 140 for measuring the temperature of the semiconductor device 20. For example, in the embodiments shown in FIGS. 2 and 3, the temperature sensor 140 is provided on the bottom surface of the pocket unit 120 and can measure the temperature of the semiconductor device 20 housed therein. The temperature information of the semiconductor device 20 measured by the temperature sensor 140 may be transmitted to the board temperature adjustment unit 1425 via a temperature sensor circuit 440 that is electrically connected to the tester contact terminal 430. The temperature sensor circuit 440 is formed across the housing portion 100 and the circuit portion 400, Cover and may be electrically connected in a state where the section 300 is coupled to the housing portion 100. A plurality of temperature sensors 140 may be formed to correspond to the plurality of semiconductor devices 20 respectively, and can measure the temperatures of the plurality of semiconductor devices 20 respectively. The board temperature adjustment unit 1425 may include a control unit, and the control unit may individually control the temperatures of the plurality of semiconductor devices 20 based on the temperatures measured by the temperature sensor 140.

[0047] On the one hand, as shown in FIGS. 2 and 3, the semiconductor device contact terminal 410 forming one end of the circuit portion 400 may be configured in the form of a connecting pin protruding upward from the bottom surface of the socket base 110. And at least one or more through holes 123 are formed in the bottom surface of the pocket unit 120, and the semiconductor device contact terminal 410 may be inserted in a form penetrating through the through hole 123. Therefore, the semiconductor device contact terminal 410 can be selectively exposed inside the accommodation space according to the position of the pocket unit 120 and electrically connected to the semiconductor device 20.

[0048] A plurality of such semiconductor device contact terminals 410 may be provided so as to be individually connected to each of the semiconductor devices 20 accommodated in the accommodation portion, and may be provided in each pocket unit 120. And each semiconductor device contact terminal 410 can be electrically connected to a tester contact terminal 430 exposed and formed under the socket board 200 by a circuit formed on the socket board 200.

[0049] In the case of the test board 10 of the present embodiment, Cover While the position of the semiconductor device 20 is fixed in the combined state of the portion 300 and the accommodation portion 100, the semiconductor device 20 and the circuit portion 400 of the test board can be electrically connected. At this time, the structure that elastically supports the pocket unit 120, the pocket unit 120, and the portion pressing the pocket unit 120 are made of a buffer material to minimize the impact applied to the semiconductor device 20. And a plurality of semiconductor devices 20 to be tested are built in the test board 10 and transferred to the test site in a protected state. Since the test can be performed using the tester contact terminal 430 of the test board 10 without additionally applying an external force to the semiconductor device 20, various tests can be performed without damaging the semiconductor device 20.

[0050] Here, such a test board 10 is exposed to an environment with a large temperature change range by being tested in a test environment with a relatively high temperature. Therefore, the pocket unit 120 and the socket base 110 that constitute the accommodating portion 100 are preferably made of a material having a similar material and thermal expansion coefficient to that of the semiconductor device 20, for example, a material such as ceramic. Further, Cover The heat transfer portion 330 of the portion 300 and other portions other than the heat transfer portion 330 can also be manufactured by selecting a material having a similar material and thermal expansion coefficient to that of the semiconductor device 20 in consideration of such a temperature change environment.

[0051] In the above, an example of the test board 10 according to the present invention has been mainly described, but the embodiments according to the present invention are not limited thereto. While configuring to support the semiconductor device 20 in the test board 10, Cover The structure of the test board 10 can be variously deformed so that the temperature of the semiconductor device 20 can be individually controlled in the combined state of the portion 300 and the accommodating portion 100.

[0052] Hereinafter, with reference to FIG. 4, a method of adjusting the temperature of the test board 10 in the test chamber 1420 of the test apparatus in an embodiment according to the present invention will be described. The test chamber 1420 creates the temperature of the internal space into a preset test environment using the board temperature adjustment unit 1425, and when the test board 10 is drawn in, the semiconductor device 20 can be tested using the tester 1421. The test chamber 1420 may include a board temperature adjustment unit 1425 that adjusts the temperature inside the chamber in order to create a preset test environment. As described above, the board temperature adjustment unit 1425 can selectively contact the test board 10 to control the temperature of the test board 10. As shown in FIG. 4, a part of the board temperature adjustment unit 1425 is the CoverIt is possible to adjust the temperature of the semiconductor device 20 in a heat conduction manner by contacting the upper surface of the unit 300. Unlike the conventional method of indirectly adjusting the temperature of the semiconductor device 20 by heating / cooling the test chamber 1420, this method directly adjusts the temperature of the semiconductor device 20, enabling the semiconductor device 20 to be adjusted more accurately to a preset test temperature. Also, as described above, since a plurality of semiconductor devices 20 can be divided into a plurality of temperature adjustment regions 150 and individually adjusted in temperature, control can be performed to compensate for temperature deviation or heating rate deviation that may occur depending on the position where the semiconductor device 20 is accommodated.

[0053] On the other hand, as shown in FIG. 4, the pushing unit 1423 of the test chamber 1420 presses the upper surface of the socket board 200 where the accommodation part 100 is not formed among the drawn-in test boards 10, whereby the tester contact terminal 430 of the test board 10 and the terminal 1422 on the tester side may come into contact and be electrically connected. In FIG. 4, for convenience of explanation, two tester contact terminals 430 are provided on the test board 10 and are shown as being connected to the tester 1421, but depending on the method of designing the circuit part 400, it is also possible to provide more tester contact terminals 430.

[0054] Conventional test chambers were designed to individually pressurize all semiconductor devices, resulting in insufficient spare space inside the chamber. However, in this embodiment, by configuring the pushing unit 1423 and the like in a compact manner, the internal space can be configured to be relatively more spacious. Therefore, in addition to the board temperature adjustment unit 1425 described above, it can also be configured to further include, as auxiliary components, a heater and / or a blower device provided on the inner wall of the test chamber 1420.

[0055] Hereinafter, with reference to FIG. 6, the structure of the test board 10 having a structure different from the above-described embodiment will be described as an example. However, configurations corresponding to those of the above-described embodiment and similar technical matters are omitted from specific description in order to avoid repetitive explanation.

[0056] FIG. 6 is a cross-sectional view showing a partial cross-section of the test board 10 according to another embodiment. In the other embodiment shown in FIG. 6, the pocket unit 120 housing the semiconductor device 20 may further include a housing portion heat conductor 160. The housing portion heat conductor 160 Cover is at least partially in contact with the second heat transfer end portion 342 of the heat transfer portion 340 in a state where the portion 300 is coupled to the housing portion 100 Cover and may include a semiconductor device contact portion 162 that is at least partially in contact with the semiconductor device 20 and a portion contact portion 161. Cover The portion contact portion 161 and the semiconductor device contact portion 162 are connected by at least one heat conductor, Cover and a heat transfer path from the portion contact portion 161 to the semiconductor device contact portion 162 can be formed.

[0057] In the above-described embodiment, Cover in the coupled state of the portion 300 Cover the heat conductor 335 of the portion 300 is in direct contact with the semiconductor device 20. Therefore, Cover direct heat exchange occurs between the heat conductor 335 of the portion 300 and the semiconductor device 20. In contrast, in the embodiment shown in FIG. 7, even if the semiconductor device 20 and the heat conductor 345 are not in direct contact, Cover a heat transfer path can be formed from the heat conductor 345 of the portion 300 through the housing portion heat conductor 160 to the semiconductor device 20, and thus heat can be exchanged between the board temperature adjustment unit 1425 and the semiconductor device 20.

[0058] Hereinafter, with reference to FIG. 7, the structure of the test board 10 having a structure different from the above-described embodiment will be described as an example. However, configurations corresponding to those of the above-described embodiment and similar technical matters are omitted from specific description in order to avoid repetitive explanation.

[0059] 7 is a cross-sectional view showing a part of a test board 10 according to another embodiment. In the other embodiment shown in FIG. 7, a heat transfer part 350 having a heat transfer channel 355 is formed. The heat transfer channel 355 is Cover The heat transfer end 351 extends from a first heat transfer end 351 exposed to the outside of the portion 300 to a second heat transfer end 352 exposed to the semiconductor device receiving groove 121 provided in the temperature adjustment region 150 . Cover With the board 300 coupled to the accommodating part 100, a heat transfer medium is supplied to the semiconductor device accommodating groove 121 in the temperature control region 150 via the heat transfer flow path 355, and the heat transfer medium heats / cools the semiconductor device 20 accommodated in the semiconductor device accommodating groove 121. In this case, the board temperature control part 1425 is configured as a device capable of supplying the heat transfer medium to each of the heat transfer flow paths 355.

[0060] In the above-described embodiment, Cover With part 300 connected Cover The thermal conductor 345 of the unit 300 or the thermal conductor 160 of the receiving unit is in direct contact with the semiconductor device 20, so that the temperature of the semiconductor device 20 can be controlled by a thermal conduction method. In contrast, in another embodiment shown in FIG 7, the temperature of the semiconductor device 20 is controlled by a thermal convection method using a heat transfer medium.

[0061] Hereinafter, with reference to FIG. 8 and FIG. 9, a temperature control area 150 partitioned in a manner different from that of the above-described embodiment will be described as an example.

[0062] In the above-described embodiment, the temperature control regions 150 are each partitioned to include one semiconductor device accommodating groove 121, but one temperature control region 150 does not necessarily have to be partitioned to include only one semiconductor device accommodating groove 121, and may be partitioned to include a plurality of semiconductor device accommodating grooves 121. In this case, the second heat transfer end 342 of the heat transfer portion 340 is formed to be exposed to the plurality of semiconductor device accommodating grooves 121, so that one heat transfer portion 340 can adjust the temperatures of a plurality of semiconductor devices 20.

[0063] In the embodiment shown in FIG. 8, the temperature adjustment region 150 is partitioned so as to include two semiconductor device accommodation grooves 121 each, and the heat transfer unit 340 can control the temperatures of two semiconductor devices 20 each. In the embodiment shown in FIG. 9, the temperature adjustment region 150 is partitioned so as to include four semiconductor device accommodation grooves 121 each, and the heat transfer unit 340 controls the temperatures of four semiconductor devices 20 each. The partitioning method of the temperature adjustment region 150 is not limited to the examples shown in FIGS. 8 and 9, and any combination may be partitioned as long as a plurality of semiconductor devices 20 can be uniformly heated.

[0064] As described above, several embodiments of the test board of the present invention have been mainly described, but the present invention is not limited to the above embodiments and the like. It is clarified that those having ordinary knowledge in the technical field to which the present invention pertains can implement the present invention with various modifications or changes without departing from the scope of the technical features of the present invention defined in the appended claims.

Explanation of reference numerals

[0065] 1 Test apparatus 10 Test board 20 Device 100 Accommodation part 200 Socket board 300 Cover Part 400 Circuit part 1400 Test part

Claims

1. In a semiconductor device test board that houses a plurality of semiconductor devices and is carried into a test apparatus, it includes a housing portion in which a plurality of semiconductor device accommodation grooves for accommodating each of the plurality of semiconductor devices are formed, and a lid portion that is detachably coupled to the housing portion. The lid portion, in a state of being coupled to the housing portion, includes a heat transfer portion having a first heat transfer end portion exposed to the outside of the lid portion and a second heat transfer end portion that extends from the first heat transfer end portion and is exposed to a temperature adjustment region partitioned to include at least one of the plurality of semiconductor device accommodation grooves. The heat transfer portion includes a heat conductor that extends from the first heat transfer end portion to the second heat transfer end portion. The housing portion includes a housing portion heat conductor having a lid portion contact portion that is at least partially in contact with the second heat transfer end portion and a semiconductor device contact portion that contacts the semiconductor device in a state where the lid portion is coupled to the housing portion, and is a semiconductor device test board that adjusts the temperature of the semiconductor device by a heat conduction method.

2. The semiconductor device test board according to claim 1, wherein in a state where the lid portion is coupled to the housing portion, at least a part of the second heat transfer end portion contacts the semiconductor device accommodated in the temperature adjustment region, and adjusts the temperature of the semiconductor device by a heat conduction method.

3. There are a plurality of the temperature adjustment regions, and the plurality of temperature adjustment regions include at least one inner peripheral portion temperature adjustment region and a plurality of outer peripheral portion temperature adjustment regions surrounding the inner peripheral portion temperature adjustment region. The semiconductor device test board according to claim 2, wherein a plurality of the heat conductors are formed so as to correspond to the plurality of temperature adjustment regions respectively.

4. The semiconductor device test board according to claim 3, wherein each of the plurality of temperature adjustment regions includes one semiconductor device accommodation groove.

5. The semiconductor device test board according to claim 3, wherein the heat conductor corresponding to the outer peripheral portion temperature adjustment region has a length from a first heat transfer end portion to a second heat transfer end portion that is shorter than the heat conductor corresponding to the inner peripheral portion temperature adjustment region.

6. The semiconductor device test board according to claim 3, wherein the heat conductor corresponding to the outer peripheral portion temperature adjustment region has an average cross-sectional area from a first heat transfer end portion to a second heat transfer end portion that is wider than the heat conductor corresponding to the inner peripheral portion temperature adjustment region.

7. The semiconductor device test board according to claim 3, wherein the heat conductor corresponding to the outer peripheral temperature adjustment region is formed of a material having a higher thermal conductivity than the heat conductor corresponding to the inner peripheral temperature adjustment region.

8. The semiconductor device test board according to claim 3, wherein the heat conductor has a larger cross-sectional area at the second heat transfer end than at the first heat transfer end.

9. The semiconductor device test board further includes a plurality of temperature sensors for measuring the temperatures of the plurality of semiconductor devices respectively, The board temperature adjustment unit is characterized in that it individually controls the temperatures of the plurality of semiconductor devices based on the temperatures measured by the temperature sensors, according to claim 1 of the semiconductor device test board.

10. The lid portion selectively pressurizes at least a part of the housing portion, The semiconductor device test board according to claim 1, further comprising a circuit for electrically connecting the semiconductor device and the tester, and a circuit portion selectively connected to the semiconductor device in the housing portion in a pressurized state by the lid portion.

11. The housing portion is configured to include a pocket unit in which the semiconductor device accommodation groove is formed and a socket base on which the pocket unit is provided to be relatively movable, The semiconductor device test board according to claim 10, wherein the lid portion pressurizes the pocket unit when coupled to the upper side of the housing portion, the position of the pocket unit is changed, and the semiconductor device accommodated in the pocket unit is connected to the circuit portion.

12. The circuit portion includes a device contact terminal selectively connected to the semiconductor device accommodated in the housing portion, The semiconductor device test board according to claim 11, wherein when the position of the pocket unit is changed by the pressurization of the lid portion, the device contact terminal is exposed inside the pocket unit and electrically connected to the semiconductor device.

13. An elastic member is provided between the socket base and the pocket unit, and the pocket unit is elastically supported on the socket base, according to claim 11 of the semiconductor device test board.

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