Display device

Abstract

To provide a novel display device.SOLUTION: The display device includes: a pixel unit; a drive circuit unit located outside the pixel unit; and a protection circuit that is electrically connected to either or both of the pixel unit and drive circuit unit, and contains a pair of electrodes. The pixel unit has: pixel electrodes arranged in a matrix; and a transistor electrically connected to the pixel electrodes. The transistor has: a first insulating layer containing nitrogen and silicon; and a second insulating layer containing oxygen, nitrogen and silicon. The protection circuit has a first insulating layer between the pair of electrodes.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to an article, a method, a manufacturing method, a process, a machine, a manufacture, or a composition of matter. In particular, the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, an electronic device, a driving method thereof, or a manufacturing method thereof. In particular, the present invention relates to, for example, a semiconductor device, a display device, an electronic device having an oxide semiconductor, or a light-emitting device.

[0002] Note that the display device refers to a device having a display element. The display device includes a driving circuit for driving a plurality of pixels and the like. Note that the display device includes a control circuit, a power supply circuit, a signal generation circuit, etc., which are disposed on another substrate.

Background Art

[0003] As a result of recent technological innovations, display devices typified by liquid crystal display devices have advanced in miniaturization of elements and wiring, and mass production technologies have also advanced at each stage. In the future, it is required to reduce costs in order to improve the manufacturing yield. When a surge voltage due to static electricity or the like is applied to a display device, the element may be damaged and normal

[0004] display may not be possible. Therefore, there is a risk that the manufacturing yield deteriorates. As a countermeasure, a protection circuit for discharging the surge voltage to another wiring is provided in the display device (see, for example, Patent Documents 1 to 7).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

[0006] In a display device, a configuration for improving reliability, typified by a protection circuit, is important .

[0007] Therefore, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can improve reliability . Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can reduce electrostatic breakdown . Or, in one aspect of the present invention , it is an object to provide a display device with a novel configuration that can reduce the influence of static electricity . Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that is hard to break . Or, in one aspect of the present invention, in the rubbing process, it is an object to provide a display device with a novel configuration that can reduce the influence on transistors . Or, in one aspect of the present invention, in the inspection process, it is an object to provide a display device with a novel configuration that can reduce the influence on transistors . Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can reduce the influence on transistors . Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can reduce the influence on transistors Alternatively, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can reduce the influence of defects when using a touch sensor. Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can reduce fluctuations or deterioration of transistor characteristics. Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can reduce fluctuations or deterioration of the threshold voltage of a transistor. Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can reduce the normal-on state of a transistor. Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can improve the manufacturing yield of a transistor. Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can shield a transistor. Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can discharge the charge accumulated in a pixel electrode. Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can discharge the charge accumulated in a wiring. Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration having an oxide semiconductor layer with improved conductivity. Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can control the conductivity of an oxide semiconductor layer. Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can control the conductivity of a gate insulating film. Or, in one aspect of the present invention, it is an object to provide a display device with a novel configuration that can facilitate normal display. ​​​​​​​​​​​​​​​ One of the problems is to provide it.

[0008] Note that the description of these problems does not prevent the existence of other problems. In addition, One aspect of the present invention does not require all of these problems to be solved. Note that problems other than the above will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract problems other than the above from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0009] One aspect of the present invention includes a pixel portion, a drive circuit portion disposed outside the pixel portion, and a protection circuit electrically connected to one or both of the pixel portion and the drive circuit portion and including a pair of electrodes. The pixel portion has pixel electrodes arranged in a matrix and transistors electrically connected to the pixel electrodes. The transistor has a first insulating layer containing nitrogen and silicon, and a second insulating layer containing oxygen, nitrogen, and silicon. The protection circuit is a display device having the first insulating layer between a pair of electrodes.

Advantages of the Invention

[0010] According to one aspect of the present invention, the reliability of the display device can be improved.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

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Figure 6

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Figure 8

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Figure 10

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Figure 14

Figure 15

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Figure 18

Figure 19

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Figure 21

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Figure 23

Figure 24

Figure 25

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it is easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0013] In the drawings, the size, layer thickness, or region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0014] In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And there is a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source.

[0015] Here, since the source and the drain change depending on the structure or operating conditions of the transistor, etc., it is difficult to limit which is the source or the drain. Therefore, the part that functions as the source and the part that functions as the drain are referred to as the source or the drain, one of the source and the drain is denoted as the first electrode, and the other of the source and the drain is denoted as the second electrode. It may be written as "polar."

[0016] In addition, the ordinal numbers "first," "second," and "third" used in this specification refer to the components of the It should be noted that this is added to avoid confusion and is not intended to limit the numbers.

[0017] In this specification, "A and B are connected" does not mean that A and B are directly connected. In addition to those that are connected electrically, A and B are also connected electrically. Being electrically connected means that there is an object between A and B that has some electrical effect. A device that enables the transmission and reception of electrical signals between A and B.

[0018] In addition, in this specification, the words "above" and "below" indicating the position of the components are used. The positional relationship is used for convenience in describing the drawings. The relationship changes depending on the direction in which each component is depicted. The above words and phrases are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0019] In addition, the positional relationship of each circuit block in the block diagram in the drawing is specified for the purpose of explanation. Although different circuit blocks are shown to realize different functions, In the circuits or regions, different functions are realized within the same circuit or region. In addition, the functions of each circuit block in the block diagram in the drawings may be different for the purpose of explanation. Although it is shown as a single circuit block, it may not correspond to the actual circuit or area. In this case, the processing that would normally be done by one circuit block is performed by multiple circuit blocks. In some cases.

[0020] A pixel is defined as a display unit capable of controlling the brightness of one color element (e.g., any one of R (red), G (green), and B (blue)). Therefore, in the case of a color display device, the minimum display unit of a color image is composed of three pixels: an R pixel, a G pixel, and a B pixel. However, the color elements for displaying a color image are not limited to three colors, and more than three colors may be used, or colors other than RGB may be used.

[0021] In this specification, embodiments of the present invention will be described with reference to the drawings. The description of each embodiment will be carried out in the following order. 1. Embodiment 1 (Regarding the basic configuration related to one aspect of the present invention) 2. Embodiment 2 (Regarding each configuration of the display device) 3. Embodiment 3 (Regarding the manufacturing method of the display device) 4. Embodiment 4 (Regarding the configuration of the pixel circuit) 5. Embodiment 5 (Regarding the configuration of the pixel portion) 6. Embodiment 6 (Regarding a modification example of the protection circuit) 7. Embodiment 7 (Regarding the configuration of the transistor) 8. Embodiment 8 (Regarding the configuration of the connection terminal portion) 9. Embodiment 9 (Regarding the touch sensor and the display module) 10. Embodiment 10 (Regarding the electronic device)

[0022] (Embodiment 1) In this embodiment, a display device according to one aspect of the present invention will be described with reference to FIGS. 1 to 5.

[0023] The display device shown in FIG. 1(A) includes a region having a display element of a pixel (hereinafter referred to as a pixel portion 102) and a circuit portion having a circuit for driving the pixel (hereinafter referred to as a driving circuit portion 104). ​, a circuit having a protection function for an element (hereinafter referred to as protection circuit 106), and a terminal portion 107 has.

[0024] The pixel portion 102 has a circuit (hereinafter referred to as pixel circuit 108) for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more), and the drive circuit section 104 has a drive circuit such as a circuit (hereinafter referred to as gate driver 104a) that outputs a signal (scanning signal) for selecting a pixel and a circuit (hereinafter referred to as source driver 104b) that supplies a signal (data signal) for driving the display element of the pixel. The gate driver 104a has a shift register or the like. The gate driver 104a receives a signal for driving the shift register via the terminal portion 107 and outputs the signal. For example, the gate driver 104a receives a start pulse signal, a clock signal, etc., and outputs a pulse signal. The gate driver 104a has a function of controlling the potential of a wiring (hereinafter referred to as scanning lines GL_1 to GL_X) to which a scanning signal is applied. Note that a plurality of gate drivers 104a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 104a. Alternatively, the gate driver 104a has a function of being able to supply an initialization signal. However, it is not limited to this, and the gate driver 10

[0025] 4a can also supply another signal. The source driver 104b has a shift register or the like. The source driver 104b receives, via the terminal portion 107, in addition to a signal for driving the shift register, a signal that serves as a source of the data signal.

[0026] 4a may be capable of supplying other signals.

[0026] The source driver 104b has a shift register or the like. The source driver 104b receives, via the terminal portion 107, in addition to a signal for driving the shift register, a signal that serves as a source of the data signal. A signal (image signal) is input. The source driver 104b has a function of generating a data signal to be written into the pixel circuit 108 based on the image signal. Also, the source driver 104b controls the output of the data signal according to a pulse signal obtained when a start pulse signal, a clock signal, etc. are input. Also, the source driver 104b has a function of controlling the potential of a wiring (hereinafter referred to as data lines DL_1 to DL_Y) to which the data signal is supplied. Or, the source driver 104b has a function of being able to supply an initialization signal. However, it is not limited to this, and the source driver 104b can also supply another signal. The source driver 104b is configured using, for example, a plurality of analog switches. The source driver 104b can output a signal obtained by time-division multiplexing the image signal as a data signal by sequentially turning on a plurality of analog switches. Also, the source driver 104b may be configured using a shift register or the like.

[0027] Each of the plurality of pixel circuits 108 has a pulse signal input via one of a plurality of wirings (hereinafter referred to as scan lines GL) to which a scan signal is supplied, and a data signal is input via one of a plurality of wirings (hereinafter referred to as data lines DL) to which the data signal is supplied. Also, each of the plurality of pixel circuits 108 has the writing and holding of the data of the data signal controlled by the gate driver 104a. For example, the pixel circuit 108 at the m-th row and n-th column has a pulse signal input from the gate driver 104a via the scan line GL_m (m

[0028] is a natural number less than or equal to X), and according to the potential of the scan line GL_m, a data signal is input via the data line DL_n (n is a natural number less than or equal to Y) from the source driver . Each of the plurality of pixel circuits 108 has the writing and holding of the data of the data signal controlled by the gate driver 104a. For example, the pixel circuit 108 at the m-th row and n-th column has a pulse signal input from the gate driver 104a via the scan line GL_m (m is a natural number less than or equal to X), and according to the potential of the scan line GL_m, a data signal is input via the data line DL_n (n is a natural number less than or equal to Y) from the source driver A data signal is input from the BA104b.

[0029] The protection circuit 106 is connected to the scanning line GL, which is a wiring between the gate driver 104a and the pixel circuit 108. Alternatively, the protection circuit 106 is connected to the data line DL, which is a wiring between the source driver 104b and the pixel circuit 108. Alternatively, the protection circuit 106 can be connected to the wiring between the gate driver 104a and the terminal portion 107. Alternatively, the protection circuit 106 can be connected to the wiring between the source driver 104b and the terminal portion 107. Note that the terminal portion 107 refers to a portion where terminals for supplying power, control signals, and image signals from an external circuit to the display device are provided. The protection circuit 106 is a circuit that makes the wiring to which it is connected and another wiring in a conductive state when a potential outside a certain range is applied to the wiring to which it is connected. However, it is not limited to this, and the protection circuit 106 can also supply another signal.

[0030]

[0031] As shown in FIG. 1(A), by providing the protection circuit 106 in the pixel portion 102 and the drive circuit portion 104 respectively, the resistance of the display device against overcurrent generated by ESD (Electro Static Discharge) etc. can be enhanced. However, the configuration of the protection circuit 106 is not limited to this. For example, it can be configured to connect the protection circuit 106 to the gate driver 104a, or to connect the protection circuit 106 to the source driver 104b. Alternatively, it can be configured to connect the protection circuit 106 to the terminal portion 107.

[0032] ​​​​​​​​​​Also, in FIG. 1(A), an example is shown in which the drive circuit section 104 is formed by the gate driver 104a and the source driver 104b, but the configuration is not limited to this. For example, only the gate driver 104a may be formed, and a separately prepared source driver circuit may be mounted on a substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film). That is, the protection circuit 106 is electrically connected to either one or both of the pixel section 102 and the drive circuit section 104. The protection circuit 106 can be configured using, for example, a resistance element. FIG. 1(B) shows an example of a specific protection circuit. In the protection circuit 106 shown in FIG. 1(B), a resistance element 114 is connected between the wiring 110 and the wiring 112. Also, the wiring 110 is, for example, a scanning line GL, a data line DL shown in FIG. 1(A), or a wiring routed from the terminal section 107 to the drive circuit section 104.

[0033] Also, the wiring 112 is, for example, a wiring to which the potential (VDD, VSS, or GND) of a power supply line for supplying power to the gate driver 104a or the source driver 104b shown in FIG. 1(A) is applied. Or, it is a wiring (common line) to which a common potential (common potential) is applied. As an example, the wiring 112 is preferably connected to a power supply line for supplying power to the gate driver 104a, particularly a wiring for supplying a low potential. This is because the scanning line GL is at a low potential for most of the period. Therefore, the potential of the wiring 112 is electrically connected to either one or both of the pixel section 102 and the drive circuit section 104.

[0034] The protection circuit 106 can be configured using, for example, a resistance element. FIG. 1(B) shows an example of a specific protection circuit. shows an example of a specific protection circuit.

[0035] In the protection circuit 106 shown in FIG. 1(B), a resistance element 114 is connected between the wiring 110 and the wiring 112. Also, the wiring 110 is, for example, a scanning line GL, a data line DL shown in FIG. 1(A), or a wiring routed from the terminal section 107 to the drive circuit section 104. Also, the wiring 112 is, for example, a wiring to which the potential (VDD, VSS, or GND) of a power supply line for supplying power to the gate driver 104a or the source driver 104b shown in FIG. 1(A) is applied. Or, it is a wiring (common line) to which a common potential (common potential) is applied. As an example, the wiring 112 is preferably connected to a power supply line for supplying power to the gate driver 104a, particularly a wiring for supplying a low potential. This is because the scanning line GL is at a low potential for most of the period. Therefore, the potential of the wiring 112 is electrically connected to either one or both of the pixel section 102 and the drive circuit section 104.

[0036] Also, the wiring 112 is, for example, a wiring to which the potential (VDD, VSS, or GND) of a power supply line for supplying power to the gate driver 104a or the source driver 104b shown in FIG. 1(A) is applied. Or, it is a wiring (common line) to which a common potential (common potential) is applied. As an example, the wiring 112 is preferably connected to a power supply line for supplying power to the gate driver 104a, particularly a wiring for supplying a low potential. This is because the scanning line GL is at a low potential for most of the period. Therefore, the potential of the wiring 112 is electrically connected to either one or both of the pixel section 102 and the drive circuit section 104. Also, the wiring 112 is, for example, a wiring to which the potential (VDD, VSS, or GND) of a power supply line for supplying power to the gate driver 104a or the source driver 104b shown in FIG. 1(A) is applied. Or, it is a wiring (common line) to which a common potential (common potential) is applied. As an example, the wiring 112 is preferably connected to a power supply line for supplying power to the gate driver 104a, particularly a wiring for supplying a low potential. This is because the scanning line GL is at a low potential for most of the period. Therefore, the potential of the wiring 112 is electrically connected to either one or both of the pixel section 102 and the drive circuit section 104. is preferably connected to a power supply line for supplying power to the gate driver 104a, particularly a wiring for supplying a low potential. This is because the scanning line GL is at a low potential for most of the period. Therefore, the potential of the wiring 112 is at a low potential for most of the period. Therefore, the potential of the wiring 112 If it is at a low potential, current leakage from the scanning line GL to the wiring 112 during normal operation can be reduced. This is because the current that would otherwise leak can be reduced.

[0037] Here, an example of a configuration that can be used as the resistance element 114 will be described with reference to FIG. 2. Explanation will be given.

[0038] The resistance element 114 shown in FIG. 2(A) has a conductive layer (hereinafter referred to as the conductive layer 142) formed on the substrate 140, an insulating layer (hereinafter referred to as the insulating layer 144) formed on the substrate 140 and the conductive layer 142, and a conductive layer (hereinafter referred to as the conductive layer 148) formed on the insulating layer 144. The resistance element 114 shown in FIG. 2(B) has a conductive layer 142 formed on the substrate 140, an insulating layer 144 formed on the substrate 140 and the conductive layer 142, an insulating layer 146 formed on the insulating layer 144, and a conductive layer 148 formed on the insulating layer 144 and the insulating layer 146. Note that the wiring 112 shown in FIG. 1(B) corresponds to the wiring formed by the conductive layer 142. Also, the wiring 110 shown in FIG. 1(B) corresponds to the wiring formed by the conductive layer 148.

[0039] In other words, the resistance element 114 shown in FIGS. 2(A) and (B) has a structure in which the insulating layer 144 is sandwiched between a pair of electrodes. By controlling the resistivity (also referred to as electrical resistivity or specific resistance) of the insulating layer 144, when an overcurrent flows through one of the pair of electrodes, a part or all of the overcurrent can be diverted to the other electrode.

[0040]

[0041]

[0042] ​​​​​​​​​However, when the resistance of the insulating layer sandwiched between a pair of electrodes is high, for example, 10 18 Ωcm or more, when an overcurrent flows through either one of the pair of electrodes, the over current cannot be suitably discharged to the other.

[0043] Therefore, as one aspect of the present invention, the resistivity of the insulating layer 144 sandwiched between a pair of electrodes is for example, 10 10 Ωcm or more and less than 10 18 Ωcm, preferably 10 11 Ωcm or more and less than 10 15 Ωcm. As the insulating film having such a resistivity, for example, an insulating film containing nitrogen and silicon can be mentioned.

[0044] Further, the resistance element 114 may be configured such that an insulating layer 146 covering an end portion of one of the pair of electrodes is provided on the insulating layer 144 as shown in FIG. 2(B). The insulating layer 146 can be formed using a material having a higher resistivity than that of the insulating layer 1 44. As the insulating layer 146, for example, an insulating film of 10 Ωcm or more may be used. As the insulating film having such a resistivity, 18 for example, an insulating film containing oxygen, nitrogen, and silicon can be mentioned.

[0045] Further, the conductive layers 142 and 148 that function as a pair of electrodes of the resistance element 114, and the insulating layers 144 and 146 that function as an insulating layer of the resistance element 114 can be formed simultaneously with the manufacturing process of the transistor constituting the pixel portion 102 and the drive circuit portion 104 of the display device shown in FIG. 1(A). Specifically, for example, the conductive layer 142 is formed in the same process as the gate electrode of the transistor.

[0046] ​​​​can be manufactured, and the conductive layer 148 can be manufactured in the same process as the source electrode or drain electrode of the transistor and the insulating layers 144 and 146 can be manufactured in the same process as the gate insulating layer of the transistor and can be manufactured in the same process as the insulating layer

[0047] By providing the protection circuit 106 in the display device shown in FIG. 1(A) in this way, the pixel section 102 and the drive circuit section 104 can be made more resistant to overcurrents generated by ESD or the like Therefore, a novel display device with improved reliability can be provided

[0048] Note that the pixel section 102 is preferably formed on the same substrate as the protection circuit 106 as an example This can reduce the number of components and terminals. Furthermore, part or all of the drive circuit section 104 is preferably formed on the same substrate as the pixel section 102 as an example This can reduce the number of components and terminals. When part or all of the drive circuit section 1 04 is not formed on the same substrate as the pixel section 102, part or all of the drive circuit section 104 is often mounted by COG or TAB

[0049] Next, the specific configuration of the display device shown in FIG. 1(A) will be described with reference to FIG. 3

[0050] The display device shown in FIG. 3 includes a pixel section 102, a gate driver 1 04a that functions as a drive circuit section, a source driver 104b, a protection circuit 106_1, a protection circuit 106_2 a protection circuit 106_3, and a protection circuit 106_4

[0051] ​​Note that the pixel section 102, the gate driver 104a, and the source driver 104b have the same configuration as shown in FIG. 1 (A).

[0052] The protection circuit 106_1 includes transistors 151, 152, 153, 154 and resistance elements 1 71, 172, 173. The protection circuit 106_1 is provided between wirings 181, 182, 183 connected to the gate driver 104 a. The transistor 15 1 has a first terminal functioning as a source electrode and a second terminal functioning as a gate electrode connected thereto, and a third terminal functioning as a drain electrode is connected to the wiring 183 . The transistor 152 has a first terminal functioning as a source electrode and a second terminal functioning as a gate electrode connected thereto, and a third terminal functioning as a drain electrode is connected to the first terminal of the transistor 151 . The transistor 153 has a first terminal functioning as a source electrode and a second terminal functioning as a gate electrode connected thereto, and a third terminal functioning as a drain electrode is connected to the first terminal of the transistor 152 . The transistor 154 has a first terminal functioning as a source electrode and a second terminal functioning as a gate electrode connected thereto, and a third terminal functioning as a drain electrode is connected to the first terminal of the transistor 153 . Further, the first terminal of the transistor 154 is connected to the wirings 183 and 181. Also , the resistance elements 171, 173 are provided on the wiring 183. The resistance element 172 is provided between the wiring 182 and the first terminal of the transistor 152 and the third terminal of the transistor 153 . .

[0053] ​​​​​​Note that the wiring 181 can be used as a power supply line to which a low power supply potential VSS is applied. Also, the wiring 182 can be used as a common line, for example. Also, the wiring 183 can be used as a power supply line to which a high power supply potential VDD is applied, for example.

[0054] The protection circuit 106_2 includes transistors 155, 156, 157, 158 and resistance elements 1 74, 175. Also, the protection circuit 106_2 is provided between the gate driver 104a and the pixel unit 102. Also, the transistor 155 has a first terminal functioning as a source electrode, a second terminal functioning as a gate electrode, and a third terminal functioning as a drain electrode, and is connected to the wiring 185. The transistor 1 56 has a first terminal functioning as a source electrode, a second terminal functioning as a gate electrode, and a third terminal functioning as a drain electrode, and is connected to the first terminal of the transistor 15 5. The transistor 157 has a first terminal functioning as a source electrode, a second terminal functioning as a gate electrode, and a third terminal functioning as a drain electrode, and is connected to the first terminal of the transistor 156. The transistor 158 has a first terminal functioning as a source electrode, a second terminal functioning as a gate electrode, and a third terminal functioning as a drain electrode, and is connected to the first terminal of the transistor 157. The first terminal of the transistor 158 is connected to the wiring 184. Also, the resistance element 174 is provided between the wiring 185 and the first terminal of the transistor 156 and the third terminal of the transistor 157. Also, the resistance element 175 is provided between the wiring 185 and the first terminal of the transistor 156 and the third terminal of the transistor 157. The transistor 157 has a first terminal functioning as a source electrode, a second terminal functioning as a gate electrode, and a third terminal functioning as a drain electrode, and is connected to the first terminal of the transistor 156. The transistor 158 has a first terminal functioning as a source electrode, a second terminal functioning as a gate electrode, and a third terminal functioning as a drain electrode, and is connected to the first terminal of the transistor 157. The first terminal of the transistor 158 is connected to the wiring 184. The transistor 158 has a first terminal functioning as a source electrode, a second terminal functioning as a gate electrode, and a third terminal functioning as a drain electrode, and is connected to the first terminal of the transistor 157. The first terminal of the transistor 158 is connected to the wiring 184. The transistor 158 has a first terminal functioning as a source electrode, a second terminal functioning as a gate electrode, and a third terminal functioning as a drain electrode, and is connected to the first terminal of the transistor 157. The first terminal of the transistor 158 is connected to the wiring 184. The first terminal of the transistor 158 is connected to the wiring 184. Also, the resistance element 174 is provided between the wiring 185 and the first terminal of the transistor 156 and the third terminal of the transistor 157. Also, the resistance element 175 is provided between the wiring 185 and the first terminal of the transistor 156 and the third terminal of the transistor 157. , provided between the wiring 184 and the first terminal of the transistor 156 and the third terminal of the transistor 157. It is provided therebetween.

[0055] Note that the wiring 184 can be used, for example, as a power supply line to which a low power supply potential VSS is applied. Also, the wiring 185 can be used, for example, as a power supply line to which a high power supply potential VDD is applied. Also, the wiring 186 can be used, for example, as a gate line.

[0056] The protection circuit 106_3 includes transistors 159, 160, 161, 162 and resistance elements 1 76, 177. Also, the protection circuit 106_3 is provided between the source driver 104b and the pixel unit 102. Further, the transistor 159 has a first terminal having a function as a source electrode connected to a second terminal having a function as a gate electrode, and a third terminal having a function as a drain electrode is connected to the wiring 190. The transistor 16 0 has a first terminal having a function as a source electrode connected to a second terminal having a function as a gate electrode, and a third terminal having a function as a drain electrode is connected to the first terminal of the transistor 15 9. The transistor 161 has a first terminal having a function as a source electrode connected to a second terminal having a function as a gate electrode, and a third terminal having a function as a drain electrode is connected to the first terminal of the transistor 160. The transistor 162 has a first terminal having a function as a source electrode connected to a second terminal having a function as a gate electrode, and a third terminal having a function as a drain electrode is connected to the first terminal of the transistor 161. Also, the first terminal of the transistor 162 is connected to the first terminal of the transistor 161. The child is connected to wiring 191. Also, resistor element 176 is provided between wiring 190 and the first terminal of transistor 160 and the third terminal of transistor 161. Also, resistor element 177 is provided between wiring 191 and the first terminal of transistor 160 and the third terminal of transistor 161.

[0057] Note that wiring 188 can be used, for example, as a common line or a source line. Also, wiring 189 and 190 can be used, for example, as power supply lines to which a high power supply potential VDD is applied. Also, wiring 191 can be used, for example, as a power supply line to which a low power supply potential VSS is applied.

[0058] Protection circuit 106_4 includes transistors 163, 164, 165, 166 and resistor elements 1 78, 179, 180. Also, protection circuit 106_4 is provided between wiring 187, 188, 189, 190, 191 that are connected to source driver 104 b. Also, transistor 163 has a first terminal having a function as a source electrode and a second terminal having a function as a gate electrode connected thereto, and a third terminal having a function as a drain electrode and is connected to wiring 187. Transistor 164 has a first terminal having a function as a source electrode and a second terminal having a function as a gate electrode connected thereto, and a third terminal having a function as a drain electrode and is connected to the first terminal of transistor 163. Transistor 165 has a first terminal having a function as a source electrode and a second terminal having a function as a gate electrode connected thereto, and a third terminal having a function as a drain electrode and is connected to the first terminal of transistor 164. Transistor 166 has a source electrode and is connected to the first terminal of transistor 165. is connected to the first terminal of transistor 165. Transistor 166 has a source electrode and A first terminal having a function as such and a second terminal having a function as a gate electrode are connected to a third terminal having a function as a drain electrode and a first terminal of transistor 165 . Also, the first terminal of transistor 166 is connected to wiring 189 . Further, resistor element 178 is provided between wiring 187 and wiring 188. Also, the res istor element 179 is provided on wiring 188 and is connected to the first terminal of transistor 164 and the third ter minal of transistor 165. Also, resistor element 180 is provided between wiring 188 and wiring 1 89

[0059] . Also, wirings 187 and 191 can be used as power supply lines to which, for example, a low power supply potential VSS is applied . Also, wiring 188 can be used as, for example, a common line or a source line . Also, wirings 189 and 190 can be used as power supply lines to which, for example, a high power supply potential VDD is applied

[0060] . Note that wirings 181 to 191 are not limited to only the functions shown by the high power supply potential VDD, low power supply potential VS S, and common line CL in FIG. 3, and may each independently have functions such as a scanning line, a signal line, a power supply line, a ground line, a capacitance line, or a common line

[0061] . Also, as the semiconductor layer of transistors 151 to 166 included in protection circuits 106_1 to 106_4, it is preferable to use an oxide semiconductor. A transistor using an oxide semiconductor has higher resistance to an electric field because it does not have an avalanche breakdown compared to a transistor using silicon or the like in the semiconductor layer. Also, the trans istors 151 to 166 ​​​As the dissta structure, for example, a planar type and an inverse stagger type can be used.

[0062] Thus, the protection circuits 106_1 to 106_4 are composed of a plurality of diode-connected transistors and a plurality of resistance elements. That is, the protection circuits 106_1 to 106_4 can be used by combining a diode-connected transistor and a resistance element in parallel. Furthermore, as shown in FIG. 3, the protection circuits 106_1 to 106_4 can be provided between the pixel portion 102 and the gate driver 104a, between the wiring connected to the gate driver 104a, between the pixel portion 102 and the source driver 104b, or between the wiring connected to the source driver 104b. Moreover, as an example, a plan view corresponding to the protection circuit 106_2 described in FIG. 3 and a cross-sectional view of a region functioning as a resistance element are shown in FIGS. 4(A) and 4(B). The reference numerals attached in the plan view shown in FIG. 4(A) correspond to the reference numerals attached in FIG. 3. Further, FIG. 4(B) is a cross-sectional view taken along the cutting line M-N of FIG. 4(A). As shown in FIGS. 4(A) and 4(B), the resistance element of the protection circuit described in the present embodiment can be used as a resistance element that preferably discharges an overcurrent by removing a part of the insulating layer overlapping the wiring and controlling the resistivity of the insulating layer between the wirings. In addition, FIG. 5 is a circuit diagram showing a configuration different from the protection circuit described in FIG. 3. In the circuit diagram shown in FIG. 5, transistors 155A, 156A, 157A, 158A, transistors 155B, 156B, 157B, 158B, resistance elements 174A, 175A, resistance elements 174

[0063] Also, as shown in FIG. 3, the protection circuits 106_1 to 106_4 can be provided between the pixel portion 102 and the gate driver 104a, between the wiring connected to the gate driver 104a, between the pixel portion 102 and the source driver 104b, or between the wiring connected to the source driver 104b. Moreover, as an example, a plan view corresponding to the protection circuit 106_2 described in FIG. 3 and a cross-sectional view of a region functioning as a resistance element are shown in FIGS. 4(A) and 4(B). The reference numerals attached in the plan view shown in FIG. 4(A) correspond to the reference numerals attached in FIG. 3. Further, FIG. 4(B) is a cross-sectional view taken along the cutting line M-N of FIG. 4(A). As shown in FIGS. 4(A) and 4(B), the resistance element of the protection circuit described in the present embodiment can be used as a resistance element that preferably discharges an overcurrent by removing a part of the insulating layer overlapping the wiring and controlling the resistivity of the insulating layer between the wirings. In addition, FIG. 5 is a circuit diagram showing a configuration different from the protection circuit described in FIG. 3. In the circuit diagram shown in FIG. 5, transistors 155A, 156A, 157A, 158A, transistors 155B, 156B, 157B, 158B, resistance elements 174A, 175A, resistance elements 174 Furthermore, as shown in FIG. 3, the protection circuits 106_1 to 106_4 can be provided between the pixel portion 102 and the gate driver 104a, between the wiring connected to the gate driver 104a, between the pixel portion 102 and the source driver 104b, or between the wiring connected to the source driver 104b.

[0064] Moreover, as an example, a plan view corresponding to the protection circuit 106_2 described in FIG. 3 and a cross-sectional view of a region functioning as a resistance element are shown in FIGS. 4(A) and 4(B). The reference numerals attached in the plan view shown in FIG. 4(A) correspond to the reference numerals attached in FIG. 3. Further, FIG. 4(B) is a cross-sectional view taken along the cutting line M-N of FIG. 4(A). As shown in FIGS. 4(A) and 4(B), the resistance element of the protection circuit described in the present embodiment can be used as a resistance element that preferably discharges an overcurrent by removing a part of the insulating layer overlapping the wiring and controlling the resistivity of the insulating layer between the wirings. In addition, FIG. 5 is a circuit diagram showing a configuration different from the protection circuit described in FIG. 3. In the circuit diagram shown in FIG. 5, transistors 155A, 156A, 157A, 158A, transistors 155B, 156B, 157B, 158B, resistance elements 174A, 175A, resistance elements 174 In the plan view shown in FIG. 4(A), the reference numerals attached correspond to the reference numerals attached in FIG. 3. Further, FIG. 4(B) is a cross-sectional view taken along the cutting line M-N of FIG. 4(A). As shown in FIGS. 4(A) and 4(B), the resistance element of the protection circuit described in the present embodiment can be used as a resistance element that preferably discharges an overcurrent by removing a part of the insulating layer overlapping the wiring and controlling the resistivity of the insulating layer between the wirings. As shown in FIGS. 4(A) and 4(B), the resistance element of the protection circuit described in the present embodiment can be used as a resistance element that preferably discharges an overcurrent by removing a part of the insulating layer overlapping the wiring and controlling the resistivity of the insulating layer between the wirings. In addition, FIG. 5 is a circuit diagram showing a configuration different from the protection circuit described in FIG. 3. In the circuit diagram shown in FIG. 5, transistors 155A, 156A, 157A, 158A, transistors 155B, 156B, 157B, 158B, resistance elements 174A, 175A, resistance elements 174 In the plan view shown in FIG. 4(A), the reference numerals attached correspond to the reference numerals attached in FIG. 3. Further, FIG. 4(B) is a cross-sectional view taken along the cutting line M-N of FIG. 4(A). As shown in FIGS. 4(A) and 4(B), the resistance element of the protection circuit described in the present embodiment can be used as a resistance element that preferably discharges an overcurrent by removing a part of the insulating layer overlapping the wiring and controlling the resistivity of the insulating layer between the wirings. As shown in FIGS. 4(A) and 4(B), the resistance element of the protection circuit described in the present embodiment can be used as a resistance element that preferably discharges an overcurrent by removing a part of the insulating layer overlapping the wiring and controlling the resistivity of the insulating layer between the wirings.

[0065] In addition, FIG. 5 is a circuit diagram showing a configuration different from the protection circuit described in FIG. 3. In the circuit diagram shown in FIG. 5, transistors 155A, 156A, 157A, 158A, transistors 155B, 156B, 157B, 158B, resistance elements 174A, 175A, resistance elements 174 In the circuit diagram shown in FIG. 5, In the circuit diagram shown in FIG. 5, transistors 155A, 156A, 157A, 158A, transistors 155B, 156B, 157B, 158B, resistance elements 174A, 175A, resistance elements 174 Shows B, 175B, resistive element 199, wiring 184, wiring 185, and wiring 186. In addition, the reference numerals attached to the circuit diagram shown in FIG. 5 are the same as those of the protection circuit 106_2 described in FIG. 3 For the same configuration, the same reference numerals are used for correspondence. The circuit diagram shown in FIG. 5 is different from the protection circuit 106_2 shown in FIG. 3 The difference is that circuits corresponding to the protection circuit 106_2 in FIG. 3 are arranged side by side And a resistive element 199 is provided between the wirings.

[0066] Note that the resistivity of the resistive element 199 included in the protection circuit 106_2 shown in FIG. 5 is such that the resistivity of the resistive elements 174A, 175A, resistive elements 174B, 175B is 10 10 Ωcm or more and 10 1 8 less than Ωcm, while 10 3 Ωcm or more and 10 6 less than Ωcm and a smaller value is preferably used. By adopting the configuration of the circuit diagram shown in FIG. 5, it is possible to suppress a sharp change in the signal applied to the wiring.

[0067] By providing a plurality of protection circuits in the display device in this way, the pixel portion 102 and the drive circuit portion 104 (gate driver 104a, source driver 104b) can further enhance the resistance to overcurrent generated by ESD or the like. Therefore, it is possible to provide a novel display device with improved reliability.

[0068] In addition, in this embodiment, examples of providing a protection circuit, a resistive element, a transistor, etc. have been described, but one aspect of the embodiment of the present invention is not limited to this. For example, in some cases it is also possible not to provide a protection circuit or the like.

[0069] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments. This is possible.

[0070] (Embodiment 2) In this embodiment, a vertical electric field type liquid crystal element having the protection circuit described in Embodiment 1 is used to explain the configuration of a display device (also referred to as a liquid crystal display device) with reference to FIG. 6.

[0071] The display device shown in FIG. 6 includes a pixel portion 102 of the display device shown in FIG. 1(A), a driving circuit portion 10 4, and a protection circuit 106. Further, as a connection portion of each conductive layer, a connection portion 109 is exemplified. The connection portion 109 shows the connection structure between the first-layer conductive layer and the second-layer conductive layer. Such a connection structure can be applied to the driving circuit portion 104 or the routing wiring or the like. This is possible.

[0072] Note that, in the display device shown in FIG. 6, a configuration in which the protection circuit 106 is connected to the driving circuit portion 104 is exemplified, but the present invention is not limited to this. For example, a configuration in which the protection circuit 106 is connected between the driving circuit portion 104 and the pixel portion 102 can be adopted. This is possible.

[0073] The display device shown in this embodiment has a liquid crystal element 268 sandwiched between a pair of substrates (substrate 202 and substrate 252).

[0074] The liquid crystal element 268 includes a conductive layer 220c formed above the substrate 202, a liquid crystal layer 260 formed on the conductive layer 220c , and a conductive layer 258 formed on the liquid crystal layer 260. The conductive layer 220c functions as one electrode of the liquid crystal element 268, and the conductive layer 258 functions as the other electrode of the liquid crystal element 268. This is possible.

[0075] In addition, in the present embodiment, the case where the liquid crystal element 268 is a vertical electric field type liquid crystal element will be described. Examples of the vertical electric field type liquid crystal element include, for example, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, and VA (Vertical Alignment) mode. However, the liquid crystal element is not limited to this, and for example, an in-plane switching (IPS) mode or a fringe field switching (FFS) mode of a horizontal electric field type may be used. That is, as the vertical electric field type liquid crystal element, for example, TN (Twisted Nematic) mode, STN (Super Twisted Nematic) mode, and VA (Vertical Alignment) mode are typical. However, the liquid crystal element is not limited to this, and for example, an in-plane switching (IPS) mode or a fringe field switching (FFS) mode of a horizontal electric field type may be used. As described above, the liquid crystal display device refers to a device having a liquid crystal element. Note that the liquid crystal display device includes a drive circuit for driving a plurality of pixels and the like. In addition, the liquid crystal display device includes a control circuit, a power supply circuit, a signal generation circuit, and a backlight module disposed on another substrate, and may also be referred to as a liquid crystal module. In the liquid crystal display device, the transistors provided in the drive circuit unit 104 and the pixel unit 102 of the liquid crystal display device can be made more resistant to overcurrent from the outside by providing the protection circuit 106 as shown in the present embodiment. For example, static electricity may be generated by a rubbing process performed when manufacturing the liquid crystal element. However, by providing the protection circuit 106, an overcurrent that may be generated by the static electricity does not flow or is suppressed in the transistors formed in the pixel unit 102 and the drive circuit unit 104. Therefore, electrostatic breakdown of the transistor can be suppressed, and a highly reliable display device can be obtained.

[0076] As described above, the liquid crystal display device refers to a device having a liquid crystal element. Note that the liquid crystal display device includes a drive circuit for driving a plurality of pixels and the like. In addition, the liquid crystal display device includes a control circuit, a power supply circuit, a signal generation circuit, and a backlight module disposed on another substrate, and may also be referred to as a liquid crystal module.

[0077] In the liquid crystal display device, the transistors provided in the drive circuit unit 104 and the pixel unit 102 of the liquid crystal display device can be made more resistant to overcurrent from the outside by providing the protection circuit 106 as shown in the present embodiment. That is, as shown in the present embodiment, by providing the protection circuit 106, the transistors formed in the pixel unit 102 and the drive circuit unit 104 can be made more resistant to overcurrent from the outside.

[0078] For example, static electricity may be generated by a rubbing process performed when manufacturing the liquid crystal element. However, by providing the protection circuit 106, an overcurrent that may be generated by the static electricity does not flow or is suppressed in the transistors formed in the pixel unit 102 and the drive circuit unit 104. Therefore, electrostatic breakdown of the transistor can be suppressed, and a highly reliable display device can be obtained. That is, by providing the protection circuit 106, an overcurrent that may be generated by the static electricity does not flow or is suppressed in the transistors formed in the pixel unit 102 and the drive circuit unit 104. Therefore, electrostatic breakdown of the transistor can be suppressed, and a highly reliable display device can be obtained.

[0079] Here, other components of the display device shown in FIG. 6 will be described below.

[0080] On the substrate 202, layers having conductivity (hereinafter referred to as conductive layers 204a, 204b, 204c, 2 04d) are formed. The conductive layer 204a is formed in the protection circuit 106 and functions as one of a pair of electrodes of a resistance element. Further, the conductive layer 204b is formed in the drive circuit section 1 04 and functions as the gate of a transistor in the drive circuit. Further, the conductive layer 204c is formed in the pixel section 102 and functions as the gate of a transistor in the pixel circuit. Further, the conductive layer 204d is formed in the connection section 109 and connects to the conductive layer 212f.

[0081] Also, on the substrate 202 and the conductive layers 204a, 204b, 204c, 204d, layers having insulating properties (hereinafter referred to as insulating layers 206, 208) are formed. The insulating layers 206, 208 function as the gate insulating layers of the transistors in the drive circuit section 104 and the pixel section 102. Further, the insulating layer 206 functions as a resistance element (resistance layer) of the protection circuit 106.

[0082] Also, on the insulating layer 208, layers having semiconductor characteristics (hereinafter referred to as semiconductor layers 210a, 210b ) are formed. The semiconductor layer 210a is formed at a position overlapping the conductive layer 204b and functions as the channel of a transistor in the drive circuit. Further, the semiconductor layer 210 b is formed at a position overlapping the conductive layer 204c and functions as the channel of a transistor in the pixel circuit.

[0083] In addition, a conductive layer is formed on the insulating layers 206 and 208 and the semiconductor layers 210a and 210b. (hereinafter referred to as conductive layers 212a, 212b, 212c, 212d, 212e, and 212f) The conductive layer 212a is formed as a pair of electrodes of the resistor element of the protection circuit 106 as well as The conductive layer 212b is electrically connected to the semiconductor layer 210a. The gate electrode 14 functions as one of the source and drain of a transistor in the driver circuit. The conductive layer 212c is electrically connected to the semiconductor layer 210a and serves as a transistor of the driving circuit. The conductive layer 212d has a function as the other of the source and drain of the transistor. The source and drain of the transistor of the pixel circuit are electrically connected to the semiconductor layer 210b. The conductive layer 212e functions as one of the electrodes. and serves as the other of the source and drain of the transistor of the pixel circuit. The conductive layer 212f is formed in the connection portion 109 and is provided on the insulating layers 206 and 208. The conductive layer 204d is electrically connected to the conductive layer 204d through the opening.

[0084] In addition, the insulating layer 208, the semiconductor layers 210a and 210b, and the conductive layers 212a and 212b, On 212c, 212d, 212e, and 212f, a layer having insulating properties (hereinafter, insulating layer 21 Insulating layers 214 and 216 are formed on the transistor. In particular, the insulating layer 214 has a function of protecting the semiconductor layers 210a and 210b. has.

[0085] Moreover, a layer having insulating properties (hereinafter referred to as insulating layer 218) is formed on insulating layer 216. The insulating layer 218 functions as a planarization layer. By doing so, it is possible to suppress the generation of parasitic capacitance that can occur between the conductive layer formed below the insulating layer 218 and the conductive layer formed above the insulating layer 218.

[0086] Also, a conductive layer (hereinafter referred to as conductive layers 220a, 220b, and 220c) is formed on the insulating layer 218. The conductive layer 220a is electrically connected to the conductive layer 212b through an opening formed through the insulating layers 214, 216, and 218, and functions as a connection electrode for electrically connecting the conductive layer 212b of the drive circuit unit 104 and other wirings. The conductive layer 220b is electrically connected to the conductive layer 212d through an opening formed through the insulating layers 214, 216, and 218, and functions as a connection electrode for electrically connecting the conductive layer 212d of the pixel unit 102 and other wirings. Further, the conductive layer 220c is electrically connected to the conductive layer 212e through an opening formed through the insulating layers 214, 216, and 218, and functions as a pixel electrode of the pixel unit 102. Note that the conductive layer 220c can function as one of a pair of electrodes of the liquid crystal element of the pixel circuit.

[0087] Also, a layer having colorability (hereinafter referred to as a colored layer 254) is formed on the substrate 252. The colored layer 254 functions as a color filter. Although not shown in FIG. 6, a light-shielding film having a function as a black matrix may be formed adjacent to the colored layer 254. Also, the colored layer 254 is not necessarily provided, and for example, when the display device is black and white, etc., the colored layer 254 may not be provided.

[0088] Further, an insulating layer (hereinafter referred to as insulating layer 256) is formed on the colored layer 254. The insulating layer 256 has a function as a planarization layer or a function of suppressing the diffusion of impurities that the colored layer 254 may contain to the liquid crystal element side.

[0089] Also, a conductive layer (hereinafter referred to as conductive layer 258) is formed on the insulating layer 256. The conductive layer 258 functions as the other of a pair of electrodes of the liquid crystal element of the pixel circuit. Note that an insulating film having a function as an alignment film may be separately formed on the conductive layers 220a, 220b, 220c, and the conductive layer 258.

[0090] Also, a liquid crystal layer 260 is formed between the conductive layers 220a, 220b, 220c and the conductive layer 258. The liquid crystal layer 260 is sealed between the substrate 202 and the substrate 252 using a sealing material (not shown). Note that the sealing material preferably has a configuration that contacts an inorganic material in order to suppress the entry of moisture or the like from the outside.

[0091] Also, a spacer for maintaining the thickness (also referred to as cell gap) of the liquid crystal layer 260 may be provided between the conductive layers 220a, 220b, 220c and the conductive layer 258.

[0092] Note that the display device shown in this embodiment can simultaneously form the transistors included in the pixel portion 102 and the drive circuit portion 104 and the protection circuit 106. Therefore, it is possible to form the protection circuit 106 without increasing the manufacturing cost or the like.

[0093] The configuration shown in this embodiment can be appropriately combined with the configurations shown in other embodiments and used.

[0094] (Embodiment 3) In this embodiment, the method for manufacturing the display device described in Embodiment 2 will be described with reference to FIGS. 7 to 12.

[0095] First, a substrate 202 is prepared. As the substrate 202, a glass material such as aluminosilicate glass, al uminoborosilicate glass, or barium borosilicate glass is used. In mass production on, the substrate 202 preferably uses mother glass of the 8th generation (2160 mm × 2460 mm), 9th generation (2400 mm × 2800 mm, or 2450 mm × 3050 mm), 10th generation (2950 mm × 3400 mm), etc. Since the mother glass shrinks significantly when the processing temperature is high and the processing time is long, when mass production is carried out using the mother glass , the heat treatment in the manufacturing process is preferably 600°C or lower, more preferably 450°C or lower, and even more preferably 350°C or lower.

[0096] Next, a conductive film is formed on the substrate 202, and by processing the conductive film in a desired region, conductive layers 204a, 204b, 204c, and 204d are formed. Note that the formation of the conductive layers 204a, 204 b, 204c, and 204d can be formed by forming a mask by first patterning in a desired region and etching the region not covered by the mask. (See FIG. 7(A)). (See FIG. 7(A)).

[0097] As the conductive layers 204a, 204b, 204c, and 204d, a metal element selected from aluminum, chromium, copper , tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements is used for formation. It is possible. Further, the conductive layers 204a, 204b, 204c, and 204d may have a single-layer structure or a laminated structure of two or more layers. For example, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a titanium nitride film, a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film is laminated with an aluminum film on the titanium film and then a titanium film is formed thereon, and the like. Further, a film of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium, or an alloy film or a nitride film formed by combining a plurality of them may be used for the aluminum. Further, the conductive layers 204a, 204b, 204c, and 204d can be formed, for example, by using a sputtering method.

[0098] Also, by the above process, the conductive layer 204a included in the protection circuit 106, the conductive layer 204c included in the pixel portion 102, and the conductive layer 204b included in the drive circuit portion 104 can be formed on the same plane.

[0099] Next, insulating layers 2 06 and 208 are formed on the substrate 202 and the conductive layers 204a, 204b, 204c, and 204d (see FIG. 7(B)).

[0100] As the insulating layer 206, for example, a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, or the like may be used, and it may be provided in a laminated or single layer using a PE-CVD apparatus. Further, when the insulating layer 206 has a laminated structure, as the first silicon nitride film, a silicon nitride film with few defects is used, and on the first silicon nitride film, as the second silicon nitride film, the hydrogen emission amount and It is preferable to provide a silicon nitride film with a small amount of ammonia emission. As a result, hydrogen and nitrogen contained in the insulating layer 2 06 can suppress the movement to the semiconductor layers 210a and 210b to be possible.

[0101] As the insulating layer 208, a silicon oxide film, a silicon oxynitride film, etc. may be used, and it may be provided in a laminated or single layer using a P E-CVD apparatus. Note that if the insulating layer 206 and the insulating layer 208 are continuously formed in a vacuum, there is little impurity mixing at the interface between the insulating layer 206 and the insulating layer 208 so it is preferable. Also, the insulating layers 206 and 208 in the region overlapping with the conductive layers 204b and 204c can function as a gate insulating layer. For example, a 3 00 nm thick silicon nitride film can be applied as the insulating layer 206, and a 50 nm thick silicon oxynitride film can be applied as the insulating layer 208.

[0102] Note that silicon oxynitride is an insulating material with a nitrogen content greater than oxygen, while on the other hand, silicon nitride oxide refers to an insulating material with an oxygen content greater than nitrogen.

[0103] By configuring the gate insulating layer as described above, for example, the following effects can be obtained can be achieved. The silicon nitride film has a higher relative permittivity than the silicon oxide film, and since the film thickness required to obtain the same static capacitance is large, the gate insulating film can be physically thickened to be possible. Therefore, it is possible to suppress a decrease in the breakdown voltage of the transistor's insulation and further improve the breakdown voltage, thereby suppressing electrostatic breakdown of the transistor. to be possible.

[0104] Next, a semiconductor film is formed on the insulating layer 208, and by processing the semiconductor film into a desired region , semiconductor layers 210a and 210b are formed. Note that the formation of the semiconductor layers 210a and 210b is performed by forming a mask by second patterning in a desired region and etching a region not covered by the mask. As the etching, dry etching, wet etching, or etching combining both can be used (see Fig. 8(A)). (See Fig. 8(A)). As the semiconductor layers 210a and 210b, for example, an oxide semiconductor can be used.

[0105] The oxide semiconductor applicable to the semiconductor layers 210a and 210b preferably includes a layer represented by an In-M-Zn oxide containing at least indium (In), zinc (Zn), and M (a metal such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf). Or, it preferably contains both In and Zn. Further, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to include a stabilizer together with them. The stabilizer includes gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), or zirconium (Zr), etc. Also, other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc. ), zinc (Zn), and M (a metal such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf). Or, it preferably contains both In and Zn. Further, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to include a stabilizer together with them. ), zinc (Zn), and M (a metal such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf). Or, it preferably contains both In and Zn. Further, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to include a stabilizer together with them. n and Zn. Also, in order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to include a stabilizer together with them. In order to reduce the variation in the electrical characteristics of the transistor using the oxide semiconductor, it is preferable to include a stabilizer together with them.

[0106] Examples of the stabilizer include gallium (Ga), tin (Sn), hafnium (Hf), aluminum (Al), or zirconium (Zr). Also, other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc. include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc. Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc. (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc. There are (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc. There are (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc.

[0107] For example, as the oxide semiconductor, indium oxide, tin oxide, zinc oxide, In-Zn oxide compounds, Sn-Zn oxides, Al-Zn oxides, Zn-Mg oxides, Sn-Mg oxides, In -Mg oxides, In-Ga oxides, In-Ga-Zn oxides, In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, Sn-A l-Zn oxides, In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-D y-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, In-Lu-Zn oxides, In-Sn-Ga-Zn acid oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-A l-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf-Al-Zn oxides can be used.

[0108] Here, for example, the In-Ga-Zn oxide means an oxide mainly composed of In, Ga, and Zn, and the ratio of In, Ga, and Zn does not matter. Also, metal elements other than In, Ga, and Zn may be included. In this specification, etc., a film composed of an In-Ga -Zn oxide is also called an IGZO film.

[0109] Also, a material represented by InMO3(ZnO) m (m > 0 and m is not an integer) may be used. Here, M represents one metal element selected from Ga, Fe, Mn, and Co or a plurality of metal elements. Also, In2SnO5(ZnO) ​​​​n (where n > 0 and n is an integer ) The material represented by may be used.

[0110] Note that for forming the oxide semiconductor film, it is preferable to use a sputtering method. Sputter As the sputtering method, an RF sputtering method, a DC sputtering method, an AC sputtering method, etc. can be used. In particular, since it is possible to reduce dust generated during film formation and the film thickness distribution is also uniform , it is preferable to use the DC sputtering method.

[0111] Here, the structure of the oxide semiconductor film will be described.

[0112] The oxide semiconductor film is roughly classified into a non-single crystal oxide semiconductor film and a single crystal oxide semiconductor film. The non-single crystal oxide semiconductor film refers to a CAAC-OS (C Axis Aligned Cry stalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, etc.

[0113] First, the CAAC-OS film will be described.

[0114] The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts oriented in the c-axis direction .

[0115] When the CAAC-OS film is observed with a transmission electron microscope (TEM: Transmission Elec tron Microscope), it is not possible to confirm a clear boundary between crystal parts, that is, a grain boundary (also referred to as a grain boundary). Therefore, it can be said that in the CAAC-OS film, a decrease in electron mobility due to grain boundaries is unlikely to occur.

[0116] ​When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation), it can be confirmed that the metal atoms are arranged in layers in the crystalline part. Each layer of the metal atoms has a shape that reflects the concavities and convexities of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film. On the other hand, when the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TEM observation), it can be confirmed that the metal atoms are arranged in a triangular or hexagonal shape in the crystalline part. However, no regularity is observed in the arrangement of the metal atoms between different crystalline parts. From the cross-sectional TEM observation and the planar TEM observation, it can be seen that the crystalline part of the CAAC-OS film has orientation. In this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0117] Moreover, most of the crystalline parts included in the CAAC-OS film are sized to fit within a cube with a side length of less than 100 nm. Therefore, the case where the crystalline part included in the CAAC-OS film has a size that fits within a cube with a side length of less than 10 nm, less than 5 nm, or less than 3 nm is also included. However, a plurality of crystalline parts included in the CAAC-OS film may be connected to form one large crystal region. For example, in the planar TEM image, 2500 nm

[0118]

[0119]

[0120] ​​​​​​​​​​​​​​2 5 μm or more 2 or 1000 μm or more 2 In some cases, a crystal region of 5 μm or more or 1000 μm or more may be observed.

[0121] When performing structural analysis on the CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the out-of-plane method analysis of the CAAC-OS film having crystals of InGaZnO4, a peak may appear at around 2θ = 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. In the out-of-plane method analysis of the CAAC-OS film having crystals of InGaZnO4, a peak may appear at around 2θ = 31°. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface. Since this peak is attributed to the (009) plane of the InGaZnO4 crystal, it can be confirmed that the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0122] On the other hand, in the in-plane method analysis in which X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis, a peak may appear at around 2θ = 56°. This peak is attributed to the (110) plane of the InGaZnO4 crystal. If it is a single crystal oxide semiconductor film of InGaZnO4, when performing analysis (φ scan) while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed at around 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. This peak is attributed to the (110) plane of the InGaZnO4 crystal. If it is a single crystal oxide semiconductor film of InGaZnO4, when performing analysis (φ scan) while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed at around 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. If it is a single crystal oxide semiconductor film of InGaZnO4, when performing analysis (φ scan) while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed at around 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. If it is a single crystal oxide semiconductor film of InGaZnO4, when performing analysis (φ scan) while rotating the sample with the normal vector of the sample surface as the axis (φ axis) with 2θ fixed at around 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed. On the other hand, in the case of the CAAC-OS film, no distinct peak appears even when performing a φ scan with 2θ fixed at around 56°. On the other hand, in the case of the CAAC-OS film, no distinct peak appears even when performing a φ scan with 2θ fixed at around 56°.

[0123] From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it has c-axis orientation, and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it has c-axis orientation, and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. From the above, in the CAAC-OS film, although the orientations of the a-axis and b-axis are irregular between different crystal parts, it has c-axis orientation, and the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Each layer of the arrayed metal atoms is a plane parallel to the ab plane of the crystal.

[0124] Note that the crystal part is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the film formation surface or the upper surface of the CAAC-OS film. Further, in the CAAC-OS film, the distribution of the c-axis oriented crystal parts does not have to be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from the vicinity of the upper surface of the CAAC-OS film, the region near the upper surface may have a higher ratio of c-axis oriented crystal parts than the region near the film formation surface. Also, when impurities are added to the CAAC-OS film, the region where the impurities are added may be altered, and regions with different ratios of c-axis oriented crystal parts may be formed partially.

[0125] For example, in the analysis by the out-of-plane method of the CAAC-OS film having InGaZnO4 crystals, in addition to the peak at around 2θ = 31°, a peak may also appear at around 2θ = 36°. The peak at around 2θ = 36° indicates that a part of the CAAC-OS film contains crystals that do not have c-axis orientation. The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°.

[0126] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurities are hydrogen, carbon

[0127] ​​​​​​​​​​​, an element other than the main components of an oxide semiconductor film such as silicon and transition metal elements. In particular, an element with a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, such as silicon, will disrupt the atomic arrangement of the oxide semiconductor film by taking oxygen from the oxide semiconductor film, resulting in a decrease in crystallinity. Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so when contained inside the oxide semiconductor film, they will disrupt the atomic arrangement of the oxide semiconductor film and become a factor in reducing crystallinity. Note that impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources. Elements such as silicon, which have a stronger binding force with oxygen than the metal elements that make up the oxide semiconductor film, disrupt the atomic arrangement of the oxide semiconductor film by taking oxygen from the oxide semiconductor film, leading to a decrease in crystallinity. By depriving the oxide semiconductor film of oxygen, it disrupts the atomic arrangement of the oxide semiconductor film and becomes a factor in reducing crystallinity. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so when contained inside the oxide semiconductor film, they will disrupt the atomic arrangement of the oxide semiconductor film and become a factor in reducing crystallinity. Since they have a large atomic radius (or molecular radius), when contained inside the oxide semiconductor film, they will disrupt the atomic arrangement of the oxide semiconductor film and become a factor in reducing crystallinity. Note that impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources. Impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources.

[0128] Also, the CAAC-OS film is an oxide semiconductor film with a low defect level density. For example, oxygen deficiencies in the oxide semiconductor film may become carrier traps or become carrier generation sources by capturing hydrogen. Oxygen deficiencies in the oxide semiconductor film may become carrier traps or become carrier generation sources by capturing hydrogen. By capturing hydrogen, it may become a carrier generation source.

[0129] A low impurity concentration and a low defect level density (few oxygen deficiencies) are called high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film is less likely to have an electrical characteristic (also called a normally-off characteristic) where the threshold voltage is negative. Also, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes time to be released. A low impurity concentration and a low defect level density (few oxygen deficiencies) are called high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film is less likely to have an electrical characteristic (also called a normally-off characteristic) where the threshold voltage is negative. (Also called a normally-off characteristic.) An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. . Note that the charge trapped in the carrier trap of the oxide semiconductor film takes time to be released. It takes a long time and may behave like a fixed charge. Therefore, when the impurity concentration is high and a transistor using an oxide semiconductor film with a high defect level density is used, the electrical characteristics may become unstable .

[0130] In addition, a transistor using a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light .

[0131] Next, the microcrystalline oxide semiconductor film will be described

[0132] In the observation image by TEM, it may not be possible to clearly confirm the crystal part in the microcrystalline oxide semiconductor film . The crystal parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size . In particular, a nano crystal (nc: nanocrystalline ) that is a microcrystal of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less, and an oxide semiconductor film having the same is called an nc-OS (nanocrystalline O xide Semiconductor) film . Also, in the observation image by TEM, for example, the nc-OS film may not be able to clearly confirm the crystal grain boundary .

[0133] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less) . Also, the nc-OS film has no regularity in the crystal orientation between different crystal parts . Therefore, no orientation is seen in the entire film . Therefore, depending on the analysis method, the nc-OS film may not be distinguishable from the amorphous oxide semiconductor film . For example, for the nc-OS film, XRD using X-rays with a diameter larger than that of the crystal part When performing structural analysis using the device, in the analysis by the out-of-plane method, no peak indicating the crystal plane is detected. Also, for the nc-OS film, electron beam diffraction (also referred to as limited field of view electron beam diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than the crystal part is performed, and a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) using an electron beam with a probe diameter close to or smaller than the size of the crystal part (for example, 1 nm or more and 30 nm or less) on the nc-OS film , spots are observed. Also, when performing nano-beam electron beam diffraction on the nc-OS film, there are cases where regions with high luminance are observed in a circular (ring-shaped) manner . Also, when performing nano-beam electron beam diffraction on the nc-OS film, there are cases where a plurality of spots are observed within the ring-shaped region . The nc-OS film is an oxide semiconductor film with higher regularity than the amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower defect level density than the amorphous oxide semiconductor film. However

[0134] , the nc-OS film does not show regularity in the crystal orientation between different crystal parts. Therefore, the nc- OS film has a higher defect level density than the CAAC-OS film. Note that the oxide semiconductor film may be a laminated film having two or more of, for example, an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a C

[0135] AAC-OS film.

[0136] Also, in order to form the CAAC-OS film, it is preferable to apply the following conditions.

[0137] By reducing the incorporation of impurities during film formation, it is possible to suppress the crystal state from being disrupted by impurities It is possible. For example, impurities (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber can be reduced. This can be achieved. Also, impurities in the film formation gas can be reduced. Specifically, a film formation gas with a dew point of -80°C or lower, preferably -100°C or lower, is used.

[0138] In addition, by increasing the substrate heating temperature during film formation, migration of sputtered particles occurs after reaching the substrate. Specifically, the substrate heating temperature is set to 100°C or higher and 740°C or lower, preferably 2 00°C or higher and 500°C or lower for film formation. By increasing the substrate heating temperature during film formation, when flat sputtered particles reach the substrate, migration occurs on the substrate, and the flat surface of the sputtered particles adheres to the substrate.

[0139] Moreover, it is preferable to reduce plasma damage during film formation by increasing the oxygen ratio in the film formation gas and optimizing the power. The oxygen ratio in the film formation gas is 30 vol% or higher, preferably 100 vol%.

[0140] As an example of a sputtering target, an In-Ga-Zn-O compound target is shown below.

[0141] InO X powder, GaO Y powder, and ZnO Z powder are mixed in a predetermined number of moles, and after pressure treatment, heat treatment is performed at a temperature of 1000°C or higher and 1500°C or lower to obtain a polycrystalline In-Ga- Zn-O compound target. Here, X, Y, and Z are arbitrary positive numbers. Here, the type of powder and the molar ratio of mixing can be appropriately changed depending on the sputtering target to be produced.

[0142] Next, it is preferable to perform a first heat treatment. The first heat treatment may be carried out at a temperature of 250°C or higher and 650 °C or lower, preferably 300°C or higher and 500°C or lower, in an inert gas atmosphere, an atmosphere containing 10 ppm or more of an oxidizing gas , or under a reduced pressure state. Further, the atmosphere for the first heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after heat treatment in an inert gas atmosphere . By the first heat treatment, the crystallinity of the oxide semiconductor used for the semiconductor layers 210a , 210b can be enhanced, and impurities such as hydrogen and water can be removed from the insulating layers 206, 208, and the semiconductor layers 210a, 210b. Note that the first heating step may be performed before etching for forming the oxide semiconductor layer . . In addition, in order to impart stable electrical characteristics to a transistor having an oxide semiconductor layer as a channel, it is effective to reduce the impurity concentration in the oxide semiconductor layer and make the oxide semiconductor layer intrinsic or substantially intrinsic. Here, substantially intrinsic means that the carrier density of the oxide semiconductor layer is less than 1×10

[0143] / cm , preferably less than 1×10 / cm , more preferably less than 1×10 17 / cm 3 . 15 / cm 3 . 13 / cm 3

[0144] . Further, in the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component become impurities. For example, hydrogen and nitrogen form donor levels and increase the carrier density . Also, silicon forms impurity levels in the oxide semiconductor layer. The impurity levels may become traps and deteriorate the electrical characteristics of the transistor . . ​​

[0145] In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, the oxide semiconductor layer is The silicon concentration is 1×10 19 atoms / cm 3 Less than 5 x 10 18 a toms / cm 3 less than 1×10 18 atoms / cm 3 Less than. The hydrogen concentration is 2×10 20 atoms / cm 3 Less than or equal to 5×10 19 at oms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 The following are more preferred Or 5×10 18 atoms / cm 3 The nitrogen concentration is 5×10 19 a toms / cm 3 Less than 5 x 10 18 atoms / cm 3 The following is more preferable: is 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / c m 3 The following applies.

[0146] In addition, when the oxide semiconductor layer contains crystals and contains silicon or carbon at a high concentration, the oxide semiconductor layer is oxidized. In order to prevent the crystallinity of the oxide semiconductor layer from being deteriorated, To achieve this, the silicon concentration is set to 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / cm3 should be less than . Also, the carbon concentration should be 1×10 19 atoms / cm 3 less than, preferably 5×10 1 8 atoms / cm 3 less than, more preferably 1×10 18 atoms / cm 3 should be less than .

[0147] In addition, for a transistor using the oxide semiconductor layer purified as described above in the channel formation region, the off-current of the transistor is extremely small, and the off-current normalized by the channel width of the transistor can be reduced to several yA / μm to several zA / μm.

[0148] Also, by reducing the localized levels in the oxide semiconductor layer, stable electrical characteristics can be imparted to the transistor using the oxide semiconductor layer. Note that in order to impart stable electrical characteristics to the transistor, the absorption coefficient due to the localized levels obtained by CPM measurement (CPM: Constant Photocurrent Method) in the oxide semiconductor layer should be less than 1×10 / cm, preferably less than 3×10 / cm. -3 / cm, preferably less than 3×10 -4 / cm.

[0149] Next, a mask is formed by a third patterning on the insulating layer 208, and by etching the regions not covered by the mask, a part of the insulating layer 208 on the protection circuit 106 and parts of the insulating layers 206 and 208 on the connection part 109 are removed. Note that the formation of the openings 207a and 2 07b may be performed before the formation of the semiconductor layers 210a and 210b (see Fig. 8(B) ). )

[0150] In addition, a multi-tone mask can be used for forming the mask by the third patterning. A multi-tone mask has three exposure levels for the exposed, intermediate and unexposed parts. It is an exposure mask that can be used to change the intensity of light transmitted through it. By the exposure and development process, a resist mass having multiple (typically two) thickness regions is formed. Therefore, by using a multi-tone mask, it is possible to form a mask of an exposure mask. It is possible to reduce the number of sheets. Examples of multi-tone masks include half-tone masks, Alternatively, a gray-tone mask and the like may be used.

[0151] The third patterning is performed by using a multi-tone mask to form openings 207a and 207b. The openings 207a and 207b can be openings having different depths. In the opening 207b, the insulating layer 206 is exposed, and in the opening 207b, the conductive layer 204d is exposed. The method for forming the openings 207a and 207b is not limited to the above, and may be, for example, Alternatively, patterning may be performed using different masks.

[0152] As a result, the insulating layers 206 and 208 formed in the pixel section 102 and the driving circuit section 104 are The gate insulating layer formed in the protection circuit 106 can function as a gate insulating layer of the stack. The insulating layer 206 can function as a resistive element.

[0153] Next, on the insulating layers 206 and 208, the semiconductor layers 210a and 210b, and the conductive layer 204d, A conductive film is formed and processed into a desired region, thereby forming conductive layers 212a, 212b, 212c, 212d, 212e, and 212f are formed. , 212c, 212d, 212e, and 212f are formed in the desired area to form a fourth pattern. The mask is formed by etching the area not covered by the mask. It is possible to achieve this (see FIG. 9(A)).

[0154] In addition, the conductive layer 212a of the protective circuit 106 and the pixel portion 102 are formed by the above process. The conductive layers 212d and 212e of the driving circuit unit 104 are and can be formed on the same plane.

[0155] The conductive layers 212a, 212b, 212c, 212d, 212e, and 212f are made of conductive Materials include aluminum, titanium, chromium, nickel, copper, yttrium, and zirconium. A single metal consisting of aluminum, molybdenum, silver, tantalum, or tungsten, or a material consisting mainly of these metals The alloy is used as a single layer or a multilayer structure. For example, a tin film is formed on an aluminum film. Two-layer structure with titanium film laminated on tungsten film, two-layer structure with titanium film laminated on tungsten film, copper-magnesium A two-layer structure in which a copper film is laminated on a nesium-aluminum alloy film, a titanium film, or a titanium nitride film a titanium film or titanium nitride film, and an aluminum film or copper film is laminated on the titanium film or titanium nitride film; A three-layer structure in which a titanium film or titanium nitride film is formed on top of the molybdenum film or the nitride film. A molybdenum nitride film and an aluminum film overlaid on the molybdenum film or molybdenum nitride film. Alternatively, a copper film is laminated, and a molybdenum film or a molybdenum nitride film is formed on the copper film. In addition, transparent conductive materials containing indium oxide, tin oxide, or zinc oxide are used. In addition, the conductive layers 212a, 212b, 212c, 212d, 212e, and 212 For example, f can be formed by using a sputtering method.

[0156] In this embodiment, the conductive layers 212b, 212c, 212d, and 212e are provided on the semiconductor layers 210a and 210b, but they may be provided between the insulating layer 208 and the semiconductor layers 210a and 210b. It is also acceptable.

[0157] Next, the insulating layers 214 and 216 are formed so as to cover the insulating layer 208, the semiconductor layers 210a and 210b, and the conductive layers 212a, 212b, 212c, 212d, 212e, and 212f (see FIG. 9(B)). (See FIG. 9(B).)

[0158] As the insulating layer 214, an inorganic insulating material containing oxygen can be used to improve the interface characteristics with the oxide semiconductor used as the semiconductor layers 210a and 210b. Further, as the insulating layer 216, a material with less entry of external impurities, such as moisture, into the oxide semiconductor used as the semiconductor layers 210a and 210b is preferably used. For example, an inorganic insulating material containing nitrogen can be used. Further, as the insulating layers 214 and 216, for example they can be formed using the PE-CVD method. As an example, as the insulating layer 214, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, etc. with a thickness of 150 nm or more and 400 nm or less can be used. As the insulating layer 216 a silicon nitride film, a silicon oxynitride film, etc. with a thickness of 150 nm or more and 400 nm or less can be used. In this embodiment, as the insulating layer 214, a silicon oxynitride film with a thickness of 300 nm

[0159] is used, and as the insulating layer 216, a silicon nitride film with a thickness of 150 nm is used. At this time, the silicon nitride film prevents moisture from entering the semiconductor layers 210a and 210b. can be used. In this embodiment, as the insulating layer 214, a silicon oxynitride film with a thickness of 300 nm is used, and as the insulating layer 216, a silicon nitride film with a thickness of 150 nm is used. In this embodiment, as the insulating layer 214, a silicon oxynitride film with a thickness of 300 nm is used, and as the insulating layer 216, a silicon nitride film with a thickness of 150 nm is used. At this time, the silicon nitride film prevents moisture from entering the semiconductor layers 210a and 210b. preventing the entry of moisture into the semiconductor layers 210a and 210b. The silicon nitride film has a function as a blocking layer to prevent the formation of a fluorine-containing gas. For this reason, it is preferable to form the film at a high temperature, for example, at a substrate temperature of 100° C. or higher and lower than the distortion point of the substrate. It is more preferable to form the film by heating at a temperature of 300° C. or more and 400° C. or less. In addition, when the film is formed at a high temperature, the oxide semiconductor used for the semiconductor layers 210a and 210b is Oxygen may be removed and the carrier concentration may increase. The temperature at which no

[0160] Next, the insulating layer 218 is formed over the insulating layer 216 (see FIG. 10A).

[0161] The insulating layer 218 may be made of an acrylic resin, a polyimide resin, or a benzocyclobutene resin. Heat-resistant organic materials such as grease, polyamide resin, and epoxy resin can be used. In addition, the insulating layer 218 can be formed by stacking a plurality of insulating films made of these materials. By using the insulating layer 218, unevenness of a transistor or the like can be flattened. The insulating layer 218 is formed by using, for example, a spin coating method. It is possible.

[0162] In addition, examples of acrylic resins that can be used for the insulating layer 218 include water-absorbent The material has low thermal conductivity and releases little outgassing components (e.g., H2O, C, F, etc.) from the film. It is preferable to use it.

[0163] Next, a mask is formed on the insulating layer 218 by a fifth patterning process. The unetched areas are etched to form openings 219a, 219b, and 219c. (See FIG. 10(B)).

[0164] Note that the openings 219a, 219b, and 219c are formed so as to reach the conductive layers 212b, 212d, 212e, respectively.

[0165] Next, a conductive film is formed so as to fill the openings 219a, 219b, and 219c, and the conductive film is processed in a desired region to form the conductive layers 220a, 220b, and 220c. Note that the formation of the conductive layers 220a, 220b, and 220c can be performed by forming a mask by sixth patterning in a desired region and etching a region not covered by the mask (see FIG. 11).

[0166] As the conductive layers 220a, 220b, and 220c, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO. ), indium zinc oxide, indium tin oxide added with silicon oxide, or other conductive materials having translucency can be used. Further, as the conductive layers 220a, 220b, and 220c, for example, they can be formed using a sputtering method.

[0167] The pixel portion and the drive circuit portion having the transistor formed on the substrate 202 in the above steps, and the protection circuit can be formed on the same substrate. Note that in the manufacturing process shown in this embodiment, the first to sixth patterning, that is, six masks can be used to simultaneously form the transistor and the protection circuit.

[0168] Next, the structure formed on the substrate 252 provided to face the substrate 202 will be described below.

[0169] First, prepare a substrate 252. As the substrate 252, the materials shown in the substrate 202 can be adopted. Next, form a colored layer 254 and an insulating layer 256 on the substrate 252 (refer to Fig. 12( A)).

[0170] The colored layer 254 may be a colored layer that transmits light in a specific wavelength band. For example, a red (R) color filter that transmits light in the red wavelength band, a green (G) color filter that transmits light in the green wavelength band a blue (B) color filter that transmits light in the blue wavelength band, etc. can be used. Each color filter can be formed at a desired position using a known material by a printing method, an inkjet method, an etching method using photolithography technology, etc. Also, as the insulating layer 256, for example, an insulating film such as an acrylic resin can be used. an inkjet method, an etching method using photolithography technology, etc. at the respective desired positions. Also, as the insulating layer 256, for example, an insulating film such as an acrylic resin can be used. an inkjet method, an etching method using photolithography technology, etc. at the respective desired positions. Also, as the insulating layer 256, for example, an insulating film such as an acrylic resin can be used. used.

[0171] Next, form a conductive layer 258 on the insulating layer 256 (refer to Fig. 12(B)). As the conductive layer 258, the materials shown in the conductive layers 220a, 220b, and 220c can be adopted.

[0172] Next, form a liquid crystal layer 260 between the substrate 202 and the substrate 252. As a method for forming the liquid crystal layer 260, a dispenser method (dropping method) or an injection method in which the substrate 202 and the substrate 252 are bonded together and then liquid crystal is injected using capillary action can be used.

[0173] Through the above steps, the display device shown in Fig. 6 can be manufactured.

[0174] Note that this embodiment can be appropriately combined with other embodiments shown in this specification. be.

[0175] (Embodiment 4) In this embodiment, a configuration that can be used for the pixel circuit 108 of the display device shown in FIG. 1(A) will be described with reference to FIG. 13.

[0176] In the display device shown in FIG. 1(A), the pixel circuit 108 can have a configuration as shown in FIG. 13(A).

[0177] The pixel circuit 108 shown in FIG. 13(A) includes a liquid crystal element 130, a transistor 131_1, and a capacitor element 133_1.

[0178] One potential of a pair of electrodes of the liquid crystal element 130 is appropriately set according to the specifications of the pixel circuit 108. The liquid crystal element 130 has its alignment state set according to the data to be written. Note that a common potential (common potential) may be applied to one of a pair of electrodes of the liquid crystal elements 130 included in each of a plurality of pixel circuits 108. Also, different potentials may be applied to one of a pair of electrodes of the liquid crystal elements 130 for each pixel circuit 108 in each row.

[0179] For example, as driving methods for a display device including the liquid crystal element 130, there are TN mode, STN mode, VA mode, ASM (Axially Symmetric Aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, etc.​​​​​​​​​​ Alignment mode, IPS mode, FFS mode, or TBA (Transverse Bend Alignment) mode, etc. may be used. Also, as a driving method of the display device, in addition to the driving methods described above, ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, guest-host mode, etc. are available. However, it is not limited to this, and various ones can be used as the liquid crystal element and its driving method. In addition, a liquid crystal element may be configured by a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent. The liquid crystal showing a blue phase has a response speed of 1 msec or less, is short, and is optically isotropic, so alignment treatment is unnecessary and viewing angle dependence is small. In the pixel circuit 108 of the m-th row and n-th column, one of the source and drain of the transistor 131_1 is electrically connected to the data line DL_n, and the other is one of the pair of electrodes of the liquid crystal element 130. is electrically connected to the other. Also, the gate of the transistor 131_1 is electrically connected to the scanning line GL_m. The transistor 131_1 has a function of controlling the writing of data of the data signal by being turned on or off. One of the pair of electrodes of the capacitor element 133_1 is electrically connected to a wiring (hereinafter referred to as a potential supply line VL) to which a potential is supplied, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 130.

[0180] Moreover, a liquid crystal element may be configured by a liquid crystal composition containing a liquid crystal showing a blue phase and a chiral agent. The liquid crystal showing a blue phase has a response speed of 1 msec or less, is short, and is optically isotropic, so alignment treatment is unnecessary and viewing angle dependence is small.

[0181] In the pixel circuit 108 of the m-th row and n-th column, one of the source and drain of the transistor 131_1 is electrically connected to the data line DL_n, and the other is one of the pair of electrodes of the liquid crystal element 130. is electrically connected to the other. Also, the gate of the transistor 131_1 is electrically connected to the scanning line GL_m. The transistor 131_1 has a function of controlling the writing of data of the data signal by being turned on or off. One of the pair of electrodes of the capacitor element 133_1 is electrically connected to a wiring (hereinafter referred to as a potential supply line VL) to which a potential is supplied, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 130.

[0182] One of the pair of electrodes of the capacitor element 133_1 is electrically connected to a wiring (hereinafter referred to as a potential supply line VL) to which a potential is supplied, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 130. is electrically connected to the other. Also, the gate of the transistor 131_1 is electrically connected to the scanning line GL_m. The transistor 131_1 has a function of controlling the writing of data of the data signal by being turned on or off. ​​​​This is done. Note that the value of the potential of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 108. The capacitive element 133_1 has a function as a holding capacitor for holding the written data.

[0183] For example, in a display device having the pixel circuit 108 of FIG. 13(A), the gate driver 104 a sequentially selects the pixel circuits 108 of each row, turns on the transistor 131_1, and writes the data of the data signal.

[0184] The pixel circuit 108 in which data has been written enters a holding state when the transistor 131_1 turns off. By sequentially performing this for each row, an image can be displayed.

[0185] Also, the pixel circuit 108 shown in FIG. 13(B) includes a transistor 131_2, a capacitive element 1 33_2, a transistor 134, and a light-emitting element 135.

[0186] One of the source and drain of the transistor 131_2 is electrically connected to a wiring (hereinafter referred to as a data line DL_n) to which a data signal is supplied. Further, the gate of the transistor 131 _2 is electrically connected to a wiring (hereinafter referred to as a scanning line GL_m) to which a gate signal is supplied.

[0187] The transistor 131_2 has a function of controlling the writing of the data of the data signal by being turned on or off.

[0188] One of the pair of electrodes of the capacitive element 133_2 is electrically connected to a wiring (hereinafter referred to as a power supply line VL _a) to which a power supply is supplied, and the other is electrically connected to the other of the source and drain of the transistor 131_2. ​​

[0189] The capacitance element 133_2 has a function as a holding capacitance for holding the written data. .

[0190] One of the source and drain of the transistor 134 is electrically connected to the power supply line VL_a. Furthermore, the gate of the transistor 134 is electrically connected to the other of the source and drain of the transistor 131_2.

[0191] One of the anode and cathode of the light emitting element 135 is electrically connected to the power supply line VL_b, and the other is electrically connected to the other of the source and drain of the transistor 134.

[0192] As the light emitting element 135, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 135 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

[0193] Note that a high power supply potential VDD is applied to one of the power supply line VL_a and the power supply line VL_b, and a low power supply potential VSS is applied to the other.

[0194] In the display device having the pixel circuit 108 in FIG. 13(B), the gate driver 104a sequentially selects the pixel circuits 108 of each row, turns on the transistor 131_2, and writes the data of the data signal.

[0195] The pixel circuit 108 in which the data is written enters a holding state when the transistor 131_2 is turned off. Furthermore, the amount of current flowing between the source and drain of the transistor 134 is controlled according to the potential of the written data signal, and the light emitting element 135 emits light according to the amount of current flowing. It emits light with a luminance corresponding thereto. By sequentially performing this for each row, an image can be displayed.

[0196] In addition, in this specification and the like, a display element, a display device which is a device having the display element, a light-emitting element, and a light-emitting device which is a device having the light-emitting element can use various forms or have various elements. As an example of the display element, the display device, the light-emitting element, or the light-emitting device , there are EL (electroluminescence) elements (EL elements including organic and inorganic substances, organic EL elements, inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc. ), transistors (transistors that emit light according to current), electron-emitting elements, liquid crystal elements, electro ink, electrophoretic elements, grating light valves (GLVs), plasma display panels (PDPs), digital micromirror devices (DMDs), piezoelectric ceramic dis plays, carbon nanotubes, etc., and those having a display medium in which contrast, luminance, reflectivity, transmittance, etc. change due to electromagnetic action. As an example of a display device using an EL element , there is an EL display, etc. As an example of a display device using an electron-emitting element , there is a field emission display (FED) or an SED type flat panel dis play (SED: Surface-conduction Electron-emitt er Display), etc. As an example of a display device using a liquid crystal element , there are liquid crystal dis plays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal dis plays, direct-view liquid crystal displays, projection liquid crystal displays), etc. As an example of a display device using electro ink or

[0197] As an example of an EL element, there is an element having an anode, a cathode, and an EL layer sandwiched between the anode and the cathode. Examples of EL layers include those that utilize light emission (fluorescence) from singlet excitons, those that utilize light emission (phosphorescence) from triplet excitons, those that include both those that utilize light emission (fluorescence) from singlet excitons and those that utilize light emission (phosphorescence) from triplet excitons, those formed of organic substances, those formed of inorganic substances, those that include both those formed of organic substances and those formed of inorganic substances, those that include polymer materials, those that include low-molecular-weight materials, or those that include polymer materials and low-molecular-weight materials, and the like. However, it is not limited to this, and various EL elements can be used.

[0198] As an example of a liquid crystal element, there is an element that controls light transmission or non-transmission by the optical modulation action of liquid crystal. The element can be structured by a pair of electrodes and a liquid crystal layer. Note that the optical modulation action of liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). Specifically, examples of liquid crystal elements include nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low-molecular-weight liquid crystal, polymer liquid crystal, polymer-dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main-chain liquid crystal, side-chain polymer liquid crystal, plasma-addressed liquid crystal (PALC), banana-type liquid crystal, and the like.

[0199] As an example of an electronic paper display method, there are those displayed by molecules (such as optical anisotropy, dye molecule orientation, etc.), those displayed by particles (such as electrophoresis, particle movement, particle rotation, phase change such as those displayed by the movement of one end of a film, those displayed by the color development / phase change of molecules, those displayed by the light absorption of molecules, or those displayed by self-luminescence due to the combination of electrons and holes, etc. can be used. Specifically, as an example of the display method of electronic paper, microcapsule electrophoresis, horizontal movement electrophoresis, vertical movement electrophoresis, spherical twist ball, magnetic twist ball, cylindrical twist ball method, charged toner, electronic powder fluid, magnetic electrophoresis type, magnetic heat-sensitive type, electro-wetting, light scattering (transparent / opaque change), cholesteric liquid crystal / photoconductive layer, cholesteric liquid crystal, bistable nematic liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion type, movable film, color development and fading by leuco dye, photochromic, electrochromic, electrodeposition, flexible organic EL, etc. are available. However, it is not limited to this, and various things can be used as electronic paper and its display method. Here, by using microcapsule electrophoresis, aggregation and precipitation of electrophoretic particles can be solved. The electronic powder fluid has merits such as high-speed response, high reflectivity, wide viewing angle, low power consumption, and memory property. Those displayed by the color development / phase change of molecules, those displayed by the light absorption of molecules, or those displayed by self-luminescence due to the combination of electrons and holes, etc. can be used. Specifically, as an example of the display method of electronic paper, microcapsule electrophoresis, horizontal movement electrophoresis, vertical movement electrophoresis, spherical twist ball, magnetic twist ball, cylindrical twist ball method, charged toner, electronic powder fluid, magnetic electrophoresis type, magnetic heat-sensitive type, electro-wetting, light scattering (transparent / opaque change), cholesteric liquid crystal / photoconductive layer, cholesteric liquid crystal, bistable nematic liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion type, movable film, color development and fading by leuco dye, photochromic, electrochromic, electrodeposition, flexible organic EL, etc. are available. However, it is not limited to this, and various things can be used as electronic paper and its display method. Here, by using microcapsule electrophoresis, aggregation and precipitation of electrophoretic particles can be solved. The electronic powder fluid has merits such as high-speed response, high reflectivity, wide viewing angle, low power consumption, and memory property. In addition, this embodiment can be appropriately combined with other embodiments shown in this specification. (Embodiment 5) In this embodiment, the configuration that can be used for the pixel portion 102 of the display device shown in FIG. 6 will be described with reference to FIG. 14. FIG. 14(A) shows a part of the configuration of the transistor that can be used for the pixel portion 102.

[0200]

[0201] (Embodiment 5) In this embodiment, the configuration that can be used for the pixel portion 102 of the display device shown in FIG. 6 will be described with reference to FIG. 14.

[0202] FIG. 14(A) shows a part of the configuration of the transistor that can be used for the pixel portion 102. The above figure, and FIG. 14(B) corresponds to the cross-section of the dashed-dotted line A1-A2 shown in FIG. 14(A). FIG. 14(C) is a top view showing a part of the structure of the transistor that can be used for the pixel portion 102, and FIG. 14(D) corresponds to the cross-section of the dashed-dotted line B1-B2 shown in FIG. 14(C). FIG. 14(D) is a figure corresponding to the cross-section of the dashed-dotted line B1-B2 shown in FIG. 14(C). Also, for parts having the same functions as those described in the previous embodiments, the same reference numerals and the same hatching are attached, and detailed descriptions thereof are omitted. In the top views shown in FIGS. 14(A) and (C), the insulating layers 206, 208, 214, 216, 218, etc. are omitted from the illustration in order to avoid complication of the drawing. The transistor that can be used for the pixel portion 102 shown in FIGS. 14(A) and (B) has a configuration including a conductive layer 204a formed on the substrate 202, the substrate 202, and insulating layers 206 and 208 formed on the conductive layer 204a, a semiconductor layer 210a formed on the insulating layer 208, and conductive layers 212d and 212e electrically connected to the semiconductor layer 210a. Above the transistor, insulating layers 214, 216, and 218 are formed, and the conductive layer 212e and the conductive layer 220c are electrically connected through openings provided in the insulating layers 214, 216, and 218.

[0203] The structure shown in FIGS. 14(A) and (B) is different from the structure shown in FIG. 6 in the position of the conductive layer 220c. Specifically, in the structure shown in FIGS. 14(A) and (B), the conductive layer 220c is disposed in a region that partially overlaps with the semiconductor layer 210a.

[0204]

[0205]

[0206]

[0207] ​​​​​​​​​​​By adopting the configurations shown in FIGS. 14(A) and (B), for the transistor used in the pixel portion 102, with respect to an overcurrent from above, the overcurrent can be discharged using the conductive layer 220c.

[0208] The transistor that can be used for the pixel portion 102 shown in FIGS. 14(C) and (D) includes a conductive layer 204a formed on a substrate 202, the substrate 202, and insulating layers 206 and 208 formed on the conductive layer 204a, and a semiconductor layer 210a formed on the insulating layer 208, and conductive layers 212d and 212e electrically connected to the semiconductor layer 210a.

[0209] Also, insulating layers 214, 216, and 218 are formed on the transistor, and the conductive layer 212e and the conductive layer 220c are electrically connected through openings provided in the insulating layers 214, 216, and 218.

[0210] The structure shown in FIGS. 14(C) and (D) is different from the structure shown in FIG. 6 in the position of the insulating layer 208. Specifically, the structure shown in FIGS. 14(C) and (D) is formed at positions substantially the same as the side end portion of the semiconductor layer 210a and the side end portion of the insulating layer 208. For example, by using the mask at the time of forming the semiconductor layer 210a and etching a part of the insulating layer 208, the configuration shown in FIGS. 14(C) and ( D) can be obtained.

[0211] By adopting the configuration shown in FIGS. 14(C) and (D), for example, the charge charged in the conductive layer 220c can be discharged to the conductive layer 204a through the conductive layer 212e and the insulating layer 206.

[0212] It should be noted that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0213] ​​​​ (Embodiment 6) In this embodiment, a configuration that can be used as the protection circuit 106 shown in FIG. 1 will be described with reference to FIGS. 15 to 17.

[0214] FIGS. 15(A) and 15(B) show top views of elements that can be used as the protection circuit 106, FIG. 15(C) is a view corresponding to the cross sections of the dashed lines C1-C2 and C3-C4 shown in FIG. 15(A), and FIG. 15(D) is a view corresponding to the cross sections of the dashed lines D1-D2 and D3- D4 shown in FIG. 15(B).

[0215] FIGS. 15(A) and 15(C) represent a resistance element that can be used as the protection circuit 106. The resistance element shown in FIGS. 15(A) and 15(C) includes insulating layers 206 and 208 formed on the substrate 202, a semiconductor layer 210c formed on the insulating layer 208, and conductive layers 212g and 212h electrically connected to the semiconductor layer 210c.

[0216] FIGS. 15(B) and 15(D) represent a resistance element that can be used as the protection circuit 106. The resistance element shown in FIGS. 15(B) and 15(D) includes insulating layers 206 and 208 formed on the substrate 202, a semiconductor layer 210c formed on the insulating layer 208, and conductive layers 212g and 212h, insulating layers 214, 216, and 218 formed on the insulating layer 208, the semiconductor layer 210c, and the conductive layers 212g and 212h, a conductive layer 220d formed on the insulating layer 218 and electrically connecting the conductive layer 212g and the semiconductor layer 210c, and a conductive layer 220e formed on the insulating layer 218 and electrically connecting the conductive layer 212h and the semiconductor layer 210c.

[0217] The above resistance element can use the semiconductor layer 210c as the resistance element. Also, by configuring the semiconductor layer 210c as shown in FIGS. 15(A) and (B), the resistivity can be controlled. Also, FIGS. 16(A), (B), and (C) show an example of a circuit configuration that can be used as the protection circuit 106.

[0218]

[0219] The circuit configuration shown in FIG. 16(A) has wirings 451, 452, 481 and transistors 402, 404.

[0220] For transistor 402, the first terminal that functions as the source electrode is electrically connected to the second terminal that functions as the gate electrode, and the third terminal that functions as the drain electrode is electrically connected to wiring 45 1. Also, the first terminal of transistor 402 is electrically connected to wiring 481. For transistor 404, the first terminal that functions as the source electrode is electrically connected to the second terminal that functions as the gate electrode, and the third terminal that functions as the drain electrode is electrically connected to wiring 45 2. Also, the first terminal of transistor 404 is electrically connected to wiring 481.

[0221] The circuit configuration shown in FIG. 16(B) has wirings 453, 454, 482, 483, 484 and transistors 406, 408, 410, 412.

[0222] For transistor 406, the first terminal that functions as the source electrode is electrically connected to the second terminal that functions as the gate electrode, and the third terminal that functions as the drain electrode is electrically connected to wiring 48 is electrically connected to 3. Further, the first terminal of the transistor 406 is electrically connected to the wiring 482.

[0223] For the transistor 408, the first terminal functioning as a source electrode is electrically connected to the second terminal functioning as a gate electrode, and the third terminal functioning as a drain electrode is electrically connected to the wiring 48 4. Further, the first terminal of the transistor 408 is electrically connected to the wiring 483. For the transistor 410, the first terminal functioning as a source electrode is electrically connected to the second terminal functioning as a gate electrode, and the third terminal functioning as a drain electrode is electrically connected to the wiring 48 2. Further, the first terminal of the transistor 410 is electrically connected to the wiring 483.

[0224] For the transistor 412, the first terminal functioning as a source electrode is electrically connected to the second terminal functioning as a gate electrode, and the third terminal functioning as a drain electrode is electrically connected to the wiring 48 3. Further, the first terminal of the transistor 412 is electrically connected to the wiring 484. For the transistor 414, the first terminal functioning as a source electrode is electrically connected to the second terminal functioning as a gate electrode, and the third terminal functioning as a drain electrode is electrically connected to the wiring 48 5. Further, the first terminal of the transistor 414 is electrically connected to the wiring 486.

[0225] For the transistor 412, the first terminal functioning as a source electrode is electrically connected to the second terminal functioning as a gate electrode, and the third terminal functioning as a drain electrode is electrically connected to the wiring 48 3. Further, the first terminal of the transistor 412 is electrically connected to the wiring 484. 3. Further, the first terminal of the transistor 412 is electrically connected to the wiring 484. The circuit configuration shown in FIG. 16(C) includes wirings 455, 456, 485, 486, and transistors 414, 416.

[0226] For the transistor 414, the first terminal functioning as a source electrode is electrically connected to the second terminal functioning as a gate electrode, and the third terminal functioning as a drain electrode is electrically connected to the wiring 48 5. Further, the first terminal of the transistor 414 is electrically connected to the wiring 486.

[0227] For the transistor 414, the first terminal functioning as a source electrode is electrically connected to the second terminal functioning as a gate electrode, and the third terminal functioning as a drain electrode is electrically connected to the wiring 48 5. Further, the first terminal of the transistor 414 is electrically connected to the wiring 486. 5. Further, the first terminal of the transistor 414 is electrically connected to the wiring 486. It is connected pneumatically.

[0228] The transistor 416 has a first terminal that functions as a source electrode electrically connected to a second terminal that functions as a gate electrode, and a third terminal that functions as a drain electrode is electrically connected to the wiring 486. Also, the first terminal of the transistor 416 is electrically connected to the wiring 485.

[0229] The protection circuit 106 that can be used in one aspect of the present invention can also use a diode-connected transistor as shown in the circuit configurations of FIGS. 16(A), (B), and (C).

[0230] Also, in the circuit configurations shown in FIGS. 16(A), (B), and (C), by making the connection between the first terminal that functions as a source electrode and the second terminal that functions as a gate electrode the configuration shown in FIG. 17, it becomes possible to arbitrarily control the resistivity.

[0231] FIG. 17(A) shows a resistance element that can be used as the protection circuit 106. Also, the resistance element shown in FIG. 17(A) includes a conductive layer 204e formed on the substrate 202, insulating layers 206 and 208 formed on the substrate 202 and the conductive layer 204e, a semiconductor layer 210d formed on the insulating layer 208, a conductive layer 212i electrically connected to the semiconductor layer 210d, insulating layers 214, 216, and 218 formed on the insulating layer 208, the semiconductor layer 210d, and the conductive layer 212i, and a conductive layer 220f formed on the insulating layer 218 to electrically connect the semiconductor layer 210d and the conductive layer 204e.

[0232] FIG. 17(B) shows a resistance element that can be used as the protection circuit 106. Also, ​​​​​​​​​​​​The resistor element shown in FIG. 17(B) includes a conductive layer 204e formed on a substrate 202, the substrate 202 and insulating layers 206 and 208 formed on the conductive layer 204e, and a semiconductor layer 210d formed on the insulating layer 208, and a conductive layer 212j, and insulating layers 214, 216, and 218 formed on the insulating layer 208, the semiconductor layer 210d, and the conductive layer 212j, and a conductive layer 220g formed on the insulating layer 218 for electrically connecting the conductive layer 212j and the semiconductor layer 210d, and a conductive layer 220h formed on the insulating layer 218 for electrically connecting the conductive layer 204e and the semiconductor layer 210d. formed and having formed on the insulating layer 218 for electrically connecting the conductive layer 204e and the semiconductor layer 210d and having.

[0233] FIG. 17(C) represents a resistor element that can be used as the protection circuit 106. Also, the resistor element shown in FIG. 17(C) includes a conductive layer 204e formed on a substrate 202, the substrate 202 and insulating layers 206 and 208 formed on the conductive layer 204e, and a semiconductor layer 210d formed on the insulating layer 208, a conductive layer 212j, and a conductive layer 212k electrically connected to the semiconductor layer 210d, and insulating layers 214, 216, and 218 formed on the insulating layer 208, the semiconductor layer 210d, the conductive layer 212j, and the conductive layer 21 2k, and a conductive layer 220i formed on the insulating layer 218 for electrically connecting the conductive layer 212j and the semiconductor layer 210d, and a conductive layer 22 0j formed on the insulating layer 218 for electrically connecting the conductive layer 212k and the conductive layer 204e. formed and having formed on the insulating layer 218 for electrically connecting the conductive layer 212k and the conductive layer 204e and having.

[0234] The semiconductor layers 210c and 210d used in the resistor elements described in FIGS. 15 to 17 can be used by referring to the materials described for the semiconductor layers 210a and 210b shown in the previous embodiment. Also, the semiconductor layers 210c and 210d can be formed in the same process as the formation of the semiconductor layers 210a and 210b. . It can be formed at.

[0235] Also, the conductive layers 212g, 212h, 21 2i, 212j, 212k used in the resistance elements described in FIGS. 15 to 17 can be used by referring to the materials described in the conductive layers 212a, 212b, 212 c, 212d, 212e, 212f shown in the previous embodiment. Also, the conductive layers 212g, 212h can be formed in the same process as the formation of the conductive layers 212a, 212b, 212c, 212d, 212 e, 212f.

[0236] Also, the conductive layers 220d, 220e, 22 0f, 220g, 220h, 220i, 220j used in the resistance elements described in FIGS. 15 to 17 can be used by referring to the materials described in the conductive layers 220 a, 220b, 220c shown in the previous embodiment. Also, the conductive layer 22 0d, 220e can be formed in the same process as the formation of the conductive layers 220a, 220b, 220c It can be done.

[0237] Thus, as the conductive layer used in the protection circuit, a conductive layer that functions as a gate electrode of a transistor and a conductive layer that functions as a source electrode and a drain electrode of a transistor can be used . For example, speaking separately about the configuration of the protection circuit 106 shown in FIG. 17(B), it can be expressed as follows . It can be expressed as follows.

[0238] The protection circuit 106 shown in FIG. 17(B) includes a first conductive layer (conductive layer 204e) formed on the same surface as the gate electrode, a first insulating layer (insulating layers 206, 208) on the first conductive layer (conductive layer 204e), and an oxide semiconductor layer (semiconductor layer 210d) formed on the first insulating layer (insulating layers 206, 208) and overlapping with the first conductive layer (conductive layer 204e). a second insulating layer (insulating layers 214, 216, 218) on the semiconductor layer (semiconductor layer 210d), and a second conductive layer (conductive layers 220g, 2 20h) on the second insulating layer (insulating layers 214, 216, 218), and the second conductive layer (conductive layers 220g, 220h) is electrically connected to the oxide semiconductor layer (semiconductor layer 210d) at an opening provided in the second insulating layer (insulating layers 214, 216, 218).

[0239] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0240] (Embodiment 7) In this embodiment, the configuration of the transistor that can be used for the pixel portion 102 and the drive circuit portion 104 of the display device shown in FIG. 1(A) of Embodiment 1 will be described below with reference to FIG. 18. The following description will be given.

[0241] The transistor shown in FIG. 18(A) has a conductive layer 204c formed on a substrate 202, insulating layers 206 and 208 formed on the substrate 202 and the conductive layer 204c, an oxide stack 211 formed on the insulating layer 208, and conductive layers 212d and 212e formed on the insulating layer 208 and the oxide stack 211. Further, the transistor shown in FIG. 18(A) may have a configuration including insulating layers 214, 216, and 218 formed on the transistor, more specifically, on the insulating layer 208, the oxide stack 211, and the conductive layers 212d and 212e.

[0242] Depending on the type of the conductive film used for the conductive layers 212d and 212e, oxygen may be taken away from a part of the oxide stack 211, or a mixed layer may be formed to form an n-type region 209 in the oxide stack 211. ​​​​​​​​​It may be formed. In FIG. 18(A), the n-type region 209 can be formed in a region near the interface in contact with the conductive layers 212d and 212e in the oxide layer 211. Note that the n-type region 20 9 can function as a source region and a drain region. 9 can function as a source region and a drain region.

[0243] In addition, in the transistor shown in FIG. 18(A), the conductive layer 204c functions as a gate electrode, the conductive layer 212d functions as a source electrode or a drain electrode, and the conductive layer 212e functions as a source electrode or a drain electrode.

[0244] In addition, in the transistor shown in FIG. 18(A), the distance between the conductive layers 212d and 212e of the oxide layer 211 in the region overlapping with the conductive layer 204c is defined as the channel length. Also, the channel formation region refers to a region in the oxide layer 211 that overlaps with the conductive layer 204c and is sandwiched between the conductive layers 21 2d and 212e. Also, the channel refers to a region in the channel formation region where current mainly flows. 2d and 212e. Also, the channel refers to a region in the channel formation region where current mainly flows. 2d and 212e. Also, the channel refers to a region in the channel formation region where current mainly flows.

[0245] Here, the details of the oxide layer 211 will be described in detail with reference to FIG. 18(B).

[0246] FIG. 18(B) is an enlarged view of the region surrounded by the broken line of the oxide layer 211 shown in FIG. 18(A). The oxide layer 211 includes an oxide semiconductor layer 211a and an oxide layer 211b. The oxide layer 211 includes an oxide semiconductor layer 211a and an oxide layer 211b.

[0247] The oxide semiconductor layer 211a preferably includes a layer represented by an In-M-Zn oxide containing at least indium (In), zinc (Zn), and M (a metal such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf). Note that the oxide semiconductor layer 211a is the above-mentioned The oxide semiconductor layer 211a preferably includes a layer represented by an In-M-Zn oxide containing at least indium (In), zinc (Zn), and M (a metal such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf). Note that the oxide semiconductor layer 211a is the above-mentioned The oxide semiconductor layer 211a preferably includes a layer represented by an In-M-Zn oxide containing at least indium (In), zinc (Zn), and M (a metal such as Al, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf). Note that the oxide semiconductor layer 211a is the above-mentioned An oxide semiconductor material that can be used for the semiconductor layers 210a and 210b shown in the embodiments, or the formation method or the like can be appropriately incorporated.

[0248] The oxide layer 211b is composed of one or more of the elements constituting the oxide semiconductor layer 211a , and the energy at the lower end of the conduction band is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less, and is an oxide film close to the vacuum level. At this time, when an electric field is applied to the conductive layer 204c that functions as a gate electrode, a channel is formed in the oxide semiconductor layer 211a having a lower energy at the lower end of the conduction band among the oxide stacks 211. That is, by having the oxide layer 211b between the oxide semiconductor layer 211a and the insulating layer 214, the channel of the transistor can be formed in the oxide semiconductor layer 211a that does not contact the insulating layer 214. Further, since the oxide layer 211b is composed of one or more of the elements constituting the oxide semiconductor layer 211a, interface scattering is unlikely to occur between the oxide semiconductor layer 211a and the oxide layer 211b. Therefore, the movement of carriers is not inhibited between the oxide semiconductor layer 211a and the oxide layer 211b, and the field-effect mobility of the transistor is increased. In addition, it is difficult to form interface levels between the oxide semiconductor layer 211a and the oxide layer 211b. If there are interface levels between the oxide semiconductor layer 211a and the oxide layer 211b, a second transistor with a different threshold voltage using the interface as a channel may be formed, and the apparent threshold voltage of the transistor may vary. Therefore, by providing the oxide layer 211b, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced. That is, by having the oxide layer 211b between the oxide semiconductor layer 211a and the insulating layer 214, the channel of the transistor can be formed in the oxide semiconductor layer 211a that does not contact the insulating layer 214. That is, by having the oxide layer 211b between the oxide semiconductor layer 211a and the insulating layer 214, the channel of the transistor can be formed in the oxide semiconductor layer 211a that does not contact the insulating layer 214. That is, by having the oxide layer 211b between the oxide semiconductor layer 211a and the insulating layer 214, the channel of the transistor can be formed in the oxide semiconductor layer 211a that does not contact the insulating layer 214. In addition, since the oxide layer 211b is composed of one or more of the elements constituting the oxide semiconductor layer 211a, the oxide layer 211b is composed of one or more of the elements constituting the oxide semiconductor layer 211a, interface scattering is unlikely to occur between the oxide semiconductor layer 211a and the oxide layer 211b. Therefore, the movement of carriers is not inhibited between the oxide semiconductor layer 211a and the oxide layer 211b, and the field-effect mobility of the transistor is increased. In addition, it is difficult to form interface levels between the oxide semiconductor layer 211a and the oxide layer 211b. If there are interface levels between the oxide semiconductor layer 211a and the oxide layer 211b, a second transistor with a different threshold voltage using the interface as a channel may be formed, and the apparent threshold voltage of the transistor may vary. Therefore, by providing the oxide layer 211b, variations in electrical characteristics such as the threshold voltage of the transistor can be reduced.

[0249] The oxide layer 211b is made of In-M-Zn oxide (Al, Ti, Ga, Ge, Y, Zr , Sn, La, Ce, Hf, or other metal), and Specifically, the oxide layer 211b includes an oxide semiconductor The above elements are contained in the layer 211a at a concentration 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more. The oxide layer contains indium at an atomic ratio of more than 100 times higher than that of the oxide layer. Therefore, it has a function of suppressing the occurrence of oxygen deficiency in the oxide layer. The layer 211b is an oxide layer in which oxygen vacancies are less likely to occur than in the oxide semiconductor layer 211a.

[0250] That is, the oxide semiconductor layer 211a and the oxide layer 211b contain at least indium, zinc and M (metals such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf) When the oxide layer 211b is an In-M-Zn oxide containing In:M:Zn=x1:y1: z1 [atomic ratio], and the oxide semiconductor layer 211a is In:M:Zn=x2:y2:z2 [atomic ratio]. It is preferable that y1 / x1 is greater than y2 / x2. 1 is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more, of y2 / x2. At this time, in the oxide semiconductor layer 211a, when y2 is equal to or larger than x2, However, if y2 is three times or more larger than x2, the electrical characteristics of the transistors become unstable. Since the field effect mobility of the transistor is reduced, y2 is preferably less than three times x2. I wish.

[0251] When the oxide semiconductor layer 211a is an In-M-Zn oxide, the number of atoms of In and M is The ratio is preferably that In is 25 atomic % or more and M is less than 75 atomic %, and further preferably that In is 34 atomic % or more and M is less than 66 atomic %. Also, when the oxide layer 211b is an In-M-Zn oxide, the atomic ratio of In and M is preferably such that In is less than 50 atomic % and M is 50 atomic % or more, and more preferably In is less than 25 atomic % and M is 75 atomic % or more.

[0252] For the oxide semiconductor layer 211a and the oxide layer 211b, for example, an oxide semiconductor containing indium, zinc, and gallium can be used. Specifically, as the oxide semiconductor layer 21 1a, an In-Ga-Zn oxide with In:Ga:Zn = 1:1:1 [atomic ratio], an In-Ga-Zn oxide with In:Ga:Zn = 3:1:2 [atomic ratio], or an oxide having a composition in the vicinity thereof can be used. As the oxide layer 211b, In:Ga:Zn = 1:3:2 [atomic ratio] In-Ga-Zn oxide, In:Ga:Zn = 1:6:4 atomic ratio] In-Ga-Zn oxide, In:Ga:Zn = 1:9:6 [atomic ratio] I n-Ga-Zn oxide, or an oxide having a composition in the vicinity thereof can be used.

[0253] Also, the thickness of the oxide semiconductor layer 211a is 3 nm or more and 200 nm or less, preferably 3 n m or more and 100 nm or less, and more preferably 3 nm or more and 50 nm or less. Also, the oxide layer 211b has a thickness of 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less as well.

[0254] Next, the band structure of the oxide stack 211 will be described with reference to FIGS. 18(C) and (D). Hereinafter.

[0255] As an example, I with an energy gap of 3.15 eV is used as the oxide semiconductor layer 211a n-Ga-Zn oxide, and In-Ga-Zn oxide with an energy gap of 3.5 eV is used as the oxide layer 211b The energy gap was measured using a spectroscopic ellipsometer (H ORIBA JOBIN YVON UT-300).

[0256] The energy difference between the vacuum level and the top of the valence band of the oxide semiconductor layer 211a and the oxide layer 211b (also referred to as the ionization potential) was 8 eV and 8.2 eV, respectively. Also, the energy difference between the vacuum level and the top of the valence band was measured using an ultraviolet photoelectron spectroscopy (UPS: Ult raviolet Photoelectron Spectroscopy) apparatus (P HI VersaProbe). The measurement was performed using the apparatus.

[0257] Therefore, the energy difference between the vacuum level and the bottom of the conduction band of the oxide semiconductor layer 211a and the oxide layer 211b (also referred to as the electron affinity) was 4.85 eV and 4.7 eV, respectively and. It was.

[0258] FIG. 18(C) schematically shows a part of the band structure of the oxide stack 211. Here is the case where a silicon oxide film is provided in contact with the oxide stack 211. Note that in FIG 18(C), EcI1 represents the energy of the bottom of the conduction band of the silicon oxide film, EcS1 represents the energy of the bottom of the conduction band of the oxide semiconductor layer 211a, EcS2 represents the energy of the bottom of the conduction band of the oxide layer 211 b, and EcI2 represents the energy of the bottom of the conduction band of the silicon oxide film . Also, EcI1 corresponds to the insulating layer 208 in FIG. 18(A), and EcI2 In FIG. 18(A), it corresponds to the insulating layer 214.

[0259] As shown in FIG. 18(C), in the oxide semiconductor layer 211a and the oxide layer 211b, the energy at the lower end of the conduction band changes smoothly without a barrier. In other words, it can be said that it changes continuously. This is because the oxide layer 211b contains elements common to the oxide semiconductor layer 211a, and a mixed layer is formed by the mutual movement of oxygen between the oxide semiconductor layer 211a and the oxide layer 211b. This can be said to be the reason.

[0260] From FIG. 18(C), it can be seen that the oxide semiconductor layer 211a of the oxide stack 211 becomes a well, and in the transistor using the oxide stack 211, the channel region is formed in the oxide semiconductor layer 211a. Note that since the energy at the lower end of the conduction band of the oxide stack 211 changes continuously, it can also be said that the oxide semiconductor layer 211a and the oxide layer 211b are continuously joined.

[0261] Note that as shown in FIG. 18(C), although trap levels due to impurities or defects may be formed near the interface between the oxide layer 211b and the insulating layer 214, by providing the oxide layer 211b, the oxide semiconductor layer 211a and the trap levels can be separated. However, when the energy difference between EcS1 and EcS2 is small, electrons may reach the trap levels exceeding the energy difference. When electrons are trapped in the trap levels, negative charges are generated at the insulating layer interface, and the threshold voltage of the transistor may shift in the positive direction. Therefore, the energy difference between EcS1 and EcS2 is 0.1 eV or more, preferably ​​​​​​​​When it is 0.15 eV or more, the variation in the threshold voltage of the transistor is reduced, resulting in stable electrical characteristics, which is preferable. It is suitable because it has stable electrical characteristics.

[0262] FIG. 18(D) schematically shows a part of the band structure of the oxide layer 211, which is a modified example of the band structure shown in FIG. 18(C). Here, the case where a silicon oxide film is provided in contact with the oxide layer 211 will be described. Note that EcI1 shown in FIG. 18(D) represents the energy at the lower end of the conduction band of the silicon oxide film, EcS1 represents the energy at the lower end of the conduction band of the oxide semiconductor layer 211a, and EcI2 represents the energy at the lower end of the conduction band of the silicon oxide film. Also, EcI1 corresponds to the insulating layer 208 in FIG. 18(A), and EcI2 corresponds to the insulating layer 214 in FIG. 18(A). In the transistor shown in FIG. 18(A), when forming the conductive layers 212d and 212e, the oxide layer 211b above the oxide layer 211, that is, the oxide layer 211b may be etched. However, the upper surface of the oxide semiconductor layer 211a may form a mixed layer of the oxide semiconductor layer 211a and the oxide layer 211b when forming the oxide layer 211b. For example, when the oxide semiconductor layer 211a is an In-Ga-Zn oxide with In:Ga:Zn = 1:1:1 [atomic ratio] or an In-Ga-Zn oxide with In:Ga:Zn = 3:1:2 [atomic ratio], and the oxide layer 211b is an In-Ga-Zn oxide with In:Ga:Zn = 1:3:2 [atomic ratio] or an In-Ga-Zn oxide with In:Ga:Zn = 1:6:4 [atomic ratio], the Ga content in the oxide layer 211b is higher than that in the oxide semiconductor layer 211a. the energy at the lower end of the conduction band of the oxide semiconductor layer 211a, and EcI2 represents the energy at the lower end of the conduction band of the silicon oxide film. Also, EcI1 corresponds to the insulating layer 208 in FIG. 18(A), and EcI2 corresponds to the insulating layer 214 in FIG. 18(A). the energy at the lower end of the conduction band of the silicon oxide film. Also, EcI1 corresponds to the insulating layer 208 in FIG. 18(A), and EcI2 corresponds to the insulating layer 214 in FIG. 18(A). In FIG. 18(A), EcI1 corresponds to the insulating layer 208, and EcI2 corresponds to the insulating layer 214. In FIG. 18(A), EcI1 corresponds to the insulating layer 208, and EcI2 corresponds to the insulating layer 214.

[0263] In the transistor shown in FIG. 18(A), when forming the conductive layers 212d and 212e, the oxide layer 211b above the oxide layer 211, that is, the oxide layer 211b may be etched. However, the upper surface of the oxide semiconductor layer 211a may form a mixed layer of the oxide semiconductor layer 211a and the oxide layer 211b when forming the oxide layer 211b. However, when forming the oxide layer 211b, a mixed layer of the oxide semiconductor layer 211a and the oxide layer 211b may be formed on the upper surface of the oxide semiconductor layer 211a. However, the upper surface of the oxide semiconductor layer 211a may form a mixed layer of the oxide semiconductor layer 211a and the oxide layer 211b when forming the oxide layer 211b. However, when forming the oxide layer 211b, a mixed layer of the oxide semiconductor layer 211a and the oxide layer 211b may be formed on the upper surface of the oxide semiconductor layer 211a.

[0264] For example, when the oxide semiconductor layer 211a is an In-Ga-Zn oxide with In:Ga:Zn = 1:1:1 [atomic ratio] or an In-Ga-Zn oxide with In:Ga:Zn = 3:1:2 [atomic ratio], and the oxide layer 211b is an In-Ga-Zn oxide with In:Ga:Zn = 1:3:2 [atomic ratio] or an In-Ga-Zn oxide with In:Ga:Zn = 1:6:4 [atomic ratio], the Ga content in the oxide layer 211b is higher than that in the oxide semiconductor layer 211a. In-Ga-Zn oxide with In:Ga:Zn = 1:3:2 [atomic ratio], or an In-Ga-Zn oxide with In:Ga:Zn = 1:6:4 [atomic ratio], the Ga content in the oxide layer 211b is higher than that in the oxide semiconductor layer 211a. In-Ga-Zn oxide with In:Ga:Zn = 1:3:2 [atomic ratio], or an In-Ga-Zn oxide with In:Ga:Zn = 1:6:4 [atomic ratio], the Ga content in the oxide layer 211b is higher than that in the oxide semiconductor layer 211a. Since the content is large, a GaOx layer or a mixed layer containing more Ga than the oxide semiconductor layer 211a can be formed on the upper surface of the oxide semiconductor layer 211a.

[0265] Therefore, even when the oxide layer 211b is etched, the energy of the lower end of the conduction band on both sides of EcI of EcS1 may increase and become like the band structure shown in FIG. 18(D).

[0266] Note that this embodiment can be appropriately combined with other embodiments shown in this specification.

[0267] (Embodiment 8) In this embodiment, the configuration of the connection terminal portion that can be used in the display device shown in FIG. 1(A) of Embodiment 1 will be described below with reference to FIG. 19. Also, for portions having the same functions as those described in the previous embodiments, the same reference numerals and the same hatching are attached, and detailed descriptions thereof are omitted.

[0268] The connection terminal portion 103 that can be used in the display device shown in FIG. 19 includes insulating layers 206 and 208 formed on the substrate 202, a conductive layer 212m formed on the insulating layer 208, and insulating layers 214 and 216 formed on the insulating layer 208. Further, the insulating layers 214 and 216 are provided with openings reaching the conductive layer 212m, and are electrically connected to the terminals of the FPC 264 via the anisotropic conductive agent 262.

[0269] Also, in the connection terminal portion 103, a sealing material 266 is formed on the insulating layer 216. The liquid crystal layer 260 is sealed between the substrate 202 and the substrate 252 by the sealing material 266.

[0270] ​​​​​​​​​​​​​ Moreover, the insulating layers 206 and 208 can be made of the materials shown in the previous embodiment.

[0271] The conductive layer 212m is a conductive layer formed in the protection circuit 106 and the drive circuit section 104. They can be formed from the same conductive film as 212a, 212b, and 212c.

[0272] The anisotropic conductive agent 262 is a mixture of thermosetting or thermosetting and photosetting resin with conductive particles. It is a paste or sheet-like material that has been mixed together and hardened. Anisotropic conductive agent 262 The anisotropic conductive agent 262 is a material that exhibits anisotropic conductivity when exposed to light or when bonded under heat. The conductive particles that can be used are, for example, spherical organic resins coated with thin gold films of Au, Ni, Co, etc. Metal coated particles can be used.

[0273] As shown in this embodiment, the present invention is applied to a connection terminal portion 103 and a driving circuit portion 104. By providing the protection circuit 106, which is an embodiment of the present invention, for example, electrostatic discharge when attaching the FPC 264 can be prevented. It is possible to protect the drive circuit unit 104 from an overcurrent caused by a fire or the like. As a result, a highly reliable display device can be provided.

[0274] In this specification, the display device refers to an image display device or a light source (including a lighting device). It also refers to modules with connectors, such as FPC or TCP. COG method for modules with printed wiring boards on the TCP ends, or display elements According to the formula, all modules on which ICs (integrated circuits) are directly mounted are also included in the display device. .

[0275] Note that the structure described in this embodiment mode may be appropriately combined with structures described in other embodiments. It can be used.

[0276] (Embodiment 9) In this embodiment, a touch sensor and a display module that can be combined with a display device according to one aspect of the present invention will be described with reference to FIGS. 20 to 23.

[0277] FIG. 20(A) is an exploded perspective view showing a configuration example of a touch sensor 4500, and FIG. 20(B) is a plan view showing a configuration example of the electrodes of the touch sensor 4500. Further, FIG. 21 is a cross-sectional view showing a configuration example of the touch sensor 4500.

[0278] The touch sensor 4500 shown in FIGS. 20(A) and 20(B) has a plurality of conductive layers 4510 arranged in the X-axis direction and a plurality of conductive layers 4520 arranged in the Y-axis direction intersecting the X-axis direction on a substrate 4910. formed. The touch sensor 4500 shown in FIGS. 20(A) and 20(B) displays a plan view of a plurality of formed conductive layers 4510 and a plan view of a plurality of conductive layers 4520 separately.

[0279] Also, FIG. 21 is an equivalent circuit diagram of the intersection portion of the conductive layer 4510 and the conductive layer 4520 of the touch sensor 4500 shown in FIG. 20. As shown in FIG. 21, a capacitor 4540 is formed at the intersection of the conductive layer 4510 and the conductive layer 45 20.

[0280] Further, the conductive layers 4510 and 4520 have a structure in which a plurality of quadrangular conductive films are connected. The plurality of conductive layers 4510 and the plurality of conductive layers 4520 are arranged so that the positions of the quadrangular portions of the conductive films do not overlap. An insulating film is provided between the intersecting portions of the conductive layer 4510 and the conductive layer 4520 so that the conductive layer 4510 and the conductive layer 4520 do not come into contact. ​​​​​​​ exists.

[0281] Further, FIG. 22 is a cross-sectional view for explaining an example of a connection structure between the conductive layer 4510 and the conductive layer 452 0 of the touch sensor 4500 shown in FIG. 20, and a cross-sectional view of a portion where the conductive layer 4510 (conductive layers 4510a, 4 510b, 4510c) and 4520 intersect is shown as an example.

[0282] As shown in FIG. 22, the conductive layer 4510 is composed of the first-layer conductive layer 4510a and the conductive layer 45 10b, and the second-layer conductive layer 4510c on the insulating layer 4810. The conductive layer 4510a and the conductive layer 4510b are connected by the conductive layer 4510c. The conductive layer 4520 is formed of a first-layer conductive film. An insulating layer 4820 is formed to cover the conductive layers 4510, 4520, and the electrode 47 10. As the insulating layers 4810 and 4820, for example, a silicon oxynitride film may be formed. Note that an underlayer film made of an insulating film may be formed between the substrate 4910 and the conductive layer 4510 and the electrode 47 10. As the underlayer film, for example, a silicon oxynitride film can be formed.

[0283] The conductive layer 4510 and the conductive layer 4520 are formed of a conductive material having translucency with respect to visible light. For example, as the conductive material having translucency, indium tin oxide containing silicon oxide, indium tin oxide, zinc oxide, indium zinc oxide, zinc oxide added with gallium, etc. are available. exist.

[0284] The conductive layer 4510a is connected to the electrode 4710. The electrode 4710 constitutes a connection terminal for connection with an FPC. The conductive layer 4520 is also connected to another electrode 4710 in the same manner as the conductive layer 4510. This continues. The electrode 4710 can be formed, for example, from a tungsten film.

[0285] An insulating layer 4820 is formed covering the conductive layers 4510, 4520 and the electrode 4710. In order to electrically connect the electrode 4710 and the FPC, openings are formed in the insulating layer 4810 and the insulating layer 4820 on the electrode 4710. A substrate 4920 is attached on the insulating layer 4820 by an adhesive or an adhesive film or the like. By attaching the substrate 4910 side to the color filter substrate of the display panel by an adhesive or an adhesive film, a touch panel is configured.

[0286] Next, a display module in which the display device according to an aspect of the present invention can be used will be described with reference to FIGS. 2 and 3.

[0287] The display module 8000 shown in FIG. 23 includes a touch panel 8004 connected to an FPC 8003, a display panel 8006 connected to an FPC 8005, a backlight unit 8007, a frame 8009, a printed circuit board 8010, and a battery 8011 between an upper cover 8001 and a lower cover 8002.

[0288] The upper cover 8001 and the lower cover 8002 can be appropriately changed in shape and dimensions according to the sizes of the touch panel 8004 and the display panel 8006.

[0289] The touch panel 8004 can be used by superimposing a resistive film type or a capacitive type touch panel on the display panel 8006. Also, it is possible to provide a touch panel function on the counter substrate (sealing substrate) of the display panel 8006. Further, for the display panel 8 ​​​It is also possible to provide a photosensor within each pixel of 006 to form an optical touch panel.

[0290] The backlight unit 8007 has a light source 8008. The light source 8008 may be provided at an end of the backlight unit 8007 and may be configured to use a light diffusing plate.

[0291] In addition to protecting the display panel 8006, the frame 8009 functions as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010. Further, the frame 8009 may have a function as a heat sink.

[0292] The printed circuit board 8010 has a power circuit and a signal processing circuit for outputting video signals and clock signals. As the power supply for supplying power to the power circuit, it may be an external commercial power supply or a power supply by a separately provided battery 8011. The battery 801

[0293] 1 can be omitted when using a commercial power supply.

[0294]

[0295] Note that the configurations shown in this embodiment can be appropriately combined with the configurations shown in other embodiments and used.

[0295] (Embodiment 10) In this embodiment, an example of an electronic device will be described.

[0296] FIGS. 24(A) to 24(H) and FIGS. 25(A) to 25(D) are diagrams showing an electronic device. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, an LE D lamp 5004, operation key 5005 (including power switch or operation switch), connection terminal 5006, sensor 5007 (having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance , light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation , flow rate, humidity, gradient, vibration, odor or infrared rays), microphone 5008, etc. can be included.

[0297] Figure 24(A) is a mobile computer, and in addition to the above-mentioned components, it can have a switch 5009 , infrared port 5010, etc. Figure 24(B) is a portable image playback device equipped with a recording medium (e.g., a DVD playback device), and in addition to the above-mentioned components, it can have a second display unit 5002, recording medium reading unit 5011, etc. Figure 24(C) is a go-go type display, and in addition to the above-mentioned components, it can have a second display unit 5002, support unit 5012 , earphone 5013, etc. Figure 24(D) is a portable game machine, and in addition to the above-mentioned components, it can have a recording medium reading unit 5011, etc. Figure 24(E) is a digital camera with a TV receiving function, and in addition to the above-mentioned components, it can have an antenna 5014, shutter button 5015, image receiving unit 5016, etc. Figure 24(F) is a portable game machine, and in addition to the above-mentioned components, it can have a second display unit 5002, recording medium reading unit 5011 , etc. Figure 24(G) is a TV receiver, and in addition to the above-mentioned components, it can have a tuner, image processing unit, etc. Figure 24(H) is a portable TV receiver , and in addition to the above-mentioned components, it can have a charger 5017 capable of transmitting and receiving signals, etc. Figure 25(A) is a display, and in addition to the above-mentioned components, it can have a support stand 5018 , , etc. ​ may include the like. FIG. 25(B) shows a camera, which may include an external connection port 5019, a shutter button 5015, an image receiving unit 5016, and the like. FIG. 25(C) shows a computer, which may include a pointing device 5 020, an external connection port 5019, a reader / writer 5021, and the like. FIG. 25(D) shows a mobile phone, which may include a transmitting unit, a receiving unit, a tuner for a one-segment partial reception service for mobile phones and mobile terminals, and the like.

[0298] The electronic devices shown in FIGS. 24(A) to 24(H) and FIGS. 25(A) to 25(D) may have various functions. For example, functions such as displaying various types of information (still images, moving images, text images, etc. ) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, etc., a function of controlling processing by various software (programs), a wireless communication function , a function of connecting to various computer networks using the wireless communication function, a function of transmitting or receiving various data using the wireless communication function , a function of reading a program or data recorded on a recording medium and displaying it on the display unit, and the like. Further, in an electronic device having a plurality of display units, a function of mainly displaying image information on one display unit and mainly displaying character information on another display unit, or a function of displaying a three-dimensional image by displaying an image considering parallax on a plurality of display units, etc. may be included. Further , in an electronic device having an image receiving unit, functions such as taking a still image, taking a moving image, automatically or manually correcting the taken image, and recording the taken image on a recording medium (external or camera internal) can be included. It can have functions such as a function of saving (stored in the built-in unit), a function of displaying the captured image on the display unit, etc. The functions that the electronic device shown in FIGS. 24(A) to 24(H) and FIGS. 25(A) to 25(D) can have are not limited to these, and it can have various functions. The electronic device described in this embodiment is characterized by having a display unit for displaying some kind of information.

[0299] Next, application examples of the display device will be described. FIG. 25(E) shows an example in which the display device is provided integrally with a building. FIG. 25(E) includes a housing 5022, a display unit 5023, a remote control device 5024 which is an operation unit, a speaker 5025, etc. The display device is wall-mounted and integrated with the building, and can be installed without requiring a large installation space.

[0300] Next, FIG. 25(F) shows another example in which the display device is provided integrally with the building inside the building. The display module 5026 is attached integrally with the unit bus 5027, and the bather can view the display module 5026.

[0301] In this embodiment, a wall and a unit bath are taken as examples of the building, but this embodiment is not limited to this, and the display device can be installed in various buildings. Next, an example in which the display device is provided integrally with a moving body will be shown. FIG. 25(G) is a diagram showing an example in which the display device is provided in an automobile. The display module It can be installed without requiring a large installation space.

[0302] FIG. 25(F) shows another example in which the display device is provided integrally with the building inside the building. The display module 5026 is attached integrally with the unit bus 5027, and the bather can view the display module 5026. In this embodiment, a wall and a unit bath are taken as examples of the building, but this embodiment is not limited to this, and the display device can be installed in various buildings.

[0303] In this embodiment, a wall and a unit bath are taken as examples of the building, but this embodiment is not limited to this, and the display device can be installed in various buildings. Next, an example in which the display device is provided integrally with a moving body will be shown.

[0304] Next, an example in which the display device is provided integrally with a moving body will be shown.

[0305] FIG. 25(G) is a diagram showing an example in which the display device is provided in an automobile. The display module The display 5028 is attached to the vehicle body 5029 of a vehicle, and can display on demand the operation of the vehicle body or information input from inside or outside the vehicle body. Note that it may have a navigation function.

[0306] FIG. 25(H) is a diagram showing an example in which the display device is provided integrally with a passenger aircraft. FIG. 25(H) is a diagram showing the shape in use when a display module 5031 is provided on the ceiling 5030 above the seat of a passenger aircraft. The display module 5031 is integrally attached to the ceiling 5030 via a hinge portion 5032, and the hinge portion 5032 is stretched and contracted so that passengers can view the display module 5031. The display module 5031 has a function of displaying information by being operated by passengers.

[0307] In the present embodiment, examples of the moving body are illustrated as an automobile body and an aircraft fuselage, but the present invention is not limited thereto, and it can be installed in various things such as motorcycles, four-wheeled vehicles (including automobiles, buses, etc.), trains (including monorails, railways, etc.), ships, etc.

[0308] In this specification and the like, in the figures or texts described in a certain embodiment, it is possible to extract a part thereof to constitute an aspect of the invention. Therefore, when a figure or text describing a certain part is described, the content obtained by extracting a part of the figure or text is also disclosed as an aspect of the invention and is assumed to be able to constitute an aspect of the invention. Therefore, for example, active elements (such as transistors and diodes), wiring, passive elements (such as capacitive elements and resistive elements), conductive layers, insulating layers, semiconductor layers, Drawings that describe one or more organic materials, inorganic materials, components, devices, operating methods, manufacturing methods, etc. In the text or figure, it is possible to extract a part of it to form an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (transistors, capacitor elements, etc.), it is possible to extract M (M is an integer, M < N) circuit elements (transistors, capacitor elements, etc.) to form an aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer, M < N) layers to form an aspect of the invention. As yet another example, from a flowchart composed of N (N is an integer) elements, it is possible to extract M (M is an integer, M < N ) elements to form an aspect of the invention.

[0309] In this specification, etc., in the figure or text described in a certain embodiment, when at least one specific example is described, it is easily understood by those skilled in the art to derive the upper concept of the specific example. Therefore, when at least one specific example is described in the figure or text described in a certain embodiment, the upper concept of the specific example is also disclosed as an aspect of the invention and can constitute an aspect of the invention.

[0310] In this specification, etc., at least the content described in the figure (even a part of the figure) is disclosed as an aspect of the invention and can constitute an aspect of the invention. Therefore, for a certain content, if it is described in the figure, even if it is not described in the text, that content is disclosed as an aspect of the invention and constitutes an aspect of the invention.​ It is possible to configure. Similarly, for a figure obtained by extracting a part of the figure, it is also disclosed as one aspect of the invention and it is possible to configure one aspect of the invention. and is disclosed as one aspect of the invention and it is possible to configure one aspect of the invention.

[0311] (Embodiment 11) Note that the conductive film and semiconductor film disclosed in the above embodiment can be formed by sputtering or plasma CVD method, but may also be formed by other methods, for example, thermal CVD (Chemical Va por Deposition) method. As an example of the thermal CVD method, MOC VD (Metal Organic Chemical Vapor Depositi on) method or ALD (Atomic Layer Deposition) method may be used. It is okay.

[0312] Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0313] In the thermal CVD method, the source gas and the oxidant are simultaneously fed into the chamber, and the inside of the chamber is set to atmospheric pressure or under reduced pressure, and the reaction is carried out near or on the substrate to deposit on the substrate to form a film. It may be performed.

[0314] Also, in the ALD method, the inside of the chamber is set to atmospheric pressure or under reduced pressure, and the source gas for the reaction is sequentially introduced into the chamber, and the film formation may be performed by repeating the order of the gas introduction. For example, by switching each switching valve (also called a high-speed valve), two or more types of source gases are sequentially supplied to the chamber, and an inert gas (such as argon or nitrogen) is introduced simultaneously or after the first source gas so that the plurality of types of source gases do not mix. Introduce the raw material gas of 2. When introducing an inert gas simultaneously, the inert gas becomes the carrier gas, and it is also possible to introduce the inert gas simultaneously when introducing the second raw material gas. Alternatively, after discharging the first raw material gas by vacuum exhaust instead of introducing the inert gas, the second raw material gas may be introduced. The first raw material gas adsorbs on the surface of the substrate to form the first layer, reacts with the second raw material gas introduced later, and the second layer is laminated on the first layer to form a thin film. By repeating this gas introduction sequence a plurality of times until the desired thickness is reached while controlling the gas introduction sequence, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, which is suitable for fabricating fine FETs. Thermal CVD methods such as MOCVD and ALD can form the conductive films and semiconductor films disclosed in the embodiments described so far. For example,

[0315] when forming an In-Ga-Zn-O film, trimethylindium, trimethylgallium, and dimethylzinc are used. Note that the chemical formula of trimethylindium is In(CH3)3. Also, the chemical formula of trimethylgallium is Ga(CH3)3. Also, the chemical formula of dimethylzinc is Zn(CH3 )2. Also, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. For example, when forming a tungsten film by a film-forming apparatus using ALD, WF6 gas is used.

[0316] For example, when forming a tungsten film by a film-forming apparatus using ALD, WF6 gas ​Si and B2H6 gases are sequentially and repeatedly introduced to form an initial tungsten film, and then WF6 gas and H2 gas are introduced simultaneously to form a tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0317] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn-O film, using a film-forming apparatus that utilizes ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In- O layer, and then Ga(CH3)3 gas and O3 gas are introduced simultaneously to form a GaO layer. Furthermore, ZnO layer is formed by introducing Zn(CH3)2 and O3 gas simultaneously. Note that the order of these layers is not limited to this example. Also, a mixed compound layer such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may be formed by mixing these gases. Note that H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas may be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, In(C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, G a(C2H5)3 gas may be used. Also, instead of In(CH3)3 gas, In(C 2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

Explanation of Symbols

[0318] 102 Pixel section 103 Connection terminal section 104 Driving circuit section 104a Gate driver 104b Source driver 106 Protection circuit 106_1 Protection circuit 106_2 Protection circuit 106_3 Protection circuit 106_4 Protection Circuit 108 Pixel Circuit 109 Connection Part 110 Wiring 112 Wiring 114 Resistor Element 130 Liquid Crystal Element 131_1 Transistor 131_2 Transistor 133_1 Capacitor Element 133_2 Capacitor Element 134 Transistor 135 Light-Emitting Element 140 Substrate 142 Conductive Layer 144 Insulating Layer 146 Insulating Layer 148 Conductive Layer 151 Transistor 152 Transistor 153 Transistor 154 Transistor 155 Transistor 155A Transistor 155B Transistor 156 Transistor 156A Transistor 156B Transistor 157 Transistor 157A Transistor 157B Transistor 158 Transistor 158A Transistor 158B Transistor 159 Transistor 160 Transistor 161 Transistor 162 Transistor 163 Transistor 164 Transistor 165 Transistor 166 Transistor 171 Resistor Element 172 Resistor Element 173 Resistor Element 174 Resistor element 174A Resistor element 174B Resistor element 175 Resistor element 175A Resistor element 175B Resistor element 176 Resistor element 177 Resistor element 178 Resistor element 179 Resistor element 180 Resistor element 181 Wiring 182 Wiring 183 Wiring 184 Wiring 185 Wiring 186 Wiring 187 Wiring 188 Wiring 189 Wiring 190 Wiring 191 Wiring 199 Resistor element 202 Substrate 204a Conductive layer 204b Conductive layer 204c Conductive layer 204d Conductive layer 204e Conductive layer 206 Insulating layer 207a Opening 207b Opening 208 Insulating layer 209 n-type region 210a Semiconductor layer 210b Semiconductor layer 210c Semiconductor layer 210d Semiconductor layer 211 Oxide stack 211a Oxide semiconductor layer 211b Oxide layer 212a Conductive layer 212b Conductive layer 212c Conductive layer 212d Conductive layer 212e Conductive layer 212f Conductive layer 212g Conductive layer 212h conductive layer 212i conductive layer 212j conductive layer 212k conductive layer 212m conductive layer 214 insulating layer 216 insulating layer 218 insulating layer 219a opening 219b opening 219c opening 220a conductive layer 220b conductive layer 220c conductive layer 220d conductive layer 220e conductive layer 220f conductive layer 220g conductive layer 220h conductive layer 220i conductive layer 220j conductive layer 252 substrate 254 colored layer 256 insulating layer 258 conductive layer 260 liquid crystal layer 262 anisotropic conductive agent 264 FPC 266 sealing material 268 liquid crystal element 402 transistor 404 transistor 406 transistor 408 transistor 410 transistor 412 transistor 414 transistor 416 transistor 451 wiring 452 wiring 453 wiring 454 wiring 455 wiring 456 wiring 481 wiring 482 wiring 483 wiring 484 wiring 485 Wiring 486 Wiring 4500 Touch Sensor 4510 Conductive Layer 4510a Conductive Layer 4510b Conductive Layer 4510c Conductive Layer 4520 Conductive Layer 4540 Capacitance 4710 Electrode 4810 Insulating Layer 4820 Insulating Layer 4910 Substrate 4920 Substrate 5000 Housing 5001 Display Unit 5002 Display Unit 5003 Speaker 5004 LED Lamp 5005 Operation Key 5006 Connection Terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared Port 5011 Recording Medium Reader 5012 Support Part 5013 Earphone 5014 Antenna 5015 Shutter Button 5016 Image Receiving Part 5017 Charger 5018 Support Stand 5019 External Connection Port 5020 Pointing Device 5021 Reader / Writer 5022 Housing 5023 Display Unit 5024 Remote Control Device 5025 Speaker 5026 Display Module 5027 Unit Bus 5028 Display Module 5029 Vehicle Body 5030 Ceiling 5031 indicates the module 5032 Hinge part 8000 indicates the module 8001 Upper cover 8002 Lower cover 8003 FPC 8004 Touch panel 8005 FPC 8006 Display panel 8007 Backlight unit 8008 Light source 8009 Frame 8010 Printed circuit board 8011 Battery

Claims

Claim 1. A pixel section, a drive circuit section disposed outside the pixel section, and a protection circuit electrically connected to either one or both of the pixel section or the drive circuit section and including a pair of electrodes. The pixel section includes pixel electrodes arranged in a matrix, and a first transistor electrically connected to the pixel electrodes. The first transistor has a first insulating layer containing nitrogen and silicon, and a second insulating layer containing oxygen, nitrogen, and silicon. The protection circuit has a second transistor. The second transistor has indium oxide in a channel formation region. In the protection circuit, the second insulating layer has an opening, one of the pair of electrodes contacts the upper surface of the first insulating layer through the opening, and the first insulating layer is provided between the pair of electrodes. A display device.

Images