Communication system, switching method, and switching program

Abstract

According to the present invention, a server switches an NIC that receives a packet to an FPGA-equipped NIC 11 when a time band set in a time table for an FPGA 111 to perform packet processing is reached. Further, even in a time band (time band for a CPU to perform packet processing) other than the time band for the FPGA 111 to perform packet processing, the server switches the NIC that receives a packet to the FPGA-equipped NIC if the amount of power consumption of the server exceeds a predetermined threshold, or if the load of packet processing in a vGW connected to an NIC 12 exceeds a predetermined threshold.

Description

Technical Field

[0001] The present invention relates to a communication system, a switching method, and a switching program.

Background Art

[0002] Conventionally, there is a technology (NFV: Network Function Virtualization) that implements the functions of network devices as VMs (Virtual Machines) on a virtualization platform of a general-purpose server. Since the NFV technology can aggregate physical devices, the equipment cost can be reduced.

[0003] In the NFV technology, the server operates the VM using the CPU and processes network packets, but there is a limit to the processing performance of the CPU. Therefore, when the traffic volume increases, it is necessary to prepare multiple servers, resulting in an increase in equipment cost and power consumption.

[0004] To solve the above problems, a technology has been proposed in which a NIC equipped with an FPGA (Field Programmable Gate Array) is connected to a server, and the packet processing performed by the CPU is offloaded to hardware (FPGA).

Prior Art Documents

Non-Patent Documents

[0005]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] Since the above FPGA has a constant power consumption regardless of the processing load, there is a problem that the power efficiency of the server is poor in a situation where the processing load is low. For example, as shown in FIG. 1, when the amount of traffic to be processed by the server is small, there is a problem that the power consumption for processing packets by the FPGA is larger than that by the CPU.

[0007] Here, for example, as shown in FIG. 2, when the amount of traffic to be processed by the server varies greatly over time, there is a problem that the power efficiency is not good when the server processes packets using the FPGA, whether in a time period with a large amount of traffic (the time period indicated by reference numeral 201) or in a time period with a small amount of traffic (the time period indicated by reference numeral 202).

[0008] To solve the above problems, for example, a method of equipping the server with a NIC (Network Interface Card) equipped with an FPGA and based on the time table shown in FIG. 3, letting the FPGA process packets in a time period with a large amount of traffic and letting the CPU process them in a time period with a small amount of traffic can be considered.

[0009] However, for example, if the amount of traffic unexpectedly increases in a time period when the server has decided to process packets using the CPU, the CPU has to process a large amount of traffic. As a result, a decrease in the power efficiency of the server may occur, and there may also be a decrease in the communication quality provided by the server or a system shutdown.

[0010] Therefore, the present invention prevents a decrease in power efficiency and a decrease in communication quality from occurring even when an unexpected increase in the amount of traffic or an increase in the processing load occurs in a time period when the server is supposed to perform processing using the CPU.

Means for Solving the Problems

[0011] To solve the above problems, the present invention provides a first NIC (Network Interface Card) connected to a virtual machine and equipped with an FPGA (Field Programmable Gate Array) for processing input packets addressed to the virtual machine, a second NIC connected to a virtual machine with the same IP address as the virtual machine and performing input packet processing, a switching unit for switching the NIC that receives the input packet, and a controller that, when a predetermined time period during which the FPGA processes packets arrives, and when the power consumption of the device equipped with the second NIC exceeds a predetermined threshold during the time period when the virtual machine processes packets, or when the packet processing load in the virtual machine connected to the second NIC exceeds a predetermined threshold, instructs the switching unit to switch the NIC that receives the packet to the first NIC.

Advantages of the Invention

[0012] According to the present invention, even when an unexpected increase in traffic volume or an increase in processing load occurs during a time period when the server is configured to perform processing using the CPU, it is possible to prevent a decrease in power efficiency and a decrease in communication quality.

Brief Description of the Drawings

[0013]

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DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments (embodiments) for carrying out the present invention will be described with reference to the drawings. The present invention is not limited to these embodiments.

[0015] [Overview] First, the outline of the server 10 of the present embodiment will be described with reference to FIGS. 4 to 6. As shown in FIG. 4, the server 10 includes a NIC (FPGA-mounted NIC, first NIC) 11 equipped with an FPGA 111 and a normal NIC (second NIC) 12.

[0016] The virtual machines (e.g., vGW (virtual gateway) 15) with redundant configuration are connected to the FPGA - equipped NICs 11 and 12. Here, among the vGWs 15 with redundant configuration, the 0 - series vGW 15 is designated as vGW15a, and the 1 - series vGW 15 is designated as vGW15b. For example, when the 0 - series vGW15a of enterprise 1 becomes incommunicable, the 1 - series vGW15b of enterprise 1 operates in place of vGW15a and processes the input packets. For example, the 0 - series vGW15a is connected to the FPGA - equipped NIC 11, and the 1 - series vGW15b is connected to the NIC 12.

[0017] Based on the time - table in the storage unit 14, the controller 131 manages whether it is the time zone when the server 10 should process packets with the FPGA111 or the time zone when the packets should be processed with the CPU (vGW15b). As shown in FIG. 4, in this time - table, the time zone when the server 10 should process packets with the FPGA111 and the time zone when the packets should be processed with the CPU are set. Note that the time zone when the packets should be processed with the FPGA111 is, for example, the time zone when the traffic volume is relatively large and it is more power - efficient for the server 10 to process packets with the FPGA111. Also, the time zone when the packets should be processed with the CPU is, for example, the time zone when the traffic volume is relatively small and it is more power - efficient for the server 10 to process packets with the CPU.

[0018] Then, based on the time - table, when it is the time zone when the packets should be processed with the FPGA111, the controller 131 gives an instruction to the switching unit 132 to process the packets with the FPGA111. Also, based on the time - table, when it is the time zone when the packets should be processed with the CPU, the controller 131 gives an instruction to the switching unit 132 to process the packets with the CPU.

[0019] Here, even when it is the time zone when the packets should be processed with the CPU, if the power consumption of the server 10 and the processing volume of each vGW15 are large, the controller 131 instructs the switching unit 132 to cause the FPGA111 to process the packets.

[0020] For example, as shown in FIG. 6, the controller 131 monitors the throughput of each vGW15b in the 1 system and obtains the power consumption of the server 10. When the time comes that was previously determined to process packets with the FPGA 111 (Yes in S1 of FIG. 5), the controller 131 instructs the switching unit 132 to process packets with the FPGA 111. On the other hand, even when it is not the time previously determined to process packets with the FPGA 111 (that is, the time when packets should be processed by the CPU) (No in S1), if the power consumption of the server 10 exceeds the threshold (No in S2), the controller 131 instructs the switching unit 132 to switch the packet processing to the FPGA 111.

[0021] Also, even when the power consumption of the server 10 is below the threshold (Yes in S2), if the throughput of each vGW15 (vGW15b) exceeds the threshold (No in S3), the controller 131 instructs the switching unit 132 to switch the packet processing to the FPGA 111.

[0022] Note that when it is not the time previously determined to process packets with the FPGA 111 (that is, the time previously determined to process packets with the CPU), and the power consumption of the server 10 is below the predetermined threshold and the throughput of each vGW15 is below the threshold (No in S1 → Yes in S2 → Yes in S3), the server 10 processes packets with the CPU.

[0023] By doing so, when an unexpected increase in traffic volume or an increase in processing load occurs during the time period previously determined to process packets with the CPU, the controller 131 can switch to process packets with the FPGA 111.

[0024] The switching unit 132 executes the switching of the NIC based on an instruction from the controller 131. For example, when the switching unit 132 receives an instruction from the controller 131 to process packets using the FPGA-mounted NIC 11, it turns on the power of the FPGA-mounted NIC 11. As a result, the vGW 15 corresponding to the VIP (virtual IP address) becomes vGW 15a, so the packets addressed to the VIP are input to the FPGA-mounted NIC 11 and processed by the FPGA 111 (see the path indicated by the thick line in FIG. 6).

[0025] On the other hand, when the switching unit 132 receives an instruction to process packets using the NIC 12, it turns off the power of the FPGA-mounted NIC 11 (see FIG. 7). As a result, the vGW 15 corresponding to the VIP becomes vGW 15b, so the packets addressed to the VIP are input to the NIC 12 and processed by the vGW 15b (see the path indicated by the thick line in FIG. 7). That is, the packets are processed by the CPU of the server 10. Also, when the power of the FPGA-mounted NIC 11 is turned off, the power consumption of the server 10 decreases.

[0026] In this way, the server 10 causes the FPGA 111 to process packets during a time period when it is more power-efficient to process packets with the FPGA 111 (for example, a time period with a large traffic volume), and causes the CPU to process packets during a time period when it is more power-efficient to process packets with the CPU (for example, a time period with a small traffic volume). As a result, it is possible to improve the power efficiency of the server 10 while maintaining the processing performance of the server 10 under high load.

[0027] Also, when an unexpected increase in traffic volume or an increase in processing load occurs during a time period when the server 10 has decided to perform processing with the CPU, the server 10 can switch to having the FPGA 111 process the packets. Thereby, even when an unexpected increase in traffic volume or an increase in processing load occurs, the server 10 can prevent a decrease in power efficiency or a decrease in communication quality from occurring.

[0028] [Configuration Example] Returning to FIG. 4, a configuration example of the server 10 will be described. The server 10 includes an FPGA-mounted NIC 11, a normal NIC 12, an OS 13, a controller 131, a switching unit 132, a storage unit 14, and redundant vGWs 15 (vGW 15a and vGW 15b).

[0029] The FPGA-mounted NIC 11 is a NIC equipped with an FPGA 111 that processes input packets. The FPGA-mounted NIC 11 includes ports (e.g., port1, port2) that control packet input and output. For example, when the FPGA-mounted NIC 11 receives a packet input from port1, the FPGA 111 processes the packet and outputs it from port2. Among the redundant vGWs 15, the 0-series vGW 15a is connected to the FPGA-mounted NIC 11.

[0030] The NIC 12 is a normal NIC, and the 1-series vGW 15b among the redundant vGWs 15 is connected to it. The NIC 12 includes ports (e.g., port3, port4) that control packet input and output. For example, a packet received by the NIC 12 from port3 reaches the vGW 15b via an IF (e.g., eth2) of the OS 13. Then, the packet processed by the vGW 15b is output from port4 of the NIC 12 via an IF (e.g., eth3) of the OS 13.

[0031] The OS 13 is the basic software that operates the server 10. The OS 13 provides, for example, IFs (eth0, eth1) for connecting the FPGA-mounted NIC 11 and the vGW 15a, and IFs (eth2, eth3) for connecting the NIC 12 and the vGW 15b.

[0032] The controller 131 instructs the switching unit 132 on whether to process packets using the FPGA 111 or the CPU. For example, based on the time slots set in the time table for processing packets using the FPGA 111 and the time slots for processing packets using the CPU, the operating status of each vGW15b, and the operating status of the server 10, the controller 131 determines whether to process packets using the FPGA 111 or the CPU and instructs the switching unit 132.

[0033] Note that the operating status of each vGW15b is measured, for example, by the amount of packets input to each vGW15b, the CPU usage rate, etc. For example, the controller 131 has reachability to each vGW15b and acquires the amount of packets input to each vGW15b, the CPU usage rate, etc.

[0034] The operating status of the server 10 is measured, for example, by the power consumption of the server 10. The controller 131 acquires the power consumption of the server 10, for example, through IPMI (Intelligent Platform Management Interface), etc.

[0035] For example, when the time slot for processing packets using the FPGA 111 set in the time table arrives, the controller 131 outputs an instruction to the switching unit 132 to perform packet processing using the FPGA 111. Also, when the time slot for processing packets using the CPU set in the time table arrives, the controller 131 outputs an instruction to the switching unit 132 to perform packet processing using the CPU.

[0036] However, even when it is the time slot for processing packets using the CPU set in the time table, if the power consumption of the server 10 (the server equipped with the NIC 12) exceeds a predetermined threshold, or if the packet processing load in each vGW15b exceeds a predetermined threshold, the controller 131 instructs the switching unit 132 to perform packet processing using the FPGA 111.

[0037] Incidentally, the above power consumption threshold value is, for example, a value at which it is determined that it is more power-efficient to process packets by FPGA 111 than by the CPU when the power consumption of server 10 exceeds the threshold value. Further, the above packet processing load threshold value is, for example, a value at which it is determined that there is a possibility of a decrease in communication quality when the packet processing load in vGW 15b exceeds the threshold value.

[0038] Based on an instruction from controller 131, switching unit 132 executes switching of the NIC. For example, when switching unit 132 receives an instruction from controller 131 to process packets by FPGA 111, it turns on the power of FPGA-mounted NIC 11. On the other hand, when switching unit 132 receives an instruction from controller 131 to process packets by the CPU, it turns off the power of FPGA-mounted NIC 11 (see Fig. 7).

[0039] Note that controller 131 and switching unit 132 may be realized by hardware or by execution processing of a program.

[0040] Storage unit 14 stores data referred to when server 10 executes various processes. For example, storage unit 14 stores a time table referred to by controller 131. As shown in Fig. 4, for example, the time table sets the time period during which server 10 executes packet processing by FPGA 111 and the time period during which it executes packet processing by the CPU.

[0041] The time period set in the time table during which packet processing is executed by FPGA 111 is a time period in which power consumption is lower when packet processing is executed by FPGA 111 than when it is executed by the CPU. The time period is, for example, a time period such as 9:00 - 20:00 when the traffic volume input to server 10 is greater than a predetermined value.

[0042] Also, the time when the CPU executes packet processing, which is set in the time table, is a time period when power consumption is lower when the CPU executes packet processing than when the FPGA-mounted NIC 11 executes packet processing. The said time period is, for example, a time period when the traffic volume input to the server 10 is below a predetermined value, such as a time period other than 9:00 - 20:00.

[0043] The time periods for executing packet processing by the FPGA 111 and the time periods for executing packet processing by the CPU, which are set in the time table, are determined, for example, based on measurement results of the input traffic volume to the server 10 for each time period, etc. Also, the time periods set in the time table can be appropriately changed by an administrator or the like.

[0044] vGW15 is a virtualized gateway that processes packets input via the NIC. vGW15 is configured redundantly. For example, as shown in FIG. 4, when the server 10 prepares vGW15 for the networks of Company 1 and Company 2 respectively, 0-series vGW15a and 1-series vGW15b are prepared for each of Company 1 and Company 2.

[0045] The 0-series vGW15a is a vGW15 that operates in a normal state. The 1-series vGW15b is a vGW15 that operates in place of vGW15a when vGW15a becomes incommunicable. The same virtual IP address is set for each of vGW15a and vGW15b. vGW15a and vGW15b are, for example, virtual routers made redundant by VRRC (Virtual Router Redundancy Protocol), and vGW15a operates as the master router by VRRP. Among vGW15a and vGW15b, vGW15a is connected to the FPGA-mounted NIC 11, and vGW15b is connected to the NIC 12.

[0046] [Example of processing procedure] Next, an example of the processing procedure of the server 10 will be described with reference to FIGS. 8 to 10. First, with reference to FIG. 8, a procedure for the server 10 to determine whether to process a packet by the FPGA 111 or the CPU will be described.

[0047] For example, when the controller 131 of the server 10 refers to the time table and determines that the current time is the time for the FPGA to process the packet (Yes in S11), it is determined to process the packet by the FPGA 111 (S12). On the other hand, when the controller 131 refers to the time table and determines that the current time is not the time for the FPGA to process the packet (No in S11), and the power consumption of the server 10 is equal to or less than the threshold value (Yes in S21), and the processing amount of each vGW15b is equal to or less than the threshold value (Yes in S22), it is determined to process the packet by the CPU (S23).

[0048] Also, when the controller 131 refers to the time table and determines that the current time is not the time for the FPGA to process the packet (No in S11), but the power consumption of the server 10 exceeds the threshold value (No in S21), it is determined to process the packet by the FPGA 111 (S12). Thereby, the server 10 can prevent the deterioration of power efficiency.

[0049] Also, even when the power consumption of the server 10 is equal to or less than the threshold value (Yes in S21), but the processing amount of each vGW15b exceeds the threshold value (No in S22), it is determined to process the packet by the FPGA 111 (S12). Thereby, even if the power efficiency is better when the server 10 processes the packet by the CPU as it is, the server 10 can prevent the deterioration of communication quality that may occur.

[0050] Next, an example of the processing procedure when the server 10 switches the packet processing performed by the FPGA 111 to be performed by the CPU based on the above determination, and an example of the processing procedure when the packet processing performed by the CPU is switched to be performed by the FPGA 111 will be described.

[0051] [Switching method (FPGA → CPU)] Referring to FIGS. 4 and 7 and using FIG. 9, an example of the processing procedure when the server 10 switches the packet processing from the FPGA 111 to the CPU will be described.

[0052] When the controller 131 of the server 10 determines to switch the packet processing from the FPGA 111 to the CPU, it outputs an instruction to the switching unit 132 to perform packet processing by the CPU (S31).

[0053] After S31, when the switching unit 132 receives an instruction to perform packet processing by the CPU (S32), it disconnects the IF (for example, eth0) connected to the FPGA-mounted NIC 11 among the IFs provided by the OS 13 (S33).

[0054] After S33, the switching unit 132 confirms that the first vGW 15b has switched to the ACT vGW 15 and user traffic has started to flow via the vGW 15b (S34). For example, the switching unit 132 confirms that user traffic has started to flow via the vGW 15b based on the traffic volume flowing through the IF (for example, eth2 shown in FIG. 4) connected to the vGW 15b. Thereafter, the switching unit 132 turns off the power of the FPGA-mounted NIC 11 (S35).

[0055] As a result, user traffic is input from the NIC 12 of the server 10, reaches the vGW 15b, is processed by the vGW 15b, and then output via the NIC 12, as shown in FIG. 7, for example.

[0056] Note that the reason for turning off the power of the FPGA-mounted NIC 11 after the switching unit 132 disconnects the IF connected to the FPGA-mounted NIC 11 is to allow user traffic to flow through the FPGA-mounted NIC 11 during the standby time until the ACT vGW 15 switches from the vGW 15a to the vGW 15b. This prevents a communication interruption of user traffic.

[0057] [Switching Method (CPU → FPGA)] Next, with reference to FIG. 4 and using FIG. 10, an example of the processing procedure when the server 10 switches packet processing from the CPU to the FPGA 111 will be described.

[0058] When the controller 131 of the server 10 determines to switch packet processing from the CPU to the FPGA 111, the switching unit 132 outputs an instruction to perform packet processing on the FPGA 111 (S41).

[0059] After S41, when the switching unit 132 receives an instruction to perform packet processing on the FPGA 111 (S42), it links up the IF (for example, eth0 shown in FIG. 4) that connects to the FPGA-mounted NIC 11 among the IFs provided by the OS 13 (S43), and turns on the power of the FPGA-mounted NIC 11 (S44). As a result, the ACT-based vGW 15 switches from the 1-based vGW 15b to the 0-based vGW 15a, and user traffic begins to flow via the FPGA-mounted NIC 11. Note that the switching unit 132 may link up the IF connecting to the FPGA-mounted NIC 11 after turning on the power of the FPGA-mounted NIC 11.

[0060] [Details of FPGA] Next, the FPGA 111 will be described in detail using FIG. 11. Here, an example will be described in which, during the time period when the server 10 performs packet processing on the FPGA 111, user traffic flows along the path indicated by the solid line in FIG. 11, and the alive / dead monitoring packets between the 0-based vGW 15a and the 1-based vGW 15b flow along the path indicated by the dashed line in FIG. 11.

[0061] In such a case, the FPGA 111 outputs packets with Dst IP = 0-based vGW 15a to eth0 of the OS 13. Also, the FPGA 111 outputs packets with Dst IP = 1-based vGW 15b to the opposite port1. Further, when Dst IP is other than the above, the FPGA 111 outputs to the port opposite to the input port (for example, if the input port is port1, port2).

[0062] In this way, the FPGA 111 can distinguish between the liveness monitoring packets between the vGWs 15a and 15b and the packets between the hosts A and B, and can perform appropriate routing control for each packet.

[0063] When the server 10 is in the time period when the CPU (that is, the vGW 15b) processes packets, for example, the user traffic flows through the route shown in FIG. 7. Also, since the power of the FPGA-mounted NIC 11 is off during this time period, no liveness monitoring packets flow between the 0-series vGW 15a and the 1-series vGW 15b.

[0064] As described above, the server 10 causes the FPGA 111 to process packets in a time period when it is more power-efficient for the FPGA 111 to process packets (for example, a time period with a large traffic volume), and causes the CPU to process packets in a time period when it is more power-efficient for the CPU to process packets (for example, a time period with a small traffic volume). As a result, while maintaining the processing performance of the server 10 under high load, the power efficiency of the server 10 can be improved.

[0065] Also, when an unexpected increase in traffic volume or an increase in processing load occurs in the time period when the server 10 is to perform processing by the CPU, the server 10 can switch to having the FPGA 111 process the packets. Thereby, even when an unexpected increase in traffic volume or an increase in processing load occurs, the server 10 can prevent a decrease in power efficiency or a decrease in communication quality from occurring.

[0066] In the above-described embodiment, the case where the vGWs 15 connected to the FPGA-mounted NICs 11 and 12 are separate vGWs 15 has been described as an example, but it is not limited thereto. For example, the FPGA-mounted NICs 11 and 12 may be connected to the same vGW 15.

[0067] Also, in the above-described embodiment, the case where the FPGA-mounted NICs 11 and 12 (and the vGWs connected to each NIC) are each installed in the same server (server 10) has been described, but they may be installed in separate servers. In this case, for example, when the switching unit 132 turns off the power of the FPGA-mounted NIC 11, it turns off the power of the server in which the FPGA-mounted NIC 11 is installed. Also, when turning on the power of the FPGA-mounted NIC 11, it turns on the power of the server in which the FPGA-mounted NIC 11 is installed.

[0068] [System configuration, etc.] Also, each component of each part shown in the figure is a functional concept, and it is not necessarily physically configured as shown in the figure. That is, the specific form of the distribution and integration of each device is not limited to that shown in the figure, and all or part of it can be functionally or physically distributed and integrated in any unit according to various loads, usage situations, etc. Furthermore, each processing function performed by each device can be realized in whole or in any part by a CPU and a program executed by the CPU, or can be realized as hardware by wired logic.

[0069] Also, among the processes described in the above-described embodiment, all or part of the processes described as being automatically performed can be manually performed, or all or part of the processes described as being manually performed can be automatically performed by a known method. In addition, regarding the processing procedures, control procedures, specific names, and information including various data and parameters shown in the above document and drawings, they can be arbitrarily changed unless otherwise specified.

[0070] [Program] The above-described controller 131 and switching unit 132 can be implemented by installing a program (switching program) as package software or online software on a desired computer. For example, by causing the information processing device to execute the above program, the information processing device can function as the controller 131 and the switching unit 132. The information processing device mentioned here includes mobile communication terminals such as smartphones, mobile phones, and PHS (Personal Handyphone System), and further includes terminals such as PDAs (Personal Digital Assistant) within its scope.

[0071] FIG. 12 is a diagram showing an example of a computer that executes a switching program. The computer 1000 has, for example, a memory 1010 and a CPU 1020. The computer 1000 also has a hard disk drive interface 1030, a disk drive interface 1040, a serial port interface 1050, a video adapter 1060, and a network interface 1070. These components are connected by a bus 1080.

[0072] The memory 1010 includes a ROM (Read Only Memory) 1011 and a RAM (Random Access Memory) 1012. The ROM 1011 stores a boot program such as a BIOS (Basic Input Output System), for example. The hard disk drive interface 1030 is connected to the hard disk drive 1090. The disk drive interface 1040 is connected to the disk drive 1100. A removable storage medium such as a magnetic disk or an optical disk is inserted into the disk drive 1100, for example. The serial port interface 1050 is connected to, for example, a mouse 1110 and a keyboard 1120. The video adapter 1060 is connected to, for example, a display 1130.

[0073] The hard disk drive 1090 stores, for example, an OS 1091, application programs 1092, program modules 1093, and program data 1094. That is, the programs that define each process executed by the controller 131 and the switching unit 132 are implemented as program modules 1093 in which computer-executable code is described. The program modules 1093 are stored, for example, in the hard disk drive 1090. For example, program modules 1093 for executing processes similar to the functional configurations in the controller 131 and the switching unit 132 are stored in the hard disk drive 1090. Note that the hard disk drive 1090 may be replaced by an SSD (Solid State Drive).

[0074] Also, the data used in the processes of the above-described embodiments is stored as program data 1094, for example, in the memory 1010 or the hard disk drive 1090. Then, the CPU 1020 reads out the program modules 1093 and the program data 1094 stored in the memory 1010 or the hard disk drive 1090 to the RAM 1012 and executes them as necessary.

[0075] Note that the program modules 1093 and the program data 1094 are not limited to being stored in the hard disk drive 1090, and may be stored, for example, in a removable storage medium and read by the CPU 1020 via a disk drive 1100 or the like. Alternatively, the program modules 1093 and the program data 1094 may be stored in another computer connected via a network (such as a LAN (Local Area Network) or a WAN (Wide Area Network)). Then, the program modules 1093 and the program data 1094 may be read by the CPU 1020 from another computer via the network interface 1070.

Explanation of Signs

[0076] 10 Server 11 FPGA-equipped NIC (First NIC) 12 NIC (Second NIC) 13 OS 14 Memory unit 15 (15a, 15b) vGW 131 Controller 132 Switching unit

Claims

1. A first NIC (Network Interface Card) connected to a virtual machine and equipped with an FPGA (Field Programmable Gate Array) that processes input packets addressed to the virtual machine; A second NIC connected to a virtual machine that is set with the same IP address as the virtual machine and processes input packets; A switching unit that switches the NIC that receives the input packet; When it reaches a predetermined time period during which the FPGA processes packets, and when the power consumption of the device equipped with the second NIC exceeds a predetermined threshold during the time period when the virtual machine processes packets, or when the packet processing load in the virtual machine connected to the second NIC exceeds a predetermined threshold, a controller that instructs the switching unit to switch the NIC that receives the packet to the first NIC; A communication system comprising the above.

2. The controller: When it reaches a predetermined time period during which the virtual machine processes packets, instructs the switching unit to switch the NIC that receives the packet to the second NIC; The switching unit: Switches the NIC that receives the packet to the second NIC by turning off the power of the first NIC or turning off the device equipped with the first NIC. The communication system according to Claim 1, characterized by the above.

3. The switching unit: Switches the NIC that receives the packet to the first NIC by turning on the power of the first NIC or turning on the device equipped with the first NIC. The communication system according to Claim 1, characterized by the above.

4. The virtual machine connected to the first NIC and the virtual machine connected to the second NIC are virtual routers made redundant by VRRC (Virtual Router Redundancy Protocol), and the virtual machine connected to the first NIC is the master router of VRRP. The communication system according to Claim 1, characterized by the above.

5. The controller: Obtains the power consumption of the server equipped with the second NIC and the processing load in the virtual machine connected to the second NIC. The communication system according to Claim 1, characterized by the above.

6. A switching method executed by a communication system, comprising: a first NIC connected to a virtual machine and equipped with an FPGA (Field Programmable Gate Array) for processing input packets addressed to the virtual machine; a second NIC having the same IP address as the virtual machine and connected to a virtual machine for processing input packets; and a switching unit for switching the NIC that receives the input packets, when it is a time period determined in advance during which the FPGA processes packets, and during a time period when the virtual machine processes packets, when the power consumption of the device equipped with the second NIC exceeds a predetermined threshold, or when the packet processing load in the virtual machine connected to the second NIC exceeds a predetermined threshold, instructing the switching unit to switch the NIC that receives the packets to the first NIC A switching method characterized by including the above.

7. In a communication system comprising a first NIC connected to a virtual machine and equipped with an FPGA (Field Programmable Gate Array) for processing input packets addressed to the virtual machine, a second NIC having the same IP address as the virtual machine and connected to a virtual machine for processing input packets, and a switching unit for switching the NIC that receives the input packets, when it is a time period determined in advance during which the FPGA processes packets, and during a time period when the virtual machine processes packets, when the power consumption of the device equipped with the second NIC exceeds a predetermined threshold, or when the packet processing load in the virtual machine connected to the second NIC exceeds a predetermined threshold, instructing the switching unit to switch the NIC that receives the packets to the first NIC A switching program for causing a computer to execute the above.

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