Electronic component

Abstract

An electronic component which contains a target to be covered, an electrode which covers the target to be covered and has an electrode lateral wall on the target to be covered, an inorganic insulating film which has an inner covering section for covering the electrode in a manner such that the electrode lateral wall is exposed, and an organic insulating film which covers the electrode lateral wall.

Description

Technical Field

[0001] This application corresponds to Japanese Patent Application No. 2020-110898 filed with the Japan Patent Office on June 26, 2020, and the entire disclosure of this application is incorporated herein by reference. The present invention relates to an electronic component.

Background Art

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, an interlayer insulating layer, an electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has an opening exposing the semiconductor substrate. The electrode enters the opening from above the interlayer insulating layer and is electrically connected to the semiconductor substrate within the opening. The inorganic protective layer has an inner edge portion covering the edge of the electrode and an outer edge portion covering the interlayer insulating layer. The organic protective layer covers the electrode and the interlayer insulating layer with the inorganic protective layer interposed therebetween.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment of the present invention provides an electronic component capable of improving reliability.

Means for Solving the Problems

[0005] One embodiment of the present invention provides an electronic component including a target to be coated, an electrode covering the target to be coated and having an electrode side wall on the target to be coated, an inorganic insulating film having an inner coating portion covering the electrode so as to expose the electrode side wall, and an organic insulating film covering the electrode side wall.

[0006] One embodiment of the present invention provides an electronic component including a target to be coated, an electrode that coats the target to be coated and has an electrode side wall on the target to be coated, an inorganic insulating film that coats the target to be coated so as to expose the electrode side wall, and an organic insulating film that coats the inorganic insulating film and the electrode and coats the electrode side wall between the inorganic insulating film and the electrode.

[0007] One embodiment of the present invention provides an electronic component including an electrode having an electrode side wall, an inorganic insulating film that coats the electrode so as to expose an inner portion of the electrode and the electrode side wall, an organic insulating film that exposes the inner portion of the electrode and coats the electrode side wall, and a pad electrode formed on the inner portion of the electrode.

[0008] The above-mentioned, or further other objects, features, and effects of the present invention will be clarified by the description of the embodiments described below with reference to the accompanying drawings.

Brief Description of the Drawings

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[0010] FIG. 1 is a plan view showing an SiC semiconductor device 1 according to the first embodiment of the present invention. FIG. 2 is a plan view showing the internal structure of the SiC semiconductor device 1 shown in FIG. 1 together with a second inorganic insulating film 30 according to the first exemplary form. FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. 1. FIG. 4 is an enlarged cross-sectional view of a main part of the structure shown in FIG. 3.

[0011] In this embodiment, the SiC semiconductor device 1 is an electronic component including an SiC chip 2 (chip / semiconductor chip) made of a hexagonal SiC single crystal. Further, in this embodiment, the SiC semiconductor device 1 is a semiconductor rectifying device including an SiC-SBD (Schottky Barrier Diode). The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like. In this embodiment, an example in which the SiC chip 2 is made of a 4H-SiC single crystal is shown, but other polytypes are not excluded.

[0012] The SiC chip 2 is formed in a rectangular parallelepiped shape. The SiC chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 is a device surface on which a functional device is formed. The second main surface 4 is a non-device surface on which a functional device is not formed. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view (hereinafter simply referred to as "plan view") when viewed from their normal direction Z.

[0013] The first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The c-plane includes the silicon plane ((0001) plane) and the carbon plane ((000-1) plane) of the SiC single crystal. It is preferable that the first main surface 3 faces the silicon plane and the second main surface 4 faces the carbon plane. The first main surface 3 and the second main surface 4 may have an off-angle inclined at a predetermined angle in an off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be more than 0° and 10° or less. The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and 4.5° or less.

[0014] The second main surface 4 may be composed of a rough surface having either or both of a grinding mark and an annealing mark (specifically, a laser irradiation mark). The annealing mark may contain amorphous SiC and / or SiC (specifically, Si) silicided (alloyed) with a metal. The second main surface 4 preferably consists of an ohmic surface having at least an annealing mark.

[0015] The first to fourth side surfaces 5A to 5D form the peripheries of the first main surface 3 and the second main surface 4. The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face each other in a second direction Y intersecting (specifically, orthogonal to) the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face each other in the first direction X. In this form, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction of the SiC single crystal. That is, the first side surface 5A and the second side surface 5B are formed by the a-plane of the SiC single crystal, and the third side surface 5C and the fourth side surface 5D are formed by the m-plane of the SiC single crystal.

[0016] The first to fourth side surfaces 5A to 5D may be composed of a ground surface having grinding marks formed by cutting with a dicing blade, or may be composed of a cleavage surface having a modified layer formed by laser light irradiation. Specifically, the modified layer is composed of a region in which a part of the crystal structure of the SiC chip 2 is modified to have different properties. That is, the modified layer is composed of a region in which the density, refractive index, or mechanical strength (crystal strength), or other physical properties are modified to have properties different from those of the SiC chip 2.

[0017] The modified layer may contain at least one of an amorphous layer, a melt re-hardened layer, a defect layer, an insulation breakdown layer, or a refractive index change layer. The amorphous layer is a layer in which a part of the SiC chip 2 is amorphized. The melt re-hardened layer is a layer in which a part of the SiC chip 2 is melted and then re-hardened. The defect layer is a layer containing voids, cracks, etc. formed in the SiC chip 2. The insulation breakdown layer is a layer in which a part of the SiC chip 2 is insulation broken down. The refractive index change layer is a layer in which a part of the SiC chip 2 changes to a refractive index different from that of the SiC chip 2.

[0018] When the first to fourth side surfaces 5A to 5D are cleavage surfaces, the first side surface 5A and the second side surface 5B may form inclined surfaces having an inclination angle due to the off-angle. The inclination angle due to the off-angle is an angle with respect to the normal direction Z when the normal direction Z is 0°. The first side surface 5A and the second side surface 5B may form inclined surfaces extending along the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal direction Z.

[0019] The inclination angle due to the off-angle is approximately equal to the off-angle. The inclination angle due to the off-angle may be more than 0° and 10° or less (preferably 2° or more and 4.5° or less). Since the third side surface 5C and the fourth side surface 5D extend in the off direction (a-axis direction), they do not have an inclination angle due to the off-angle. The third side surface 5C and the fourth side surface 5D extend planar in the second direction Y (a-axis direction) and the normal direction Z. Specifically, the third side surface 5C and the fourth side surface 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4.

[0020] The SiC semiconductor device 1 includes an n-type (first conductivity type) first semiconductor region 6 (high concentration region) formed in the surface layer portion of the second main surface 4 of the SiC chip 2. The first semiconductor region 6 has an n-type impurity concentration that is substantially constant in the thickness direction. The n-type impurity concentration of the first semiconductor region 6 is 1×10 18 cm -3 or more and 1×10 21 cm -3 or less. The first semiconductor region 6 forms the cathode of the SBD. The first semiconductor region 6 may also be referred to as a cathode region.

[0021] The first semiconductor region 6 is formed over the entire surface layer portion of the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. That is, the first semiconductor region 6 has a part of the second main surface 4 and the first to fourth side surfaces 5A to 5D. The thickness of the first semiconductor region 6 may be 5 μm or more and 300 μm or less. The thickness of the first semiconductor region 6 is typically 50 μm or more and 250 μm or less. The thickness of the first semiconductor region 6 is adjusted by grinding the second main surface 4. In this form, the first semiconductor region 6 is formed of an n-type semiconductor substrate (SiC substrate).

[0022] The SiC semiconductor device 1 includes an n-type second semiconductor region 7 (low concentration region) formed in the surface layer portion of the first main surface 3 of the SiC chip 2. The second semiconductor region 7 has an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6. The second semiconductor region 7 is electrically connected to the first semiconductor region 6 and forms a cathode of the SBD together with the first semiconductor region 6. The second semiconductor region 7 may be referred to as a drift region.

[0023] The second semiconductor region 7 is formed over the entire surface layer portion of the first main surface 3 and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D. That is, the second semiconductor region 7 has a part of the first main surface 3 and the first to fourth side surfaces 5A to 5D. The n-type impurity concentration of the second semiconductor region 7 may be 1×10 15 cm -3 or more and 1×10 18 cm -3 or less. The thickness of the second semiconductor region 7 may be 5 μm or more and 20 μm or less. In this form, the second semiconductor region 7 is formed of an n-type epitaxial layer (SiC epitaxial layer).

[0024] The SiC semiconductor device 1 includes an n-type third semiconductor region 8 (concentration transition region) interposed between the first semiconductor region 6 and the second semiconductor region 7 in the SiC chip 2. The third semiconductor region 8 has a concentration gradient in which the n-type impurity concentration decreases (specifically, gradually decreases) from the n-type impurity concentration of the first semiconductor region 6 toward the n-type impurity concentration of the second semiconductor region 7. The third semiconductor region 8 is interposed across the entire region between the first semiconductor region 6 and the second semiconductor region 7 and is exposed from the first to fourth side surfaces 5A to 5D. That is, the third semiconductor region 8 has a part of the first to fourth side surfaces 5A to 5D.

[0025] The third semiconductor region 8 is electrically connected to the first semiconductor region 6 and the second semiconductor region 7, and forms a cathode of an SBD together with the first semiconductor region 6 and the second semiconductor region 7. The third semiconductor region 8 may be referred to as a buffer region. The thickness of the third semiconductor region 8 may be 1 μm or more and 10 μm or less. In this form, the third semiconductor region 8 is formed of an n-type epitaxial layer (SiC epitaxial layer).

[0026] The SiC semiconductor device 1 includes a p-type (second conductivity type) guard region 9 formed in the surface layer portion of the first main surface 3. The p-type impurities in the guard region 9 may or may not be activated. The p-type impurity concentration of the guard region 9 may be 1×10 15 cm -3 or more and 1×10 18 cm -3 or less. The guard region 9 is formed on the first main surface 3 at a distance inward from the periphery (the first to fourth side surfaces 5A to 5D) of the first main surface 3, exposing the inner portion of the first main surface 3. The guard region 9 extends in a band shape along the periphery of the first main surface 3.

[0027] The guard region 9 is formed in an annular shape surrounding the inner portion of the first main surface 3 in plan view. Specifically, the guard region 9 is formed in a square annular shape having four sides parallel to the periphery of the first main surface 3 in plan view. Thereby, the guard region 9 is formed as a guard ring region. The guard region 9 has an inner edge portion on the inner side of the inner portion of the first main surface 3 and an outer edge portion on the peripheral side of the first main surface 3.

[0028] The SiC semiconductor device 1 includes a first inorganic insulating film 10 formed on a first main surface 3 as an example of an object to be coated. The first inorganic insulating film 10 may be referred to as an interlayer insulating film. The first inorganic insulating film 10 may have a laminated structure including a plurality of insulating films, or may have a single-layer structure composed of a single insulating film. The first inorganic insulating film 10 preferably includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first inorganic insulating film 10 may have a laminated structure including a plurality of silicon oxide films, a laminated structure including a plurality of silicon nitride films, or a laminated structure including a plurality of silicon oxynitride films.

[0029] The first inorganic insulating film 10 may have a laminated structure in which at least two of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film are laminated in an arbitrary order. The first inorganic insulating film 10 may have a single-layer structure composed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In this form, the first inorganic insulating film 10 has a single-layer structure composed of a silicon oxide film.

[0030] In this form, the first inorganic insulating film 10 is composed of a field oxide film containing an oxide of the SiC chip 2 (second semiconductor region 7). Therefore, the first inorganic insulating film 10 contains an n-type impurity of the same type as the n-type impurity in the second semiconductor region 7 in an insulator (silicon oxide). The first inorganic insulating film 10 has a first insulation thickness T1. The first insulation thickness T1 may be 0.1 μm or more and 5 μm or less. The first insulation thickness T1 is preferably 0.5 μm or more and 2 μm or less.

[0031] The first inorganic insulating film 10 exposes the inner part of the first main surface 3. In this form, the first inorganic insulating film 10 is formed in an annular shape surrounding the inner part of the first main surface 3 in plan view. Specifically, the first inorganic insulating film 10 is formed in a square annular shape having four sides parallel to the periphery of the first main surface 3 in plan view. The first inorganic insulating film 10 covers the outer edge of the guard region 9 over the entire circumference and exposes the inner edge of the guard region 9 over the entire circumference.

[0032] Specifically, the first inorganic insulating film 10 has an inner wall portion 11 on the inner side of the first main surface 3 and an outer wall portion 12 on the peripheral side of the first main surface 3. The inner wall portion 11 is formed at an interval from the inner edge portion to the outer edge portion side of the guard region 9 so as to expose the inner portion (second semiconductor region 7) of the first main surface 3 and the inner edge portion of the guard region 9. Thereby, the inner wall portion 11 defines a contact opening 13 that exposes the inner portion (second semiconductor region 7) of the first main surface 3 and the inner edge portion of the guard region 9. The inner wall portion 11 (contact opening 13) is formed in a rectangular shape having four sides parallel to the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3 in a plan view and surrounds the inner edge portion of the guard region 9.

[0033] The outer wall portion 12 is formed at an interval from the periphery of the first main surface 3 to the inner side of the first main surface 3 and exposes the peripheral portion (second semiconductor region 7) of the first main surface 3. The outer wall portion 12 is formed at an interval from the outer edge portion of the guard region 9 to the peripheral side of the first main surface 3. Thereby, the outer wall portion 12 defines a notch opening 14 that exposes the peripheral portion (second semiconductor region 7) of the first main surface 3. The outer wall portion 12 (notch opening 14) is formed in a rectangular shape having four sides parallel to the periphery of the first main surface 3 in a plan view and surrounds the outer edge portion of the guard region 9.

[0034] The first inorganic insulating film 10 defines a hidden surface, an active surface, and an outer surface on the first main surface 3. In other words, the first main surface 3 includes the hidden surface 15, the active surface 16, and the outer surface 17 partitioned by the first inorganic insulating film 10.

[0035] The hidden surface 15 consists of a portion covered (hidden) by the first inorganic insulating film 10 on the first main surface 3, and is formed in a square-ring shape in plan view. The active surface 16 consists of a portion exposed from the first inorganic insulating film 10 in the inner part of the first main surface 3, and is partitioned into a square shape by the inner wall portion 11 (contact opening 13) in plan view. The outer surface 17 consists of a portion exposed from the first inorganic insulating film 10 at the peripheral edge of the first main surface 3, and is partitioned into a square-ring shape by the outer wall portion 12 (notch opening 14) in plan view.

[0036] In this form, the active surface 16 is recessed with respect to the hidden surface 15 on the bottom side (second main surface 4 side) of the second semiconductor region 7. Specifically, the active surface 16 is recessed by one step with respect to the hidden surface 15 on the bottom side of the second semiconductor region 7 starting from the inner wall portion 11 (contact opening 13). The active surface 16 is formed at a depth position between the bottom of the guard region 9 and the hidden surface 15 with respect to the normal direction Z.

[0037] The active surface 16 exposes the inner edge portions of the second semiconductor region 7 and the guard region 9. Preferably, the active surface 16 is recessed in a range exceeding 0 μm and equal to or less than 1 μm (preferably equal to or less than 0.5 μm) with respect to the hidden surface 15 with respect to the normal direction Z. The n-type impurity concentration of the second semiconductor region 7 in the surface layer portion of the active surface 16 is higher than the n-type impurity concentration of the second semiconductor region 7 in the surface layer portion of the hidden surface 15.

[0038] In this form, the outer surface 17 is recessed with respect to the hidden surface 15 on the bottom side (second main surface 4 side) of the second semiconductor region 7. Specifically, the outer surface 17 is recessed by one step with respect to the hidden surface 15 on the bottom side of the second semiconductor region 7 starting from the outer wall portion 12 (notch opening 14). The outer surface 17 is formed at a depth position between the bottom of the guard region 9 and the hidden surface 15 with respect to the normal direction Z.

[0039] The outer surface 17 exposes the second semiconductor region 7. The outer surface 17 preferably recesses with respect to the hidden surface 15 in the range of more than 0 μm and 1 μm or less (preferably 0.5 μm or less) with respect to the normal direction Z. The outer surface 17 is preferably located on substantially the same plane as the active surface 16. The n-type impurity concentration of the second semiconductor region 7 in the surface layer portion of the outer surface 17 is higher than the n-type impurity concentration of the second semiconductor region 7 in the surface layer portion of the hidden surface 15.

[0040] The SiC semiconductor device 1 includes a first main surface electrode 20 formed on the first main surface 3. In this form, the first main surface electrode 20 is formed in a rectangular shape having four sides parallel to the periphery of the first main surface 3 in plan view. The first main surface electrode 20 is a Schottky electrode. The first main surface electrode 20 forms a Schottky junction with the first main surface 3. Specifically, the first main surface electrode 20 is electrically connected to the inner edge portions of the second semiconductor region 7 and the guard region 9 on the active surface 16 that is recessed on the bottom side of the second semiconductor region 7 with respect to the hidden surface 15. The first main surface electrode 20 forms a Schottky junction with the second semiconductor region 7 on the active surface 16.

[0041] Thereby, an SiC-SBD as an example of a functional device is formed on the active surface 16. The SiC-SBD includes the first main surface electrode 20 as an anode and the second semiconductor region 7 (the first semiconductor region 6 and the third semiconductor region 8) as a cathode.

[0042] The first main surface electrode 20 has an electrode side wall 21 located on the first inorganic insulating film 10. The electrode side wall 21 is formed at an interval from the periphery of the first main surface 3 (the first to fourth side surfaces 5A to 5D) to the inner wall portion 11 side (active surface 16 side) of the first inorganic insulating film 10 in plan view. Specifically, the electrode side wall 21 is formed between the inner wall portion 11 and the outer wall portion 12 of the first inorganic insulating film 10 on the first inorganic insulating film 10.

[0043] In this form, the electrode sidewall 21 is formed at a distance from the outer edge of the guard region 9 toward the inner wall portion 11 side of the first inorganic insulating film 10 in a plan view. The electrode sidewall 21 faces the guard region 9 with the first inorganic insulating film 10 interposed therebetween. The electrode sidewall 21 is formed in a tapered shape that slopes obliquely downward from the main surface of the first main surface electrode 20. In this form, the electrode sidewall 21 is formed in a curved tapered shape that curves toward the first inorganic insulating film 10.

[0044] More specifically, the first main surface electrode 20 includes a main body portion 22 that covers the active surface 16 and a lead-out portion 23 that covers the first inorganic insulating film 10. The main body portion 22 may be referred to as a Schottky electrode portion, and the lead-out portion 23 may be referred to as a field electrode portion. The main body portion 22 is located within the contact opening 13 and is electrically connected to the inner edge portions of the second semiconductor region 7 and the guard region 9. The main body portion 22 fills the contact opening 13 from the active surface 16 so as to protrude above the first inorganic insulating film 10. The main body portion 22 extends substantially flat along the active surface 16.

[0045] The lead-out portion 23 is drawn out from the main body portion 22 onto the first inorganic insulating film 10 and forms the electrode sidewall 21 on the first inorganic insulating film 10. The lead-out portion 23 extends substantially flat along the first inorganic insulating film 10. The lead-out portion 23 faces the guard region 9 with the first inorganic insulating film 10 interposed therebetween. In this form, the entire lead-out portion 23 faces the guard region 9.

[0046] The lead-out portion 23 forms a protruding portion 24 that protrudes above the main body portion 22 (in a direction away from the SiC chip 2) at the peripheral edge of the first main surface electrode 20. In other words, the first main surface electrode 20 includes an inner portion (main body portion 22) that covers the first main surface 3 and a peripheral portion that covers the first inorganic insulating film 10 and has a protruding portion 24 (lead-out portion 23) that protrudes above the inner portion (main body portion 22). That is, a gradient (step) is formed in the peripheral edge portion of the first main surface electrode 20 (the region between the main body portion 22 and the lead-out portion 23) due to the protruding portion 24.

[0047] The first main surface electrode 20 has a laminated structure including a first electrode film 25, a second electrode film 26, and a third electrode film 27 laminated in this order from the SiC chip 2 side. The first electrode film 25 is formed in a film shape along the active surface 16, the inner wall portion 11 (i.e., the contact opening 13) of the first inorganic insulating film 10, and the main surface of the first inorganic insulating film 10. The first electrode film 25 is composed of a Schottky barrier electrode film and forms a Schottky junction with the first main surface 3 (the second semiconductor region 7). The electrode material of the first electrode film 25 is arbitrary as long as a Schottky junction is formed with the first main surface 3 (the second semiconductor region 7).

[0048] The first electrode film 25 may contain at least one of magnesium (Mg), aluminum (Al), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), cobalt (Co), nickel (Ni), copper (Cu), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), indium (In), tin (Sn), tantalum (Ta), tungsten (W), platinum (Pt), and gold (Au).

[0049] The first electrode film 25 may be composed of an alloy film containing at least one of the above metal species. In this form, the first electrode film 25 is composed of a titanium film. The first electrode film 25 has a first electrode thickness TE1. The first electrode thickness TE1 may be 50 Å or more and 1000 Å or less. Preferably, the first electrode thickness TE1 is 250 Å or more and 500 Å or less.

[0050] The second electrode film 26 is formed in a film shape along the main surface of the first electrode film 25. The second electrode film 26 is composed of a metal barrier film. In this form, the second electrode film 26 is composed of a Ti-based metal film. The second electrode film 26 contains at least one of a titanium film and a titanium nitride film. The second electrode film 26 may have a single-layer structure composed of a titanium film or a titanium nitride film, or a laminated structure containing a titanium film and a titanium nitride film in an arbitrary order.

[0051] In this form, the second electrode film 26 has a single-layer structure made of a titanium nitride film. The second electrode film 26 has a second electrode thickness TE2. The second electrode thickness TE2 may be 500 Å or more and 5000 Å or less. The second electrode thickness TE2 is preferably 1500 Å or more and 4500 Å or less. The second electrode thickness TE2 preferably exceeds the first electrode thickness TE1 (TE1 < TE2).

[0052] The third electrode film 27 is formed in a film shape along the main surface of the second electrode film 26. The third electrode film 27 is made of a Cu-based metal film or an Al-based metal film. The third electrode film 27 may contain at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this form, the third electrode film 27 has a single-layer structure made of an AlCu alloy film.

[0053] The third electrode film 27 has a third electrode thickness TE3. The third electrode thickness TE3 may be 0.5 μm (= 5000 Å) or more and 10 μm (= 100000 Å) or less. The third electrode thickness TE3 is preferably 2.5 μm or more and 7.5 μm or less. The third electrode thickness TE3 preferably exceeds the first electrode thickness TE1 and the second electrode thickness TE2 (TE1 < TE3, TE2 < TE3). The third electrode thickness TE3 particularly preferably exceeds the sum of the first electrode thickness TE1 and the second electrode thickness TE2 (= TE1 + TE2) (TE1 + TE2 < TE3).

[0054] The SiC semiconductor device 1 includes a second inorganic insulating film 30. The second inorganic insulating film 30 is made of an inorganic insulator having a relatively high density and has a barrier property (shielding property) against moisture. For example, the oxide of the first main surface electrode 20 (aluminum oxide in this form) deteriorates the electrical characteristics of the first main surface electrode 20. In addition, the oxide of the first main surface electrode 20 is a factor that causes partial peeling, cracks, etc. of the first main surface electrode 20 and other structures due to thermal expansion.

[0055] The second inorganic insulating film 30 shields moisture (humidity) from the outside by covering either one or both of the first inorganic insulating film 10 and the first main surface electrode 20, and protects the SiC chip 2 and the first main surface electrode 20 from oxidation. The second inorganic insulating film 30 may be referred to as a passivation film.

[0056] The second inorganic insulating film 30 may have a laminated structure including a plurality of insulating films, or may have a single-layer structure composed of a single insulating film. The second inorganic insulating film 30 preferably includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second inorganic insulating film 30 may have a laminated structure including a plurality of silicon oxide films, a laminated structure including a plurality of silicon nitride films, or a laminated structure including a plurality of silicon oxynitride films.

[0057] The second inorganic insulating film 30 may have a laminated structure in which at least two of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film are laminated in an arbitrary order. The second inorganic insulating film 30 may have a single-layer structure composed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In this form, the second inorganic insulating film 30 has a single-layer structure composed of a silicon nitride film. That is, the second inorganic insulating film 30 is made of an insulator different from the first inorganic insulating film 10.

[0058] The second inorganic insulating film 30 has a second insulation thickness T2. The second insulation thickness T2 may be 0.05 μm or more and 5 μm or less. The second insulation thickness T2 is preferably 0.1 μm or more and 2 μm or less. The second insulation thickness T2 may be equal to or greater than the first insulation thickness T1 (T1 ≦ T2). The second insulation thickness T2 is preferably less than the first insulation thickness T1 (T1 > T2).

[0059] The second insulation thickness T2 preferably exceeds the first electrode thickness TE1 of the first electrode film 25 and the second electrode thickness TE2 of the second electrode film 26 (TE1 < T2, TE2 < T2). Particularly preferably, the second insulation thickness T2 exceeds the sum of the first electrode thickness TE1 and the second electrode thickness TE2 (= TE1 + TE2) (TE1 + TE2 < T2). The second insulation thickness T2 is preferably less than or equal to the third electrode thickness TE3 of the third electrode film 27 (TE3 ≧ T2). Particularly preferably, the second insulation thickness T2 is less than the third electrode thickness TE3 (TE3 > T2).

[0060] In this form, the second inorganic insulation film 30 includes an inner coating portion 31 (electrode coating portion), an outer coating portion 32 (insulation coating portion), and a removal portion 33. The second inorganic insulation film 30 only needs to have at least one of the inner coating portion 31 and the outer coating portion 32, and does not necessarily need to include both the inner coating portion 31 and the outer coating portion 32. Preferably, the second inorganic insulation film 30 has at least the inner coating portion 31. Most preferably, the second inorganic insulation film 30 includes both the inner coating portion 31 and the outer coating portion 32.

[0061] The inner coating portion 31 of the second inorganic insulation film 30 covers the first main surface electrode 20 so as to expose the electrode side wall 21. The inner coating portion 31 also exposes the inner portion of the first main surface electrode 20. The inner coating portion 31 is formed in a strip shape extending along the electrode side wall 21 in a plan view. In this form, the inner coating portion 31 is formed in an annular shape surrounding the inner portion of the first main surface electrode 20 in a plan view. Specifically, the inner coating portion 31 is formed in a square annular shape having four sides parallel to the electrode side wall 21 (the periphery of the first main surface 3) in a plan view.

[0062] The inner covering portion 31 covers the first main surface electrode 20 with a space from the electrode side wall 21 so as to expose the peripheral portion of the first main surface electrode 20. Specifically, the inner covering portion 31 is formed on the main body portion 22 of the first main surface electrode 20 so as to expose the lead-out portion 23 (protrusion portion 24) of the first main surface electrode 20. In this case, it is preferable that the inner covering portion 31 is formed with a space inward from the inner wall portion 11 of the first inorganic insulating film 10 in a plan view with respect to the first main surface electrode 20. Further, the inner covering portion 31 is preferably formed with a space inward from the lead-out portion 23 (protrusion portion 24) to expose the entire lead-out portion 23 (protrusion portion 24).

[0063] In this form, the inner covering portion 31 is formed in a flat film shape extending along the main surface of the main body portion 22 so as to avoid the gradient (step) of the first main surface electrode 20. In this form, the main surface of the inner covering portion 31 is located on the main surface side of the main body portion 22 with respect to the main surface of the lead-out portion 23. Of course, the main surface of the inner covering portion 31 may be located above the main surface of the lead-out portion 23. That is, the inner covering portion 31 may have a thickness exceeding the thickness of the protrusion portion 24. The thickness of the protrusion portion 24 is defined by the distance (thickness) between the main surface of the main body portion 22 and the main surface of the lead-out portion 23 in the normal direction Z.

[0064] The inner covering portion 31 faces the active surface 16 with the first main surface electrode 20 interposed therebetween. In this form, the inner covering portion 31 is formed with a space inward from the inner wall portion 11 of the first inorganic insulating film 10 in a plan view. Therefore, the inner covering portion 31 does not face the first inorganic insulating film 10 with the first main surface electrode 20 interposed therebetween.

[0065] The inner covering portion 31 is formed with a space inward from the inner edge portion of the guard region 9 in a plan view. The inner covering portion 31 does not face the guard region 9 with the first main surface electrode 20 interposed therebetween. That is, the inner covering portion 31 faces only the second semiconductor region 7 with the first main surface electrode 20 interposed therebetween. Of course, the inner covering portion 31 may face one or both of the guard region 9 and the first inorganic insulating film 10 with the first main surface electrode 20 (lead-out portion 23) interposed therebetween.

[0066] The inner covering portion 31 has a first inner wall portion 34 on the inner side of the inner portion of the first main surface electrode 20 and a first outer wall portion 35 on the side of the electrode side wall 21 of the first main surface electrode 20. The first inner wall portion 34 defines a first opening 36 that exposes the inner portion of the first main surface electrode 20. The first inner wall portion 34 (the first opening 36) is formed in a rectangular shape having four sides parallel to the electrode side wall 21 in a plan view in this form.

[0067] In this form, the first inner wall portion 34 is formed on the main body portion 22 at a distance inward from the lead-out portion 23 (the protruding portion 24). Thereby, the first inner wall portion 34 defines a first opening 36 that exposes the inner portion of the main body portion 22. The first inner wall portion 34 is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 30 toward the inner side of the first main surface electrode 20.

[0068] The first outer wall portion 35 is formed on the first main surface electrode 20 at a distance from the electrode side wall 21 so as to expose the peripheral portion of the first main surface electrode 20. Specifically, the first outer wall portion 35 is formed on the main body portion 22 so as to expose the lead-out portion 23 (the protruding portion 24). More specifically, the first outer wall portion 35 is formed at a distance inward from the lead-out portion 23 (the protruding portion 24). Thereby, the first outer wall portion 35 exposes a part of the main body portion 22 and the entire lead-out portion 23 (the protruding portion 24).

[0069] The first outer wall portion 35 is formed at a distance from the inner wall portion 11 of the first inorganic insulating film 10 toward the inner side of the first main surface electrode 20 in a plan view. Further, the first outer wall portion 35 is formed at a distance inward from the inner edge portion of the guard region 9 in a plan view. In this form, the first outer wall portion 35 is formed in a rectangular shape having four sides parallel to the electrode side wall 21 in a plan view. The first outer wall portion 35 is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 30 toward the lead-out portion 23 of the first main surface electrode 20.

[0070] The outer covering portion 32 of the second inorganic insulating film 30 covers the first inorganic insulating film 10 so as to expose the electrode side wall 21. The outer covering portion 32 is formed in a strip shape extending along the electrode side wall 21 in a plan view. The outer covering portion 32 is formed in an annular shape surrounding the first main surface electrode 20 (electrode side wall 21) in a plan view. Specifically, the outer covering portion 32 is formed in a square annular shape having four sides parallel to the electrode side wall 21 (the periphery of the first main surface 3) in a plan view.

[0071] The outer covering portion 32 covers the first inorganic insulating film 10 at a distance from the electrode side wall 21 to the peripheral side of the first main surface 3 so as to expose a part of the first inorganic insulating film 10. In this form, the outer covering portion 32 faces the guard region 9 with the first inorganic insulating film 10 interposed therebetween. The outer covering portion 32 extends across the outer edge portion of the guard region 9 in a plan view and faces the second semiconductor region 7 outside the guard region 9 with the first inorganic insulating film 10 interposed therebetween. In this form, the outer covering portion 32 is drawn out from the upper side of the first inorganic insulating film 10 to the outer surface 17.

[0072] As a result, the outer covering portion 32 includes a first portion 37 covering the first inorganic insulating film 10 and a second portion 38 directly covering the outer surface 17. The first portion 37 extends in a film shape along the first inorganic insulating film 10 and faces the hidden surface 15 with the first inorganic insulating film 10 interposed therebetween. That is, the first portion 37 faces the second semiconductor region 7 and the guard region 9 with the first inorganic insulating film 10 interposed therebetween. The main surface of the first portion 37 is located on the first inorganic insulating film 10 side with respect to the main surface of the lead-out portion 23 of the first main surface electrode 20. In this form, the main surface of the first portion 37 is located on the first inorganic insulating film 10 side with respect to the main surface of the main body portion 22 of the first main surface electrode 20.

[0073] The second portion 38 extends in a film shape along the outer surface 17 and directly covers the outer surface 17. That is, the second portion 38 directly covers the second semiconductor region 7. The main surface of the second portion 38 is located on the side of the first main surface 3 (outer surface 17) with respect to the main surface of the lead-out portion 23. The main surface of the second portion 38 is located on the side of the first main surface 3 (outer surface 17) with respect to the main surface of the main body portion 22. In this form, the main surface of the second portion 38 is located between the main surface of the first inorganic insulating film 10 and the hidden surface 15.

[0074] In this form, the second portion 38 is formed at a distance from the periphery of the first main surface 3 (the first to fourth side surfaces 5A to 5D) toward the first inorganic insulating film 10 so as to expose the peripheral portion of the first main surface 3 (outer surface 17). The second portion 38 demarcates a dicing street 39 in which the peripheral portion of the first main surface 3 (outer surface 17) is exposed between the second portion 38 and the periphery of the first main surface 3. The dicing street 39 is demarcated in a rectangular ring shape extending along the periphery of the first main surface 3. The width of the dicing street 39 may be 5 μm or more and 25 μm or less. The width of the dicing street 39 is the width in a direction orthogonal to the direction in which the dicing street 39 extends.

[0075] The outer covering portion 32 has a second inner wall portion 40 on the side of the electrode side wall 21 and a second outer wall portion 41 on the peripheral side of the first main surface 3 (outer surface 17). The second inner wall portion 40 is formed on the first inorganic insulating film 10 at a distance from the electrode side wall 21 so as to expose the first inorganic insulating film 10. That is, the second inner wall portion 40 is formed in the region between the inner wall portion 11 and the outer wall portion 12 of the first inorganic insulating film 10 in a plan view.

[0076] In this embodiment, the second inner wall portion 40 is formed in a region between the electrode side wall 21 and the outer edge of the guard region 9 in a plan view. Thereby, the second inner wall portion 40 exposes a portion of the first inorganic insulating film 10 that covers the guard region 9. In this embodiment, the second inner wall portion 40 is formed in a rectangular shape having four sides parallel to the electrode side wall 21 in a plan view, and surrounds the first main surface electrode 20. The second inner wall portion 40 is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 30 toward the inside of the first main surface 3.

[0077] In this embodiment, the second outer wall portion 41 is formed on the outer surface 17. The second outer wall portion 41 is formed in a region between the outer wall portion 12 (notch opening 14) of the first inorganic insulating film 10 and the periphery of the first main surface 3 in a plan view, and exposes the peripheral portion of the first main surface 3 (outer surface 17). The second outer wall portion 41 is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 30 toward the periphery of the first main surface 3 (outer surface 17). The second outer wall portion 41 demarcates the dicing street 39 with the periphery of the first main surface 3.

[0078] The removal portion 33 of the second inorganic insulating film 30 is demarcated between the inner covering portion 31 (first outer wall portion 35) and the outer covering portion 32 (second inner wall portion 40), and exposes the electrode side wall 21 of the first main surface electrode 20. In this embodiment, the removal portion 33 is formed in a strip shape extending along the electrode side wall 21 in a plan view. Specifically, the removal portion 33 is formed in an annular shape (a square annular shape in this embodiment) extending along the electrode side wall 21 in a plan view.

[0079] That is, the removal portion 33 exposes the electrode side wall 21, the lead-out portion 23 (protrusion 24) of the first main surface electrode 20, and a part of the first inorganic insulating film 10 over the entire circumference of the electrode side wall 21. In the second inorganic insulating film 30, the inner covering portion 31 is formed on the flat first main surface electrode 20, and the outer covering portion 32 is formed on the flat first inorganic insulating film 10. Therefore, in the second inorganic insulating film 30, the step caused by the electrode side wall 21 is removed by the removal portion 33.

[0080] The SiC semiconductor device 1 includes an organic insulating film 50 that covers the electrode sidewall 21 of the first main surface electrode 20. The organic insulating film 50 has a hardness lower than that of the second inorganic insulating film 30. In other words, the organic insulating film 50 has a modulus of elasticity smaller than that of the second inorganic insulating film 30 and functions as a buffer material (protective film) against external forces. The organic insulating film 50 protects the SiC chip 2, the first main surface electrode 20, the second inorganic insulating film 30, etc. from external forces.

[0081] The organic insulating film 50 preferably contains a photosensitive resin. The photosensitive resin may be of a negative type or a positive type. The organic insulating film 50 may contain at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. In this form, the organic insulating film 50 contains a polyimide film.

[0082] The organic insulating film 50 has a third insulation thickness T3. It is preferable that the third insulation thickness T3 exceeds the second insulation thickness T2 of the second inorganic insulating film 30 (T2 < T3). It is particularly preferable that the third insulation thickness T3 exceeds the total thickness of the first main surface electrode 20 (= TE1 + TE1 + TE3) (TE1 + TE1 + TE3 < T3). The third insulation thickness T3 may be 1 μm or more and 50 μm or less. The third insulation thickness T3 is preferably 5 μm or more and 30 μm or less.

[0083] The organic insulating film 50 covers the first electrode film 25, the second electrode film 26, and the third electrode film 27 on the electrode sidewall 21. The organic insulating film 50 is formed in a strip shape extending along the electrode sidewall 21 in a plan view. In this form, the organic insulating film 50 is formed in an annular shape surrounding the inner part of the first main surface electrode 20 in a plan view and covers the electrode sidewall 21 over the entire circumference. Specifically, the organic insulating film 50 is formed in a square annular shape having four sides parallel to the electrode sidewall 21 (the periphery of the first main surface 3) in a plan view.

[0084] The organic insulating film 50 covers the edge of the first main surface electrode 20. That is, the organic insulating film 50 extends from the electrode side wall 21 toward the inner covering portion 31 side of the second inorganic insulating film 30, and covers the peripheral edge portion of the first main surface electrode 20 exposed between the electrode side wall 21 and the inner covering portion 31. Specifically, the organic insulating film 50 covers the lead-out portion 23 (protrusion portion 24) of the first main surface electrode 20. Further, the organic insulating film 50 extends from above the lead-out portion 23 (protrusion portion 24) toward the main body portion 22 side of the first main surface electrode 20 and covers a part of the main body portion 22.

[0085] Furthermore, the organic insulating film 50 extends from above the lead-out portion 23 (protrusion portion 24) toward the inner covering portion 31 of the second inorganic insulating film 30 and covers the inner covering portion 31. The organic insulating film 50 covers the inner covering portion 31 so as to expose the inner part of the first main surface electrode 20. Specifically, the organic insulating film 50 covers the inner covering portion 31 so as to expose the first inner wall portion 34 of the inner covering portion 31. More specifically, the organic insulating film 50 covers the inner covering portion 31 with a space from the first inner wall portion 34 toward the first outer wall portion 35 side, and exposes the inner part of the first main surface electrode 20 and the edge portion 51 of the inner covering portion 31 in plan view.

[0086] The organic insulating film 50 extends from the electrode side wall 21 toward the outer covering portion 32 of the second inorganic insulating film 30 and covers the portion exposed between the electrode side wall 21 and the outer covering portion 32 in the first inorganic insulating film 10. The organic insulating film 50 faces the guard region 9 with the first inorganic insulating film 10 sandwiched therebetween between the electrode side wall 21 and the outer covering portion 32. Further, the organic insulating film 50 extends from above the first inorganic insulating film 10 toward the outer covering portion 32 and covers the outer covering portion 32. The organic insulating film 50 covers the outer covering portion 32 so as to expose the peripheral edge portion of the first main surface 3 (outer side surface 17).

[0087] Specifically, the organic insulating film 50 covers the outer covering portion 32 so as to expose the second outer wall portion 41. More specifically, the organic insulating film 50 covers the outer covering portion 32 at an interval from the second outer wall portion 41 toward the second inner wall portion 40 side, and exposes a peripheral portion of the first main surface 3 (outer surface 17) and a part of the outer covering portion 32 in a plan view. That is, the organic insulating film 50 covers the first portion 37 and the second portion 38 of the outer covering portion 32 so as to expose the outer surface 17.

[0088] The organic insulating film 50 has a third inner wall portion 52 on the side of the electrode side wall 21 and a third outer wall portion 53 on the side opposite to the third inner wall portion 52 (the peripheral portion side of the first main surface 3). The third inner wall portion 52 defines a second opening 54 that exposes an inner portion of the first main surface electrode 20. The third inner wall portion 52 (second opening 54) extends along the first inner wall portion 34 (first opening 36) of the inner covering portion 31. In this form, the third inner wall portion 52 is formed in a rectangular shape having four sides parallel to the first inner wall portion 34 of the inner covering portion 31 in a plan view.

[0089] The third inner wall portion 52 is formed on the inner covering portion 31 at an interval from the first inner wall portion 34 toward the first outer wall portion 35 side, and exposes an inner portion of the first main surface electrode 20 and an edge portion 51 of the inner covering portion 31. That is, the second opening 54 exposes an inner portion of the first main surface electrode 20 and an edge portion 51 of the inner covering portion 31. The exposure width WE of the edge portion 51 may be more than 0 μm and 10 μm or less. The exposure width WE is preferably 1 μm or more and 5 μm or less.

[0090] The third inner wall portion 52 (second opening 54) communicates with the first inner wall portion 34 (first opening 36) and forms one pad opening 55 with the first inner wall portion 34 (first opening 36). The third inner wall portion 52 is formed in a tapered shape that slopes obliquely downward from the main surface of the organic insulating film 50 toward the first inner wall portion 34. In this form, the third inner wall portion 52 is formed in a curved tapered shape that curves toward the inner covering portion 31.

[0091] The third outer wall portion 53 is formed at a distance from the peripheral edge (the first to fourth side surfaces 5A to 5D) of the first main surface 3 toward the outer covering portion 32 so as to expose the outer surface 17. The third outer wall portion 53 exposes the second outer wall portion 41 of the outer covering portion 32. Specifically, the third outer wall portion 53 is formed at a distance from the second outer wall portion 41 toward the second inner wall portion 40 so as to expose the peripheral edge portion of the outer covering portion 32. The third outer wall portion 53 is located on the second portion 38 of the outer covering portion 32 and faces the outer surface 17 with the outer covering portion 32 interposed therebetween.

[0092] That is, the third outer wall portion 53 is located between the outer wall portion 12 (notch opening 14) of the first inorganic insulating film 10 and the peripheral edge of the first main surface 3. The third outer wall portion 53 and the second outer wall portion 41 define the dicing street 39. In this form, the third outer wall portion 53 is formed in a quadrangular shape having four sides parallel to the electrode side wall 21 in a plan view. The third outer wall portion 53 is formed in a tapered shape that slopes obliquely downward from the main surface of the organic insulating film 50 toward the second outer wall portion 41 of the outer covering portion 32. In this form, the third outer wall portion 53 is formed in a curved tapered shape that curves toward the outer covering portion 32.

[0093] In this way, the organic insulating film 50 is formed across the inner covering portion 31 and the outer covering portion 32 of the second inorganic insulating film 30, and covers the electrode side wall 21 of the first main surface electrode 20 in the removal portion 33 between the inner covering portion 31 and the outer covering portion 32. Specifically, the organic insulating film 50 covers the electrode side wall 21 of the first main surface electrode 20, a part of the main body portion 22 of the first main surface electrode 20, the lead-out portion 23 (protrusion 24) of the first main surface electrode 20, and a part of the first inorganic insulating film 10 in the removal portion 33. That is, the organic insulating film 50 fills the unevenness formed by the first inorganic insulating film 10, the first main surface electrode 20, and the second inorganic insulating film 30 in the removal portion 33.

[0094] The SiC semiconductor device 1 includes a pad electrode 60 formed on the inner part of the first main surface electrode 20. The pad electrode 60 is a terminal electrode for external connection and, in this embodiment, is made of a plating film. The pad electrode 60 includes a Ni plating film 61 formed on the inner part of the first main surface electrode 20 within the pad opening 55. The Ni plating film 61 is formed at a distance from the main surface of the organic insulating film 50 toward the first main surface electrode 20 in the normal direction Z. The Ni plating film 61 covers the main body portion 22 of the first main surface electrode 20 and the first inner wall portion 34 of the inner covering portion 31 within the first opening 36.

[0095] The Ni plating film 61 is drawn from above the main body portion 22 of the first main surface electrode 20 to above the edge portion 51 of the inner covering portion 31. As a result, the Ni plating film 61 has a plating covering portion 62 that covers the edge portion 51 of the inner covering portion 31 within the second opening 54. The plating covering portion 62 is formed in an arc shape starting from the first inner wall portion 34 toward the organic insulating film 50 (the third inner wall portion 52) above the edge portion 51.

[0096] In this embodiment, the plating covering portion 62 covers the organic insulating film 50 (the third inner wall portion 52) within the second opening 54. The plating covering portion 62 covers the region on the side of the second inorganic insulating film 30 with respect to the middle portion of the third inner wall portion 52 of the organic insulating film 50. In other words, the plating covering portion 62 covers the organic insulating film 50 such that the exposed area of the third inner wall portion 52 exceeds the hidden area of the third inner wall portion 52. Thus, the plating covering portion 62 fills the entire first opening 36 and a part of the second opening 54.

[0097] The Ni plating film 61 has a first plating thickness TP1. The first plating thickness TP1 is the thickness of the Ni plating film 61 with respect to the main surface of the first main surface electrode 20 (the main body portion 22). The first plating thickness TP1 exceeds the second insulation thickness T2 of the second inorganic insulating film 30 (T2 < TP1). The first plating thickness TP1 is less than the third insulation thickness T3 of the organic insulating film 50 (TP1 < T3).

[0098] The first plating thickness TP1 exceeds the sum (=T2 + WE) of the second insulation thickness T2 of the second inorganic insulating film 30 and the exposed width WE of the second inorganic insulating film 30 (T2 + WE < T4). This is one condition for the Ni plating film 61 to contact the third inner wall portion 52. The first plating thickness TP1 may be 0.1 μm or more and 15 μm or less. Preferably, the first plating thickness TP1 is 2 μm or more and 8 μm or less.

[0099] The pad electrode 60 is made of a metal material different from that of the Ni plating film 61 and includes an outer plating film 63 that covers the outer surface of the Ni plating film 61. The outer plating film 63 is formed in a film shape along the outer surface of the Ni plating film 61. The outer plating film 63 covers the third inner wall portion 52 of the organic insulating film 50 within the second opening 54.

[0100] The outer plating film 63 has a terminal surface 64 for external connection. The terminal surface 64 is located on the Ni plating film 61 side with respect to the main surface of the organic insulating film 50 (the opening end of the second opening 54) in the normal direction Z. Thereby, the outer plating film 63 exposes a part of the third inner wall portion 52 of the organic insulating film 50. The outer plating film 63 has a second plating thickness TP2. The second plating thickness TP2 is less than the first plating thickness TP1 of the Ni plating film 61 (TP2 < TP1).

[0101] In this form, the outer plating film 63 has a laminated structure including a Pd plating film 65 and an Au plating film 66 laminated in this order from the Ni plating film 61 side. The Pd plating film 65 is formed in a film shape along the outer surface of the Ni plating film 61. The Pd plating film 65 covers the Ni plating film 61 with a space from the opening end of the second opening 54 toward the second inorganic insulating film 30 side in the normal direction Z. The Pd plating film 65 covers the third inner wall portion 52 of the organic insulating film 50 within the second opening 54. The thickness of the Pd plating film 65 may be 0.01 μm or more and 1 μm or less.

[0102] The Au plating film 66 is formed in a film shape along the outer surface of the Pd plating film 65. The Au plating film 66 covers the Pd plating film 65 with a space from the opening end of the second opening 54 toward the second inorganic insulating film 30 side with respect to the normal direction Z. The Au plating film 66 covers the third inner wall portion 52 of the organic insulating film 50 within the second opening 54. The thickness of the Au plating film 66 may be 0.01 μm or more and 1 μm or less. The Au plating film 66 preferably has a thickness less than that of the Pd plating film 65.

[0103] The SiC semiconductor device 1 includes a second main surface electrode 70 that covers the second main surface 4. The second main surface electrode 70 covers the entire area of the second main surface 4 and is continuous with the first to fourth side surfaces 5A to 5D. The second main surface electrode 70 is electrically connected to the first semiconductor region 6 (the second main surface 4). Specifically, the second main surface electrode 70 forms an ohmic contact with the first semiconductor region 6 (the second main surface 4).

[0104] In this form, the second main surface electrode 70 includes a Ti film 71, a Ni film 72, a Pd film 73, an Au film 74, and an Ag film 75 laminated in this order from the second main surface 4 side. The second main surface electrode 70 only needs to include at least the Ti film 71, and the presence or absence of the Ni film 72, the Pd film 73, the Au film 74, and the Ag film 75 is arbitrary respectively. As an example, the second main surface electrode 70 may have a laminated structure including the Ti film 71, the Ni film 72, and the Au film 74.

[0105] As described above, the SiC semiconductor device 1 (electronic component) includes the first inorganic insulating film 10 (object to be covered), the first main surface electrode 20 (electrode), the second inorganic insulating film 30, and the organic insulating film 50. The second inorganic insulating film 30 covers the first inorganic insulating film 10 and has electrode sidewalls 21 on the first inorganic insulating film 10. The second inorganic insulating film 30 has an inner covering portion 31 that covers the first main surface electrode 20 so as to expose the electrode sidewalls 21. The organic insulating film 50 covers the electrode sidewalls 21.

[0106] Since electronic components are used in various environments according to their applications, durability suitable for various usage environmental conditions is required. In particular, as an example of an electronic component, the SiC semiconductor device 1 is mounted on vehicles such as hybrid vehicles, electric vehicles, and fuel cell vehicles that use a motor as a drive source due to the physical properties (electrical characteristics) of SiC. Therefore, the SiC semiconductor device 1 is required to have excellent durability suitable for severe usage environmental conditions. The durability of electronic components is evaluated, for example, by a high-temperature and high-humidity bias test. In the high-temperature and high-humidity bias test, the electrical operation of the electronic component is evaluated while being exposed to a high-temperature and high-humidity environment.

[0107] In a high-temperature environment, the stress caused by the thermal expansion of the first main surface electrode 20 concentrates near the electrode side wall 21 of the first main surface electrode 20. When the second inorganic insulating film 30 covers the electrode side wall 21 of the first main surface electrode 20, the second inorganic insulating film 30 may peel off from the electrode side wall 21 due to the stress of the first main surface electrode 20, and the reliability may decrease. When the peeling of the second inorganic insulating film 30 occurs, in a high-humidity environment, the first main surface electrode 20 etc. may be oxidized due to the moisture (humidity) that has entered the peeled portion of the second inorganic insulating film 30, and the reliability may further decrease.

[0108] Therefore, in the SiC semiconductor device 1, the second inorganic insulating film 30 is formed so as to expose the electrode side wall 21. Thereby, the peeling starting point of the second inorganic insulating film 30 due to the stress of the first main surface electrode 20 can be reduced. As a result, the peeling of the second inorganic insulating film 30 due to the stress of the first main surface electrode 20 can be suppressed. Therefore, the first main surface electrode 20 can be appropriately protected by the second inorganic insulating film 30.

[0109] On the other hand, the organic insulating film 50 covers the electrode side wall 21. The organic insulating film 50 has a lower hardness than the second inorganic insulating film 30. Therefore, even if stress occurs in the first main surface electrode 20, the stress can be elastically absorbed. Thereby, the peeling of the organic insulating film 50 from the electrode side wall 21 can be suppressed. As a result, the electrode side wall 21 can be protected by the organic insulating film 50. Therefore, a SiC semiconductor device 1 with improved reliability can be provided. In the SiC semiconductor device 1, the reliability of the first main surface electrode 20 and its periphery is particularly improved.

[0110] The organic insulating film 50 preferably covers the inner covering portion 31. According to this structure, peeling of the second inorganic insulating film 30 from the first main surface electrode 20 can be suppressed, so that peeling of the organic insulating film 50 due to peeling of the second inorganic insulating film 30 can be suppressed. Therefore, by forming the organic insulating film 50 that covers the inner covering portion 31, the first main surface electrode 20 can be protected by both the second inorganic insulating film 30 and the organic insulating film 50.

[0111] The inner covering portion 31 preferably covers the first main surface electrode 20 at an interval from the electrode side wall 21 so as to expose the peripheral portion of the first main surface electrode 20. According to this structure, the influence of the stress of the first main surface electrode 20 on the inner covering portion 31 can be reduced. In this case, the inner covering portion 31 preferably exposes the lead-out portion 23 (protruding portion 24). According to this structure, the influence of the stress of the lead-out portion 23 (protruding portion 24) on the inner covering portion 31 can be reduced.

[0112] In these cases, the organic insulating film 50 preferably covers the portion exposed between the electrode side wall 21 and the inner covering portion 31 on the first main surface electrode 20. According to this structure, the portion exposed from the second inorganic insulating film 30 on the first main surface electrode 20 can be protected by the organic insulating film 50. The inner covering portion 31 preferably exposes the inner portion of the first main surface electrode 20. According to this structure, the contact portion of the first main surface electrode 20 can be ensured. In this case, the inner covering portion 31 preferably surrounds the inner portion of the first main surface electrode 20.

[0113] The second inorganic insulating film 30 preferably has an outer covering portion 32 that covers the first inorganic insulating film 10 so as to expose the electrode side wall 21 of the first main surface electrode 20. According to this structure, in the region outside the first main surface electrode 20, peeling of the second inorganic insulating film 30 from the first inorganic insulating film 10 due to the stress of the first main surface electrode 20 can be suppressed. Thereby, the first main surface electrode 20 can be protected by the second inorganic insulating film 30 from the region outside the first main surface electrode 20.

[0114] The organic insulating film 50 preferably covers the outer covering portion 32. According to this structure, peeling of the second inorganic insulating film 30 from the first inorganic insulating film 10 can be suppressed, so that peeling of the organic insulating film 50 due to peeling of the second inorganic insulating film 30 can be suppressed. Therefore, by forming the organic insulating film 50 that covers the outer covering portion 32, the first main surface electrode 20 can be protected by both the second inorganic insulating film 30 and the organic insulating film 50.

[0115] The outer covering portion 32 preferably covers the first inorganic insulating film 10 with a space from the electrode side wall 21 of the first main surface electrode 20. According to this structure, the influence of the stress of the first main surface electrode 20 on the outer covering portion 32 can be reduced. The organic insulating film 50 preferably covers the portion exposed between the electrode side wall 21 and the outer covering portion 32 in the first inorganic insulating film 10. According to this structure, the portion exposed between the electrode side wall 21 and the outer covering portion 32 in the first inorganic insulating film 10 can be protected by the organic insulating film 50. The outer covering portion 32 preferably surrounds the first main surface electrode 20 in a plan view. According to this structure, the first main surface electrode 20 can be appropriately protected by the second inorganic insulating film 30 from the region outside the first main surface electrode 20.

[0116] The SiC semiconductor device 1 (electronic component) includes a first main surface electrode 20 (electrode), a second inorganic insulating film 30, an organic insulating film 50, and a pad electrode 60. The first main surface electrode 20 has an electrode side wall 21. The second inorganic insulating film 30 covers the first main surface electrode 20 so as to expose the inner portion of the first main surface electrode 20 and the electrode side wall 21 of the first main surface electrode 20.

[0117] The organic insulating film 50 covers the electrode side wall 21 of the first main surface electrode 20 and exposes the inner portion of the first main surface electrode 20. The pad electrode 60 is formed on the inner portion of the first main surface electrode 20. According to this structure, peeling of the second inorganic insulating film 30 can be suppressed. Therefore, peeling of the pad electrode 60 due to peeling of the second inorganic insulating film 30 can also be suppressed. Thus, a SiC semiconductor device 1 with improved reliability can be provided. In the SiC semiconductor device 1, the reliability of the first main surface electrode 20 and its periphery is particularly improved.

[0118] The second inorganic insulating film 30 preferably extends in a strip shape along the side wall 21 of the electrode in plan view. In this case, it is particularly preferable that the second inorganic insulating film 30 surrounds the inner part of the first main surface electrode 20 in plan view. According to this structure, the first main surface electrode 20 can be appropriately protected by the second inorganic insulating film 30.

[0119] The pad electrode 60 preferably contacts the second inorganic insulating film 30. According to this structure, peeling of the second inorganic insulating film 30 can be suppressed, so that the pad electrode 60 in contact with the second inorganic insulating film 30 can be appropriately formed. Thereby, the connection area of the pad electrode 60 to the base can be appropriately increased, so that peeling of the pad electrode 60 can be appropriately suppressed.

[0120] The organic insulating film 50 preferably covers the second inorganic insulating film 30 on the first main surface electrode 20. According to this structure, peeling of the second inorganic insulating film 30 from the first main surface electrode 20 can be suppressed, so that peeling of the organic insulating film 50 due to peeling of the second inorganic insulating film 30 can be suppressed. Therefore, by forming the organic insulating film 50 that covers the inner coating portion 31, both the second inorganic insulating film 30 and the organic insulating film 50 can protect the first main surface electrode 20 and the pad electrode 60.

[0121] In this structure, the pad electrode 60 preferably contacts the organic insulating film 50. According to this structure, peeling of the organic insulating film 50 can be suppressed, so that peeling of the pad electrode 60 due to peeling of the organic insulating film 50 can be suppressed. Also, since the connection area of the pad electrode 60 to the base can be increased, peeling of the pad electrode 60 can be suppressed.

[0122] The organic insulating film 50 preferably covers the edge portion 51 of the second inorganic insulating film 30 so as to expose the edge portion 51 of the second inorganic insulating film 30 on the inner side of the first main surface electrode 20. In this case, the pad electrode 60 preferably covers the edge portion 51 of the second inorganic insulating film 30. According to this structure, since the connection area of the pad electrode 60 to the base can be increased, peeling of the pad electrode 60 can be appropriately suppressed.

[0123] In this case, the pad electrode 60 preferably includes a Ni plating film 61. The Ni plating film 61 has good adhesion to the second inorganic insulating film 30. Therefore, by forming the Ni plating film 61 that covers the edge portion 51 of the second inorganic insulating film 30, peeling of the pad electrode 60 can be appropriately suppressed.

[0124] The Ni plating film 61 preferably covers a region on the second inorganic insulating film 30 side with respect to the middle portion of the third inner wall portion 52 of the organic insulating film 50. That is, the Ni plating film 61 preferably covers the organic insulating film 50 such that the hidden area of the third inner wall portion 52 is less than the exposed area of the third inner wall portion 52.

[0125] The pad electrode 60 may include an outer plating film 63 that covers the outer surface of the Ni plating film 61. According to this structure, peeling of the Ni plating film 61 can be suppressed, so peeling of the outer plating film 63 due to peeling of the Ni plating film 61 can be suppressed. Therefore, the Ni plating film 61 can be appropriately covered by the outer plating film 63. The outer plating film 63 may include at least one of a Pd plating film 65 and an Au plating film 66.

[0126] The second inorganic insulating film 30 can take various forms shown in FIGS. 5A to 5F. FIG. 5A corresponds to FIG. 2 and is a plan view showing the internal structure of the SiC semiconductor device 1 together with the second inorganic insulating film 30 according to the second exemplary form. Hereinafter, structures corresponding to the structures shown in FIGS. 1 to 4 are given the same reference numerals, and their descriptions are omitted.

[0127] Referring to FIG. 5A, the inner covering portion 31 of the second inorganic insulating film 30 has an inner opening 76 that exposes the first main surface electrode 20. The inner opening 76 is formed in the inner portion of the inner covering portion 31 at a distance from the first inner wall portion 34 and the first outer wall portion 35. The inner opening 76 is formed in a strip shape extending along the first inner wall portion 34 and the first outer wall portion 35. In this form, the inner opening 76 is formed in an annular shape (specifically, a square annular shape) extending along the first inner wall portion 34 and the first outer wall portion 35. The inner opening 76 exposes the main body portion 22 of the first main surface electrode 20 at a distance from the lead-out portion 23 (protrusion 24) of the first main surface electrode 20.

[0128] The organic insulating film 50 enters the inner opening 76 from above the inner covering portion 31 and covers the portion of the first main surface electrode 20 exposed from the inner opening 76. The portion of the organic insulating film 50 located within the inner opening 76 of the second inorganic insulating film 30 forms an anchor portion. Thereby, the contact area of the organic insulating film 50 with respect to the second inorganic insulating film 30 increases, and peeling of the organic insulating film 50 from the second inorganic insulating film 30 can be suppressed.

[0129] FIG. 5B corresponds to FIG. 2 and is a plan view showing the internal structure of the SiC semiconductor device 1 together with the second inorganic insulating film 30 according to the third exemplary form. Hereinafter, the same reference numerals are given to the structures corresponding to the structures shown in FIGS. 1 to 4, and the descriptions thereof are omitted.

[0130] Referring to FIG. 5B, the outer covering portion 32 of the second inorganic insulating film 30 has an outer opening 77 that exposes the first inorganic insulating film 10. The outer opening 77 is formed in the inner portion of the outer covering portion 32 at a distance from the second inner wall portion 40 and the second outer wall portion 41. The outer opening 77 is formed in a strip shape extending along the second inner wall portion 40 and the second outer wall portion 41. In this form, the outer opening 77 is formed in an annular shape (specifically, a square annular shape) extending along the second inner wall portion 40 and the second outer wall portion 41.

[0131] The organic insulating film 50 enters the outer opening 77 from above the outer covering portion 32 and covers the portion exposed from the outer opening 77 in the first inorganic insulating film 10. The portion of the organic insulating film 50 located within the outer opening 77 forms an anchor portion. As a result, the contact area of the organic insulating film 50 with respect to the second inorganic insulating film 30 increases, and peeling of the organic insulating film 50 from the second inorganic insulating film 30 can be suppressed.

[0132] FIG. 5C corresponds to FIG. 2 and is a plan view showing the internal structure of the SiC semiconductor device 1 together with the second inorganic insulating film 30 according to the fourth exemplary embodiment. Hereinafter, structures corresponding to the structures shown in FIGS. 1 to 4 are given the same reference numerals, and their descriptions are omitted.

[0133] Referring to FIG. 5C, the inner covering portion 31 of the second inorganic insulating film 30 has an inner opening 76 that exposes the first main surface electrode 20 (also refer to FIG. 5A). The outer covering portion 32 of the second inorganic insulating film 30 has an outer opening 77 that exposes the first inorganic insulating film 10 (also refer to FIG. 5B). The portions of the organic insulating film 50 located within the inner opening 76 and within the outer opening 77 respectively form anchor portions. As a result, peeling of the organic insulating film 50 from the second inorganic insulating film 30 can be suppressed at the inner and outer portions of the first main surface electrode 20.

[0134] FIG. 5D corresponds to FIG. 2 and is a plan view showing the internal structure of the SiC semiconductor device 1 together with the second inorganic insulating film 30 according to the fifth exemplary embodiment. Hereinafter, structures corresponding to the structures shown in FIGS. 1 to 4 are given the same reference numerals, and their descriptions are omitted.

[0135] Referring to FIG. 5D, the inner covering portion 31 of the second inorganic insulating film 30 has a plurality of inner openings 76 that expose the first main surface electrode 20. The plurality of inner openings 76 are respectively formed in the inner portion of the inner covering portion 31 at intervals from the first inner wall portion 34 and the first outer wall portion 35. The plurality of inner openings 76 are formed at intervals along the first inner wall portion 34 (the first outer wall portion 35).

[0136] In this form, each inner opening 76 is formed in a strip shape extending along the first inner wall portion 34 in a plan view. The planar shape of each inner opening 76 is arbitrary. Each inner opening 76 may be formed in a polygonal shape or a circular shape in a plan view. Each inner opening 76 exposes the main body portion 22 of the first main surface electrode 20 with a space from the lead-out portion 23 (protrusion 24) of the first main surface electrode 20.

[0137] The outer covering portion 32 of the second inorganic insulating film 30 has a plurality of outer openings 77 that expose the first inorganic insulating film 10. The plurality of outer openings 77 are respectively formed in the inner portion of the outer covering portion 32 at intervals from the second inner wall portion 40 and the second outer wall portion 41. The plurality of outer openings 77 are formed at intervals along the second inner wall portion 40 (second outer wall portion 41). In this form, each outer opening 77 is formed in a strip shape extending along the second inner wall portion 40 in a plan view. The planar shape of each outer opening 77 is arbitrary. Each outer opening 77 may be formed in a polygonal shape or a circular shape in a plan view.

[0138] The portions of the organic insulating film 50 located within the plurality of inner openings 76 and the portions located within the plurality of outer openings 77 respectively form anchor portions. Thereby, the contact area of the organic insulating film 50 with respect to the second inorganic insulating film 30 increases, and peeling of the organic insulating film 50 from the second inorganic insulating film 30 can be suppressed.

[0139] In this form, an example in which the inner covering portion 31 has a plurality of inner openings 76 and the outer covering portion 32 has a plurality of outer openings 77 has been described. However, the inner covering portion 31 may have only one inner opening 76 formed in an end shape. Further, the outer covering portion 32 may have only one outer opening 77 formed in an end shape. Also, while the outer covering portion 32 does not have an outer opening 77, the inner covering portion 31 may have at least one inner opening 76. Further, while the inner covering portion 31 does not have an inner opening 76, the outer covering portion 32 may have at least one outer opening 77.

[0140] FIG. 5E corresponds to FIG. 2 and is a plan view showing the internal structure of the SiC semiconductor device 1 together with the second inorganic insulating film 30 according to the sixth exemplary embodiment. Hereinafter, the same reference numerals are given to the structures corresponding to the structures shown in FIGS. 1 to 4, and the descriptions thereof are omitted.

[0141] Referring to FIG. 5E, the inner covering portion 31 of the second inorganic insulating film 30 is formed on the first main surface electrode 20 so as to expose the corner portions (four corners) of the first main surface electrode 20. Specifically, the inner covering portion 31 has a form in which the corner portions (four corners) of the inner covering portion 31 (see FIG. 2) according to the first exemplary embodiment are removed, and the corner portions (four corners) of the first main surface electrode 20 are exposed. That is, the inner covering portion 31 includes a plurality of inner segment portions 78 formed on the first main surface electrode 20 with a space therebetween. Each inner segment portion 78 is formed in a one-to-one correspondence with each side of the electrode side wall 21 and extends in a strip shape along each side of the electrode side wall 21.

[0142] The outer covering portion 32 of the second inorganic insulating film 30 is formed on the first inorganic insulating film 10 so as to expose the portion along the corner portion of the first main surface electrode 20 in the first inorganic insulating film 10. Specifically, the outer covering portion 32 has a form in which the corner portions (four corners) of the outer covering portion 32 (see FIG. 2) according to the first exemplary embodiment are removed, and the portion along the corner portion of the first main surface electrode 20 in the first inorganic insulating film 10 is exposed. That is, the outer covering portion 32 includes a plurality of outer segment portions 79 formed on the first inorganic insulating film 10. Each outer segment portion 79 is formed in a one-to-one correspondence with each side of the electrode side wall 21 and extends in a strip shape along each side of the electrode side wall 21.

[0143] The organic insulating film 50 covers the plurality of inner segment portions 78 of the inner covering portion 31 on the first main surface electrode 20. Further, the organic insulating film 50 covers the corner portions (four corners) of the first main surface electrode 20. The organic insulating film 50 covers the plurality of outer segment portions 79 of the outer covering portion 32 on the first inorganic insulating film 10. Further, the organic insulating film 50 covers the portion along the corner portion of the first main surface electrode 20 in the first inorganic insulating film 10.

[0144] Even with such a structure, the contact area of the organic insulating film 50 with respect to the second inorganic insulating film 30 can be increased. Therefore, peeling of the organic insulating film 50 from the second inorganic insulating film 30 can be suppressed. At the corners (four corners) of the first main surface electrode 20, stress due to thermal expansion tends to concentrate. Therefore, by forming the second inorganic insulating film 30 so as to expose the corners (four corners) of the first main surface electrode 20, the influence of the stress of the first main surface electrode 20 on the second inorganic insulating film 30 can be reduced.

[0145] In this embodiment, an example in which the inner covering portion 31 has four inner segment portions 78 and the outer covering portion 32 has four outer segment portions 79 has been described. However, the inner covering portion 31 may have at least one inner segment portion 78 formed in an end shape. Further, the outer covering portion 32 may have at least one outer segment portion 79 formed in an end shape. Further, even when the outer covering portion 32 does not have the outer segment portion 79, the inner covering portion 31 may have at least one inner segment portion 78. Further, even when the inner covering portion 31 does not have the inner segment portion 78, the outer covering portion 32 may have at least one outer segment portion 79.

[0146] FIG. 5F corresponds to FIG. 2 and is a plan view showing the internal structure of the SiC semiconductor device 1 together with the second inorganic insulating film 30 according to the seventh embodiment. Hereinafter, the same reference numerals are given to the structures corresponding to the structures shown in FIGS. 1 to 4, and the description thereof is omitted.

[0147] Referring to FIG. 5F, the inner covering portion 31 of the second inorganic insulating film 30 includes a plurality of inner segment portions 78 that expose the corners (four corners) of the first main surface electrode 20, similar to the second inorganic insulating film 30 according to the sixth embodiment. In this embodiment, the plurality of inner segment portions 78 are formed in a one-to-many correspondence with each side of the electrode side wall 21 and are formed at intervals along each side of the electrode side wall 21. The planar shape of each inner segment portion 78 is arbitrary. Each inner segment portion 78 may be formed in a square shape, a polygonal shape, a circular shape, or the like in plan view.

[0148] The outer covering portion 32 of the second inorganic insulating film 30 includes a plurality of outer segment portions 79 that expose portions along the corners of the first main surface electrode 20 in the first inorganic insulating film 10, similar to the second inorganic insulating film 30 according to the sixth exemplary form. In this form, the plurality of outer segment portions 79 are formed in a one-to-many correspondence with each side of the electrode sidewall 21 and are formed at intervals along each side of the electrode sidewall 21. The planar shape of each outer segment portion 79 is arbitrary. Each outer segment portion 79 may be formed in a square shape, a polygonal shape, a circular shape, etc. in a plan view.

[0149] In this form, an example in which the inner covering portion 31 has a plurality of inner segment portions 78 and the outer covering portion 32 has a plurality of outer segment portions 79 has been described. However, while the outer covering portion 32 does not have the outer segment portions 79, the inner covering portion 31 may have a plurality of inner segment portions 78. Also, while the inner covering portion 31 does not have the inner segment portions 78, the outer covering portion 32 may have a plurality of outer segment portions 79.

[0150] Figs. 6A to 6N are cross-sectional views for explaining an example of a manufacturing method of the SiC semiconductor device 1 shown in Fig. 1.

[0151] Referring to Fig. 6A, a SiC wafer 81 (wafer / semiconductor wafer) serving as a base of the first semiconductor region 6 is prepared. Next, a semiconductor crystal (SiC in this form) is crystal-grown from one surface of the SiC wafer 81 by an epitaxial growth method. Thereby, a third semiconductor region 8 having a predetermined n-type impurity concentration and a second semiconductor region 7 having a predetermined n-type impurity concentration are formed in this order on the SiC wafer 81. In this form, the third semiconductor region 8 and the second semiconductor region 7 are each formed from a SiC epitaxial layer.

[0152] Hereinafter, a wafer structure including a first semiconductor region 6 (SiC wafer 81), a third semiconductor region 8, and a second semiconductor region 7 is referred to as an SiC epitaxial wafer 82. The SiC epitaxial wafer 82 has a first wafer main surface 83 on one side and a second wafer main surface 84 on the other side. The first wafer main surface 83 and the second wafer main surface 84 respectively correspond to the first main surface 3 and the second main surface 4 of the SiC chip 2.

[0153] Next, a plurality of device regions 85 and dicing planned lines 86 partitioning the plurality of device regions 85 are set on the first wafer main surface 83. The plurality of device regions 85 are set in a matrix at intervals in a first direction X and a second direction Y in a plan view, for example. The dicing planned lines 86 are set in a grid according to the arrangement of the plurality of device regions 85 in a plan view. In FIG. 6A, one device region 85 is shown, and the dicing planned line 86 is shown by a dashed-dotted line (the same applies in FIGS. 6B to 6N below).

[0154] Next, referring to FIG. 6B, a first base insulating film 87 serving as a base of the first inorganic insulating film 10 is formed on the first wafer main surface 83. In this form, the first base insulating film 87 is made of a silicon oxide film. The first base insulating film 87 may be formed by a CVD (Chemical Vapor Deposition) method and / or a thermal oxidation treatment method. In this form, the first base insulating film 87 is formed by a thermal oxidation treatment method.

[0155] That is, the first base insulating film 87 is made of a field oxide film containing an oxide of the SiC epitaxial wafer 82 (specifically, the second semiconductor region 7). The first base insulating film 87 grows while absorbing n-type impurities in the vicinity of the first wafer main surface 83. Therefore, the first base insulating film 87 contains n-type impurities in the second semiconductor region 7.

[0156] Next, referring to FIG. 6C, a first resist mask 88 having a predetermined pattern is formed on the first base insulating film 87. The first resist mask 88 has an opening that exposes the region where the guard region 9 is to be formed on the first wafer main surface 83. Next, p-type impurities are introduced into the surface layer portion of the first wafer main surface 83 by an ion implantation method through the first resist mask 88. The p-type impurities are introduced into the surface layer portion of the first wafer main surface 83 through the first base insulating film 87. Thereby, the guard region 9 is formed. After the formation of the guard region 9, the first resist mask 88 is removed.

[0157] Next, referring to FIG. 6D, a second resist mask 89 having a predetermined pattern is formed on the first base insulating film 87. The second resist mask 89 has an opening that covers the region where the first inorganic insulating film 10 is to be formed in the first base insulating film 87 and exposes the other regions. Next, unnecessary portions of the first base insulating film 87 are removed by an etching method through the second resist mask 89.

[0158] The etching method may be a wet etching method and / or a dry etching method. The first base insulating film 87 is removed until the first wafer main surface 83 is exposed. Thereby, the first inorganic insulating film 10 having the contact opening 13 and the notch opening 14 and partitioning the hidden surface 15, the active surface 16, and the outer surface 17 on the first wafer main surface 83 is formed.

[0159] In this step, the portion exposed from the first inorganic insulating film 10 on the first wafer main surface 83 is also partially removed. That is, the surface layer portion of the active surface 16 and the surface layer portion of the outer surface 17 are partially removed. The etching method may be a wet etching method and / or a dry etching method. Thereby, the active surface 16 and the outer surface 17 that are recessed on the bottom side of the second semiconductor region 7 with respect to the hidden surface 15 are formed.

[0160] Next, referring to FIG. 6E, a base electrode film 90 that serves as the base of the first main surface electrode 20 is formed on the first wafer main surface 83. The base electrode film 90 is formed on the first wafer main surface 83 so as to cover the entire region of the first inorganic insulating film 10. The base electrode film 90 forms a Schottky junction with the active surface 16 exposed from the contact opening 13.

[0161] The base electrode film 90 has a stacked structure including a first electrode film 25, a second electrode film 26, and a third electrode film 27 stacked in this order from the first wafer main surface 83 side. The first electrode film 25 is formed of various metals that form a Schottky junction with the first wafer main surface 83. In this form, the first electrode film 25 is made of a titanium film. The second electrode film 26 is made of a Ti-based metal film (a titanium nitride film in this form).

[0162] The third electrode film 27 is made of a Cu-based metal film or an Al-based metal film (an AlCu alloy film in this form). The first electrode film 25, the second electrode film 26, and the third electrode film 27 may be formed by at least one of sputtering, vapor deposition, and electroplating methods. In this form, the first electrode film 25, the second electrode film 26, and the third electrode film 27 are each formed by sputtering.

[0163] Next, referring to FIG. 6F, a third resist mask 91 having a predetermined pattern is formed on the base electrode film 90. The third resist mask 91 has an opening that covers the region where the first main surface electrode 20 is to be formed in the base electrode film 90 and exposes the other regions. Next, unnecessary portions of the base electrode film 90 are removed by an etching method through the third resist mask 91. The etching method may be a wet etching method and / or a dry etching method. Thereby, the first main surface electrode 20 is formed. After the formation of the first main surface electrode 20, the third resist mask 91 is removed.

[0164] Next, referring to FIG. 6G, a second base insulating film 92 that serves as a base for the second inorganic insulating film 30 is formed on the first wafer main surface 83 so as to cover the first inorganic insulating film 10 and the first main surface electrode 20. In this embodiment, the second base insulating film 92 is made of a silicon nitride film. The second base insulating film 92 may be formed by a CVD method.

[0165] Next, referring to FIG. 6H, a fourth resist mask 93 having a predetermined pattern is formed on the second base insulating film 92. The fourth resist mask 93 has an opening that covers an area where the second inorganic insulating film 30 is to be formed in the second base insulating film 92 and exposes other areas. Specifically, the fourth resist mask 93 covers portions that will become the inner covering portion 31 and the outer covering portion 32 of the second inorganic insulating film 30 in the second base insulating film 92, and exposes portions that will become the removal portion 33 and the dicing street 39 of the second inorganic insulating film 30 in the second base insulating film 92.

[0166] Next, unnecessary portions of the second base insulating film 92 are removed by an etching method through the fourth resist mask 93. The etching method may be a wet etching method and / or a dry etching method. Thereby, the second inorganic insulating film 30 having an inner covering portion 31, an outer covering portion 32, and a removal portion 33 is formed. The outer covering portion 32 of the second inorganic insulating film 30 demarcates a dicing street 39 that exposes a planned cutting line 86 on the first wafer main surface 83. After the formation of the second inorganic insulating film 30, the fourth resist mask 93 is removed.

[0167] Next, referring to FIG. 6I, an organic insulating film 50 is formed on the first wafer main surface 83 so as to cover the first main surface electrode 20, the first inorganic insulating film 10, and the second inorganic insulating film 30. The organic insulating film 50 is formed by applying a photosensitive resin on the first wafer main surface 83. In this embodiment, the organic insulating film 50 is made of a polyimide film.

[0168] Next, referring to FIG. 6J, after the organic insulating film 50 is exposed in a pattern corresponding to the second opening 54 and the dicing street 39, it is developed. As a result, a second opening 54 that exposes the first main surface electrode 20 and a dicing street 39 that extends in a lattice shape along the planned cutting line 86 are formed in the organic insulating film 50.

[0169] Next, referring to FIG. 6K, the pad electrode 60 is formed on the portion of the first main surface electrode 20 that is exposed from the first opening 36 and the second opening 54. In this form, the pad electrode 60 includes a Ni plating film 61, a Pd plating film 65, and an Au plating film 66 laminated in this order from the side of the first main surface electrode 20. The Ni plating film 61, the Pd plating film 65, and the Au plating film 66 are each formed by an electrolytic plating method or an electroless plating method (in this form, the electroless plating method).

[0170] Next, referring to FIG. 6L, the SiC epitaxial wafer 82 is thinned by grinding the second wafer main surface 84 until it reaches a desired thickness. The grinding process may be performed by a CMP (Chemical Mechanical Polishing) method. As a result, grinding marks are formed on the second wafer main surface 84. The grinding process of the second wafer main surface 84 does not necessarily have to be performed and may be omitted as necessary.

[0171] However, thinning of the first semiconductor region 6 is effective in reducing the resistance value of the SiC chip 2. After the grinding process of the second wafer main surface 84, an annealing process may be performed on the second wafer main surface 84. The annealing process may be performed by a laser irradiation method. As a result, the second wafer main surface 84 (the second main surface 4) becomes an ohmic surface having grinding marks and laser irradiation marks.

[0172] Next, referring to FIG. 6M, the second main surface electrode 70 is formed on the second wafer main surface 84. The second main surface electrode 70 forms an ohmic contact with the second wafer main surface 84. The second main surface electrode 70 has a stacked structure including a Ti film 71, a Ni film 72, a Pd film 73, an Au film 74, and an Ag film 75 stacked in this order from the second wafer main surface 84 side. The Ti film 71, the Ni film 72, the Pd film 73, the Au film 74, and the Ag film 75 may be formed by at least one method among sputtering, vapor deposition, and plating (sputtering in this embodiment).

[0173] Next, referring to FIG. 6N, the SiC epitaxial wafer 82 is cut along the planned cutting line 86. The cutting process of the SiC epitaxial wafer 82 may include a cutting process using a dicing blade. In this case, the SiC epitaxial wafer 82 is cut along the planned cutting line 86 partitioned by the dicing street 39. The dicing blade preferably has a blade width less than the width of the dicing street 39. Since the first inorganic insulating film 10, the second inorganic insulating film 30, and the organic insulating film 50 are not located on the planned cutting line 86, they are exempt from cutting by the dicing blade.

[0174] The cutting process of the SiC epitaxial wafer 82 may include a cleavage process using a laser light irradiation method. In this case, laser light is irradiated into the SiC epitaxial wafer 82 through the dicing street 39 from a laser light irradiation device (not shown). The laser light is preferably irradiated in a pulsed manner into the SiC epitaxial wafer 82 from the first wafer main surface 83 side without the second main surface electrode 70. The condensing part (focus) of the laser light is set inside the SiC epitaxial wafer 82 (in the middle of the thickness direction), and the irradiation position of the laser light is moved along the dicing street 39 (specifically, the planned cutting line 86).

[0175] As a result, a modified layer that extends in a lattice pattern along the dicing street 39 in plan view is formed inside the SiC epitaxial wafer 82. The modified layer is preferably formed inside the SiC epitaxial wafer 82 at a distance from the first wafer main surface 83. The modified layer is preferably formed in a portion of the SiC epitaxial wafer 82 that consists of the first semiconductor region 6 (SiC wafer 81). It is particularly preferable that the modified layer is formed in the first semiconductor region 6 (SiC wafer 81) at a distance from the second semiconductor region 7 (SiC epitaxial layer). Most preferably, the modified layer is not formed in the second semiconductor region 7 (SiC epitaxial layer).

[0176] After the step of forming the modified layer, an external force is applied to the SiC epitaxial wafer 82, and the SiC epitaxial wafer 82 is cleaved starting from the modified layer. The external force is preferably applied to the SiC epitaxial wafer 82 from the side of the second wafer main surface 84. The second main surface electrode 70 is cleaved simultaneously with the cleavage of the SiC epitaxial wafer 82. Since the first inorganic insulating film 10, the second inorganic insulating film 30, and the organic insulating film 50 are not located on the planned cutting line 86, they are spared from cleavage. Through the steps including the above, the SiC semiconductor device 1 is manufactured.

[0177] FIG. 7 corresponds to FIG. 4 and is a cross-sectional view for explaining the SiC semiconductor device 101 according to the second embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 1, the same reference numerals are given, and their descriptions are omitted.

[0178] Referring to FIG. 7, in the SiC semiconductor device 101 according to the second embodiment, the plating covering portion 62 of the Ni plating film 61 covers the edge portion 51 of the inner covering portion 31 at a distance from the third inner wall portion 52 of the organic insulating film 50. The plating covering portion 62 exposes a part of the edge portion 51 and the entire area of the third inner wall portion 52. The plating covering portion 62 is formed in an arc shape starting from the first inner wall portion 34 toward the third inner wall portion 52 above the edge portion 51.

[0179] In this form, the first plating thickness TP1 of the Ni plating film 61 is less than the sum (=T2 + WE) of the second insulation thickness T2 of the second inorganic insulation film 30 and the exposed width WE of the second inorganic insulation film 30 (T2 + WE > TP1). This is one condition for the Ni plating film 61 not to contact the third inner wall portion 52. On the other hand, in this form, the outer plating film 63 covers the edge portion 51 at a distance from the third inner wall portion 52 within the second opening 54. The outer plating film 63 exposes a part of the edge portion 51 and the entire third inner wall portion 52.

[0180] As described above, the SiC semiconductor device 101 also exhibits the same effects as those described for the SiC semiconductor device 1. In this form, an example in which the outer plating film 63 that exposes the entire third inner wall portion 52 is formed has been described. However, an outer plating film 63 that covers a part of the third inner wall portion 52 may be formed. In this case, either one or both of the Pd plating film 65 and the Au plating film 66 may cover a part of the third inner wall portion 52.

[0181] FIG. 8 corresponds to FIG. 4 and is a cross-sectional view for explaining the SiC semiconductor device 111 according to the third embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 1, the same reference numerals are given, and their descriptions are omitted.

[0182] Referring to FIG. 8, in the SiC semiconductor device 111 according to the third embodiment, the first inorganic insulation film 10 is continuous with the periphery of the first main surface 3 (the first to fourth side surfaces 5A to 5D). Therefore, the first inorganic insulation film 10 does not partition the outer surface 17 on the first main surface 3. The first inorganic insulation film 10 partitions only the hidden surface 15 and the active surface 16 on the first main surface 3. In the second inorganic insulation film 30, the entire outer covering portion 32 is formed on the first inorganic insulation film 10.

[0183] In this form, the second outer wall portion 41 of the outer covering portion 32 is formed in a region between the outer edge of the guard region 9 and the periphery of the first main surface 3 in a plan view, exposing the peripheral portion of the first inorganic insulating film 10. Thereby, the outer covering portion 32 faces the second semiconductor region 7 and the guard region 9 with the first inorganic insulating film 10 interposed therebetween. The second outer wall portion 41 demarcates a dicing street 39 that exposes the peripheral portion of the first inorganic insulating film 10 between the second outer wall portion 41 and the periphery of the first main surface 3.

[0184] As described above, the SiC semiconductor device 111 also exhibits the same effects as those described for the SiC semiconductor device 1.

[0185] FIG. 9 corresponds to FIG. 4 and is a cross-sectional view for explaining the SiC semiconductor device 121 according to the fourth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 1, the same reference numerals are given, and the descriptions thereof are omitted.

[0186] Referring to FIG. 9, in the SiC semiconductor device 121 according to the fourth embodiment, the first inorganic insulating film 10 is continuous with the periphery of the first main surface 3 (the first to fourth side surfaces 5A to 5D). Therefore, the first inorganic insulating film 10 does not demarcate the outer side surface 17 on the first main surface 3. The first inorganic insulating film 10 demarcates only the hidden surface 15 and the active surface 16 on the first main surface 3.

[0187] The second inorganic insulating film 30 is formed on the first inorganic insulating film 10 so as to be continuous with the periphery of the first main surface 3 (the first to fourth side surfaces 5A to 5D). Therefore, in this form, the second inorganic insulating film 30 does not demarcate the dicing street 39 between the second inorganic insulating film 30 and the periphery of the first main surface 3. The organic insulating film 50 (the third outer wall portion 53) is formed at a distance inward from the periphery of the first main surface 3 in a plan view in this form, and demarcates the dicing street 39 where the second inorganic insulating film 30 is exposed.

[0188] As described above, the SiC semiconductor device 121 also exhibits the same effects as those described for the SiC semiconductor device 1.

[0189] FIG. 10 corresponds to FIG. 4 and is a cross-sectional view for explaining an SiC semiconductor device 131 according to the fifth embodiment of the present invention. Hereinafter, for structures corresponding to the structures described for the SiC semiconductor device 1, the same reference numerals are given, and their descriptions are omitted.

[0190] Referring to FIG. 10, in the SiC semiconductor device 131 according to the fifth embodiment, the active surface 16 and the outer surface 17 are located substantially on the same plane as the shielding surface 15. The shielding surface 15, the active surface 16, and the outer surface 17 having such a form are formed, for example, by forming the first base insulating film 87 by CVD method in the above-described formation step of the first base insulating film 87 (see FIG. 6B). In this case, since oxidation of the first wafer main surface 83 is suppressed, it is possible to suppress partial removal of the first wafer main surface 83 in the above-described removal step of the first base insulating film 87 (see FIG. 6D).

[0191] As described above, the SiC semiconductor device 131 also exhibits the same effects as those described for the SiC semiconductor device 1. The form in which the active surface 16 and the outer surface 17 are located substantially on the same plane as the shielding surface 15 can be applied not only to the first embodiment but also to the second to fourth embodiments.

[0192] FIG. 11 is a plan view showing an SiC semiconductor device 201 according to the sixth embodiment of the present invention. FIG. 12 is a plan view showing the internal structure of the SiC semiconductor device 201 shown in FIG. 11 together with the second inorganic insulating film 320 according to the first form example. FIG. 13 is an enlarged view of the region XIII shown in FIG. 11. FIG. 14 is a cross-sectional view taken along the line XIV-XIV shown in FIG. 13. FIG. 15 is a cross-sectional view taken along the line XV-XV shown in FIG. 11. FIG. 16 is a cross-sectional view taken along the line XVI-XVI shown in FIG. 11. FIG. 17 is an enlarged cross-sectional view of the main part of the structure shown in FIG. 15. FIG. 18 is an enlarged cross-sectional view of the main part of the structure shown in FIG. 16.

[0193] Referring to FIGS. 11 to 18, in this embodiment, the SiC semiconductor device 201 is an electronic component including a SiC chip 202 (chip / semiconductor chip) made of a hexagonal SiC single crystal. Further, in this embodiment, the SiC semiconductor device 201 is a semiconductor switching device including a SiC-MISFET (Metal Insulator Semiconductor Field Effect Transistor). The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc. In this embodiment, an example in which the SiC chip 202 is made of a 4H-SiC single crystal is shown, but other polytypes are not excluded.

[0194] The SiC chip 202 is formed in a rectangular parallelepiped shape. The SiC chip 202 has a first main surface 203 on one side, a second main surface 204 on the other side, and first to fourth side surfaces 205A to 205D connecting the first main surface 203 and the second main surface 204. The first main surface 203 is a device surface on which a functional device is formed. The second main surface 204 is a non-device surface on which a functional device is not formed. The first main surface 203 and the second main surface 204 are formed in a quadrangular shape (specifically, a rectangular shape) in a plan view (hereinafter, simply referred to as "plan view") as viewed from the normal direction Z thereof.

[0195] The first main surface 203 and the second main surface 204 face the c-plane of the SiC single crystal. The c-plane includes the silicon plane ((0001) plane) and the carbon plane ((000-1) plane) of the SiC single crystal. It is preferable that the first main surface 203 faces the silicon plane and the second main surface 204 faces the carbon plane. The first main surface 203 and the second main surface 204 may have an off-angle inclined at a predetermined angle in an off-direction with respect to the c-plane. The off-direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal. The off-angle may be more than 0° and 10° or less. The off-angle is preferably 5° or less. The off-angle is particularly preferably 2° or more and 4.5° or less.

[0196] The second major surface 204 may be composed of a rough surface having either or both of grinding marks and annealing marks (specifically, laser irradiation marks). The annealing marks may contain amorphous SiC and / or SiC (specifically, Si) silicided (alloyed) with a metal. The second major surface 204 preferably consists of an ohmic surface having at least annealing marks.

[0197] The first to fourth side surfaces 205A to 205D form the peripheries of the first major surface 203 and the second major surface 204. The first side surface 205A and the second side surface 205B extend in a first direction X along the first major surface 203 and face each other in a second direction Y intersecting (specifically, orthogonal) the first direction X. The first side surface 205A and the second side surface 205B form the short sides of the SiC chip 202. The third side surface 205C and the fourth side surface 205D extend in the second direction Y and face each other in the first direction X. The third side surface 205C and the fourth side surface 205D form the long sides of the SiC chip 202.

[0198] In this form, the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal, and the second direction Y is the a-axis direction of the SiC single crystal. That is, the first side surface 205A and the second side surface 205B are formed by the a-plane of the SiC single crystal, and the third side surface 205C and the fourth side surface 205D are formed by the m-plane of the SiC single crystal.

[0199] The first to fourth side surfaces 205A to 205D may be composed of a ground surface having grinding marks formed by cutting with a dicing blade, or may be composed of a cleavage surface having a modified layer formed by laser light irradiation. Specifically, the modified layer consists of a region where a part of the crystal structure of the SiC chip 202 is modified to another property. That is, the modified layer consists of a region where the density, refractive index, or mechanical strength (crystal strength), or other physical properties are modified to properties different from those of the SiC chip 202. The modified layer may contain at least one layer of an amorphous layer, a melt re-hardened layer, a defect layer, an insulation breakdown layer, or a refractive index change layer.

[0200] When the first to fourth side surfaces 205A to 205D are cleavage surfaces, the first side surface 205A and the second side surface 205B may form inclined surfaces having an inclination angle due to the off-angle. The inclination angle due to the off-angle is an angle with respect to the normal direction Z when the normal direction Z is 0°. The first side surface 205A and the second side surface 205B may form inclined surfaces extending along the c-axis direction (

[0001] direction) of the SiC single crystal with respect to the normal direction Z.

[0201] The inclination angle due to the off-angle is approximately equal to the off-angle. The inclination angle due to the off-angle may be more than 0° and 10° or less (preferably 2° or more and 4.5° or less). Since the third side surface 205C and the fourth side surface 205D extend in the off direction (a-axis direction), they do not have an inclination angle due to the off-angle. The third side surface 205C and the fourth side surface 205D extend planar in the second direction Y (a-axis direction) and the normal direction Z. Specifically, the third side surface 205C and the fourth side surface 205D are formed substantially perpendicular to the first main surface 203 and the second main surface 204.

[0202] Referring to FIGS. 15 and 16, in this form, the first main surface 203 has an active surface 206, an outer surface 207, and a boundary side-surface 208. The active surface 206, the outer surface 207, and the boundary side-surface 208 demarcate an active mesa 209 on the first main surface 203.

[0203] The active surface 206 is a surface on which a MISFET as an example of a functional device is formed. The active surface 206 is formed at an interval inward from the periphery of the first main surface 203 (the first to fourth side surfaces 205A to 205D). Specifically, the active surface 206 is formed in a rectangular shape having four sides parallel to the periphery of the first main surface 203 in plan view (specifically, a rectangular shape extending in the second direction Y). The active surface 206 has a flat surface extending in the first direction X and the second direction Y.

[0204] The outer surface 207 is located outside the active surface 206 and is formed in a strip shape extending along the active surface 206 in a plan view. Specifically, the outer surface 207 is formed in an annular shape (specifically, a square annular shape) surrounding the active surface 206 in a plan view. The outer surface 207 is recessed with respect to the active surface 206 in the thickness direction of the SiC chip 202 (the second main surface 204 side) and is located on the second main surface 204 side with respect to the active surface 206.

[0205] The outer surface 207 has a flat surface extending in the first direction X and the second direction Y and communicates with the periphery of the first main surface 203 (the first to fourth side surfaces 205A to 205D). The outer surface 207 extends substantially parallel to the active surface 206. With respect to the normal direction Z, the depth of the outer surface 207 with respect to the active surface 206 may be 0.5 μm or more and 10 μm or less. The depth of the outer surface 207 is preferably 5 μm or less.

[0206] The boundary side surface 208 extends in the normal direction Z and connects the active surface 206 and the outer surface 207. The boundary side surface 208 has a rectangular shape (specifically, a rectangular shape) having four sides parallel to the periphery of the first main surface 203 in a plan view. That is, the boundary side surface 208 is formed by the a-plane and m-plane of the SiC polycrystal.

[0207] The boundary side surface 208 may be formed substantially perpendicular to the active surface 206 and the outer surface 207. In this case, on the first main surface 203, a square columnar active pedestal 209 is defined by the active surface 206, the outer surface 207, and the boundary side surface 208. The boundary side surface 208 may be inclined obliquely downward from the active surface 206 toward the outer surface 207.

[0208] In this case, on the first main surface 203, a square frustum-shaped active pedestal 209 is defined by the active surface 206, the outer surface 207, and the boundary side surface 208. The inclination angle of the boundary side surface 208 may be more than 90° and 135° or less. The inclination angle of the boundary side surface 208 is the angle formed between the boundary side surface 208 and the active surface 206 within the SiC chip 202. The inclination angle of the boundary side surface 208 is preferably 95° or less.

[0209] The SiC semiconductor device 201 includes an n-type (first conductivity type) first semiconductor region 210 formed in the surface layer portion of the second main surface 204 of the SiC chip 202. The first semiconductor region 210 has an n-type impurity concentration that is substantially constant in the thickness direction. The n-type impurity concentration of the first semiconductor region 210 is 1×10 18 cm -3 or more and may be 1×10 21 cm -3 or less. The first semiconductor region 210 forms the drain of the MISFET. The first semiconductor region 210 may be referred to as the drain region.

[0210] The first semiconductor region 210 is formed in the surface layer portion of the second main surface 204 at a distance from the outer surface 207 toward the second main surface 204 side. The first semiconductor region 210 is formed over the entire surface layer portion of the second main surface 204 and is exposed from the second main surface 204 and the first to fourth side surfaces 205A to 205D. That is, the first semiconductor region 210 has a part of the second main surface 204 and the first to fourth side surfaces 205A to 205D.

[0211] The thickness of the first semiconductor region 210 may be 5 μm or more and 300 μm or less. The thickness of the first semiconductor region 210 is typically 50 μm or more and 250 μm or less. The thickness of the first semiconductor region 210 is adjusted by grinding the second main surface 204. In this form, the first semiconductor region 210 is formed of an n-type semiconductor substrate (SiC substrate).

[0212] The SiC semiconductor device 201 includes an n-type second semiconductor region 211 formed in the surface layer portion of the first main surface 203 of the SiC chip 202. The second semiconductor region 211 has an n-type impurity concentration that is less than the n-type impurity concentration of the first semiconductor region 210. The n-type impurity concentration of the second semiconductor region 211 is 1×10 15 cm -3 or more and 1×10 18 cm -3The following may be applicable. The second semiconductor region 211 is electrically connected to the first semiconductor region 210 and forms the drain of the MISFET together with the first semiconductor region 210. The second semiconductor region 211 may be referred to as a drift region.

[0213] The second semiconductor region 211 is formed over the entire surface layer portion of the first main surface 203 and is exposed from the first main surface 203 and the first to fourth side surfaces 205A to 205D. Specifically, the second semiconductor region 211 is exposed from the active surface 206, the outer surface 207, and the boundary side surface 208. That is, the second semiconductor region 211 has a part of the first main surface 203 and the first to fourth side surfaces 205A to 205D. The thickness of the second semiconductor region 211 may be 5 μm or more and 20 μm or less. The thickness of the second semiconductor region 211 is the thickness with reference to the active surface 206. In this form, the second semiconductor region 211 is formed of an n-type epitaxial layer (SiC epitaxial layer).

[0214] The second semiconductor region 211 preferably has a concentration gradient in which the n-type impurity concentration increases (specifically, gradually increases) from the first semiconductor region 210 side toward the first main surface 203. That is, the second semiconductor region 211 preferably has a relatively low-concentration first concentration region 212 (low-concentration region) located on the first semiconductor region 210 side with respect to the outer surface 207, and a second concentration region 213 (high-concentration region) located on the first main surface 203 side with respect to the first concentration region 212 and having a higher concentration than the first concentration region 212.

[0215] The first concentration region 212 is located on the first semiconductor region 210 side with respect to the outer surface 207. The second concentration region 213 is located on the first main surface 203 side with respect to the first concentration region 212 and is exposed from the active surface 206, the outer surface 207, and the boundary side surface 208. The n-type impurity concentration of the first concentration region 212 is 1×10 15 cm -3 or more and 1×10 17 cm -3 or less. The n-type impurity concentration of the second concentration region 213 is 1×10 16 cm -3 or more and 1×10 18 cm -3It may be as follows.

[0216] The SiC semiconductor device 201 includes an n-type third semiconductor region 214 (concentration transition region) interposed between a first semiconductor region 210 and a second semiconductor region 211 in the SiC chip 202. The third semiconductor region 214 has a concentration gradient in which the n-type impurity concentration decreases (specifically, gradually decreases) from the n-type impurity concentration of the first semiconductor region 210 toward the n-type impurity concentration of the second semiconductor region 211. The third semiconductor region 214 is electrically connected to the first semiconductor region 210 and the second semiconductor region 211, and forms a drain of a MISFET together with the first semiconductor region 210 and the second semiconductor region 211. The third semiconductor region 214 may be referred to as a buffer region.

[0217] The third semiconductor region 214 is interposed across the entire area between the first semiconductor region 210 and the second semiconductor region 211, and is exposed from the first to fourth side surfaces 205A to 205D. That is, the third semiconductor region 214 has a part of the first to fourth side surfaces 205A to 205D. The thickness of the third semiconductor region 214 may be 1 μm or more and 10 μm or less. In this form, the third semiconductor region 214 is formed by an n-type epitaxial layer (SiC epitaxial layer).

[0218] Referring to FIGS. 13 and 14, the SiC semiconductor device 201 includes a trench insulated gate type MISFET formed on the active surface 206. Specifically, the SiC semiconductor device 201 includes a plurality of first trench structures 220 formed on the active surface 206. The first trench structure 220 may be referred to as a trench gate structure. The plurality of first trench structures 220 form a gate of the MISFET.

[0219] The plurality of first trench structures 220 are formed on the active surface 206 at intervals inward from the boundary side surface 208. The plurality of first trench structures 220 are each formed in a strip shape (rectangular shape) extending in a first direction X in plan view, and are formed at intervals in a second direction Y. Thereby, the plurality of first trench structures 220 are formed in a stripe shape extending in the first direction X in plan view.

[0220] The plurality of first trench structures 220 preferably extend in the first direction X so as to cross a line passing through the central portion of the active surface 206 in the second direction Y in plan view. The distance between two adjacent first trench structures 220 may be 0.4 μm or more and 5 μm or less. The distance between two adjacent first trench structures 220 is preferably 0.8 μm or more and 3 μm or less.

[0221] Each first trench structure 220 includes side walls and a bottom wall. The portion forming the long side among the side walls of each first trench structure 220 is formed by the a-plane of the SiC single crystal. The portion forming the short side among the side walls of each first trench structure 220 is formed by the m-plane of the SiC single crystal. The bottom wall of each first trench structure 220 is formed by the c-plane of the SiC single crystal. The bottom wall of each first trench structure 220 is preferably formed in a curved shape toward the second main surface 204. Of course, the bottom wall of each first trench structure 220 may have a flat surface parallel to the active surface 206.

[0222] Each first trench structure 220 is formed at a distance from the bottom of the second semiconductor region 211 toward the active surface 206 side, and faces the first semiconductor region 210 (third semiconductor region 214) with a part of the second semiconductor region 211 interposed therebetween. That is, the side walls and the bottom wall of each first trench structure 220 are in contact with the second semiconductor region 211. Each first trench structure 220 is formed at a distance from the bottom of the second concentration region 213 toward the active surface 206 side.

[0223] Each first trench structure 220 is further formed at a distance from the depth position of the outer surface 207 toward the active surface 206 side with respect to the normal direction Z. That is, each first trench structure 220 is formed in the second concentration region 213 and faces the first concentration region 212 with a part of the second concentration region 213 interposed therebetween. Each first trench structure 220 may be formed in a vertical shape having a substantially constant opening width. Each first trench structure 220 may be formed in a tapered shape having an opening width that narrows toward the bottom wall.

[0224] Each first trench structure 220 has a first width W1 and a first depth D1. The first width W1 is the width in a direction orthogonal to the direction in which each first trench structure 220 extends (i.e., the second direction Y). The first width W1 may be 0.1 μm or more and 3 μm or less. The first width W1 is preferably 0.5 μm or more and 1.5 μm or less.

[0225] The first depth D1 may be 0.1 μm or more and 3 μm or less. The first depth D1 is preferably 0.5 μm or more and 2 μm or less. The aspect ratio D1 / W1 of each first trench structure 220 is preferably 1 or more and 5 or less. The aspect ratio D1 / W1 is particularly preferably 1.5 or more. The aspect ratio D1 / W1 is the ratio of the first depth D1 to the first width W1.

[0226] The plurality of first trench structures 220 each include a gate trench 221, a gate insulating film 222, and a gate electrode 223. Hereinafter, one first trench structure 220 will be described. The gate trench 221 forms the side walls and the bottom wall of the first trench structure 220. The side walls and the bottom wall form the wall surfaces (inner wall and outer wall) of the gate trench 221.

[0227] The opening edge portion of the gate trench 221 slopes obliquely downward from the active surface 206 toward the gate trench 221. The opening edge portion is the connection portion between the active surface 206 and the side wall of the gate trench 221. In this form, the opening edge portion is formed in a curved shape that is recessed toward the SiC chip 202. The opening edge portion may be formed in a convex curved shape toward the gate trench 221.

[0228] The gate insulating film 222 is formed in a film shape on the inner wall of the gate trench 221 and partitions a recessed space within the gate trench 221. The gate insulating film 222 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this form, the gate insulating film 222 has a single-layer structure made of a silicon oxide film.

[0229] The gate insulating film 222 includes a first portion 224, a second portion 225, and a third portion 226. The first portion 224 covers the sidewall of the gate trench 221. The second portion 225 covers the bottom wall of the gate trench 221. The third portion 226 covers the opening edge portion. In this form, the third portion 226 bulges in a curved shape toward the inside of the gate trench 221 at the opening edge portion.

[0230] The thickness of the first portion 224 may be 10 nm or more and 100 nm or less. The second portion 225 may have a thickness exceeding that of the first portion 224. The thickness of the second portion 225 may be 50 nm or more and 200 nm or less. The third portion 226 has a thickness exceeding that of the first portion 224. The thickness of the third portion 226 may be 50 nm or more and 200 nm or less. Of course, a gate insulating film 222 having a uniform thickness may be formed.

[0231] The gate electrode 223 is embedded in the gate trench 221 with the gate insulating film 222 interposed therebetween. A gate potential is applied to the gate electrode 223. The gate electrode 223 is preferably made of conductive polysilicon. In this form, the gate electrode 223 includes n-type polysilicon doped with n-type impurities. The gate electrode 223 has an electrode surface exposed from the gate trench 221. The electrode surface of the gate electrode 223 is formed in a curved shape recessed toward the bottom wall of the gate trench 221 and is narrowed by the third portion 226 of the gate insulating film 222.

[0232] The SiC semiconductor device 201 includes a plurality of second trench structures 230 formed on the active surface 206. The second trench structure 230 may be referred to as a trench source structure. The plurality of second trench structures 230 form a breakdown voltage reinforcement structure of the MISFET. The plurality of second trench structures 230 are respectively formed in regions between two adjacent first trench structures 220 on the active surface 206.

[0233] The plurality of second trench structures 230 are formed in the active surface 206 at intervals inward from the boundary side surface 208. The plurality of second trench structures 230 are each formed in a strip shape extending in the first direction X in plan view, and are formed at intervals in the second direction Y in a manner of sandwiching one first trench structure 220. Thereby, the plurality of second trench structures 230 are formed in a stripe shape extending in the first direction X in plan view.

[0234] The plurality of second trench structures 230 preferably extend in the first direction X so as to cross a line passing through the central portion of the active surface 206 in the second direction Y in plan view. The length of each second trench structure 230 in the first direction X is preferably less than the length of each first trench structure 220 in the first direction X. The distance between two adjacent second trench structures 230 may be 0.4 μm or more and 5 μm or less. The distance between two adjacent second trench structures 230 is preferably 0.8 μm or more and 3 μm or less.

[0235] Each second trench structure 230 includes side walls and a bottom wall. The portion forming the long side among the side walls of each second trench structure 230 is formed by the a-plane of the SiC single crystal. The portion forming the short side among the side walls of each second trench structure 230 is formed by the m-plane of the SiC single crystal. The bottom wall of each second trench structure 230 is formed by the c-plane of the SiC single crystal. The bottom wall of each second trench structure 230 is preferably formed in a curved shape toward the second main surface 204. Of course, the bottom wall of each second trench structure 230 may have a flat surface parallel to the active surface 206.

[0236] Each second trench structure 230 is formed at a distance from the bottom of the second semiconductor region 211 toward the active surface 206 side, and faces the first semiconductor region 210 (third semiconductor region 214) with a part of the second semiconductor region 211 interposed therebetween. That is, the side walls and the bottom wall of each second trench structure 230 are in contact with the second semiconductor region 211. Specifically, each second trench structure 230 is formed at a distance from the bottom of the second concentration region 213 toward the active surface 206 side. That is, each second trench structure 230 is formed in the second concentration region 213 and faces the first concentration region 212 with a part of the second concentration region 213 interposed therebetween.

[0237] In this form, each second trench structure 230 is formed deeper than each first trench structure 220. That is, the bottom wall of each second trench structure 230 is located on the bottom side of the second semiconductor region 211 (second concentration region 213) with respect to the bottom wall of each first trench structure 220. Specifically, the bottom wall of each second trench structure 230 is formed at a depth position between the outer surface 207 and the bottom wall of each first trench structure 220 with respect to the normal direction Z.

[0238] In this case, it is preferable that the bottom wall of each second trench structure 230 is located substantially on the same plane as the outer surface 207. That is, it is preferable that each second trench structure 230 is formed at substantially the same depth as the outer surface 207. Each second trench structure 230 may be formed in a vertical shape having a substantially constant opening width. Each second trench structure 230 may be formed in a tapered shape having an opening width that narrows toward the bottom wall.

[0239] Each second trench structure 230 has a second width W2 and a second depth D2. The second width W2 is the width in a direction orthogonal to the direction in which each second trench structure 230 extends (that is, the second direction Y). The second width W2 may be 0.1 μm or more and 3 μm or less. The second width W2 is preferably 0.5 μm or more and 1.5 μm or less. In this form, the second width W2 is substantially equal to the first width W1 of each first trench structure 220. The second width W2 preferably has a value within a range of ±10% of the value of the first width W1.

[0240] The second depth D2 is preferably 1.5 times or more and 3 times or less the first depth D1 of the first trench structure 220. The second depth D2 may be 0.5 μm or more and 10 μm or less. The second depth D2 is preferably 5 μm or less. The aspect ratio D2 / W2 of each second trench structure 230 is preferably 1 or more and 5 or less. The aspect ratio D2 / W2 is particularly preferably 2 or more. The aspect ratio D2 / W2 is the ratio of the second depth D2 to the second width W2.

[0241] The plurality of second trench structures 230 each include a source trench 231, a source insulating film 232, and a source electrode 233. Hereinafter, one second trench structure 230 will be described. The source trench 231 forms the side wall and the bottom wall of the second trench structure 230. The side wall and the bottom wall form the wall surfaces (inner wall and outer wall) of the source trench 231.

[0242] The opening edge portion of the source trench 231 is inclined obliquely downward from the first main surface 203 toward the source trench 231. The opening edge portion is the connection portion between the first main surface 203 and the side wall of the source trench 231. In this form, the opening edge portion is formed in a curved shape recessed toward the SiC chip 202. The opening edge portion may be formed in a curved shape toward the inside of the source trench 231.

[0243] The source insulating film 232 is formed in a film shape on the inner wall of the source trench 231 and partitions a recessed space in the source trench 231. The source insulating film 232 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this form, the source insulating film 232 has a single-layer structure made of a silicon oxide film.

[0244] The source insulating film 232 includes a first portion 234 and a second portion 235. The first portion 234 covers the side wall of the source trench 231. The second portion 235 covers the bottom wall of the source trench 231. The thickness of the first portion 234 may be 10 nm or more and 100 nm or less. The second portion 235 may have a thickness exceeding the thickness of the first portion 234. The thickness of the second portion 235 may be 50 nm or more and 200 nm or less.

[0245] The source electrode 233 is embedded in the source trench 231 with the source insulating film 232 interposed therebetween. A source potential (for example, a reference potential) is applied to the source electrode 233. The source electrode 233 is preferably made of the same material as the gate electrode 223. That is, the source electrode 233 is preferably made of conductive polysilicon. In this form, the source electrode 233 includes n-type polysilicon doped with n-type impurities.

[0246] The source electrode 233 has an electrode surface exposed from the source trench 231. The electrode surface of the source electrode 233 is formed in a curved shape recessed toward the bottom wall of the source trench 231. A part of the side wall of the source electrode 233 may be exposed from the source insulating film 232 at the open end of the source trench 231.

[0247] The SiC semiconductor device 201 includes a p-type body region 250 formed in the surface layer portion of the active surface 206. The body region 250 is formed over the entire surface layer portion of the active surface 206. The p-type impurity concentration of the body region 250 may be 1×10 16 cm -3 or more and 1×10 18 cm -3 or less.

[0248] The body region 250 is formed on the active surface 206 side with respect to the bottom wall of the first trench structure 220. The body region 250 covers the side walls of the first trench structure 220 and the second trench structure 230. The body region 250 faces the gate electrode 223 with the gate insulating film 222 interposed therebetween.

[0249] The SiC semiconductor device 201 includes a plurality of n-type source regions 251 formed in regions between the adjacent first trench structure 220 and second trench structure 230 in the surface layer portion of the body region 250. Each source region 251 has an n-type impurity concentration exceeding the n-type impurity concentration of the second semiconductor region 211 (specifically, the second concentration region 213). The n-type impurity concentration of each source region 251 is 1×10 18 cm -3 or more and may be 1×10 21 cm -3 or less.

[0250] Each source region 251 is formed on the active surface 206 side with respect to the bottom of the body region 250. Each source region 251 covers the side wall of the first trench structure 220 and faces the gate electrode 223 and the first low-resistance layer 241 with the gate insulating film 222 interposed therebetween. Each source region 251 forms a channel with the second semiconductor region 211 (the second concentration region 213) in the body region 250 for the MISFET.

[0251] The SiC semiconductor device 201 includes a plurality of p-type contact regions 252 formed along the plurality of second trench structures 230 in the surface layer portion of the active surface 206. Each contact region 252 has a p-type impurity concentration exceeding the p-type impurity concentration of the body region 250. The p-type impurity concentration of each contact region 252 is 1×10 18 cm -3 or more and may be 1×10 21 cm -3 or less.

[0252] The plurality of contact regions 252 are formed in a one-to-many correspondence with respect to each second trench structure 230 in plan view. The plurality of contact regions 252 are formed at intervals along each second trench structure 230 in plan view and partially cover each second trench structure 230. The plurality of contact regions 252 are formed at intervals from the first trench structure 220 toward the second trench structure 230 side, exposing the first trench structure 220.

[0253] Each contact region 252 is formed at a distance from the bottom of the second semiconductor region 211 (second concentration region 213) toward the active surface 206 side, and faces the first semiconductor region 210 (third semiconductor region 214) with a part of the second semiconductor region 211 interposed therebetween. Each contact region 252 covers the side walls and the bottom wall of each second trench structure 230 in the second semiconductor region 211 (second concentration region 213).

[0254] The SiC semiconductor device 201 includes a plurality of p-type well regions 253 formed in the surface layer portion of the active surface 206. Each well region 253 has a p-type impurity concentration less than the p-type impurity concentration of each contact region 252. The p-type impurity concentration of each well region 253 preferably exceeds the p-type impurity concentration of the body region 250. The p-type impurity concentration of each well region 253 is 1×10 16 cm -3 or more and may be 1×10 18 cm -3 or less.

[0255] The plurality of well regions 253 are formed in a one-to-one correspondence with respect to each second trench structure 230. Each well region 253 is formed in a strip shape extending along each second trench structure 230 in plan view. Each contact region 252 is formed at a distance from the first trench structure 220 toward the second trench structure 230 side, exposing the first trench structure 220.

[0256] Each well region 253 is formed at a distance from the bottom of the second semiconductor region 211 (second concentration region 213) toward the active surface 206 side, and faces the first semiconductor region 210 (third semiconductor region 214) with a part of the second semiconductor region 211 interposed therebetween. That is, each well region 253 is electrically connected to the second semiconductor region 211 (second concentration region 213). Each well region 253 covers the side walls and the bottom wall of each second trench structure 230.

[0257] The plurality of well regions 253 form a pn junction with the second semiconductor region 211 (second concentration region 213) and expand the depletion layer toward the first trench structure 220 (gate trench 221). The plurality of well regions 253 bring the trench insulated gate type MISFET closer to the structure of the pn junction diode and relax the electric field in the SiC chip 202.

[0258] The plurality of well regions 253 are preferably formed such that the depletion layer overlaps the bottom wall of the first trench structure 220. The second concentration region 213 intervening between the plurality of well regions 253 reduces the JFET (Junction Field Effect Transistor) resistance. The second concentration region 213 located directly below the plurality of well regions 253 reduces the current spreading resistance. The first concentration region 212 increases the breakdown voltage of the SiC chip 202 in such a structure.

[0259] The SiC semiconductor device 201 includes a plurality of p-type gate well regions 254 formed in regions along the wall surfaces at both ends of the plurality of first trench structures 220 in the surface layer portion of the active surface 206. Each gate well region 254 has a p-type impurity concentration less than the p-type impurity concentration of each contact region 252. The p-type impurity concentration of each gate well region 254 preferably exceeds the p-type impurity concentration of the body region 250. The p-type impurity concentration of each gate well region 254 may be 1×10 16 cm -3 or more and 1×10 18 cm -3 or less. The p-type impurity concentration of each gate well region 254 is preferably substantially equal to the p-type impurity concentration of each well region 253.

[0260] Each gate well region 254 is formed in a strip shape extending along each first trench structure 220 in plan view. Each gate well region 254 is formed at a distance from the second trench structure 230 toward the first trench structure 220, exposing the portion of the first trench structure 220 along the source region 251. Each gate well region 254 covers the side wall and the bottom wall of each first trench structure 220.

[0261] Each gate well region 254 is formed at a distance from the bottom of the second semiconductor region 211 (second concentration region 213) toward the first main surface 3 side, and faces the first semiconductor region 210 (third semiconductor region 214) with a part of the second semiconductor region 211 interposed therebetween. In this form, each gate well region 254 is formed in the second concentration region 213 and faces the first concentration region 212 with a part of the second concentration region 213 interposed therebetween. Each gate well region 254 is connected to the body region 250 at a portion covering the side wall of each first trench structure 220.

[0262] The bottoms of the plurality of gate well regions 254 are located on the bottom wall side of the first trench structure 220 with respect to the bottoms of the plurality of well regions 253. It is preferable that the thickness of the portion of each gate well region 254 covering the bottom wall of each first trench structure 220 exceeds the thickness of the portion of each gate well region 254 covering the side wall of each first trench structure 220. The thickness of the portion of each gate well region 254 covering the side wall of the first trench structure 220 is the thickness in the normal direction of the side wall of the first trench structure 220. The thickness of the portion of each gate well region 254 covering the bottom wall of the first trench structure 220 is the thickness in the normal direction of the bottom wall of the first trench structure 220.

[0263] The portions covering the bottom walls of the plurality of first trench structures 220 at the bottoms of the plurality of gate well regions 254 are formed at substantially the same depth. The plurality of gate well regions 254 form a pn junction with the second semiconductor region 211 (second concentration region 213) and expand the depletion layer toward the first trench structure 220 and the second trench structure 230. The plurality of gate well regions 254 bring the trench insulated gate type MISFET closer to the structure of a pn junction diode and relax the electric field in the SiC chip 202.

[0264] Referring to FIGS. 15 and 16, the SiC semiconductor device 201 includes trench termination structures 255 formed at the ends on the first side surface 205A side and the ends on the second side surface 205B side at the active surface 206, respectively. The trench termination structure 255 includes a plurality of second trench structures 230 and does not include the first trench structure 220. Further, the trench termination structure 255 includes a well region 253 and does not include a contact region 252.

[0265] In the trench termination structure 255, the plurality of second trench structures 230 are each formed in a strip shape extending in the first direction X and are formed with a space in the second direction Y. In the trench termination structure 255, the source electrode 233 of each second trench structure 230 is formed in an electrically floating state. The well region 253 of the trench termination structure 255 also covers the boundary side surface 208 in addition to the plurality of second trench structures 230.

[0266] The SiC semiconductor device 201 includes a p-type outer contact region 260 formed in the surface layer portion of the outer surface 207. The outer contact region 260 may have a p-type impurity concentration of 1×10 18 cm -3 or more and 1×10 21 cm -3 or less. The outer contact region 260 has a p-type impurity concentration exceeding that of the p-type impurity concentration of the body region 250. The p-type impurity concentration of the outer contact region 260 is preferably substantially equal to the p-type impurity concentration of the contact region 252.

[0267] The outer contact region 260 is formed in a region between the boundary side surface 208 and the periphery of the first main surface 203 (the first to fourth side surfaces 205A to 205D) on the outer surface 207. The outer contact region 260 extends in a strip shape along the active surface 206 (the boundary side surface 208) in plan view. In this form, the outer contact region 260 is formed in an annular shape surrounding the active surface 206 in plan view. Specifically, the outer contact region 260 is formed in a square annular shape having four sides parallel to the active surface 206 in plan view.

[0268] The outer contact region 260 is formed at a distance from the bottom of the second semiconductor region 211 to the outer surface 207. Specifically, the outer contact region 260 is formed at a distance from the bottom of the second concentration region 213 to the outer surface 207. The entire outer contact region 260 is located on the bottom side of the second semiconductor region 211 with respect to the bottom wall of each first trench structure 220. The bottom of the outer contact region 260 is located on the bottom side of the second semiconductor region 211 with respect to the bottom wall of each second trench structure 230.

[0269] Preferably, the bottom of the outer contact region 260 is formed at a depth position substantially equal to the bottom of each contact region 252. The outer contact region 260 forms a pn junction with the second semiconductor region 211 (specifically, the second concentration region 213). Thereby, a pn junction diode is formed with the outer contact region 260 as the anode and the second semiconductor region 211 as the cathode. The outer contact region 260 may be referred to as an anode region.

[0270] The SiC semiconductor device 201 includes a p-type outer well region 261 formed in the surface layer portion of the outer surface 207. The p-type impurity concentration of the outer well region 261 may be 1×10 16 cm -3 or more and 1×10 18 cm -3 or less. The outer well region 261 has a p-type impurity concentration lower than the p-type impurity concentration of the outer contact region 260. Preferably, the p-type impurity concentration of the outer well region 261 is substantially equal to the p-type impurity concentration of the well region 253.

[0271] The outer well region 261 is formed in a region between the boundary side surface 208 and the outer contact region 260 in a plan view. In this form, the outer well region 261 is formed over the entire region between the boundary side surface 208 and the outer contact region 260, and is connected to the well region 253 at the boundary side surface 208. The outer well region 261 extends in a strip shape along the active surface 206 (boundary side surface 208) in a plan view. In this form, the outer well region 261 is formed in an endless shape (a square ring shape in this form) surrounding the active surface 206 (boundary side surface 208) in a plan view.

[0272] The outer well region 261 is formed deeper than the outer contact region 260. The outer well region 261 is formed at a distance from the bottom of the second semiconductor region 211 to the outer side surface 207. Specifically, the outer well region 261 is formed at a distance from the bottom of the second concentration region 213 to the outer side surface 207. The entire outer well region 261 is located on the bottom side of the second semiconductor region 211 with respect to the bottom wall of each first trench structure 220.

[0273] The bottom of the outer well region 261 is located on the bottom side of the second semiconductor region 211 with respect to the bottom wall of each second trench structure 230. It is preferable that the bottom of the outer well region 261 is formed at a depth position substantially equal to the bottom of each well region 253. The outer well region 261 forms a pn junction with the second semiconductor region 211 (specifically, the second concentration region 213) together with the outer contact region 260.

[0274] The SiC semiconductor device 201 includes at least one (preferably one or more and 20 or less) p-type field region 262 formed in a region between the outer contact region 260 and the periphery of the first main surface 203 (the first to fourth side surfaces 205A to 205D) in the surface layer portion of the outer side surface 207. The field region 262 relaxes an electric field on the outer side surface 207. The number, width, depth, p-type impurity concentration, etc. of the field region 262 can take various values according to the electric field to be relaxed. The p-type impurity concentration of the field region 262 is 1×1015 cm -3 1×10 or more 18 cm -3 It may be less than this value.

[0275] In this embodiment, the SiC semiconductor device 201 includes five field regions 262. The five field regions 262 include a first field region 262A, a second field region 262B, a third field region 262C, a fourth field region 262D, and a fifth field region 262E. The first to fifth field regions 262A to 262E are formed at intervals in this order from the outer contact region 260 side toward the peripheral side of the outer surface 207.

[0276] Each field region 262 is formed in a strip shape extending along the active surface 206 in a plan view. Each field region 262 is formed in an annular shape surrounding the active surface 206 in a plan view. Specifically, each field region 262 is formed in a square annular shape having four sides parallel to the active surface 206 (boundary side surface 208) in a plan view. Each field region 262 may be referred to as a FLR (Field Limiting Ring) region.

[0277] Each field region 262 is formed deeper than the outer contact region 260. Each field region 262 is formed at an interval from the bottom of the second semiconductor region 211 to the outer surface 207. Specifically, each field region 262 is formed at an interval from the bottom of the second concentration region 213 to the outer surface 207. The whole of each field region 262 is located on the bottom side of the second semiconductor region 211 with respect to the bottom wall of each first trench structure 220. The bottom of each field region 262 is located on the bottom side of the second semiconductor region 211 with respect to the bottom wall of each second trench structure 230.

[0278] In this form, the innermost first field region 262A is connected to the outer contact region 260. The innermost first field region 262A forms a pn junction with the second semiconductor region 211 (specifically, the second concentration region 213) together with the outer contact region 260. On the other hand, the second to fifth field regions 262B to 262E are formed in an electrically floating state.

[0279] Referring to FIGS. 14 to 16, the SiC semiconductor device 201 includes a main surface insulating film 270 that covers the first main surface 203. Specifically, the main surface insulating film 270 is formed in a film shape along the active surface 206, the outer surface 207, and the boundary side surface 208. The main surface insulating film 270 includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. In this form, the main surface insulating film 270 has a single-layer structure made of a silicon oxide film.

[0280] The main surface insulating film 270 exposes a plurality of second trench structures 230, a plurality of source regions 251, and a plurality of contact regions 252 on the active surface 206. The main surface insulating film 270 covers the opening edge portions of the plurality of first trench structures 220 and is continuous with the gate insulating film 222 of each first trench structure 220. The main surface insulating film 270 is formed at an interval inward from the periphery of the outer surface 207 (the first to fourth side surfaces 205A to 205D) and has a first peripheral wall 271 that exposes the peripheral portion of the outer surface 207. The thickness of the main surface insulating film 270 may be 50 nm or more and 500 nm or less.

[0281] The SiC semiconductor device 201 includes a sidewall structure 272 that covers the boundary side surface 208 on the main surface insulating film 270. The sidewall structure 272 is formed as a step relaxation structure that relaxes a step formed between the active surface 206 and the outer surface 207. The sidewall structure 272 is formed in a strip shape extending along the boundary side surface 208 in plan view.

[0282] The sidewall structure 272 is specifically formed self-aligned with respect to the active surface 206 and is formed in an annular shape (specifically, a square annular shape) surrounding the active surface 206 in plan view. The sidewall structure 272 has an outer surface that slopes obliquely downward from the active surface 206 toward the outer surface 207. The outer surface of the sidewall structure 272 may be formed in a curved shape protruding toward the side opposite to the boundary side surface 208, or may be formed in a curved shape recessed toward the boundary side surface 208 side.

[0283] The sidewall structure 272 includes either one or both of a conductor and an insulator. In this form, the sidewall structure 272 includes conductive polysilicon. The sidewall structure 272 is preferably made of the same conductive material as the gate electrode 223 and / or the source electrode 233. The sidewall structure 272 may include n-type polysilicon.

[0284] The SiC semiconductor device 201 includes a first inorganic insulating film 280 formed on the main surface insulating film 270 as an example of a coating target. The first inorganic insulating film 280 may be referred to as an interlayer insulating film. The first inorganic insulating film 280 may have a laminated structure including a plurality of insulating films, or may have a single-layer structure composed of a single insulating film. The first inorganic insulating film 280 preferably includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The first inorganic insulating film 280 may have a laminated structure including a plurality of silicon oxide films, a laminated structure including a plurality of silicon nitride films, or a laminated structure including a plurality of silicon oxynitride films.

[0285] The first inorganic insulating film 280 may have a laminated structure in which at least two of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film are laminated in an arbitrary order. The first inorganic insulating film 280 may have a single-layer structure composed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In this form, the first inorganic insulating film 280 has a laminated structure in which a plurality of silicon oxide films are laminated.

[0286] Specifically, the first inorganic insulating film 280 has a laminated structure including an NSG (Nondoped Silicate Glass) film and a PSG (Phosphor Silicate Glass) film laminated in this order from the main surface insulating film 270 side. The NSG film is made of a silicon oxide film without added impurities. The PSG film is made of a silicon oxide film added with phosphorus. The thickness of the NSG film may be 10 nm or more and 300 nm or less. The thickness of the PSG film may be 50 nm or more and 500 nm or less. The thickness of the first inorganic insulating film 280 preferably exceeds the thickness of the main surface insulating film 270.

[0287] The first inorganic insulating film 280 is formed in a film shape on the main surface insulating film 270 along the active surface 206, the outer surface 207, and the boundary side surface 208, and covers the active surface 206, the outer surface 207, and the boundary side surface 208 with the main surface insulating film 270 interposed therebetween. The first inorganic insulating film 280 covers the sidewall structure 272 between the active surface 206 and the outer surface 207.

[0288] The first inorganic insulating film 280 has a second peripheral end wall 281 formed at an interval inward from the periphery of the outer surface 207 (the first to fourth side surfaces 205A to 205D), exposing the peripheral portion of the outer surface 207. The second peripheral end wall 281 of the first inorganic insulating film 280 and the first peripheral end wall 271 of the main surface insulating film 270 define a notch opening 282 that exposes the peripheral portion of the outer surface 207.

[0289] The first inorganic insulating film 280 has a plurality of gate contact openings 283 that respectively expose a plurality of first trench structures 220 on the active surface 206. The plurality of gate contact openings 283 expose the plurality of first trench structures 220 in a one-to-one correspondence. Specifically, the plurality of gate contact openings 283 are respectively formed on both end sides of the plurality of first trench structures 220, exposing the corresponding gate electrodes 223.

[0290] The first inorganic insulating film 280 has a plurality of source contact openings 284 that expose the plurality of second trench structures 230 on the active surface 206. The plurality of source contact openings 284 are respectively formed in a one-to-one correspondence with the plurality of second trench structures 230. The plurality of source contact openings 284 expose the corresponding source electrodes 233, source regions 251, and contact regions 252, respectively. Each source contact opening 284 may be formed in a strip shape extending along each second trench structure 230.

[0291] The first inorganic insulating film 280 includes at least one outer contact opening 285 that exposes the outer contact region 260 on the outer surface 207. In this form, the first inorganic insulating film 280 includes one outer contact opening 285. The outer contact opening 285 is formed in a strip shape extending along the outer contact region 260 in a plan view. The outer contact opening 285 is formed in an annular shape (specifically, a square annular shape) extending along the outer contact region 260 in a plan view.

[0292] The SiC semiconductor device 201 includes a plurality of first main surface electrodes 300 formed on the first inorganic insulating film 280. The plurality of first main surface electrodes 300 are disposed on the active surface 206. In this form, the plurality of first main surface electrodes 300 are disposed only on the active surface 206 and not on the outer surface 207.

[0293] The plurality of first main surface electrodes 300 include a gate main surface electrode 301 disposed on a portion of the first inorganic insulating film 280 that covers the active surface 206. The gate main surface electrode 301 is electrically connected to the plurality of first trench structures 220 (gate electrodes 223) and transmits the input gate potential (gate signal) to the plurality of first trench structures 220 (gate electrodes 223). The gate potential may be 10V or more and 50V or less (for example, about 30V).

[0294] Specifically, the gate main surface electrode 301 is disposed on the peripheral portion of the active surface 206 at an interval from the boundary side surface 208 in a plan view. In this form, the gate main surface electrode 301 is disposed in a region facing the central portion of the first side surface 205A at the peripheral portion of the active surface 206 in a plan view. The gate main surface electrode 301 faces the trench termination structure 255 with the first inorganic insulating film 280 interposed therebetween and is electrically separated from the trench termination structure 255. The gate main surface electrode 301 is formed in a rectangular shape having four sides parallel to the active surface 206 in a plan view.

[0295] The gate main surface electrode 301 has a gate electrode side wall 302 located on the first inorganic insulating film 280. The gate electrode side wall 302 is formed in a tapered shape inclined obliquely downward from the main surface of the gate main surface electrode 301. In this form, the gate electrode side wall 302 is formed in a curved tapered shape curved toward the first inorganic insulating film 280. The arrangement of the gate main surface electrode 301 is arbitrary. The gate main surface electrode 301 may be disposed on any corner of the active surface 206 in a plan view.

[0296] The plurality of first main surface electrodes 300 includes a source main surface electrode 303 disposed on a portion of the first inorganic insulating film 280 covering the active surface 206 at an interval from the gate main surface electrode 301. The source main surface electrode 303 is electrically connected to a plurality of second trench structures 230 (source electrodes 233) and transmits the input source potential to the plurality of second trench structures 230 (source electrodes 233). The source potential may be a reference potential (for example, a ground potential).

[0297] Specifically, the source main surface electrode 303 is formed on the active surface 206 at a distance from the boundary side surface 208 in a plan view. In this form, the source main surface electrode 303 is formed in a rectangular shape (specifically, a rectangular shape) having four sides parallel to the active surface 206 (boundary side surface 208) in a plan view. Specifically, the source main surface electrode 303 has a concave portion 304 recessed inward so as to align with the gate main surface electrode 301 at the side along the first side surface 205A. The source main surface electrode 303 has a planar area exceeding the planar area of the gate main surface electrode 301.

[0298] The source main surface electrode 303 enters the plurality of source contact openings 284 from above the first inorganic insulating film 280 and is electrically connected to the plurality of source electrodes 233, the plurality of source regions 251, and the plurality of contact regions 252. Thereby, the source potential applied to the source main surface electrode 303 is transmitted to the plurality of source electrodes 233, the plurality of source regions 251, and the plurality of contact regions 252. The source main surface electrode 303 faces the trench termination structure 255 with the first inorganic insulating film 280 interposed therebetween at the peripheral portion of the active surface 206 and is electrically separated from the trench termination structure 255.

[0299] The source main surface electrode 303 has a source electrode side wall 305 located on the first inorganic insulating film 280. The source electrode side wall 305 is formed in a tapered shape inclined obliquely downward from the main surface of the source main surface electrode 303. In this form, the source electrode side wall 305 is formed in a curved tapered shape curved toward the first inorganic insulating film 280.

[0300] The SiC semiconductor device 201 includes a plurality of wiring electrodes 306 formed on the first inorganic insulating film 280. The plurality of wiring electrodes 306 are routed to an arbitrary region including the active surface 206 and the outer surface 207 on the first inorganic insulating film 280.

[0301] The plurality of wiring electrodes 306 includes a gate wiring electrode 307 drawn from the gate main surface electrode 301 onto a portion of the first inorganic insulating film 280 that covers the active surface 206. Specifically, the gate wiring electrode 307 is formed on the active surface 206 and not on the outer surface 207. The gate wiring electrode 307 transmits the gate potential applied to the gate main surface electrode 301 to other regions.

[0302] The gate wiring electrode 307 is drawn from the gate main surface electrode 301 to a region between the boundary side surface 208 and the source main surface electrode 303 and is formed in a strip shape extending along the boundary side surface 208. Specifically, the gate wiring electrode 307 extends in a strip shape along the boundary side surface 208 so as to face the source main surface electrode 303 from a plurality of directions in a plan view. In this form, the gate wiring electrode 307 extends in a strip shape along the boundary side surface 208 so as to face the source main surface electrode 303 from four directions in a plan view. The gate wiring electrode 307 has an opening 308 on the second side surface 205B side. The position and size of the opening 308 are arbitrary.

[0303] The gate wiring electrode 307 intersects (specifically, is orthogonal to) a plurality of first trench structures 220 in a plan view. Specifically, the gate wiring electrode 307 intersects (specifically, is orthogonal to) both ends of a plurality of first trench structures 220 in a plan view. The gate wiring electrode 307 enters a plurality of gate contact openings 283 from above the first inorganic insulating film 280 and is electrically connected to a plurality of gate electrodes 223.

[0304] Thereby, the gate potential applied to the gate main surface electrode 301 is transmitted to the plurality of first trench structures 220 via the gate wiring electrode 307. The gate wiring electrode 307 faces the trench termination structure 255 with the first inorganic insulating film 280 interposed therebetween at the peripheral portion of the active surface 206 and is electrically separated from the trench termination structure 255.

[0305] The gate wiring electrode 307 has a gate wiring sidewall 309 positioned on the first inorganic insulating film 280. The gate wiring sidewall 309 is formed in a tapered shape that slopes diagonally downward from the main surface of the gate wiring electrode 307. In this form, the gate wiring sidewall 309 is formed in a curved tapered shape that curves toward the first inorganic insulating film 280.

[0306] The plurality of wiring electrodes 306 includes a source wiring electrode 310 drawn out from the source main surface electrode 303 onto a portion of the first inorganic insulating film 280 that covers the outer surface 207. Specifically, the source wiring electrode 310 is drawn out from the source main surface electrode 303 above the active surface 206, passes through the opening 308 of the gate wiring electrode 307, and is drawn out onto the outer surface 207. The source wiring electrode 310 faces the sidewall structure 272 across the first inorganic insulating film 280 at the boundary between the active surface 206 and the outer surface 207. The source wiring electrode 310 transmits the source potential applied to the source main surface electrode 303 from the active surface 206 side to the outer surface 207 side.

[0307] The source wiring electrode 310 is drawn out onto the outer contact region 260 on the outer surface 207 side and is formed in a strip shape that extends along the outer contact region 260 in a plan view. In this form, the source wiring electrode 310 is formed in an annular shape (specifically, a square annular shape) that extends along the outer contact region 260 in a plan view. That is, the source wiring electrode 310 surrounds the gate main surface electrode 301, the source main surface electrode 303, and the gate wiring electrode 307 together in a plan view. In this form, the source wiring electrode 310 covers the outer contact region 260 and the sidewall structure 272 over the entire circumference.

[0308] The source wiring electrode 310 enters the outer contact opening 285 from above the first inorganic insulating film 280 and is electrically connected to the outer contact region 260. Thereby, the source potential applied to the source main surface electrode 303 is transmitted to the outer contact region 260 via the source wiring electrode 310.

[0309] The source wiring electrode 310 has a source wiring sidewall 311 positioned on the first inorganic insulating film 280. The source wiring sidewall 311 is formed in a tapered shape that slopes obliquely downward from the main surface of the source main surface electrode 303. In this form, the source wiring sidewall 311 is formed in a curved tapered shape that curves toward the first inorganic insulating film 280.

[0310] The plurality of first main surface electrodes 300 and the plurality of wiring electrodes 306 each have a stacked structure including a first electrode film 312 and a second electrode film 313 stacked in this order from the side of the first inorganic insulating film 280. The first electrode film 312 is formed in a film shape along the first inorganic insulating film 280. The first electrode film 312 is made of a metal barrier film. In this form, the first electrode film 312 is made of a Ti-based metal film. The first electrode film 312 includes at least one of a titanium film and a titanium nitride film.

[0311] The first electrode film 312 may have a single-layer structure made of a titanium film or a titanium nitride film. In this form, the first electrode film 312 has a stacked structure including a titanium film and a titanium nitride film stacked in this order from the side of the first main surface 203. The thickness of the first electrode film 312 may be 10 nm or more and 500 nm or less.

[0312] The second electrode film 313 is formed in a film shape along the main surface of the first electrode film 312. The first electrode film 312 is made of a Cu-based metal film or an Al-based metal film. The first electrode film 312 may include at least one of a pure Cu film (a Cu film with a purity of 99% or more), a pure Al film (an Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this form, the first electrode film 312 has a single-layer structure made of an AlCu alloy film. The thickness of the second electrode film 313 may be 0.5 μm or more and 10 μm or less. The thickness of the second electrode film 313 is preferably 2.5 μm or more and 7.5 μm or less.

[0313] The SiC semiconductor device 201 includes a second inorganic insulating film 320. The second inorganic insulating film 320 is made of an inorganic insulator having a relatively high density and has a barrier property (shielding property) against moisture (humidity). For example, the oxide of the first main surface electrode 300 (aluminum oxide in this form) degrades the electrical characteristics of the first main surface electrode 300. In addition, the oxides of the plurality of first main surface electrodes 300 are one of the factors causing partial peeling, cracks, etc. of the first main surface electrode 300 and other structures due to thermal expansion.

[0314] The second inorganic insulating film 320 shields moisture (humidity) from the outside by covering either one or both of the first inorganic insulating film 280 and the first main surface electrode 300, and protects the SiC chip 202 and the first main surface electrode 300 from oxidation. The second inorganic insulating film 320 may be referred to as a passivation film.

[0315] The second inorganic insulating film 320 may have a laminated structure including a plurality of insulating films, or may have a single-layer structure composed of a single insulating film. The second inorganic insulating film 320 preferably includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second inorganic insulating film 320 may have a laminated structure including a plurality of silicon oxide films, a laminated structure including a plurality of silicon nitride films, or a laminated structure including a plurality of silicon oxynitride films.

[0316] The second inorganic insulating film 320 may have a laminated structure in which at least two of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film are laminated in an arbitrary order. The second inorganic insulating film 320 may have a single-layer structure composed of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In this form, the second inorganic insulating film 320 has a single-layer structure composed of a silicon nitride film. That is, the second inorganic insulating film 320 is made of an insulator different from the first inorganic insulating film 280.

[0317] The thickness of the second inorganic insulating film 320 may be equal to or greater than the thickness of the first inorganic insulating film 280. Preferably, the thickness of the second inorganic insulating film 320 is less than the thickness of the first inorganic insulating film 280. Preferably, the thickness of the second inorganic insulating film 320 exceeds the thickness of the first electrode film 312. Preferably, the second insulating thickness T2 is equal to or less than the thickness of the second electrode film 313. Particularly preferably, the thickness of the second inorganic insulating film 320 is less than the thickness of the second electrode film 313. The thickness of the second inorganic insulating film 320 may be equal to or greater than 0.05 μm and equal to or less than 5 μm. Preferably, the thickness of the second inorganic insulating film 320 is equal to or greater than 0.1 μm and equal to or less than 2 μm.

[0318] In this form, the second inorganic insulating film 320 includes a plurality of inner coating portions 321 (electrode coating portions), an outer coating portion 322 (insulating coating portion), and a removal portion 323. The plurality of inner coating portions 321 respectively cover the plurality of first main surface electrodes 300 so as to expose the electrode side walls of the plurality of first main surface electrodes 300. Specifically, the plurality of inner coating portions 321 include a first inner coating portion 324 (gate inner coating portion) that covers the gate main surface electrode 301 and a second inner coating portion 325 (source inner coating portion) that covers the source main surface electrode 303.

[0319] The second inorganic insulating film 320 only needs to have at least one of the first inner coating portion 324 and the second inner coating portion 325, and does not necessarily need to include both the first inner coating portion 324 and the second inner coating portion 325. Preferably, the second inorganic insulating film 320 has a second inner coating portion 325 that covers the source main surface electrode 303, which has a larger area than the gate main surface electrode 301.

[0320] Particularly preferably, the second inorganic insulating film 320 has both the first inner coating portion 324 and the second inner coating portion 325. Also, the second inorganic insulating film 320 only needs to have at least one of the plurality of inner coating portions 321 and the outer coating portion 322, and does not necessarily need to include both the plurality of inner coating portions 321 and the outer coating portion 322. Preferably, the second inorganic insulating film 320 has at least the plurality of inner coating portions 321. Most preferably, it includes both the plurality of inner coating portions 321 and the outer coating portion 322.

[0321] Referring to FIG. 15, the first inner coating portion 324 of the second inorganic insulating film 320 covers the gate main surface electrode 301 so as to expose the gate electrode sidewall 302 above the active surface 206. Specifically, the first inner coating portion 324 covers the gate main surface electrode 301 at a distance from the gate electrode sidewall 302 so as to expose the peripheral portion of the gate main surface electrode 301. The first inner coating portion 324 also exposes the inner portion of the gate main surface electrode 301.

[0322] The first inner coating portion 324 is formed in a strip shape extending along the gate electrode sidewall 302 in a plan view. In this form, the first inner coating portion 324 is formed in an annular shape surrounding the inner portion of the gate main surface electrode 301 in a plan view. Specifically, the first inner coating portion 324 is formed in an annular shape (specifically, a square annular shape) having four sides parallel to the gate electrode sidewall 302 in a plan view.

[0323] The first inner coating portion 324 has a first inner wall portion 326 on the inner portion side of the gate main surface electrode 301 and a first outer wall portion 327 on the gate electrode sidewall 302 side. The first inner wall portion 326 defines a first gate opening 328 that exposes the inner portion of the gate main surface electrode 301. The first inner wall portion 326 (the first gate opening 328) is formed in a square shape having four sides parallel to the gate electrode sidewall 302 in a plan view. The first inner wall portion 326 is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 320 toward the inner portion of the gate main surface electrode 301.

[0324] The first outer wall portion 327 is formed on the gate main surface electrode 301 at a distance from the gate electrode sidewall 302 so as to expose the peripheral portion of the gate main surface electrode 301. The first outer wall portion 327 is formed in a square shape having four sides parallel to the gate electrode sidewall 302 in a plan view. The first outer wall portion 327 is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 320 toward the gate electrode sidewall 302 of the gate main surface electrode 301.

[0325] Referring to FIG. 16, the second inner coating portion 325 of the second inorganic insulating film 320 covers the source main surface electrode 303 so as to expose the source electrode side wall 305 on the active surface 206. Specifically, the second inner coating portion 325 covers the source main surface electrode 303 at a distance from the source electrode side wall 305 so as to expose the peripheral portion of the source main surface electrode 303. The second inner coating portion 325 also exposes the inner portion of the source main surface electrode 303.

[0326] The second inner coating portion 325 is formed in a strip shape extending along the source electrode side wall 305 in a plan view. In this form, the second inner coating portion 325 is formed in an annular shape surrounding the inner portion of the source main surface electrode 303 in a plan view. The second inner coating portion 325 has a recessed portion that is recessed inwardly toward the source main surface electrode 303 along the portion of the source electrode side wall 305 where the recess 304 is formed. As a result, the second inner coating portion 325 is formed in an annular shape (specifically, a polygonal annular shape) having sides parallel to the source electrode side wall 305 in a plan view.

[0327] The second inner coating portion 325 has a second inner wall portion 329 on the inner portion side of the source main surface electrode 303 and a second outer wall portion 330 on the source electrode side wall 305 side of the source main surface electrode 303. The second inner wall portion 329 defines a first source opening 331 that exposes the inner portion of the source main surface electrode 303. The second inner wall portion 329 (the first source opening 331) is formed in a polygonal shape having sides parallel to the source electrode side wall 305 in a plan view. The second inner wall portion 329 is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 320 toward the inner portion of the source main surface electrode 303.

[0328] The second outer wall portion 330 is formed on the source main surface electrode 303 with a space from the source electrode side wall 305 so as to expose the peripheral portion of the source main surface electrode 303. In this form, the second outer wall portion 330 is formed in a polygonal shape having sides parallel to the source electrode side wall 305 in plan view. The second outer wall portion 330 is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 320 toward the source electrode side wall 305 of the source main surface electrode 303.

[0329] Referring to FIGS. 15 and 16, the outer covering portion 322 of the second inorganic insulating film 320 covers the first inorganic insulating film 280 with a space from the gate main surface electrode 301 and the source main surface electrode 303 to the peripheral side of the first main surface 203 so as to expose the gate electrode side wall 302 and the source electrode side wall 305.

[0330] The outer covering portion 322 is formed with a space from the gate wiring electrode 307 to the periphery of the first main surface 203 so as to expose the gate wiring side wall 309. The outer covering portion 322 is formed with a space from the source wiring electrode 310 to the periphery of the first main surface 203 so as to expose the source wiring side wall 311. The outer covering portion 322 covers the first inorganic insulating film 280 with a space from the boundary side surface 208 to the outer side surface 207.

[0331] That is, the outer covering portion 322 covers the first inorganic insulating film 280 on the outer side surface 207 so as to expose the gate main surface electrode 301 (gate electrode side wall 302), the source main surface electrode 303 (source electrode side wall 305), the gate wiring electrode 307 (gate wiring side wall 309), and the source wiring electrode 310 (source wiring side wall 311).

[0332] The outer covering portion 322 is formed in a strip shape extending along the active surface 206 (the boundary side surface 208) in a plan view. The outer covering portion 322 is formed in an annular shape surrounding the active surface 206 in a plan view. Specifically, the outer covering portion 322 is formed in a square annular shape having four sides parallel to the active surface 206 in a plan view. That is, the outer covering portion 322 surrounds the gate main surface electrode 301, the source main surface electrode 303, the gate wiring electrode 307, and the source wiring electrode 310 together in a plan view.

[0333] The outer covering portion 322 is formed at a distance from the outer contact region 260 to the peripheral edge (the first to fourth side surfaces 205A to 205D) of the first main surface 203 in a plan view. The outer covering portion 322 faces at least one field region 262 with the first inorganic insulating film 280 interposed therebetween.

[0334] In this form, the outer covering portion 322 is formed at a distance from the innermost first field region 262A to the peripheral edge side of the first main surface 203 in a plan view, and faces the second to fifth field regions 262B to 262E with the first inorganic insulating film 280 interposed therebetween. Of course, the outer covering portion 322 may face all of the first to fifth field regions 262A to 262E with the first inorganic insulating film 280 interposed therebetween.

[0335] In this form, the outer covering portion 322 is drawn out onto the outer surface 207 exposed from the notch opening 282 across the notch opening 282 (the first peripheral end wall 271 and the second peripheral end wall 281) from above the first inorganic insulating film 280. Thereby, the outer covering portion 322 includes a first covering portion 332 covering the first inorganic insulating film 280 and a second covering portion 333 directly covering the outer surface 207.

[0336] The first covering portion 332 extends in a film shape along the first inorganic insulating film 280 and faces the outer surface 207 with the first inorganic insulating film 280 interposed therebetween. The first covering portion 332 faces the second semiconductor region 211 and at least one field region 262 (in this form, the second to fifth field regions 262B to 262E) with the first inorganic insulating film 280 interposed therebetween. The main surface of the first covering portion 332 is located on the side of the first inorganic insulating film 280 with respect to the active surface 206. The main surface of the first covering portion 332 is located on the side of the first inorganic insulating film 280 with respect to the main surface of the source wiring electrode 310 in this form.

[0337] The second covering portion 333 extends in a film shape along the outer surface 207 and directly covers the outer surface 207. That is, the second covering portion 333 directly covers the second semiconductor region 211 (the second concentration region 213). The main surface of the second covering portion 333 is located on the side of the outer surface 207 with respect to the active surface 206. The main surface of the second covering portion 333 is located on the side of the outer surface 207 with respect to the main surface of the source wiring electrode 310. The main surface of the second covering portion 333 is located between the main surfaces of the outer surface 207 and the first inorganic insulating film 280 in this form.

[0338] The second covering portion 333 is formed at a distance from the periphery of the first main surface 203 (the first to fourth side surfaces 205A to 205D) toward the first inorganic insulating film 280 so as to expose the peripheral portion of the outer surface 207. The second covering portion 333 demarcates a dicing street 334 in which the peripheral portion of the outer surface 207 is exposed between the second covering portion 333 and the periphery of the first main surface 203. The dicing street 334 is demarcated in a rectangular ring shape extending along the periphery of the first main surface 203. The width of the dicing street 334 may be 5 μm or more and 25 μm or less. The width of the dicing street 334 is the width in a direction orthogonal to the direction in which the dicing street 334 extends.

[0339] The outer covering portion 322 has a third inner wall portion 335 on the active surface 206 side and a third outer wall portion 336 on the peripheral side of the first main surface 203. The third inner wall portion 335 is formed on the first inorganic insulating film 280 with a space from the source wiring sidewall 311 of the source wiring electrode 310 so as to expose the first inorganic insulating film 280 on the outer surface 207.

[0340] In this form, the third inner wall portion 335 is formed in a rectangular shape having four sides parallel to the source wiring electrode 310 (source wiring sidewall 311) in plan view, and collectively surrounds the gate main surface electrode 301, the source main surface electrode 303, the gate wiring electrode 307, and the source wiring electrode 310. The third inner wall portion 335 is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 320 toward the first inorganic insulating film 280.

[0341] The third outer wall portion 336 is formed in a region between the notch opening 282 and the periphery of the first main surface 203 (the first to fourth side surfaces 205A to 205D) in plan view, and exposes the peripheral portion of the outer surface 207. The third outer wall portion 336 is formed in a tapered shape that slopes obliquely downward from the main surface of the second inorganic insulating film 320 toward the outer surface 207. The third outer wall portion 336 demarcates the dicing street 334 from the periphery of the first main surface 203.

[0342] The removal portion 323 of the second inorganic insulating film 320 is demarcated between the first inner covering portion 324 (first outer wall portion 327) and the outer covering portion 322 (third inner wall portion 335), between the second inner covering portion 325 (second outer wall portion 330) and the outer covering portion 322 (third inner wall portion 335), and between the first inner covering portion 324 (first outer wall portion 327) and the second inner covering portion 325 (second outer wall portion 330). In this form, the removal portion 323 is formed in a strip shape extending along the boundary side surface 208, the first outer wall portion 327, and the second outer wall portion 330 in plan view. In this form, the removal portion 323 integrally includes an annular portion extending along the first outer wall portion 327 and an annular portion extending along the second outer wall portion 330 (boundary side surface 208) in plan view.

[0343] The removal portion 323 exposes the stepped portion (i.e., the boundary side surface 208) between the active surface 206 and the outer surface 207 over the entire circumference, and at the same time exposes the gate electrode sidewall 302, the source electrode sidewall 305, the gate wiring sidewall 309, and the source wiring sidewall 311 over the entire circumference. That is, the removal portion 323 exposes the entire area of the gate wiring electrode 307, the entire area of the source wiring electrode 310, and the entire area of the sidewall structure 272 interposed between the gate wiring electrode 307 and the source wiring electrode 310.

[0344] In the second inorganic insulating film 320, the first inner coating portion 324 is formed on the flat gate main surface electrode 301, the second inner coating portion 325 is formed on the flat source main surface electrode 303, and the outer coating portion 322 is formed on the flat first inorganic insulating film 280. Therefore, in the second inorganic insulating film 320, the steps caused by the gate electrode sidewall 302, the source electrode sidewall 305, the gate wiring sidewall 309, and the source wiring sidewall 311 are removed by the removal portion 323. Also, in the second inorganic insulating film 320, the steps caused by the active mesa 209 are removed by the removal portion 323.

[0345] The SiC semiconductor device 201 includes an organic insulating film 340 that selectively covers the second inorganic insulating film 320 and the plurality of first main surface electrodes 300. The organic insulating film 340 has a hardness lower than that of the second inorganic insulating film 320. In other words, the organic insulating film 340 has an elastic modulus smaller than that of the second inorganic insulating film 320 and functions as a buffer material (protective film) against external forces. The organic insulating film 340 protects the SiC chip 202, the first main surface electrode 300, the second inorganic insulating film 320, etc. from external forces.

[0346] The organic insulating film 340 preferably contains a photosensitive resin. The photosensitive resin may be of a negative type or a positive type. The organic insulating film 340 may contain at least one of a polyimide film, a polyamide film, and a polybenzoxazole film. In this form, the organic insulating film 340 contains a polybenzoxazole film.

[0347] The thickness of the organic insulating film 340 may be 1 μm or more and 50 μm or less. The thickness of the organic insulating film 340 is preferably 5 μm or more and 20 μm or less. The thickness of the organic insulating film 340 preferably exceeds the thickness of the second inorganic insulating film 320. The thickness of the organic insulating film 340 particularly preferably exceeds the thickness of the first main surface electrode 300.

[0348] The organic insulating film 340 covers the gate electrode sidewall 302 of the gate main surface electrode 301 on the active surface 206. Specifically, the organic insulating film 340 covers the gate electrode sidewall 302 across the entire circumference of the gate main surface electrode 301. The organic insulating film 340 covers the first electrode film 312 and the second electrode film 313 on the gate electrode sidewall 302. The organic insulating film 340 covers the edge of the gate main surface electrode 301.

[0349] That is, the organic insulating film 340 extends from the gate electrode sidewall 302 toward the first inner covering portion 324 and covers the peripheral edge of the gate main surface electrode 301 exposed between the gate electrode sidewall 302 and the first inner covering portion 324. The organic insulating film 340 further extends from the peripheral edge of the gate main surface electrode 301 onto the first inner covering portion 324 and covers the first inner covering portion 324.

[0350] The organic insulating film 340 covers the first inner covering portion 324 so as to expose the inner portion of the gate main surface electrode 301. Specifically, the organic insulating film 340 covers the first inner covering portion 324 so as to expose the first inner wall portion 326 of the first inner covering portion 324. More specifically, the organic insulating film 340 covers the first inner covering portion 324 at an interval from the first inner wall portion 326 toward the first outer wall portion 327, exposing the inner portion of the gate main surface electrode 301 and the edge of the first inner covering portion 324 (hereinafter referred to as the "first edge 341").

[0351] The organic insulating film 340 covers the source electrode sidewall 305 of the source main surface electrode 303 on the active surface 206. Specifically, the organic insulating film 340 covers the source electrode sidewall 305 across the entire circumference of the source main surface electrode 303. The organic insulating film 340 covers the first electrode film 312 and the second electrode film 313 on the source electrode sidewall 305. The organic insulating film 340 covers the edge of the source main surface electrode 303.

[0352] That is, the organic insulating film 340 extends from the source electrode sidewall 305 toward the second inner covering portion 325 side, and covers the peripheral portion of the source main surface electrode 303 exposed between the source electrode sidewall 305 and the second inner covering portion 325. The organic insulating film 340 further extends from the peripheral portion of the source main surface electrode 303 onto the second inner covering portion 325 and covers the second inner covering portion 325.

[0353] The organic insulating film 340 covers the second inner covering portion 325 so as to expose the inner portion of the source main surface electrode 303. Specifically, the organic insulating film 340 covers the second inner covering portion 325 so as to expose the second inner wall portion 329 of the second inner covering portion 325. More specifically, the organic insulating film 340 covers the second inner covering portion 325 at an interval from the second inner wall portion 329 toward the second outer wall portion 330 side, and exposes the inner portion of the source main surface electrode 303 and the edge portion of the second inner covering portion 325 (hereinafter referred to as "second edge portion 342").

[0354] The organic insulating film 340 covers the gate wiring sidewall 309 of the gate wiring electrode 307 on the active surface 206. Specifically, the organic insulating film 340 covers the gate wiring sidewall 309 across the entire circumference of the gate wiring electrode 307. The organic insulating film 340 covers the first electrode film 312 and the second electrode film 313 on the gate wiring sidewall 309. The organic insulating film 340 extends from the gate wiring sidewall 309 onto the gate wiring electrode 307 and covers the entire area of the gate wiring electrode 307.

[0355] The organic insulating film 340 covers the periphery of the active surface 206, passes through the sidewall structure 272, and covers the outer surface 207. The organic insulating film 340 covers the source wiring sidewall 311 of the source wiring electrode 310 on the outer surface 207. Specifically, the organic insulating film 340 covers the source wiring sidewall 311 over the entire circumference of the source wiring electrode 310. The organic insulating film 340 covers the first electrode film 312 and the second electrode film 313 on the source wiring sidewall 311. The organic insulating film 340 extends from the source wiring sidewall 311 onto the source wiring electrode 310 and covers the entire area of the source wiring electrode 310.

[0356] The organic insulating film 340 is drawn from the source wiring electrode 310 side onto the outer covering portion 322 of the second inorganic insulating film 320 and covers the outer covering portion 322. The organic insulating film 340 covers the outer covering portion 322 so as to expose the periphery of the outer surface 207. Specifically, the organic insulating film 340 covers the outer covering portion 322 so as to expose the third outer wall portion 336 of the outer covering portion 322.

[0357] More specifically, the organic insulating film 340 covers the outer covering portion 322 with a space from the third outer wall portion 336 toward the third inner wall portion 335, and exposes the periphery of the outer surface 207 and the periphery of the outer covering portion 322 in plan view. That is, the organic insulating film 340 covers the first covering portion 332 and the second covering portion 333 of the outer covering portion 322 so as to expose the outer surface 207.

[0358] The organic insulating film 340 has a fourth inner wall portion 343 on the gate main surface electrode 301 side. The fourth inner wall portion 343 defines a second gate opening 344 that exposes the inner portion of the gate main surface electrode 301. The fourth inner wall portion 343 (the second gate opening 344) extends along the first inner wall portion 326 (the first gate opening 328) of the first inner covering portion 324. In this form, the fourth inner wall portion 343 is formed in a quadrangular shape having four sides parallel to the first inner wall portion 326 in plan view.

[0359] Specifically, the fourth inner wall portion 343 is formed on the first inner coating portion 324 with a space from the first inner wall portion 326 toward the first outer wall portion 327, exposing the inner portion of the gate main surface electrode 301 and the first edge portion 341 of the first inner coating portion 324. That is, the second gate opening 344 exposes the inner portion of the gate main surface electrode 301 and the first edge portion 341 of the first inner coating portion 324. The exposed width of the first edge portion 341 may be more than 0 μm and 10 μm or less. Preferably, the exposed width of the first edge portion 341 is 1 μm or more and 5 μm or less.

[0360] The fourth inner wall portion 343 (second gate opening 344) communicates with the first inner wall portion 326 (first gate opening 328) and forms one gate pad opening 345 with the first inner wall portion 326 (first gate opening 328). The fourth inner wall portion 343 (second gate opening 344) is formed in a tapered shape that slopes obliquely downward from the main surface of the organic insulating film 340 toward the first inner wall portion 326. In this form, the fourth inner wall portion 343 is formed in a curved tapered shape that curves toward the first inner coating portion 324.

[0361] The organic insulating film 340 has a fifth inner wall portion 346 on the source main surface electrode 303 side. The fifth inner wall portion 346 defines a second source opening 347 that exposes the inner portion of the source main surface electrode 303. The fifth inner wall portion 346 (second source opening 347) extends along the second inner wall portion 329 (first source opening 331) of the second inner coating portion 325. In this form, the fifth inner wall portion 346 is formed in a polygonal shape having sides parallel to the second inner wall portion 329 of the second inner coating portion 325 in plan view.

[0362] The fifth inner wall portion 346 is specifically formed on the second inner covering portion 325 with a space from the second inner wall portion 329 of the second inner covering portion 325 toward the second outer wall portion 330, exposing the inner portion of the source main surface electrode 303 and the second edge portion 342 of the second inner covering portion 325. That is, the second source opening 347 exposes the inner portion of the source main surface electrode 303 and the second edge portion 342 of the second inner covering portion 325. The exposed width of the second edge portion 342 may be more than 0 μm and 10 μm or less. The exposed width of the second edge portion 342 is preferably 1 μm or more and 5 μm or less.

[0363] The fifth inner wall portion 346 (second source opening 347) communicates with the second inner wall portion 329 (first source opening 331) of the second inner covering portion 325, and forms one source pad opening 348 with the second inner wall portion 329 (first source opening 331). The fifth inner wall portion 346 (second source opening 347) is formed in a tapered shape that slopes obliquely downward from the main surface of the organic insulating film 340 toward the second inner wall portion 329. In this form, the fifth inner wall portion 346 is formed in a curved tapered shape that curves toward the second inner covering portion 325.

[0364] The organic insulating film 340 has a fourth outer wall portion 349. The fourth outer wall portion 349 is formed with a space from the periphery of the first main surface 203 (first to fourth side surfaces 205A to 205D) toward the outer covering portion 322 so as to expose the outer surface 207. Specifically, the fourth outer wall portion 349 is formed on the third outer wall portion 336 of the outer covering portion 322 so as to expose the third outer wall portion 336. More specifically, the fourth outer wall portion 349 is formed with a space from the third outer wall portion 336 toward the third inner wall portion 335 so as to expose the peripheral portion of the outer covering portion 322.

[0365] The fourth outer wall portion 349 is located on the second covering portion 333 of the outer covering portion 322 and faces the outer surface 207 with the outer covering portion 322 interposed therebetween. The fourth outer wall portion 349, together with the third outer wall portion 336, demarcates the dicing street 334. In this form, the fourth outer wall portion 349 is formed in a rectangular shape having four sides parallel to the active surface 206 in plan view. The fourth outer wall portion 349 is formed in a tapered shape that slopes obliquely downward from the main surface of the organic insulating film 340 toward the third outer wall portion 336 of the outer covering portion 322. In this form, the fourth outer wall portion 349 is formed in a curved tapered shape that curves toward the outer covering portion 322.

[0366] Thus, the organic insulating film 340 covers the edge of the gate main surface electrode 301, the edge of the source main surface electrode 303, the entire area of the gate wiring electrode 307, and the plurality of inner covering portions 321 of the second inorganic insulating film 320 above the active surface 206. The organic insulating film 340 covers, above the active surface 206, the portions of the first inorganic insulating film 280 that are exposed from the gate main surface electrode 301, the gate wiring electrode 307, and the source main surface electrode 303. The organic insulating film 340 may face the plurality of first trench structures 220 and the plurality of second trench structures 230 with the first inorganic insulating film 280 interposed therebetween.

[0367] The organic insulating film 340 covers the sidewall structure 272 between the active surface 206 and the outer surface 207. The organic insulating film 340 covers the entire area of the source wiring electrode 310 and the outer covering portion 322 of the second inorganic insulating film 320 above the outer surface 207. The organic insulating film 340 covers, above the outer surface 207, the portions of the first inorganic insulating film 280 that are exposed from the source wiring electrode 310 and the second inorganic insulating film 320.

[0368] Also, the organic insulating film 340 is formed across the plurality of inner covering portions 321 and the outer covering portion 322 of the second inorganic insulating film 320, and covers the edge of the gate main surface electrode 301, the edge of the source main surface electrode 303, the entire area of the gate wiring electrode 307, and the entire area of the source wiring electrode 310 within the removal portion 323 between the plurality of inner covering portions 321 and the outer covering portion 322.

[0369] That is, the organic insulating film 340 fills the unevenness formed by the first inorganic insulating film 280, the second inorganic insulating film 320, the gate main surface electrode 301, the source main surface electrode 303, the gate wiring electrode 307, and the source wiring electrode 310 within the removal portion 323. The step of the portion located within the removal portion 323 in the organic insulating film 340 is alleviated by the sidewall structure 272.

[0370] Referring to FIGS. 17 and 18, the SiC semiconductor device 201 includes a plurality of pad electrodes 360 respectively formed on the plurality of first main surface electrodes 300. The plurality of pad electrodes 360 are terminal electrodes for external connection, and in this form, they are respectively made of plating films. The plurality of pad electrodes 360 include a gate pad electrode 361 and a source pad electrode 362.

[0371] The gate pad electrode 361 is formed on the inner part of the gate main surface electrode 301 within the gate pad opening 345. The gate pad electrode 361 includes a first Ni plating film 363. The first Ni plating film 363 is formed at a distance from the main surface of the organic insulating film 340 toward the gate main surface electrode 301 with respect to the normal direction Z. The first Ni plating film 363 covers the gate main surface electrode 301 and the first inner wall portion 326 of the first inner covering portion 324 within the first gate opening 328.

[0372] Specifically, the first Ni plating film 363 has a first covering portion 364 that is drawn from above the gate main surface electrode 301 onto the first inner covering portion 324 and covers the first edge portion 341 of the first inner covering portion 324 within the second gate opening 344. The first covering portion 364 is formed in an arc shape starting from the first inner wall portion 326 toward the organic insulating film 340 (the fourth inner wall portion 343) above the first inner covering portion 324.

[0373] In this embodiment, the first coating portion 364 covers the fourth inner wall portion 343 of the organic insulating film 340. The first coating portion 364 covers the region on the side of the second inorganic insulating film 320 with respect to the middle portion of the fourth inner wall portion 343. In other words, the first coating portion 364 covers the fourth inner wall portion 343 such that the exposed area of the fourth inner wall portion 343 exceeds the hidden area of the fourth inner wall portion 343. Thus, the first Ni plating film 363 fills the entire first gate opening 328 and a part of the second gate opening 344.

[0374] The thickness of the first Ni plating film 363 exceeds the thickness of the second inorganic insulating film 320. The thickness of the first Ni plating film 363 is less than the thickness of the organic insulating film 340. The thickness of the first Ni plating film 363 is the thickness of the first Ni plating film 363 with respect to the main surface of the gate main surface electrode 301. The thickness of the first Ni plating film 363 exceeds the sum of the thickness of the second inorganic insulating film 320 and the exposed width of the first edge portion 341. This is one condition for the first Ni plating film 363 to contact the fourth inner wall portion 343. The thickness of the first Ni plating film 363 may be 0.1 μm or more and 15 μm or less. Preferably, the thickness of the first Ni plating film 363 is 2 μm or more and 8 μm or less.

[0375] The gate pad electrode 361 is made of a metal material different from that of the first Ni plating film 363 and includes a first outer plating film 365 that covers the outer surface of the first Ni plating film 363. The first outer plating film 365 is formed in a film shape along the outer surface of the first Ni plating film 363. The first outer plating film 365 covers the fourth inner wall portion 343 of the organic insulating film 340.

[0376] The first outer plating film 365 has a first terminal surface 366 for external connection. The first terminal surface 366 is located on the side of the first Ni plating film 363 with respect to the main surface of the organic insulating film 340 (the opening end of the second gate opening 344) in the normal direction Z. Thereby, the first outer plating film 365 exposes a part of the fourth inner wall portion 343. The thickness of the first outer plating film 365 is less than the thickness of the first Ni plating film 363.

[0377] In this form, the first outer plating film 365 has a laminated structure including a first Pd plating film 367 and a first Au plating film 368 laminated in this order from the side of the first Ni plating film 363. The first Pd plating film 367 is formed in a film shape along the outer surface of the first Ni plating film 363. The first Pd plating film 367 covers the first Ni plating film 363 at a distance from the main surface of the organic insulating film 340 toward the second inorganic insulating film 320 with respect to the normal direction Z. The first Pd plating film 367 covers the fourth inner wall portion 343. The thickness of the first Pd plating film 367 may be 0.01 μm or more and 1 μm or less.

[0378] The first Au plating film 368 is formed in a film shape along the outer surface of the first Pd plating film 367. The first Au plating film 368 covers the first Pd plating film 367 at a distance from the main surface of the organic insulating film 340 toward the second inorganic insulating film 320 with respect to the normal direction Z. The first Au plating film 368 covers the fourth inner wall portion 343. The thickness of the first Au plating film 368 may be 0.01 μm or more and 1 μm or less. Preferably, the first Au plating film 368 has a thickness less than that of the first Pd plating film 367.

[0379] The source pad electrode 362 is formed on the inner part of the source main surface electrode 303 within the source pad opening 348. The source pad electrode 362 includes a second Ni plating film 373. The second Ni plating film 373 is formed at a distance from the main surface of the organic insulating film 340 toward the source main surface electrode 303 with respect to the normal direction Z. The second Ni plating film 373 covers the source main surface electrode 303 and the second inner wall portion 329 of the second inner covering portion 325 within the first source opening 331.

[0380] Specifically, the second Ni plating film 373 has a second covering portion 374 that is drawn from above the source main surface electrode 303 onto the second inner covering portion 325 and covers the second edge portion 342 of the second inner covering portion 325 within the second source opening 347. The second covering portion 374 is formed in an arc shape starting from the second inner wall portion 329 and extending toward the organic insulating film 340 (the fifth inner wall portion 346) above the second inner covering portion 325.

[0381] In this form, the second covering portion 374 covers the fifth inner wall portion 346 of the organic insulating film 340. The second covering portion 374 covers the region on the side of the second inorganic insulating film 320 with respect to the middle portion of the fifth inner wall portion 346. In other words, the second covering portion 374 covers the fifth inner wall portion 346 such that the exposed area of the fifth inner wall portion 346 exceeds the hidden area of the fifth inner wall portion 346. Thus, the second Ni plating film 373 fills the entirety of the first source opening 331 and a part of the second source opening 347.

[0382] The thickness of the second Ni plating film 373 exceeds the thickness of the second inorganic insulating film 320. The thickness of the second Ni plating film 373 is less than the thickness of the organic insulating film 340. The thickness of the second Ni plating film 373 is the thickness of the second Ni plating film 373 with respect to the main surface of the source main surface electrode 303. The thickness of the second Ni plating film 373 exceeds the sum of the thickness of the second inorganic insulating film 320 and the exposed width of the second edge portion 342. This is one condition for the second Ni plating film 373 to contact the fifth inner wall portion 346. The thickness of the second Ni plating film 373 may be 0.1 μm or more and 15 μm or less. Preferably, the thickness of the second Ni plating film 373 is 2 μm or more and 8 μm or less.

[0383] The source pad electrode 362 is made of a metal material different from that of the second Ni plating film 373 and includes a second outer plating film 375 that covers the outer surface of the second Ni plating film 373. The second outer plating film 375 is formed in a film shape along the outer surface of the second Ni plating film 373. The second outer plating film 375 covers the fifth inner wall portion 346 of the organic insulating film 340.

[0384] The second outer plating film 375 has a source terminal surface 376 for external connection. The source terminal surface 376 is located on the side of the second Ni plating film 373 with respect to the main surface of the organic insulating film 340 (the opening end of the second source opening 347) with respect to the normal direction Z. Thereby, the second outer plating film 375 exposes a part of the fifth inner wall portion 346. The thickness of the second outer plating film 375 is less than the thickness of the second Ni plating film 373.

[0385] In this form, the second outer plating film 375 has a laminated structure including a second Pd plating film 377 and a second Au plating film 378 laminated in this order from the side of the second Ni plating film 373. The second Pd plating film 377 is formed in a film shape along the outer surface of the second Ni plating film 373. The second Pd plating film 377 covers the second Ni plating film 373 at an interval from the main surface of the organic insulating film 340 toward the second inorganic insulating film 320 with respect to the normal direction Z. The second Pd plating film 377 covers the fifth inner wall portion 346 in the second source opening 347. The thickness of the second Pd plating film 377 may be 0.01 μm or more and 1 μm or less.

[0386] The second Au plating film 378 is formed in a film shape along the outer surface of the second Pd plating film 377. The second Au plating film 378 covers the second Pd plating film 377 at an interval from the main surface of the organic insulating film 340 toward the second inorganic insulating film 320 with respect to the normal direction Z. The second Au plating film 378 covers the fifth inner wall portion 346 in the second source opening 347. The thickness of the second Au plating film 378 may be 0.01 μm or more and 1 μm or less. Preferably, the second Au plating film 378 has a thickness less than that of the second Pd plating film 377.

[0387] The SiC semiconductor device 201 includes a second main surface electrode 380 that covers the second main surface 204. The second main surface electrode 380 covers the entire area of the second main surface 204 and is continuous with the periphery of the first main surface 203 (the first to fourth side surfaces 205A to 205D). The second main surface electrode 380 is electrically connected to the first semiconductor region 210 (the second main surface 204). Specifically, the second main surface electrode 380 forms an ohmic contact with the first semiconductor region 210 (the second main surface 204).

[0388] In this form, the second main surface electrode 380 includes a Ti film 381, a Ni film 382, a Pd film 383, an Au film 384, and an Ag film 385 laminated in this order from the second main surface 204 side. The second main surface electrode 380 only needs to include at least the Ti film 381, and the presence or absence of the Ni film 382, the Pd film 383, the Au film 384, and the Ag film 385 is arbitrary respectively. As an example, the second main surface electrode 380 may have a laminated structure including the Ti film 381, the Ni film 382, and the Au film 384.

[0389] As described above, the SiC semiconductor device 201 also exhibits the same effects as those described for the SiC semiconductor device 1. The second inorganic insulating film 320 can take various forms shown in FIGS. 19A to 19F.

[0390] FIG. 19A corresponds to FIG. 12 and is a plan view showing the internal structure of the SiC semiconductor device 201 together with the second inorganic insulating film 320 according to the second exemplary form. Hereinafter, the same reference numerals are given to the structures corresponding to the structures shown in FIGS. 11 to 18, and their descriptions are omitted.

[0391] Referring to FIG. 19A, the first inner covering portion 324 of the second inorganic insulating film 320 has a first inner opening 391 that exposes the gate main surface electrode 301. The first inner opening 391 is formed in the inner portion of the first inner covering portion 324 at a distance from the first inner wall portion 326 and the first outer wall portion 327. The first inner opening 391 is formed in a strip shape extending along the first inner wall portion 326 and the first outer wall portion 327. In this form, the first inner opening 391 is formed in an annular shape (specifically, a square annular shape) extending along the first inner wall portion 326 and the first outer wall portion 327.

[0392] The second inner covering portion 325 of the second inorganic insulating film 320 has a second inner opening 392 that exposes the source main surface electrode 303. The second inner opening 392 is formed in the inner portion of the second inner covering portion 325 at a distance from the second inner wall portion 329 and the second outer wall portion 330. The second inner opening 392 is formed in a strip shape extending along the second inner wall portion 329 and the second outer wall portion 330. In this form, the second inner opening 392 is formed in an annular shape (specifically, a polygonal annular shape) extending along the second inner wall portion 329 and the second outer wall portion 330.

[0393] The organic insulating film 340 enters the first inner opening 391 from above the first inner covering portion 324 and covers the portion exposed from the first inner opening 391 at the gate main surface electrode 301. The organic insulating film 340 enters the second inner opening 392 from above the second inner covering portion 325 and covers the portion exposed from the second inner opening 392 at the source main surface electrode 303.

[0394] The portions of the organic insulating film 340 located within the first inner opening 391 and the second inner opening 392 respectively form anchor portions. As a result, in the portion covering the plurality of first main surface electrodes 300, the contact area of the organic insulating film 340 with respect to the second inorganic insulating film 320 increases, and peeling of the organic insulating film 340 from the second inorganic insulating film 320 can be suppressed.

[0395] In this form, an example in which the first inner covering portion 324 includes the first inner opening 391 and the second inner covering portion 325 includes the second inner opening 392 has been described. However, a structure may be adopted in which the first inner covering portion 324 includes the first inner opening 391 while the second inner covering portion 325 does not include the second inner opening 392. Conversely, a structure may be adopted in which the first inner covering portion 324 does not include the first inner opening 391 while the second inner covering portion 325 includes the second inner opening 392.

[0396] FIG. 19B corresponds to FIG. 12 and is a plan view showing the internal structure of the SiC semiconductor device 201 together with the second inorganic insulating film 320 according to the third exemplary embodiment. Hereinafter, the structures corresponding to the structures shown in FIGS. 11 to 18 are given the same reference numerals, and their descriptions are omitted.

[0397] Referring to FIG. 19B, the outer covering portion 322 of the second inorganic insulating film 320 has an outer opening portion 393 that exposes the first inorganic insulating film 280. The outer opening portion 393 is formed in the inner portion of the outer covering portion 322 at an interval from the third inner wall portion 335 and the third outer wall portion 336. The outer opening portion 393 is formed in a strip shape extending along the third inner wall portion 335 and the third outer wall portion 336. In this embodiment, the outer opening portion 393 is formed in an annular shape (specifically, a square annular shape) extending along the third inner wall portion 335 and the third outer wall portion 336.

[0398] The organic insulating film 340 enters the outer opening portion 393 from above the outer covering portion 322 and covers the portion of the first inorganic insulating film 280 exposed from the outer opening portion 393. The portion of the organic insulating film 340 located within the outer opening portion 393 forms an anchor portion. Thereby, in the regions outside the plurality of first main surface electrodes 300, the contact area of the organic insulating film 340 with respect to the second inorganic insulating film 320 increases, and peeling of the organic insulating film 340 from the second inorganic insulating film 320 can be suppressed.

[0399] FIG. 19C corresponds to FIG. 12 and is a plan view showing the internal structure of the SiC semiconductor device 201 together with the second inorganic insulating film 320 according to the fourth exemplary embodiment. Hereinafter, the structures corresponding to the structures shown in FIGS. 11 to 18 are given the same reference numerals, and their descriptions are omitted.

[0400] Referring to FIG. 19C, the first inner covering portion 324 of the second inorganic insulating film 320 has a first inner opening 391 that exposes the gate main surface electrode 301 (see FIG. 19A). The second inner covering portion 325 of the second inorganic insulating film 320 has a second inner opening 392 that exposes the source main surface electrode 303 (see FIG. 19A). The outer covering portion 322 of the second inorganic insulating film 320 has an outer opening 393 that exposes the first inorganic insulating film 280 (see FIG. 19B).

[0401] The portions of the organic insulating film 340 located within the first inner opening 391, the second inner opening 392, and the outer opening 393 respectively form anchor portions. As a result, in the portion covering the plurality of first main surface electrodes 300 and the region outside the plurality of first main surface electrodes 300, the contact area of the organic insulating film 340 with respect to the second inorganic insulating film 320 increases, and peeling of the organic insulating film 340 from the second inorganic insulating film 320 can be suppressed.

[0402] FIG. 19D corresponds to FIG. 12 and is a plan view showing the internal structure of the SiC semiconductor device 201 together with the second inorganic insulating film 320 according to the fifth exemplary embodiment. Hereinafter, the same reference numerals are assigned to the structures corresponding to the structures shown in FIGS. 11 to 18, and the descriptions thereof are omitted.

[0403] Referring to FIG. 19D, the first covering portion 364 of the second inorganic insulating film 320 has a plurality of first inner openings 391 that expose the gate main surface electrode 301. The plurality of first inner openings 391 are respectively formed inside the first inner covering portion 324 at intervals from the first inner wall portion 326 and the first outer wall portion 327.

[0404] The plurality of first inner openings 391 are formed at intervals along the first inner wall portion 326 (the first outer wall portion 327). In this embodiment, each first inner opening 391 is formed in a strip shape extending along the first inner wall portion 326 in a plan view. The planar shape of each first inner opening 391 is arbitrary. Each first inner opening 391 may be formed in a polygonal shape or a circular shape in a plan view.

[0405] The second covering portion 374 of the second inorganic insulating film 320 has a plurality of second inner openings 392 that expose the source main surface electrode 303. The plurality of second inner openings 392 are respectively formed in the inner part of the second inner covering portion 325 at intervals from the second inner wall portion 329 and the second outer wall portion 330. The plurality of second inner openings 392 are formed at intervals along the second inner wall portion 329 (the second outer wall portion 330). In this form, each second inner opening 392 is formed in a strip shape extending along the second inner wall portion 329 in plan view. The planar shape of each second inner opening 392 is arbitrary. Each second inner opening 392 may be formed in a polygonal shape or a circular shape in plan view.

[0406] The outer covering portion 322 of the second inorganic insulating film 320 has a plurality of outer openings 393 that expose the first inorganic insulating film 280. The plurality of outer openings 393 are respectively formed in the inner part of the outer covering portion 322 at intervals from the third inner wall portion 335 and the third outer wall portion 336. The plurality of outer openings 393 are formed at intervals along the third inner wall portion 335 (the third outer wall portion 336). In this form, each outer opening 393 is formed in a strip shape extending along the third inner wall portion 335 in plan view. The planar shape of each outer opening 393 is arbitrary. Each outer opening 393 may be formed in a polygonal shape or a circular shape in plan view.

[0407] The portions located within the plurality of first inner openings 391, the portions located within the plurality of second inner openings 392, and the portions located within the plurality of outer openings 393 in the organic insulating film 340 respectively form anchor portions. Thereby, in the portion covering the plurality of first main surface electrodes 300 and the region outside the plurality of first main surface electrodes 300, the contact area of the organic insulating film 340 with respect to the second inorganic insulating film 320 increases, and peeling of the organic insulating film 340 from the second inorganic insulating film 320 can be suppressed.

[0408] In this embodiment, an example in which the second inorganic insulating film 320 has a plurality of first inner openings 391, a plurality of second inner openings 392, and a plurality of outer openings 393 has been described. However, the second inorganic insulating film 320 may have only any one or two of the plurality of first inner openings 391, the plurality of second inner openings 392, and the plurality of outer openings 393.

[0409] FIG. 19E corresponds to FIG. 12 and is a plan view showing the internal structure of the SiC semiconductor device 201 together with the second inorganic insulating film 320 according to the sixth exemplary embodiment. Hereinafter, the same reference numerals are given to the structures corresponding to the structures shown in FIGS. 11 to 18, and the description thereof is omitted.

[0410] Referring to FIG. 19E, the first inner covering portion 324 of the second inorganic insulating film 320 is formed on the gate main surface electrode 301 so as to expose the corner portions (four corners) of the gate main surface electrode 301. Specifically, the first inner covering portion 324 has a form in which the corner portions (four corners) of the first inner covering portion 324 (see FIG. 12) according to the first exemplary embodiment are removed, and the corner portions (four corners) of the gate main surface electrode 301 are exposed. That is, the first inner covering portion 324 includes a plurality of first inner segment portions 394 formed on the gate main surface electrode 301 with a space therebetween. Each first inner covering portion 324 is formed in a one-to-one correspondence with each side of the gate electrode side wall 302 and extends in a strip shape along each side of the gate electrode side wall 302.

[0411] The second inner covering portion 325 of the second inorganic insulating film 320 is formed on the source main surface electrode 303 so as to expose the corner portions (four corners) of the source main surface electrode 303. Specifically, the second inner covering portion 325 has a form in which the corner portions (four corners) of the second inner covering portion 325 (see FIG. 12) according to the first exemplary embodiment are removed, and the corner portions (four corners) of the source main surface electrode 303 are exposed. That is, the second inner covering portion 325 includes a plurality of second inner segment portions 395 formed on the source main surface electrode 303 with a space therebetween. Each second inner segment portion 395 is formed in a one-to-one correspondence with each side of the source electrode side wall 305 and extends in a strip shape along each side of the source electrode side wall 305.

[0412] The covering portion 322 of the second inorganic insulating film 320 is formed on the first inorganic insulating film 280 so as to expose a portion along the corner of the source wiring electrode 310 in the first inorganic insulating film 280. Specifically, the covering portion 322 has a form in which the corners (four corners) of the covering portion 322 (see FIG. 12) according to the first embodiment are removed, and a portion along the corner of the source wiring electrode 310 in the first inorganic insulating film 280 is exposed. That is, the covering portion 322 includes a plurality of outer segment portions 396 formed on the first inorganic insulating film 280. Each outer segment portion 396 is formed in a one-to-one correspondence with each side of the source wiring electrode 310 and extends in a strip shape along each side of the source wiring electrode 310.

[0413] The organic insulating film 340 covers a plurality of first inner segment portions 394 on the gate main surface electrode 301. Further, the organic insulating film 340 covers the corners (four corners) of the gate main surface electrode 301. The organic insulating film 340 covers a plurality of second inner segment portions 395 on the source main surface electrode 303. Further, the organic insulating film 340 covers the corners (four corners) of the source main surface electrode 303. The organic insulating film 340 covers the plurality of outer segment portions 396 of the covering portion 322 on the outer surface 207.

[0414] Even with such a structure, since the contact area of the organic insulating film 340 with respect to the second inorganic insulating film 320 increases, peeling of the organic insulating film 340 from the second inorganic insulating film 320 can be suppressed. At the corners (four corners) of the gate main surface electrode 301 and the corners (four corners) of the source main surface electrode 303, stress due to thermal expansion tends to concentrate. Therefore, by forming the second inorganic insulating film 320 so as to expose the corners (four corners) of the gate main surface electrode 301 and the corners (four corners) of the source main surface electrode 303, the influence of stress of the gate main surface electrode 301 and the source main surface electrode 303 on the second inorganic insulating film 320 can be reduced.

[0415] The first inner covering portion 324 may have only one first inner segment portion 394 formed in an end shape. The second inner covering portion 325 may have only one second inner segment portion 395 formed in an end shape. The outer covering portion 322 may have only one outer segment portion 396 formed in an end shape.

[0416] Further, while the first inner covering portion 324 does not have the first inner segment portion 394, the second inner covering portion 325 may have at least one second inner segment portion 395. Also, while the second inner covering portion 325 does not have the second inner segment portion 395, the first inner covering portion 324 may have at least one first inner segment portion 394. In these cases, the outer covering portion 322 may have at least one outer segment portion 396, or may not have the outer segment portion 396.

[0417] FIG. 19F corresponds to FIG. 12 and is a plan view showing the internal structure of the SiC semiconductor device 201 together with the second inorganic insulating film 320 according to the seventh exemplary form. Hereinafter, the same reference numerals are given to the structures corresponding to the structures shown in FIGS. 11 to 18, and the descriptions thereof are omitted.

[0418] Referring to FIG. 19F, the first inner covering portion 324 of the second inorganic insulating film 320 includes a plurality of first inner segment portions 394 that expose the corner portions (four corners) of the gate main surface electrode 301, similar to the first inner covering portion 324 according to the sixth exemplary form. In this form, the plurality of first inner segment portions 394 are formed in a one-to-many correspondence with each side of the gate electrode side wall 302 and are formed at intervals along each side of the gate electrode side wall 302. The planar shape of each first inner segment portion 394 is arbitrary. Each first inner segment portion 394 may be formed in a square shape, a polygonal shape, a circular shape, etc. in a plan view.

[0419] The second inner coating portion 325 of the second inorganic insulating film 320 includes a plurality of second inner segment portions 395 that expose the corner portions (four corners) of the source main surface electrode 303, similar to the second inner coating portion 325 according to the sixth exemplary embodiment. In this embodiment, the plurality of second inner segment portions 395 are formed in a one-to-many correspondence with each side of the source main surface electrode 303 and are formed at intervals along each side of the source main surface electrode 303. The planar shape of each second inner segment portion 395 is arbitrary. Each second inner segment portion 395 may be formed in a square shape, a polygonal shape, a circular shape, or the like in a plan view.

[0420] The outer coating portion 322 of the second inorganic insulating film 320 includes a plurality of outer segment portions 396 that expose portions along the corner portions of the source wiring electrode 310 in the first inorganic insulating film 280, similar to the outer coating portion 322 according to the sixth exemplary embodiment. In this embodiment, the plurality of outer segment portions 396 are formed in a one-to-many correspondence with each side of the source wiring electrode 310 and are formed at intervals along each side of the source wiring electrode 310. The planar shape of each outer segment portion 396 is arbitrary. Each outer segment portion 396 may be formed in a square shape, a polygonal shape, a circular shape, or the like in a plan view.

[0421] While the first inner coating portion 324 does not have the first inner segment portion 394, the second inner coating portion 325 may have a plurality of second inner segment portions 395. Also, while the second inner coating portion 325 does not have the second inner segment portion 395, the first inner coating portion 324 may have a plurality of first inner segment portions 394. In these cases, the outer coating portion 322 may or may not have a plurality of outer segment portions 396.

[0422] FIG. 20 corresponds to FIG. 17 and is a cross-sectional view for explaining the SiC semiconductor device 401 according to the seventh embodiment of the present invention. FIG. 21 corresponds to FIG. 18 and is a cross-sectional view for explaining the SiC semiconductor device 401 shown in FIG. 20. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 201, the same reference numerals are given and their descriptions are omitted.

[0423] Referring to Fig. 20, in the SiC semiconductor device 401 according to the seventh embodiment, the first covering portion 364 of the first Ni plating film 363 covers the first edge portion 341 of the first inner covering portion 324 with a space from the fourth inner wall portion 343 of the organic insulating film 340. The first covering portion 364 is formed in an arc shape starting from the first inner wall portion 326 and heading towards the fourth inner wall portion 343 above the first inner covering portion 324. In this embodiment, the thickness of the first Ni plating film 363 is less than the sum of the thickness of the second inorganic insulating film 320 and the exposed width of the first edge portion 341.

[0424] This is one of the conditions for the first Ni plating film 363 not to contact the fourth inner wall portion 343. On the other hand, in this embodiment, the first outer plating film 365 covers the first edge portion 341 with a space from the fourth inner wall portion 343. The first outer plating film 365 exposes a part of the first edge portion 341 and the entire fourth inner wall portion 343.

[0425] Referring to Fig. 21, in this embodiment, the second covering portion 374 of the second Ni plating film 373 covers the second edge portion 342 of the second inner covering portion 325 with a space from the fifth inner wall portion 346 of the organic insulating film 340. The second covering portion 374 is formed in an arc shape starting from the second inner wall portion 329 and heading towards the fifth inner wall portion 346 above the second inner covering portion 325. In this embodiment, the thickness of the second Ni plating film 373 is less than the sum of the thickness of the second inorganic insulating film 320 and the exposed width of the second edge portion 342.

[0426] This is one of the conditions for the second Ni plating film 373 not to contact the fifth inner wall portion 346. On the other hand, in this embodiment, the second outer plating film 375 covers the second edge portion 342 with a space from the fifth inner wall portion 346. The second outer plating film 375 exposes a part of the second edge portion 342 and the entire fifth inner wall portion 346.

[0427] As described above, the SiC semiconductor device 401 also exhibits the same effects as those described for the SiC semiconductor device 1. Further, according to the SiC semiconductor device 401, the same effects as those described for the SiC semiconductor device 101 according to the second embodiment are achieved.

[0428] In this embodiment, an example in which the first external plating film 365 that exposes the entire area of the fourth inner wall portion 343 is formed has been described. However, the first external plating film 365 that covers a part of the fourth inner wall portion 343 may be formed. In this case, either one or both of the first Pd plating film 367 and the first Au plating film 368 may cover a part of the fourth inner wall portion 343.

[0429] In this embodiment, an example in which the second external plating film 375 that exposes the entire area of the fifth inner wall portion 346 is formed has been described. However, the second external plating film 375 that covers a part of the fifth inner wall portion 346 may be formed. In this case, either one or both of the second Pd plating film 377 and the second Au plating film 378 may cover a part of the fifth inner wall portion 346.

[0430] FIG. 22 corresponds to FIG. 15 and is a cross-sectional view for explaining the SiC semiconductor device 411 according to the eighth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 201, the same reference numerals are given, and their descriptions are omitted.

[0431] Referring to FIG. 22, in the SiC semiconductor device 411 according to the eighth embodiment, the main surface insulating film 270 and the first inorganic insulating film 280 are continuous with the periphery of the first main surface 203 (the first to fourth side surfaces 205A to 205D). Therefore, the main surface insulating film 270 and the first inorganic insulating film 280 do not expose the outer surface 207. In the second inorganic insulating film 320, the entire outer covering portion 322 is formed on the first inorganic insulating film 280. The third outer wall portion 336 of the outer covering portion 322 defines a dicing street 334 that exposes the peripheral portion of the first inorganic insulating film 280 between the periphery of the first main surface 203.

[0432] As described above, the SiC semiconductor device 411 also exhibits the same effects as those described for the SiC semiconductor device 1.

[0433] FIG. 23 corresponds to FIG. 15 and is a cross-sectional view for explaining the SiC semiconductor device 421 according to the ninth embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 201, the same reference numerals are given, and their descriptions are omitted.

[0434] Referring to FIG. 23, in the SiC semiconductor device 421 according to the ninth embodiment, the main surface insulating film 270 and the first inorganic insulating film 280 are continuous with the periphery of the first main surface 203 (the first to fourth side surfaces 205A to 205D). Therefore, the main surface insulating film 270 and the first inorganic insulating film 280 do not expose the outer surface 207.

[0435] The second inorganic insulating film 320 (outer covering portion 322) is formed on the first inorganic insulating film 280 so as to be continuous with the periphery of the first main surface 203 (the first to fourth side surfaces 205A to 205D). Therefore, in this embodiment, the second inorganic insulating film 320 does not partition the dicing street 334 from the periphery of the first main surface 203. The organic insulating film 340 (fourth outer wall portion 349) is formed at an interval inward from the periphery of the first main surface 203 in a plan view in this embodiment, and partitions the dicing street 334 where the second inorganic insulating film 320 is exposed.

[0436] As described above, the SiC semiconductor device 421 also exhibits the same effects as those described for the SiC semiconductor device 1.

[0437] FIG. 24 corresponds to FIG. 13 and is an enlarged view for explaining the SiC semiconductor device 431 according to the tenth embodiment of the present invention. FIG. 25 is a cross-sectional view taken along line XXV-XXV shown in FIG. 24. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 201, the same reference numerals are given, and their descriptions are omitted.

[0438] Referring to FIGS. 24 and 25, the SiC semiconductor device 431 has a second trench structure 230 having a structure different from that of the second trench structure 230 according to the SiC semiconductor device 201. Specifically, the source trench 231 includes a first trench portion 231a on the opening side and a second trench portion 231b on the bottom wall side. The first trench portion 231a has a first trench width WT1 with respect to the second direction Y. The first trench width WT1 is the second width W2 of the second trench structure 230. The first trench portion 231a may be formed in a tapered shape in which the first trench width WT1 narrows toward the bottom wall side.

[0439] The first trench portion 231a is preferably formed in a region on the active surface 206 side with respect to the bottom wall of the gate trench 221. That is, the depth of the first trench portion 231a is preferably less than the first depth D1 of the first trench structure 220. Of course, the first trench portion 231a may be formed deeper than the first trench structure 220.

[0440] The second trench portion 231b communicates with the first trench portion 231a and extends from the first trench portion 231a toward the bottom of the second semiconductor region 211. In this form, the second trench portion 231b crosses the bottom wall of the first trench structure 220 in the plane direction along the first main surface 203. The second trench portion 231b may be formed in a vertical shape having a substantially constant opening width. The second trench portion 231b may be formed in a tapered shape having an opening width that narrows toward the bottom wall.

[0441] The depth of the second trench portion 231b with respect to the first trench portion 231a is preferably greater than the first depth D1 of the first trench structure 220. The second trench portion 231b has a second trench width WT2 (WT2 < WT1) that is less than the first trench width WT1 with respect to the second direction Y.

[0442] The source insulating film 232 is formed in a film shape on the inner wall of the source trench 231 and partitions a recessed space in the source trench 231. Specifically, the source insulating film 232 has a window portion 232a that exposes the first trench portion 231a and partitions a recessed space in the second trench portion 231b.

[0443] Specifically, the source insulating film 232 includes the aforementioned first portion 234 and second portion 235. The first portion 234 covers the side wall of the source trench 231 (second trench portion 231b) and partitions the window portion 232a on the opening side (first trench portion 231a side) of the source trench 231. The second portion 235 covers the bottom wall of the source trench 231 (second trench portion 231b).

[0444] The source electrode 233 is embedded in the source trench 231 with the source insulating film 232 interposed therebetween. Specifically, the source electrode 233 is embedded in the first trench portion 231a and the second trench portion 231b with the source insulating film 232 interposed therebetween, and has a contact portion 233a that contacts the first trench portion 231a exposed from the window portion 232a.

[0445] In this embodiment, the body region 250 covers the first trench portion 231a of the second trench structure 230. The body region 250 is electrically connected to the contact portion 233a of the source electrode 233 exposed from the first trench portion 231a. As a result, the body region 250 is source-grounded within the SiC chip 202. The body region 250 may cover a part of the second trench portion 231b and face the source electrode 233 with a part of the source insulating film 232 interposed therebetween.

[0446] In this embodiment, each source region 251 covers the first trench portion 231a of the second trench structure 230 and is electrically connected to the contact portion 233a of the source electrode 233. As a result, each source region 251 is source-grounded within the SiC chip 202.

[0447] In this form, each contact region 252 is formed along the first trench portion 231a and the second trench portion 231b of each second trench structure 230. The portion covering the first trench portion 231a in each contact region 252 is electrically connected to the contact portion 233a, the body region 250, and the source region 251. That is, each contact region 252 is source-grounded within the SiC chip 202. The portion covering the second trench portion 231b in each contact region 252 faces the source electrode 233 with the source insulating film 232 interposed therebetween.

[0448] In this form, each well region 253 covers each second trench structure 230 (the first trench portion 231a and the second trench portion 231b) with a plurality of contact regions 252 interposed therebetween. That is, each well region 253 includes a portion directly covering the second trench structure 230 and a portion covering the second trench structure 230 with the contact region 252 interposed therebetween.

[0449] The portion covering the first trench portion 231a in each well region 253 is connected to the body region 250. That is, each contact region 252 is source-grounded within the SiC chip 202. The portions covering the bottom walls of the plurality of second trench structures 230 (the second trench portions 231b) in the plurality of well regions 253 are formed at a substantially constant depth.

[0450] In this form, the first inorganic insulating film 280 covers the plurality of first trench structures 220, the plurality of source regions 251, the plurality of contact regions 252, and the trench end structure 255 on the active surface 206. Specifically, the first inorganic insulating film 280 covers the entire source region 251 and the entire contact region 252 in a cross-sectional view along the second direction Y.

[0451] Further, the first inorganic insulating film 280 covers the entire source region 251 and the entire contact region 252 in plan view. The first inorganic insulating film 280 is further drawn from above the active surface 206 onto the second trench structure 230 and covers the edge of the source electrode 233 (i.e., the contact portion 233a). In this form, the first inorganic insulating film 280 covers the edge of the source electrode 233 over the entire circumference of the second trench structure 230.

[0452] In this form, the plurality of source contact openings 284 expose the plurality of second trench structures 230 in a one-to-one correspondence. Each source contact opening 284 is formed in a region surrounded by the side walls of the second trench structure 230 in plan view. Specifically, each source contact opening 284 is formed at an interval inward from the side wall of the second trench structure 230 and exposes only the source electrode 233. Each source contact opening 284 may be formed in a strip shape extending along each second trench structure 230.

[0453] In this form, the source main surface electrode 303 enters the plurality of source contact openings 284 from above the first inorganic insulating film 280 and is electrically connected only to the plurality of source electrodes 233. Thereby, the source potential is transmitted to the body region 250, the plurality of source regions 251, the plurality of contact regions 252, and the plurality of well regions 253 through the contact portions 233a of the plurality of source electrodes 233.

[0454] Regarding other structures, since they are the same as those of the aforementioned SiC semiconductor device 201, the description of those structures is omitted. As described above, the SiC semiconductor device 431 also exhibits the same effects as those described for the SiC semiconductor device 201. Further, the SiC semiconductor device 431 has a contact portion 233a in which the source electrode 233 is exposed from the side wall of the source trench 231 in the region on the opening side of the source trench 231.

[0455] According to such a structure, the semiconductor region to be source-grounded can be source-grounded within the SiC chip 202 by the contact portion 233a of the source electrode 233. In this form, the body region 250, the source region 251, the contact region 252, and the well region 253 are electrically connected to the source electrode 233 within the SiC chip 202. Such a structure is effective in relaxing the alignment margins such as the body region 250, the source region 251, the contact region 252, the well region 253, and the source contact opening 284. The structure of the SiC semiconductor device 431 can also be applied to the seventh to ninth embodiments.

[0456] FIG. 26 corresponds to FIG. 14 and is a cross-sectional view for explaining an SiC semiconductor device 441 according to the eleventh embodiment of the present invention. Hereinafter, for the structures corresponding to the structures described for the SiC semiconductor device 201, the same reference numerals are given, and their descriptions are omitted.

[0457] Referring to FIG. 26, the SiC semiconductor device 441 according to the eleventh embodiment includes a gate electrode 223 including p-type polysilicon doped with p-type impurities. Specifically, the gate electrode 223 is made of p-type polysilicon. The p-type impurity concentration of the p-type polysilicon of the gate electrode 223 may be 1×10 18 cm -3 or more and 1×10 22 cm -3 or less. The sheet resistance of the gate electrode 223 may be 10 Ω / □ or more and 500 Ω / □ or less.

[0458] The SiC semiconductor device 441 includes a source electrode 233 including the same conductive material as the gate electrode 223. That is, the source electrode 233 includes p-type polysilicon doped with p-type impurities. Specifically, the source electrode 233 is made of p-type polysilicon. The p-type impurity concentration of the p-type polysilicon of the source electrode 233 may be 1×10 18 cm -3 or more and 1×10 22 cm -3 or less. The sheet resistance of the source electrode 233 may be 10 Ω / □ or more and 500 Ω / □ or less.

[0459] The SiC semiconductor device 441 includes a first low-resistance layer 442 that covers the gate electrode 223. The first low-resistance layer 442 covers the gate electrode 223 within the gate trench 221. That is, the first low-resistance layer 442 forms a part of the first trench structure 220. The first low-resistance layer 442 is in contact with the gate insulating film 222 within the gate trench 221. Preferably, the first low-resistance layer 442 is in contact with the corner portion of the gate insulating film 222 (that is, the third portion 226).

[0460] The first low-resistance layer 442 includes a conductive material having a sheet resistance lower than that of the gate electrode 223. The sheet resistance of the first low-resistance layer 442 may be 0.01 Ω / sq or more and 10 Ω / sq or less. Preferably, the first low-resistance layer 442 has a specific resistance of 10 μΩ·cm or more and 110 μΩ·cm or less. In this form, the first low-resistance layer 442 is composed of a polysilicide layer (specifically, a p-type polysilicide layer) in which the surface layer portion of the gate electrode 223 is silicided with a metal. That is, the first low-resistance layer 442 is integrally formed with the gate electrode 223 at the surface layer portion of the gate electrode 223 and forms the electrode surface of the gate electrode 223.

[0461] The first low-resistance layer 442 may include at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. Preferably, the first low-resistance layer 442 includes at least one of NiSi, CoSi2, and TiSi2. Particularly preferably, the first low-resistance layer 442 is composed of CoSi2.

[0462] The SiC semiconductor device 441 includes a second low-resistance layer 443 that covers the source electrode 233. The second low-resistance layer 443 covers the source electrode 233 within the source trench 231. That is, the second low-resistance layer 443 forms a part of the second trench structure 230. The second low-resistance layer 443 may be in contact with the source insulating film 232 (that is, the second portion 235) within the source trench 231.

[0463] The second low-resistance layer 443 includes a conductive material having a sheet resistance less than that of the source electrode 233. The sheet resistance of the second low-resistance layer 443 may be 0.01 Ω / sq or more and 10 Ω / sq or less. The second low-resistance layer 443 preferably has a specific resistance of 10 μΩ·cm or more and 110 μΩ·cm or less. In this form, the second low-resistance layer 443 is composed of a polysilicide layer (specifically, a p-type polysilicide layer) in which the surface layer portion of the source electrode 233 is silicided with a metal. That is, the second low-resistance layer 443 is integrally formed with the source electrode 233 at the surface layer portion of the source electrode 233 and forms the electrode surface of the source electrode 233.

[0464] The second low-resistance layer 443 may contain at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2. The second low-resistance layer 443 preferably contains at least one of NiSi, CoSi2, and TiSi2. The second low-resistance layer 443 particularly preferably consists of CoSi2. The second low-resistance layer 443 preferably consists of the same material as the first low-resistance layer 442. In such a structure, the p-type impurity concentration in the body region 250 is preferably less than the p-type impurity concentrations of the gate electrode 223 and the source electrode 233.

[0465] As described above, the SiC semiconductor device 441 exhibits the same effects as those described for the SiC semiconductor device 201. The SiC semiconductor device 441 includes a gate electrode 223 containing p-type polysilicon and a first low-resistance layer 442 covering the gate electrode 223.

[0466] According to the gate electrode 223 containing p-type polysilicon, the sheet resistance in the gate trench 221 increases while the gate threshold voltage Vth can be increased by about 1 V as compared with the case of an n-type polysilicon. According to the first low-resistance layer 442, the parasitic resistance in the gate trench 221 can be reduced while suppressing a decrease in the gate threshold voltage Vth. Therefore, according to the SiC semiconductor device 441, the parasitic resistance in the gate trench 221 can be reduced while increasing the gate threshold voltage Vth.

[0467] The first low-resistance layer 442 and the second low-resistance layer 443 related to the SiC semiconductor device 441 can also be applied to the seventh to tenth embodiments. When the first low-resistance layer 442 and the second low-resistance layer 443 are applied to the SiC semiconductor device 431 according to the tenth embodiment, the second low-resistance layer 443 forms a contact portion 233a that contacts the first trench portion 231a together with the source electrode 233. That is, the body region 250, the source region 251, the contact region 252, the well region 253, etc. are each source-grounded to the second low-resistance layer 443 within the SiC chip 202.

[0468] FIG. 27 is a plan view of the semiconductor package 501 as viewed from one side. FIG. 28 is a plan view of the semiconductor package 501 shown in FIG. 27 as viewed from the other side. FIG. 29 is a perspective view of the semiconductor package 501 shown in FIG. 27. FIG. 30 is an exploded perspective view of the semiconductor package 501 shown in FIG. 27. FIG. 31 is a cross-sectional view taken along line XXXI-XXXI shown in FIG. 27. FIG. 32 is a circuit diagram of the semiconductor package 501 shown in FIG. 27.

[0469] Referring to FIGS. 27 to 32, in this embodiment, the semiconductor package 501 has a form called a power guard package. The semiconductor package 501 includes a resin package body 502. The package body 502 is made of a molding resin including a filler (for example, an insulating filler) and a matrix resin. The matrix resin is preferably made of an epoxy resin.

[0470] The package body 502 has a first main surface 503 (first surface) on one side, a second main surface 504 (second surface) on the other side, and first to fourth side surfaces 505A to 505D connecting the first main surface 503 and the second main surface 504. The first main surface 503 and the second main surface 504 are formed in a rectangular shape (a rectangular shape in this embodiment) in a plan view as viewed from their normal direction Z.

[0471] The first side surface 505A and the second side surface 505B extend along a first direction X along the first main surface 503 and face a second direction Y that intersects (specifically, is orthogonal to) the first direction X. The first side surface 505A and the second side surface 505B form the long sides of the package body 502. The third side surface 505C and the fourth side surface 505D extend along the second direction Y and face the first direction X. The third side surface 505C and the fourth side surface 505D form the short sides of the package body 502.

[0472] The semiconductor package 501 includes a first metal plate 510 disposed within the package body 502. The first metal plate 510 is disposed on the first main surface 503 side of the package body 502 and integrally includes a first heat dissipation portion 511 and a first terminal portion 512. The first heat dissipation portion 511 is disposed within the package body 502 so as to be exposed from the first main surface 503. The first heat dissipation portion 511 has a planar area less than the planar area of the first main surface 503 and is exposed from the first main surface 503 with a space inward from the first to fourth side surfaces 505A to 505D. The first heat dissipation portion 511 is formed in a rectangular shape extending in the first direction X in plan view.

[0473] The first terminal portion 512 is drawn out in a strip shape extending in the second direction Y from the first heat dissipation portion 511 so as to penetrate the first side surface 505A and straddles the inside and outside of the package body 502. When a center line LC that crosses the center portion of the first side surface 505A (the second side surface 505B) in the second direction Y is set, the first heat dissipation portion 511 is disposed on the fourth side surface 505D side with respect to the center line LC.

[0474] The first terminal portion 512 has a first length L1 in the second direction Y. The width of the first terminal portion 512 in the first direction X is less than the width of the first heat dissipation portion 511 in the first direction X. The first terminal portion 512 is connected to the first heat dissipation portion 511 via a first bending portion 513 that is bent from the first main surface 503 side to the second main surface 504 side within the package body 502. Thereby, the first terminal portion 512 is exposed from the first side surface 505A with a space from the first main surface 503 to the second main surface 504 side.

[0475] The semiconductor package 501 includes a second metal plate 520 disposed within the package body 502. The second metal plate 520 integrally includes a second heat radiating portion 521 and a second terminal portion 522, and is disposed on the second main surface 504 side of the package body 502 with a space from the first metal plate 510. The second heat radiating portion 521 is disposed within the package body 502 so as to be exposed from the second main surface 504.

[0476] The second heat radiating portion 521 has a planar area less than the planar area of the second main surface 504, and is exposed from the second main surface 504 with a space inward from the first to fourth side surfaces 505A to 505D. The second heat radiating portion 521 is formed in a rectangular shape extending in the first direction X in a plan view. The second terminal portion 522 is drawn out from the second heat radiating portion 521 in a strip shape extending in the second direction Y so as to penetrate the first side surface 505A, and straddles the inside and outside of the package body 502. The second terminal portion 522 is disposed on the third side surface 505C side with respect to the center line LC.

[0477] In this form, the second terminal portion 522 has a second length L2 different from the first length L1 of the first terminal portion 512 with respect to the second direction Y. The first terminal portion 512 and the second terminal portion 522 are distinguishable from each other by their shapes (lengths). The second length L2 of the second terminal portion 522 may be greater than the first length L1, or may be less than the first length L1. Of course, a second terminal portion 522 having a second length L2 equal to the first length L1 may be formed.

[0478] The width of the second terminal portion 522 in the first direction X is less than the width of the second heat radiating portion 521 in the first direction X. The second terminal portion 522 is connected to the second heat radiating portion 521 via a second bent portion 523 bent from the second main surface 504 side to the first main surface 503 side within the package body 502. Thereby, the second terminal portion 522 is exposed from the second side surface 505B with a space from the second main surface 504 to the first main surface 503 side.

[0479] The second terminal portion 522 is drawn out from a thickness position different from that of the first terminal portion 512 with respect to the normal direction Z. In this form, the second terminal portion 522 is formed at a distance from the first terminal portion 512 toward the second main surface 504 side. The second terminal portion 522 does not face the first terminal portion 512 with respect to the first direction X.

[0480] The semiconductor package 501 includes one or a plurality (five in this form) of control terminals 530 disposed in the package body 502. The plurality of control terminals 530 are exposed from the second side surface 505B opposite to the first side surface 505A where the first terminal portion 512 and the second terminal portion 522 are exposed. The plurality of control terminals 530 are disposed on the third side surface 505C side with respect to the center line LC. The plurality of control terminals 530 are disposed on the same straight line as the second terminal portion 522 of the second metal plate 520 in a plan view. The arrangement of the plurality of control terminals 530 is arbitrary.

[0481] The plurality of control terminals 530 are each formed in a strip shape extending in the second direction Y. Specifically, the plurality of control terminals 530 each include an inner end portion 531, an outer end portion 532, and a lead portion 533. The inner end portion 531 is disposed in the package body 502. The outer end portion 532 is disposed outside the package body 502.

[0482] The lead portion 533 is drawn out from inside the package body 502 to outside the package body 502 so as to penetrate the second side surface 505B, and connects the inner end portion 531 and the outer end portion 532 inside and outside the package body 502. The lead portion 533 may have a curved portion 534 recessed toward the first main surface 503 and / or the second main surface 504 at a portion located outside the package body 502. Of course, a lead portion 533 without the curved portion 534 may be formed.

[0483] The plurality of control terminals 530 are drawn out from thickness positions different from those of the first heat dissipation part 511 and the second heat dissipation part 521 with respect to the normal direction Z. In this form, the plurality of control terminals 530 are arranged in the region between the first heat dissipation part 511 and the second heat dissipation part 521 at intervals from the first heat dissipation part 511 and the second heat dissipation part 521.

[0484] The semiconductor package 501 includes an SBD chip 541 disposed in the package body 502. The SBD chip 541 is composed of any one of the SiC semiconductor devices (reference numerals omitted) according to the first to fifth embodiments. The SBD chip 541 is disposed in the space sandwiched between the first heat dissipation part 511 and the second heat dissipation part 521 within the package body 502. In this form, the SBD chip 541 is disposed on the second heat dissipation part 521 with the second main surface electrode 70 facing the second heat dissipation part 521. The SBD chip 541 is disposed on the fourth side surface 505D side of the package body 502 with respect to the center line LC.

[0485] The semiconductor package 501 includes a MISFET chip 542 disposed in the package body 502 at an interval from the SBD chip 541. The MISFET chip 542 is composed of any one of the SiC semiconductor devices (reference numerals omitted) according to the sixth to eleventh embodiments. The MISFET chip 542 is disposed in the space sandwiched between the first heat dissipation part 511 and the second heat dissipation part 521 within the package body 502. In this form, the MISFET chip 542 is disposed on the second heat dissipation part 521 with the second main surface electrode 380 facing the second heat dissipation part 521. The MISFET chip 542 is disposed on the third side surface 505C side of the package body 502 with respect to the center line LC.

[0486] The semiconductor package 501 includes a first conductive bonding material 543. The first conductive bonding material 543 is interposed between the second main surface electrode 70 of the SBD chip 541 and the second heat dissipation part 521, and thermally, mechanically, and electrically connects the SBD chip 541 to the second heat dissipation part 521. The first conductive bonding material 543 may include solder or a metal paste.

[0487] The semiconductor package 501 includes a second conductive bonding material 544. The second conductive bonding material 544 is interposed between the second main surface electrode 380 of the MISFET chip 542 and the second heat dissipation part 521, and thermally, mechanically and electrically connects the MISFET chip 542 to the second heat dissipation part 521. The second conductive bonding material 544 may include solder or a metal paste.

[0488] Thereby, the drain of the MISFET chip 542 is electrically connected to the cathode of the SBD chip 541. That is, the second metal plate 520 (the second terminal part 522) functions as a cathode-drain terminal for the SBD chip 541 and the MISFET chip 542.

[0489] The semiconductor package 501 includes a first metal spacer 551. The first metal spacer 551 may include a plate-like member containing copper. The first metal spacer 551 is interposed between the SBD chip 541 and the first heat dissipation part 511.

[0490] The semiconductor package 501 includes a second metal spacer 552. The first metal spacer 551 may include a plate-like member containing copper. The second metal spacer 552 preferably has a thickness substantially equal to the thickness of the first metal spacer 551. The second metal spacer 552 is provided at a distance from the first metal spacer 551 and is interposed between the MISFET chip 542 and the first heat dissipation part 511. In this form, the second metal spacer 552 is separate from the first metal spacer 551, but the second metal spacer 552 may be integrally formed with the first metal spacer 551.

[0491] The semiconductor package 501 includes a third conductive bonding material 553. The third conductive bonding material 553 is interposed between the pad electrode 60 of the SBD chip 541 and the first metal spacer 551, and thermally, mechanically and electrically connects the SBD chip 541 to the first metal spacer 551. The third conductive bonding material 553 may include solder or a metal paste. The third conductive bonding material 553 preferably consists of solder.

[0492] The semiconductor package 501 includes a fourth conductive bonding material 554. The fourth conductive bonding material 554 is interposed between the source pad electrode 362 of the MISFET chip 542 and the second metal spacer 552, thermally, mechanically, and electrically connecting the MISFET chip 542 to the second metal spacer 552. The fourth conductive bonding material 554 may include solder or a metal paste. Preferably, the fourth conductive bonding material 554 is composed of solder.

[0493] The semiconductor package 501 includes a fifth conductive bonding material 555. The fifth conductive bonding material 555 is interposed between the first heat dissipation part 511 and the first metal spacer 551, thermally, mechanically, and electrically connecting the first metal spacer 551 to the first heat dissipation part 511. The fifth conductive bonding material 555 may include solder or a metal paste.

[0494] The semiconductor package 501 includes a sixth conductive bonding material 556. The sixth conductive bonding material 556 is interposed between the first heat dissipation part 511 and the second metal spacer 552, thermally, mechanically, and electrically connecting the second metal spacer 552 to the first heat dissipation part 511. The sixth conductive bonding material 556 may include solder or a metal paste.

[0495] As a result, the source of the MISFET chip 542 is electrically connected to the anode of the SBD chip 541. That is, the first metal plate 510 (the first terminal part 512) functions as an anode-source terminal for the SBD chip 541 and the MISFET chip 542.

[0496] The semiconductor package 501 includes one or more (four in this form) conductive wires 557. The conductive wires 557 are also referred to as bonding wires. The conductive wires 557 may include at least one of a gold wire, a copper wire, and an aluminum wire. The plurality of conductive wires 557 are respectively connected to the inner ends 531 of the plurality of control terminals 530 and the gate pad electrode 361 of the MISFET chip 542.

[0497] As a result, the gate of the MISFET chip 542 is electrically connected to the plurality of control terminals 530. That is, the plurality of control terminals 530 each function as a gate terminal of the MISFET chip 542. The conductive wire 557 does not necessarily need to be connected to all the control terminals 530 and the gate pad electrode 361. Any of the control terminals 530 may be electrically open.

[0498] As described above, according to the semiconductor package 501, the first conductive bonding material 543 is connected to the pad electrode 60 of the SBD chip 541. The pad electrode 60 includes a Ni plating film 61 as described in the first to fifth embodiments. Thereby, the first conductive bonding material 543 can be appropriately connected to the pad electrode 60. Therefore, the SBD chip 541 can be appropriately thermally, mechanically, and electrically connected to the first heat radiating portion 511 and the second heat radiating portion 521. In particular, according to the pad electrode 60 including the external plating film 63, the affinity for the first conductive bonding material 543 can be enhanced.

[0499] When the SBD chip 541 does not include the organic insulating film 50, cracks, peeling, etc. may occur in the first main surface electrode 20, the pad electrode 60, etc. due to the filler contained in the package body 502. This type of problem is called filler attack and is one of the factors causing a decrease in the reliability of the first main surface electrode 20, the pad electrode 60, etc. Therefore, in the SBD chip 541, the organic insulating film 50 is formed. Thereby, since the organic insulating film 50 serves as a cushion against the filler, the first main surface electrode 20, the pad electrode 60, etc. can be appropriately protected.

[0500] Furthermore, in the SBD chip 541, as described in the first to fifth embodiments, in the structure including the organic insulating film 50, it has a structure in which the Ni plating film 61 is connected to the edge portion 51 of the second inorganic insulating film 30. Thereby, cracks, peeling, etc. of the Ni plating film 61 (external plating film 63) due to filler attack can also be appropriately suppressed.

[0501] Also, according to the semiconductor package 501, a second conductive bonding material 544 is connected to the source pad electrode 362 of the MISFET chip 542. The source pad electrode 362 includes a second Ni plating film 373 as described in the sixth to eleventh embodiments. Thereby, the second conductive bonding material 544 can be appropriately connected to the source pad electrode 362. Therefore, the MISFET chip 542 can be appropriately thermally, mechanically, and electrically connected to the first heat dissipation portion 511 and the second heat dissipation portion 521. In particular, according to the source pad electrode 362 including the second outer plating film 375, the affinity for the second conductive bonding material 544 can be enhanced.

[0502] When the MISFET chip 542 does not include the organic insulating film 340, cracks, peeling, etc. may occur in the plurality of first main surface electrodes 300, the source pad electrode 362, etc. of the MISFET chip 542 due to the filler contained in the package body 502. Therefore, in the MISFET chip 542, an organic insulating film 340 is formed on the second inorganic insulating film 320. Thereby, since the organic insulating film 340 serves as a cushion against the filler, the plurality of first main surface electrodes 300, the source pad electrode 362, etc. can be appropriately protected.

[0503] Furthermore, in the MISFET chip 542, as described in the sixth to eleventh embodiments, in the structure including the organic insulating film 340, the second Ni plating film 373 is connected to the second inner covering portion 325 of the second inorganic insulating film 320. Thereby, cracks, peeling, etc. of the second Ni plating film 373 (the second outer plating film 375) due to filler attack can also be appropriately suppressed. In the MISFET chip 542, the same effect as that on the source pad electrode 362 side is achieved also on the gate pad electrode 361 side.

[0504] In this form, an example in which the semiconductor package 501 includes the SBD chip 541 and the MISFET chip 542 has been described. However, a semiconductor package 501 including only one of the SBD chip 541 and the MISFET chip 542 may be adopted. Also, a semiconductor package 501 including a plurality of SBD chips 541 and / or a plurality of MISFET chips 542 may be adopted.

[0505] The SBD chip 541 is not limited to the semiconductor package 501 having a power guard form, and may be mounted on TO (Transistor Outline), SOP (Small Outline Package), QFN (Quad Flat Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package), or SOJ (Small Outline J-leaded Package), or various packages similar thereto.

[0506] The MISFET chip 542 is not limited to the semiconductor package 501 having a power guard form, and may be mounted on TO (Transistor Outline), SOP (Small Outline Package), QFN (Quad Flat Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package), or S...

Claims

1. A coating target, An electrode that covers the coating target and has an electrode side wall on the coating target, An inorganic insulating film having an inner coating portion that covers the electrode and exposes the electrode side wall, An organic insulating film that covers the electrode side wall, and includes, The organic insulating film covers the inner coating portion, an electronic component.

2. The inner coating portion exposes the peripheral portion of the electrode, The organic insulating film covers the peripheral portion of the electrode, the electronic component according to claim 1.

3. The inner coating portion exposes the inner portion of the electrode, the electronic component according to any one of claims 1 or 2.

4. The inner coating portion surrounds the inner portion of the electrode, the electronic component according to claim 3.

5. The organic insulating film exposes the edge portion of the inner coating portion on the inner side portion of the electrode, the electronic component according to claim 3 or 4.

6. The inorganic insulating film has an outer coating portion that covers the coating target so as to expose the electrode side wall, the electronic component according to any one of claims 1 to 5.

7. The organic insulating film covers the outer coating portion, the electronic component according to claim 6.

8. The outer coating portion covers the coating target with a space from the electrode side wall, The organic insulating film covers a portion exposed between the electrode and the outer coating portion in the coating target, the electronic component according to claim 6 or 7.

9. The outer coating portion surrounds the electrode in a plan view, the electronic component according to any one of claims 6 to 8.

10. A coating target, An electrode that covers the coating target and has an electrode side wall on the coating target, An inorganic insulating film that covers the coating target so as to expose the electrode side wall, An organic insulating film that covers the inorganic insulating film and the electrode and covers the electrode side wall between the inorganic insulating film and the electrode, an electronic component.

11. The inorganic insulating film covers the coating target with a space from the electrode side wall, The organic insulating film covers the coating target between the electrode and the inorganic insulating film, the electronic component according to claim 10.

12. The inorganic insulating film surrounds the electrode in a plan view, the electronic component according to claim 10 or 11.

13. An electrode having an electrode side wall, An inorganic insulating film that exposes the inner portion of the electrode and covers the electrode so as to expose the electrode side wall of the electrode, Exposing the inner part of the electrode, and an organic insulating film covering the side wall of the electrode, and a pad electrode formed on the inner part of the electrode, wherein the organic insulating film covers the inorganic insulating film so as to expose an edge portion of the inorganic insulating film on the inner part side of the electrode, and the pad electrode covers the edge portion of the inorganic insulating film, an electronic component.

14. The pad electrode is in contact with the inorganic insulating film, the electronic component according to claim 13.

15. The pad electrode is in contact with the organic insulating film, the electronic component according to claim 13 or 14.

16. The inorganic insulating film covers the electrode with a space from the side wall of the electrode, and the organic insulating film covers a portion exposed between the side wall of the electrode and the inorganic insulating film in the electrode, the electronic component according to any one of claims 13 to 15.

17. The inorganic insulating film surrounds the inner part of the electrode in a plan view, the electronic component according to any one of claims 13 to 16.

18. The pad electrode includes a Ni plating film in contact with the inorganic insulating film, the electronic component according to any one of claims 13 to 17.

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