Apparatus, method, and computer software product for testing a device under test

Abstract

To provide an apparatus for generating Automatic Test Equipment (ATE) testing patterns used in an electronic device-under-test, a method, and a computer software product.SOLUTION: An electric device-under-test includes electrical circuitry, at least one input port, and at least one output port. An apparatus includes a memory and a processor. The memory is configured to store (i) a hardware verification language (HVL) model of an integrated circuit, including a model input which models at least one DUT input port and a model output which models at least one OUT output port, the HVL model configured to determine, obliviously to the electrical circuitry, a logic state of the model output responsively to a logic state of the model input, and (ii) a simulation program configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE testing pattern for the DUT by executing the simulation program.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to electrical testing, and more particularly, to a method and system for generating integrated circuit test patterns.

Background Art

[0002] Integrated circuits (ICs) can be tested at the wafer level (“wafer sort”) and at the package unit level using an automatic test equipment (ATE) that executes test patterns.

[0003] U.S. Patent No. 6,205,407 discloses a system and method for generating test code for testing electronic devices on an automatic test equipment (ATE) platform. This system and method translate scan and pattern test data into test code based on user-defined settings. The test data is preferably from a test data generation program such as automatic test pattern generation (ATPG) or a simulation program that generates test data. The test data is streamed to the system in serial fashion by using function calls embedded in the test data generation program. The user preferably defines the desired ATE platform type and other custom formatting functions for the output data using a graphical user interface (GUI). Preferably, the translation that runs concurrently with the test data generation plan creates the test code in the same way the test data is generated.

[0004] U.S. Patent No. 6,925,617 discloses a method for generating test patterns for use in integrated circuit (IC) design using a functional verification program. The functional verification program includes a stimulus generator, an expected-response generator, and an interface that defines the ports of the IC design. The method includes (a) converting input ports within the interface to bidirectional in / out ports, (b) supplying stimuli to the converted in / out ports and the original in / out ports within the interface by executing the stimulus generator, (c) sampling the stimuli supplied to the converted in / out ports and the original in / out ports, and (d) recording the sampled stimuli. The method may further include (e) generating a bidirectional shadow port within the interface, the shadow port corresponding to the in / out ports and output ports of the IC design, (f) supplying an expected response to the shadow port by executing the expected-response generator, (g) sampling the expected response from the shadow port, and (h) recording the sampled expected response. SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] The present invention provides an apparatus, a method, and a computer software product for testing a device under test to generate ATE test patterns for use in the device under test. MEANS FOR SOLVING THE PROBLEMS

[0006] The present invention provides an apparatus for generating an automatic test equipment (ATE) test pattern to test a device under test (DUT) including an electrical circuit, at least one input port, and at least one output port. The apparatus includes a memory and a processor. The memory is configured to store (i) a hardware verification language (HVL) model of an integrated circuit (IC) including model inputs that model at least one input port and model outputs that model at least one output port, and configured to determine the logical state of the model outputs in response to the logical state of the model inputs, ignoring the electrical circuit, and (ii) a simulation program configured to simulate the HVL model of the DUT. The processor is configured to generate an ATE test pattern for use with the DUT by executing the simulation program.

[0007] The present invention provides a method for generating an automatic test equipment (ATE) test pattern to test a device under test (DUT) including an electrical circuit, at least one input port, and at least one output port. The method includes storing in a memory an HVL model of an integrated circuit including model inputs that model at least one input port and model outputs that model at least one output port, and configured to determine the logical state of the model outputs in response to the logical state of the model inputs, ignoring the electrical circuit. The method further includes storing in the memory a simulation program configured to simulate the HVL model of the DUT. An ATE test pattern for use with the DUT is generated by executing the simulation program.

[0008] The present invention provides a computer software product for generating an automatic test equipment (ATE) test pattern to test a device under test (DUT) including an electrical circuit, at least one input port, and at least one output port. The computer software product includes a tangible non-transitory computer-readable medium storing program instructions, which, when read by a processor, include a model input for modeling at least one input port and a model output for modeling at least one output port, and store in memory a hardware verification language (HVL) model of an integrated circuit (IC) configured to determine a logical state of the model output in response to a logical state of the model input while ignoring the electrical circuit, further store in memory a simulation program configured to simulate the HVL model of the DUT, and cause the processor to generate an ATE test pattern for use with the DUT by executing the simulation program.

Advantages of the Invention

[0009] Based on the above, an ATE pattern file for use in ATE can be generated in a relatively short time.

Brief Description of the Drawings

[0010] The accompanying drawings are included to further understand the principles of the present invention, are incorporated herein, and constitute a part hereof. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention.

[0011]

Figure 1

Figure 2

Figure 3

Embodiments for Carrying Out the Invention

[0012] An automatic test equipment (ATE) is widely used for production testing of integrated circuits (ICs) and other electronic devices (collectively referred to as devices under test (DUTs) in test technical terms). The ATE drives the input ports of the DUT and checks whether the output ports are at preset levels (the input and output ports are also referred to as "terminals", "pads", or "pins").

[0013] A list of values applied to the DUT input and expected response values of the DUT output is usually listed in a CSV (comma - separated - value) test pattern file.

[0014] One method of generating a test pattern file for testing a DUT includes performing a functional test of the DUT on a DUT simulation model that models the circuit of the DUT, monitoring the inputs and outputs of the DUT model, and generating corresponding test patterns. However, the simulation of a DUT that includes millions or sometimes billions of devices can take a fairly long time.

[0015] Embodiments of the present invention provide a method and apparatus for quickly generating functional test patterns for a DUT. In one embodiment, a computer simulates a hardware verification language (HVL) model of an integrated circuit (also known as a high - level verification language model), ignores the circuit of the DUT, and defines the response of the DUT to any stimulus. In some embodiments, the HVL model simulates substantially faster than a model that simulates the circuit of the DUT.

[0016] In an embodiment, the computer can hold a simulation temporary I / O log file and then execute a translation program that translates the temporary I / O log file into an ATE test pattern.

[0017] System Description

[0018] The embodiments disclosed herein relate to the generation of test patterns for use in the automatic testing of integrated circuits. However, the disclosed techniques can also be used for the generation of test patterns for use in the automatic testing of systems (e.g., multi-chip modules (MCMs)) or any other arbitrary electronic circuits.

[0019] FIG. 1 is a hardware-centric block diagram of a system 100 for use in generating test patterns for an integrated circuit according to one embodiment of the present invention.

[0020] A user 102 (e.g., a test engineer) communicates with a computer 104 via a human interface (including a monitor, a pointing device, and a keyboard). The computer 104 includes a processor 108 and a memory 110. (The computer 104 and the human interface 106, which include various hardware and software elements, may hereinafter also be referred to as an apparatus for generating an ATE test pattern.)

[0021] The user 102 wishes to generate a test pattern by an automatic test equipment (ATE) 114 and test a device under test (DUT) 112 (e.g., an IC). The test pattern is typically formatted in the CSV file format, and the CSV file includes input stimuli applied to the DUT input and response outputs expected to be generated by the DUT (the DUT 112 may include bidirectional ports that are driven by the input stimuli and generate response outputs. The treatment of the bidirectional ports according to one embodiment will be described below).

[0022] According to the embodiment shown in FIG. 1, user 102 executes software stored in memory 110 of computer 104 to generate test patterns. The software includes a hardware verification language (HVL) model 116 and an HVL simulator 118 of DUT 112. In an embodiment, the HVL model of the DUT ignores the actual electrical circuit and describes the input / output behavior of the DUT. That is, different circuit implementations that output the same output when given the same input are described by the same HVL model.

[0023] DUT 112 includes various internal circuits and calculates and outputs binary numbers and logic instructions on the output pins of the DUT in response to the input binary numbers and input instructions applied to the input pins of the DUT and in response to the internal state of the DUT. The HVL model is configured to generate the same number of outputs and instructions without requiring knowledge of the DUT circuit and functionality.

[0024] As a simple example, the DUT may include a hardware driver that divides two numbers, or a circuit that implements a hardware division algorithm. The HVL model may include the same statement A = B / C for both implementations to achieve the same result. In contrast, a structural model of the DUT (e.g., a Verilog model) typically includes models of all internal DUT circuits. Therefore, simulation of the structural level model is much slower than simulation of the HVL level model. In some cases, HVL level simulation is at least 100 times faster.

[0025] An example of a language for writing an HVL model (and for generating tests to test the model) is the e language (e.g., the e language reference is, for example, "Elementary e Language Reference Draft - CSE IIT Kgp"; "e Basics" which describes the basic structure of the language in Chapter 2). Alternatively, any other suitable type of HVL may be used.

[0026] Memory 110 further stores an HVL simulator 118 configured to simulate HVL model 116, and a stimuli file 120 including the input vectors applied to the input ports of HVL model 116 by HVL simulator 118.

[0027] When processor 108 of computer 104 uses HVL simulator 118 and applies stimuli file 120 to simulate HVL model 116, HVL simulator 118 monitors the input and output ports of the DUT model and stores the monitored values in an input / output port log file 122 (also referred to as a temporary I / O log file). In some embodiments, HVL simulator 118 adds high-level debug data to the temporary I / O log file (e.g., if the DUT is processor-executed software, HVL simulator 118 can add the processor instructions corresponding to the monitored I / O values). As will be described later, by using such additional high-level debug data, the debugging of test patterns can be facilitated.

[0028] When the simulation is successfully completed, user 102 can execute a translation program 124 that reads the I / O log file and generates an ATE pattern file 126 (a CSV format file), which can then be downloaded by ATE 114. (The I / O log file can also be used for debugging if problems are found.) Therefore, by using the HVL model and translation program 124 instead of the structural model of the DUT, user 102 can generate the ATE pattern file 126 of ATE 114 in a relatively short time. By using the temporary I / O log file, the debugging of the test program can be facilitated.

[0029] The arrangement of the system 100 shown in FIG. 1 and described above is an example cited for clarity of concept. In alternative embodiments, other arrangements may be used. For example, ATE pattern generation (using computer 104) and test execution (using ATE 114) can be performed at different locations. That is, the connection between computer 104 and ATE 114 in FIG. 1 may be a logical connection (e.g., by any method of file transfer) and need not be a physical connection.

[0030] As another example, each component of memory 110 may be distributed across multiple computers. Some, or all, of the components can be stored in a communication network “cloud”. In some embodiments, HVL does not require a stimulus file, for example, because it includes automatic generation of test patterns using randomly generated tests.

[0031] FIG. 2 is a software - centric block diagram of a system 200 used for ATE pattern generation according to one embodiment of the present invention. The HVL simulator 202 simulates the HVL model 204 by applying stimuli from the stimulus file 206 and using the arrangement set by the configuration file 208. In some embodiments, the configuration file 208 can select one of several DUT arrangement options and / or one of several simulator options.

[0032] The stimulus and response monitor 210 monitors the states of the DUT model ports (inputs and outputs) and saves the monitored values to a temporary I / O log file 212 (in some embodiments, the temporary I / O log file may further include high - level debug simulation data). The translation program 214 then translates the I / O log file into an ATE pattern file 216 (e.g., a CSV - format file). The translation program typically includes scripts written in some scripting language (e.g., PowerShell, AWK, or PERL).

[0033] The arrangement of the system 200 shown in FIG. 2 and described above is an example arrangement cited for illustration purposes. In alternative embodiments, other arrangements may be used. In some embodiments, for example, there is no configuration file. Instead, typically, before starting a simulation, the user is prompted by the simulation program to enter the placement options. In another embodiment, there is no configuration file because the placement is fixed. In one embodiment, the stimulus file is generated by the simulation software (e.g., when the simulator is configured to generate random test patterns).

[0034] Debug

[0035] In some embodiments, the HVL simulator inserts high-level debug simulation data into a temporary I / O log file regarding the monitored I / O values. For example, if the DUT is a processor, the temporary I / O file may include lines regarding the I / O values over a continuous period, and each line may include the corresponding processor instruction.

[0036] If the test program fails, the temporary I / O file can be used to debug the test pattern. In an embodiment, such debugging can be done more easily than debugging an ATE test pattern that does not include high-level simulation data.

[0037] Bidirectional port

[0038] In some embodiments, the DUT can include bidirectional ports and thus can function as an input to or an output from the DUT at different times. In one embodiment, the HVL model of the DUT includes a direction indication for use with each such bidirectional pin (sometimes a single indication determines the direction of a group of ports, e.g., a bidirectional data bus).

[0039] In some embodiments, the HVL simulator monitors the direction indication signal and then saves it to the temporary I / O log file 212, and the translation program 214 adds the direction indication sequence to the ATE pattern file 216. The ATE drives the bidirectional port only when the corresponding direction indication indicates that the port is an input.

[0040] Method description

[0041] FIG. 3 is a flowchart 300 of a method used for ATE pattern generation according to one embodiment of the present invention. This flow is executed by the computer 104 (FIG. 1).

[0042] The flow starts with an operation 302 of obtaining an HVL model, and the computer receives the HVL model of the device under test (DUT). The HVL model is configured to model the behavior of the DUT output port in response to the stimulus applied at the DUT input port, ignoring the internal structure of the DUT. (Typically, the accuracy of the HVL model is verified during the development stage of the DUT.)

[0043] In an embodiment, the HVL is written in the e language. In another embodiment, any other suitable HVL language may be used.

[0044] Next, in an operation 304 of obtaining a stimulus file, the computer receives a file that describes the stimulus applied to the DUT input port. Usually, the stimulus file is created by a test engineer and is designed to execute the functional test of the DUT.

[0045] The computer then executes a simulation program that uses the HVL model to simulate DUT operations in the stimulating operation 306. The computer applies the stimuli defined in the stimulus file, monitors all inputs and outputs, and saves the logical states of the inputs and outputs to a temporary I / O log file. Finally, in the operation 308 to convert to an ATE pattern, the computer executes a translation program that converts the temporary I / O log file into a test pattern (e.g., a CSV file) compatible with the ATE. In one embodiment, the conversion program is written in a scripting language (e.g., PowerShell, AWK, or PERL).

[0046] The flowcharts shown in FIG. 3 and described above are cited for purposes of illustration. In alternative embodiments, other flowcharts may be used. For example, in some embodiments, the translation of the temporary I / O log to an ATE test pattern can be gradually completed whenever the simulator outputs the input and output logic values.

[0047] The arrangement of the test pattern generation system including the computer 104, the content of the memory 110, and the flowchart 300 shown in FIGS. 1 - 3 and described above are merely examples of the arrangements and flowcharts shown for purposes of clarifying the concept. In alternative embodiments, any other suitable arrangements and flowcharts may be used. Different subunits of the computer 104 can be implemented using appropriate hardware, e.g., in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs), using software, using hardware, or using a combination of hardware and software elements.

[0048] Computer 104 can include one or more general-purpose processors programmed with software to perform the functions described herein. The software may be downloaded to the processor in electronic form, over a network, or from a host, or alternatively, and / or additionally, may be provided and / or stored on a tangible, transient medium such as magnetic, optical, or electronic memory.

[0049] It will be understood that the above-described embodiments are cited for purposes of illustration and that the invention is not limited to what has been particularly shown and described above. Rather, the scope of the invention includes both combinations and sub-combinations of the various features described above, as well as modifications and variations not disclosed in the prior art that will occur to those of skill in the art upon reading the above description. Documents incorporated by reference into this patent application are considered to be a part of this application, except that in the event that any term is defined in these incorporated documents in a manner that conflicts with the explicit or implicit definitions made herein, only the definitions made herein shall be considered.

Industrial Applicability

[0050] The apparatus, method, and computer software product of the present invention can be applied to the testing of a device under test.

Explanation of Signs

[0051] 100 System 102 User 104 Computer 106 Human Interface 108 Processor 110 Memory 112 DUT 114 ATE 116 HVL Model 118 HVL Simulator 120 Stimulus File 122 Input / Output Port Log File 124 Translation Program 126 ATE Pattern File 200 System 202 HVL Simulator 204 HVL Model 206 Stimulus File 208 Configuration File 210 Monitor 212 Temporary I / O Log File 214 Translation Program 216 ATE Pattern File 300 Flowchart 302 Operation to Obtain HVL Model 304 Operation to Obtain Stimulus File 306 Operation to Stimulate 308 Operation to Convert to ATE Pattern

Claims

1. An apparatus for generating an automatic test equipment (ATE) test pattern and testing a device under test (DUT) including an electrical circuit, at least one input port, and at least one output port, comprising: a hardware verification language (HVL) model of an integrated circuit including a model input for modeling the at least one input port and a model output for modeling the at least one output port, configured to determine a logical state of the model output in response to a logical state of the model input, ignoring all internal structures of the DUT including the electrical circuit; a simulation program configured to simulate the HVL model of the DUT; a memory configured to store; a processor configured to generate an ATE test pattern for use with the DUT by executing the simulation program; wherein the processor is configured to store in the memory a log file including the logical state of the model output; the memory is further configured to read the log file and store a translation program for translating the logical states of the model input and the model output into the ATE test pattern; the memory is further configured to store a stimulus file including an input vector applied to the at least one input port, the apparatus being configured to display a stimulus applied to the model input.

2. The apparatus according to claim 1, wherein the processor is configured to generate the ATE test pattern by executing the translation program.

3. The apparatus according to claim 1, wherein the processor is configured to store in the log file high-level debug simulation data regarding monitored I / O values of the DUT.

4. The apparatus according to claim 1, wherein the memory is further configured to store a pattern file including the ATE test pattern.

5. The apparatus according to claim 1, wherein the ATE test pattern includes a CSV file.

6. A method for generating an automatic test equipment (ATE) test pattern and testing a device under test (DUT) including an electrical circuit, at least one input port, and at least one output port, the method comprising: Save in memory a hardware verification language (HVL) model of an integrated circuit that includes a model input for creating a model of at least one input port and a model output for creating a model of at least one output port, and is configured to determine the logical state of the model output in response to the logical state of the model input, ignoring all internal structures of the test electronic device including the electrical circuit. Further save in the memory a simulation program configured to simulate the HVL model of the test electronic device. Generate an ATE test pattern for use in the test electronic device by executing the simulation program. Save in the memory a log file including the logical state of the model output. Read the log file and save in the memory a translation program for translating the logical states of the model input and the model output into the ATE test pattern. Save in the memory a stimulus file including an input vector applied to the at least one input port to display the stimulus applied to the model input. A method including the above.

7. The method according to claim 6, wherein generating the ATE test pattern includes executing the translation program.

8. The method according to claim 6, further including saving in the log file high-level debug simulation data regarding monitored I / O values of the test electronic device.

9. The method according to claim 6, further including saving in the memory a pattern file including the ATE test pattern.

10. The method according to claim 6, wherein the ATE test pattern includes a CSV file.

11. A computer software product for generating an automatic test equipment (ATE) test pattern to test a test electronic device including an electrical circuit, at least one input port, and at least one output port, the computer software product including a tangible non-transitory computer-readable medium in which program instructions are stored, the program instructions, when read by a processor, Storing in a memory a hardware verification language (HVL) model of an integrated circuit that includes a model input for creating a model of the at least one input port and a model output for creating a model of the at least one output port, and is configured to determine a logical state of the model output in response to a logical state of the model input while ignoring all internal structures of the test electronic device including the electrical circuit. Further storing in the memory a simulation program configured to simulate the HVL model of the test electronic device. Generating an ATE test pattern for use in the test electronic device by executing the simulation program. Causing the processor to execute. The processor is configured to store in the memory a log file including the logical state of the model output. The memory is further configured to read the log file and store a translation program for translating the logical states of the model input and the model output into the ATE test pattern. The memory is further a computer software product configured to store a stimulus file including an input vector applied to the at least one input port and display the stimulus applied to the model input.

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