Communication between integrated circuit (IC) dies within a wafer-level fan-out package

Abstract

[0003] Embodiments described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fanout package. In one embodiment, an electronic device includes a wafer-level fanout package. The wafer-level fanout package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure is electrically connected to the transmitter circuit and the receiver circuit and includes a physical channel between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit a plurality of single-ended data signals and a differential clock signal to the receiver circuit through the physical channel. The receiver circuit is configured to capture data from the plurality of single-ended data signals using a first single-ended clock signal based on the differential clock signal.

Description

Technical Field

[0001] (Rights of the Government) The present invention was made with government support under Contract No. HR0011-19-3-0004 awarded by the Defense Advanced Research Projects Agency. The United States government has certain rights in this invention.

[0002] (Field of the Invention) Embodiments of the present disclosure generally relate to communication between integrated circuit (IC) dies within a wafer-level fan-out package.

Background Art

[0003] Recently, it has been observed that Moore's Law is slowing down. This slowdown has driven the integration of complex systems from system-on-chip (SoC) to multi-chip modules (MCMs) where different integrated circuit (IC) dies (or chips) are integrated within the same IC package. The advantages of MCMs include enabling heterogeneous integration of IC dies of different process nodes and improving yield by incorporating smaller IC dies with a lower probability of having defects.

[0004] Generally, the IC dies within an MCM need to communicate with each other. The footprint and thermal constraints of the MCM drive the need for high-density, high-bandwidth, and lower-power short-distance links for die-to-die communication. The ever-increasing data traffic in such die-to-die communication can make it more difficult to achieve such short-distance links for die-to-die communication.

[0005] To improve bandwidth density compared to conventional differential signaling, signaling techniques such as single-ended and code signaling have been used in the die-to-die transceiver. Theoretically, a signaling scheme with high pin efficiency can also be more power efficient because the amount of capacitive load that needs to be driven is reduced. However, the effectiveness of this signaling scheme depends greatly on the signal-to-noise ratio (SNR) of the received signal. Therefore, this signaling scheme can be very channel-dependent.

[0006] Another area that can limit bandwidth density and energy efficiency is packaging technology. The organic substrates commonly used by most MCMs as interconnects typically have relatively large line widths and spacings, which can limit the achievable bandwidth density and energy efficiency. SUMMARY OF THE INVENTION

[0007] The embodiments described herein generally relate to communication between integrated circuit (IC) dies within a wafer-level fan-out package. Various embodiments can achieve communications and / or corresponding structures that are power efficient and have high bandwidth density.

[0008] The embodiments described herein are electronic devices that include a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure is electrically connected to the transmitter circuit and the receiver circuit and includes a physical channel between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit a plurality of single-ended data signals and a differential clock signal through the physical channel to the receiver circuit. The receiver circuit is configured to capture data from the plurality of single-ended data signals using a first single-ended clock signal based on the differential clock signal.

[0009] Another embodiment described herein is an electronic device. The electronic device includes a first transceiver circuit in a first IC die, a second transceiver circuit in a second IC die, and a physical channel. The first IC die is disposed within a wafer-level fan-out package. The second IC die is disposed within the wafer-level fan-out package. The physical channel is within the redistribution structure of the wafer-level fan-out package. The first transceiver circuit is configured to transmit a plurality of first single-ended data signals and a first differential clock signal through a first subset of the physical channel to the second transceiver circuit. The second transceiver circuit is configured to transmit a plurality of second single-ended data signals and a second differential clock signal through a second subset of the physical channel to the first transceiver circuit. The second transceiver circuit is configured to capture data from the plurality of first single-ended data signals using a first single-ended clock signal based on the first differential clock signal. The first transceiver circuit is configured to capture data from the plurality of second single-ended data signals using a second single-ended clock signal based on the second differential clock signal.

[0010] Another embodiment described herein is a method of operating an electronic device. A differential clock signal is generated based on a first single-ended clock signal by a single-ended to differential converter circuit of a first transceiver circuit of a first IC die. The first IC die is disposed within a wafer-level fan-out package. Parallel data is serialized based on the first single-ended clock signal by a serializer circuit of the first transceiver circuit. The serialized data and the differential clock signal from the serializer circuit are transmitted through a physical channel of the wafer-level fan-out package to a second transceiver circuit of a second IC die. The second IC die is disposed within the wafer-level fan-out package. The serialized data is deserialized based on the differential clock signal by a deserialization circuit of the second transceiver circuit.

[0011] These and other aspects can be understood with reference to the following detailed description. As the foregoing features can be understood in detail, a more specific description, briefly summarized above, can be obtained by reference to the exemplary implementations, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical exemplary implementations and should not be considered as limiting the scope thereof.

Brief Description of the Drawings

[0012]

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Best Mode for Carrying Out the Invention

[0013] For ease of understanding, the same reference numbers are used to denote the same elements common to the figures, where possible. It is contemplated that elements of one embodiment may be beneficially incorporated into other embodiments.

[0014] The embodiments described in this specification generally relate to communication between integrated circuit (IC) dies within a wafer-level fan-out package. In some embodiments, an electronic device includes a wafer-level fan-out package that includes at least two IC dies, and each of the two IC dies includes a transceiver circuit. The transmitter circuit of the transceiver circuit includes a serializer circuit that serializes parallel data based on a single-ended clock signal and outputs the serialized data through a physical channel of a redistribution structure of the wafer-level fan-out package via one or more signal driver circuits. The transmitter circuit also includes a single-ended-to-differential (S2D) converter circuit that converts the single-ended clock signal into a differential clock signal that the transmitter circuit outputs through a physical channel of the redistribution structure via one or more signal driver circuits. The receiver circuit of the transceiver circuit includes a differential-to-single-ended (D2S) converter circuit that converts a differential clock signal received from a physical channel of the redistribution structure into a single-ended clock signal. The receiver includes a deserialization circuit that deserializes data captured from a physical channel of the redistribution structure based on the single-ended clock signal from the D2S converter circuit.

[0015] According to some embodiments, a plurality of single-ended data signals transmitted from a first IC die (e.g., from a transmitter circuit of a transceiver circuit of the first IC die) to a second IC die (e.g., to a receiver circuit of a transceiver circuit of the second IC die) share a differential clock signal. Thus, data communication can be source synchronous. The receiver circuit can omit a clock data recovery (CDR) circuit, and the power consumption of the receiver circuit can be reduced. The data signals can be single-ended (and further can be single-ended non-return to zero (NRZ) signals), which, as opposed to two signals of a differential signal, can achieve a reduction in area consumption of physical channels within a redistribution structure of a wafer-level fan-out package and can reduce power consumption. Further, by using a plurality of single-ended data signals that share a differential clock signal (e.g., as opposed to each data signal having its own differential clock signal), area consumption in a physical channel can be reduced and power consumption can be reduced. Generally, various embodiments can achieve power-efficient communication and / or corresponding structures having a high bandwidth density. Other advantages can be achieved by other embodiments.

[0016] Various features are described below with reference to the figures. Note that the figures may or may not be drawn to scale, and elements of similar structure or function are represented by like reference numerals throughout the figures. It should be noted that the figures are intended only to facilitate the description of the features. They are not intended as an exhaustive description of the invention recited in the claims or as limiting the scope of the invention recited in the claims. Additionally, the illustrated embodiments need not have all of the aspects or advantages shown. Aspects or advantages described in connection with a particular embodiment are not necessarily limited to that embodiment and may be implemented in any other example, whether or not so illustrated or explicitly described as such. Further, the methods described herein may be described in terms of acts in a particular order, but other methods according to other embodiments may be implemented in various other orders having more or fewer acts (e.g., including different serial or parallel performances of the various acts).

[0017] In the following description, various signals or data are described in the context of the operation of various circuits. The signals or data described indicate the corresponding nodes to which the signal or data is applied or propagated, and further indicate nodes that are communicatively coupled and / or electrically connected. For example, the description of a signal or data output from a first circuit and input to a second circuit indicates that the output node of the first circuit (where the signal or data is output from the first circuit) is communicatively coupled and / or electrically connected to the input node of the second circuit (where the signal or data is input to the second circuit). Explicit description of such nodes may be omitted in the following description, but those skilled in the art will readily understand the existence of the nodes.

[0018] FIG. 1 illustrates a cross-sectional view of an exemplary multi-die wafer-level fan-out (WLFO) package 100 according to some embodiments. The WLFO package 100 may be an integrated fan-out (InFO) package of multiple dies in some embodiments. In other embodiments, other configurations of the WLFO package may be implemented.

[0019] As illustrated, the WLFO package 100 includes integrated circuit (IC) dies 102-1, 102-2 (collectively or individually, IC die 102). The WLFO package 100 can include two or more IC dies 102. For example, the WLFO package 100 can include additional IC dies 102-3, 102-4 as described below. Each IC die 102 can be or include a processor, an application specific integrated circuit (ASIC), a programmable integrated circuit (e.g., a field-programmable gate array (FPGA) or a complex programmable logic device (CPLD)), a memory die, etc.

[0020] Each of the IC dies 102 has conductive pillars 104 (e.g., metal pillars such as copper pillars) disposed on conductive pads 106 (e.g., metal pads such as aluminum pads) disposed on the active side of the respective IC die 102. The conductive pillars 104 are at least laterally encapsulated with a dielectric material 108. The conductive pillars 104 are on the active side of the respective IC die 102 and form electrical connections between the redistribution structure 110 and the circuits on the respective IC die 102.

[0021] The encapsulant 112 encapsulates the IC die 102 in the lateral direction. The encapsulant 112 can be a molding compound, epoxy, or the like. The redistribution structure 110 is on the IC die 102 and the encapsulant 112. The redistribution structure 110 includes dielectric layers 120, 122, 124, 126 in which metal pattern layers 130, 132, 134 are disposed. Each of the dielectric layers 120, 122, 124, 126 can be, for example, polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. Each metal pattern of the metal pattern layers 130, 132, 134 can be or include a metal wire and / or via, and can be formed on and / or through each of the dielectric layers 120, 122, 124 and down to the metal pattern of the underlying metal pattern layer 130, 132 or the conductive pillar 104. For example, the metal pattern layer 130 is disposed on the dielectric layer 120, and at least some of the metal patterns of the metal pattern layer 130 are formed through the dielectric layer 120 so as to contact the respective conductive pillars 104. The dielectric layer 122 is disposed on the metal pattern layer 130 and the dielectric layer 120. The metal pattern layer 132 is disposed on the dielectric layer 122, and at least some of the metal patterns of the metal pattern layer 132 are formed through the dielectric layer 122 and contact the respective metal patterns of the metal pattern layer 130. The dielectric layer 124 is disposed on the metal pattern layer 132 and the dielectric layer 122. The metal pattern layer 134 is disposed on the dielectric layer 124, and at least some of the metal patterns of the metal pattern layer 134 are formed through the dielectric layer 124 and contact the respective metal patterns of the metal pattern layer 132. The dielectric layer 126 is disposed on the metal pattern layer 134 and the dielectric layer 124. The metal patterns of the metal pattern layers 130, 132, 134 can be or include, for example, copper, titanium, tungsten, aluminum, or the like.The metal patterns of the metal pattern layers 130, 132, 134 within the redistribution structure 110 can interconnect the IC dies 102 and can be used to avoid or route connections from the IC dies 102 to the under bump metallizations (UBMs) 140 and the bumps 142. The redistribution structure 110 can include any number of dielectric layers and metal pattern layers.

[0022] The UBM 140 is formed on and through the outer dielectric layer 126 up to the metal pattern of the metal pattern layer 134. In some embodiments, the UBM 140 can be of various configurations of metal layers such as a chromium / chromium copper alloy / copper / gold configuration, a titanium / titanium tungsten / copper configuration, a copper / nickel / gold configuration, etc., or can include them.

[0023] The bump 142 is attached to the UBM 140. The bump 142 can be, for example, a controlled collapse chip connection (C4) bump that can include a conductive material such as solder (e.g., lead-free solder), copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. The bump 142 can further be attached to a package substrate, enabling the WLFO package 100 to be attached to the package substrate.

[0024] The IC die 102-1 has a lateral sidewall 152-1, and the IC die 102-2 has a lateral sidewall 152-2. The lateral sidewalls 152-1, 152-2 are adjacent and face each other in the WLFO package 100. The lateral sidewalls 152-1, 152-2 are sealed and adhered by the encapsulant 112. The cross-section A-A is illustrated for orienting subsequent figures. The XYZ axes are also illustrated for orientation purposes. The cross-section A-A is in the lateral direction between the lateral sidewalls 152-1, 152-2 and passes through the redistribution structure 110.

[0025] FIG. 2 depicts the layout of the IC dies 102 and the encapsulant 112 within the WLFO package 100 according to several embodiments. The layout shows the IC dies 102-1, 102-2, 102-3, 102-4 laterally encapsulated by the encapsulant 112. The layout further schematically shows the transceiver circuits 202-1, 202-2, 202-3, 202-4 (collectively or individually, the transceiver circuits 202). Each transceiver circuit 202 is disposed within each IC die 102. The physical channels 204-12, 204-21, 204-34, 204-43 are schematically depicted. The physical channel 204-12 extends from the transmitter circuit of the transceiver circuit 202-1 on the IC die 102-1 to the receiver circuit of the transceiver circuit 202-2 on the IC die 102-2. The physical channel 204-21 extends from the transmitter circuit of the transceiver circuit 202-2 on the IC die 102-2 to the receiver circuit of the transceiver circuit 202-1 on the IC die 102-1. The physical channel 204-34 extends from the transmitter circuit of the transceiver circuit 202-3 on the IC die 102-3 to the receiver circuit of the transceiver circuit 202-4 on the IC die 102-4. The physical channel 204-43 extends from the transmitter circuit of the transceiver circuit 202-4 on the IC die 102-4 to the receiver circuit of the transceiver circuit 202-3 on the IC die 102-3. In other embodiments, other layouts of the IC dies and other configurations of the physical channels can be implemented.

[0026] The physical channels 204-12, 204-21 include metal patterns of the metal pattern layers 130, 132, 134 within the redistribution structure 110 that interconnect the IC die 102-1 and the IC die 102-2. The physical channels 204-34, 204-43 include metal patterns of the metal pattern layers 130, 132, 134 within the redistribution structure 110 that interconnect the IC die 102-3 and the IC die 102-4. In some embodiments, the physical channels 204-12, 204-21, 204-34, 204-43 do not include metal patterns (e.g., metal lines) within the metal pattern layer (e.g., the metal pattern layer 134) of the redistribution structure 110 that is most distal from the IC die 102.

[0027] FIG. 3 illustrates a cross-section of the WLFO package 100 for illustrating the arrangement of metal patterns for physical channels according to some embodiments. The cross-section of FIG. 3 is the cross-section A-A of FIGS. 1 and 2. The cross-section of FIG. 3 shows patterns of channel metal lines and shield metal lines. The metal patterns in the cross-section are, for example, metal lines extending between the IC dies 102-1 and 102-2. The metal pattern layer 130 includes alternating channel metal lines 130-C and shield metal lines 130-S. The metal pattern layer 132 includes alternating channel metal lines 132-C and shield metal lines 132-S. The channel metal lines 130-C, 132-C form a checkerboard pattern with the shield metal lines 130-S, 132-S. The metal pattern layer 134 includes, or consists of, shield metal lines 134-S in the illustrated cross-section.

[0028] In some embodiments, each channel metal line 130-C, 132-C in the cross-section forms at least a portion of the physical channels 204-12, 204-21. The shield metal lines 130-S, 132-S, 134-S are configured to be electrically connected to the ground potential during operation and / or to form a ground node. In other embodiments, the shield metal lines 130-S, 132-S, 134-S may be configured to be electrically connected to the power supply voltage VDD during operation and / or to form a power supply node VDD. Due to the checkerboard pattern, the channel metal lines 130-C, 132-C are not directly adjacent to another channel metal line 130-C, 132-C either horizontally or vertically. For example, the channel metal line 132-C in FIG. 3 can have the shield metal line 134-S directly above the channel metal line 132-C, the shield metal line 130-S directly below the channel metal line 132-C, and the respective shield metal lines 132-S in the horizontal direction from the channel metal line 132-C. This pattern can reduce crosstalk between the channel metal lines, which can reduce crosstalk between the physical channels 204-12, 204-21. One skilled in the art will readily understand that this pattern can be extended horizontally and / or vertically to accommodate any number of physical channels. Such a pattern can be implemented for the metal lines extending between the IC dies 102-3, 102-4 for the physical channels 204-34, 204-43.

[0029] Figures 4A and 4B illustrate circuit diagrams of transceiver circuits 202-1 and 202-2 communicatively coupled to each other according to some embodiments. Similar schematic diagrams can be implemented for transceiver circuits 202-3 and 202-4 for those skilled in the art to easily understand. Figures 4A and 4B show the transmitter circuit 202-1T of transceiver circuit 202-1 and the receiver circuit 202-2R of transceiver circuit 202-2. The receiver circuit 202-1R of transceiver circuit 202-1 is generally shown, and the transmitter circuit 202-2T of transceiver circuit 202-2 is generally shown. The transmitter circuit 202-2T can implement a circuit diagram as shown for the transmitter circuit 202-1T, the receiver circuit 202-1R can implement a circuit diagram as shown for the receiver circuit 202-2R, and the transmitter circuit 202-2T and the receiver circuit 202-1R can be communicatively coupled like the transmitter circuit 202-1T and the receiver circuit 202-2R. Those skilled in the art will easily understand such implementations, so the detailed description of the transmitter circuit 202-2T and the receiver circuit 202-1R is omitted for brevity.

[0030] The circuit diagrams illustrated in the following figures are shown and described in detail to clearly illustrate and convey aspects of various embodiments. Other embodiments can implement more general applications of the illustrated embodiments without the illustrated details and / or with other details.

[0031] The transmitter circuit 202-1T includes buffer circuits 402, 404, clock driver circuits 406, a first bank of serializer circuits 410-1, 410-2, 410-3, 410-4, a first bank of single-ended to differential (S2D) converter circuits 412-1, 412-2, a first bank of clock driver circuits 414-1, 414-2, 414-3, 414-4, a retimer circuit 418, a second bank of serializer circuits 420-1, 420-2, 420-3, 420-4, a second bank of S2D converter circuits 422-1, 422-2, a second bank of clock driver circuits 424-1, 424-2, 424-3, 424-4, and a signal driver circuit 428.

[0032] The buffer circuit 402 can include, in the illustrated embodiment, 64 buffer circuits, and each buffer circuit has an input node electrically connected to a data lane from an interface circuit (not shown) of the IC die 102-1 and an output node electrically connected to a data lane within the transmitter circuit 202-1T. Accordingly, 64 data lanes electrically coupled to the input node of the buffer circuit 402 are shown (" / 64"), and a total of 64 data lanes electrically coupled to the output node of the buffer circuit 402 are shown (" / 32", " / 16", and " / 16"). Similarly, the buffer circuit 404 can include, in the illustrated embodiment, 64 buffer circuits, and each buffer circuit has an input node electrically connected to a data lane from an interface circuit of the IC die 102-1 and an output node electrically connected to a data lane within the transmitter circuit 202-1T. Accordingly, 64 data lanes electrically coupled to the input node of the buffer circuit 404 are shown (" / 64"), and a total of 64 data lanes electrically coupled to the output node of the buffer circuit 402 are shown (" / 32", " / 16", and " / 16"). The buffer circuits 402, 404 are configured to receive parallel data from their respective 64 data lanes and output the parallel data to their respective 64 data lanes within the transmitter circuit 202-1T.

[0033] In the illustrated embodiment, the clock driver circuit 406 includes a capacitor, a resistor, and two buffer circuits. The capacitor has a first terminal electrically connected to a clock node (CLK) from the interface circuit of the IC die 102-1. The second terminal of the capacitor (opposite the first terminal) is electrically connected to the input node of the first buffer and the first terminal of the resistor element. The output node of the first buffer and the second terminal of the resistor (opposite the first terminal) are electrically connected to each other and connected to the input node of the second buffer. The output node of the second buffer is the output node of the clock driver circuit 406. In the illustrated embodiment, the clock driver circuit 406 is configured to receive a single-ended clock signal on the clock node and drive a single-ended clock signal on the clock lane (" / 1") as an output signal.

[0034] In the illustrated embodiment, each serializer circuit 410-1, 410-2, 410-3, 410-4, 420-1, 420-2, 420-3, 420-4 includes a pair of 8-to-4 ("8:4") serializers. Each 8:4 serializer is configured to receive data from eight data lanes, serialize the received data, and output the serialized data onto four data lanes. Each 8:4 serializer is configured to serialize data based on a single-ended clock signal. Other embodiments may implement different serializer circuits that may have different serialization ratios and / or different numbers of serializers.

[0035] Each of the serializer circuits 410-1 and 410-2 has an input node electrically connected to each output node of the buffer circuit 402. Therefore, each of the serializer circuits 410-1 and 410-2 has an input node electrically connected to the data lanes from the buffer circuit 402. In the illustrated embodiment, the serializer circuit 410-1 has an input node electrically connected to 16 data lanes (“ / 16”) from the buffer circuit 402, and the serializer circuit 410-2 has an input node electrically connected to 16 data lanes (“ / 16”) from the buffer circuit 402.

[0036] Each of the serializer circuits 410-3 and 410-4 has an input node electrically connected to each output node of the buffer circuit 404. Therefore, each of the serializer circuits 410-3 and 410-4 has an input node electrically connected to the data lanes from the buffer circuit 404. In the illustrated embodiment, the serializer circuit 410-3 has an input node electrically connected to 16 data lanes (“ / 16”) from the buffer circuit 404, and the serializer circuit 410-4 has an input node electrically connected to 16 data lanes (“ / 16”) from the buffer circuit 404.

[0037] Each of the serializer circuits 410-1, 410-2, 410-3, and 410-4 has an output node electrically connected to each input node of the signal driver circuit 428. Therefore, each of the serializer circuits 410-1, 410-2, 410-3, and 410-4 has an output node electrically connected to the data lanes to the signal driver circuit 428. In the illustrated embodiment, each of the serializer circuits 410-1, 410-2, 410-3, and 410-4 has an output node electrically connected to 8 data lanes (“ / 8”) to the signal driver circuit 428.

[0038] Each of the S2D converter circuits 412-1, 412-2, 422-1, and 422-2 is configured to receive a single-ended clock signal from a clock lane, generate a differential clock signal from the received single-ended clock signal, and output the differential clock signal. Any single-ended to differential converter circuit can be implemented as the S2D converter circuits 412-1, 412-2, 422-1, and 422-2.

[0039] Each of the clock driver circuits 414-1, 414-2, 414-3, 414-4, 424-1, 424-2, 424-3, and 424-4 is configured to receive a single-ended clock signal, buffer the single-ended clock signal, and output the buffered single-ended clock signal. In some embodiments, each of the clock driver circuits 414-1, 414-2, 414-3, 414-4, 424-1, 424-2, 424-3, and 424-4 can adjust the duty cycle of the single-ended clock signal and, further, can be programmable to adjust the duty cycle of the single-ended clock signal. Further details of this programmability and duty cycle adjustment will be described later. The clock driver circuits 414-1, 414-2, 414-3, 414-4, 424-1, 424-2, 424-3, and 424-4 are shown in FIG. 4A independent of the S2D converter circuit and the serializer circuit, but in practice, the clock driver circuits 414-1, 414-2, 414-3, 414-4, 424-1, 424-2, 424-3, and 424-4 may be embedded in and / or be part of the corresponding S2D converter circuit and / or serializer circuit. Additionally, although a single clock driver circuit is shown for the corresponding S2D converter circuit and serializer circuit, multiple clock driver circuits may be implemented for the corresponding S2D converter circuit and serializer circuit.

[0040] Each of the S2D converter circuits 412-1 and 412-2 has an input node electrically connected to the output node of the clock driver circuit 406. Each of the S2D converter circuits 412-1 and 412-2 has an input node electrically connected to a clock lane driven by the clock driver circuit 406. The S2D converter circuit 412-1 includes one or more single-ended output nodes electrically connected to the respective input nodes of the clock driver circuits 414-1 and 414-3. The S2D converter circuit 412-2 includes one or more single-ended output nodes electrically connected to the respective input nodes of the clock driver circuits 414-2 and 414-4. The S2D converter circuits 412-1 and 412-2 include respective differential output nodes electrically connected to the respective input nodes of the signal driver circuit 428. Thus, each of the S2D converter circuits 412-1 and 412-2 has a differential output node electrically connected to the clock lane to the signal driver circuit 428. In the illustrated embodiment, each of the S2D converter circuits 412-1 and 412-2 has a differential output node electrically connected to two clock lanes (" / 2") to the signal driver circuit 428.

[0041] The clock driver circuit 414-1 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit 410-1. The clock driver circuit 414-2 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit 410-2. The clock driver circuit 414-3 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit 410-3. The clock driver circuit 414-4 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit 410-4. The serializer circuits 410-1, 410-2, 410-3, 410-4 are configured to serialize data using the single-ended clock signals received from their respective single-ended clock input nodes and from their respective clock driver circuits 414-1, 414-2, 414-3, 414-4.

[0042] In the illustrated embodiment, as described above, each serializer circuit 410-1, 410-2, 410-3, 410-4 includes a pair of 8-to-4 (“8:4”) serializers. Each 8-to-4 serializer has a clock driver circuit. Thus, each clock driver circuit 414-1, 414-2, 414-3, 414-4 includes two clock driver circuits, although not explicitly shown. The S2D converter circuits 412-1, 412-2 are configured to provide a single-ended clock signal from a clock lane from the clock driver circuit 406 to each of the two clock driver circuits of each of the clock driver circuits 414-1, 414-2, 414-3, 414-4. Each clock driver circuit of the clock driver circuits 414-1, 414-2, 414-3, 414-4 drives a single-ended clock signal and is configured to adjust the duty cycle of the single-ended clock signal for each of the respective 8-to-4 serializers in some cases. For example, the S2D converter circuit 412-1 is configured to provide a single-ended clock signal to the two clock driver circuits of the clock driver circuit 414-1, and each of those clock driver circuits can drive a respective single-ended clock signal output to each of the 8-to-4 serializers of the serializer circuit 410-1.

[0043] The retimer circuit 418 has input nodes electrically connected to the output nodes of each of the buffer circuits 402, 404. Thus, the retimer circuit 418 has input nodes electrically connected to the data lanes from the buffer circuits 402, 404. In the illustrated embodiment, the retimer circuit 418 has input nodes electrically connected to 32 data lanes (" / 32") from the buffer circuit 402 and input nodes electrically connected to 32 data lanes (" / 32") from the buffer circuit 404. The retimer circuit 418 further has an input node electrically connected to the output node of the clock driver circuit 406. Thus, the retimer circuit 418 has an input node electrically connected to the clock lane driven by the clock driver circuit 406. The retimer circuit 418 can include, for example, a buffer circuit or a driver circuit for further driving the clock signal received from the clock lane, and can include flip - flops for each data lane connected to the input nodes of the retimer circuit 418. The clock signal can trigger the flip - flops to realign the data signals received from the data lanes of the buffer circuits 402, 404. The retimer circuit 418 can provide an increased timing margin, for example, when a bank of serializer circuits is disposed at a relatively large distance from the buffer circuits 402, 404.

[0044] The retimer circuit 418 has output nodes electrically connected to the respective data lanes. In the illustrated embodiment, a total of 64 data lanes (" / 16", " / 16", " / 16", and " / 16") electrically coupled to the output nodes of the retimer circuit 418 are shown. The retimer circuit 418 has an output node electrically connected to the clock lane. In the illustrated embodiment, the clock lane is for a single - ended clock signal.

[0045] Each serializer circuit 420-1, 420-2, 420-3, 420-4 has an input node electrically connected to a respective output node of the retimer circuit 418. Thus, each serializer circuit 420-1, 420-2, 420-3, 420-4 has an input node electrically connected to the data lanes from the retimer circuit 418. In the illustrated embodiment, each serializer circuit 420-1, 420-2, 420-3, 420-4 has an input node electrically connected to respective 16 data lanes (“ / 16”) from the retimer circuit 418.

[0046] Each serializer circuit 420-1, 420-2, 420-3, 420-4 has an output node electrically connected to a respective input node of the signal driver circuit 428. Thus, each of the serializer circuits 420-1, 420-2, 420-3, 420-4 has an output node electrically connected to the data lanes to the signal driver circuit 428. In the illustrated embodiment, each serializer circuit 420-1, 420-2, 420-3, 420-4 has an output node electrically connected to 8 data lanes (“ / 8”) to the signal driver circuit 428.

[0047] Each of the S2D converter circuits 422-1 and 422-2 has an input node electrically connected to the output node of the retimer circuit 418. Each of the S2D converter circuits 422-1 and 422-2 has an input node electrically connected to a clock lane driven by the retimer circuit 418. The S2D converter circuit 422-1 includes one or more single-ended output nodes electrically connected to one or more single-ended input nodes of the clock driver circuits 424-1 and 424-3. The S2D converter circuit 422-2 includes one or more single-ended output nodes electrically connected to one or more single-ended input nodes of the clock driver circuits 424-2 and 424-4. The S2D converter circuits 422-1 and 422-2 include respective differential output nodes electrically connected to respective input nodes of the signal driver circuit 428. Thus, each of the S2D converter circuits 422-1 and 422-2 has a differential output node electrically connected to the clock lane to the signal driver circuit 428. In the illustrated embodiment, each S2D converter circuit 422-1 and 422-2 has a differential output node electrically connected to two clock lanes (" / 2") to the signal driver circuit 428.

[0048] The clock driver circuit 424-1 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit 420-1. The clock driver circuit 424-2 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit 420-2. The clock driver circuit 424-3 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit 420-3. The clock driver circuit 424-4 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the serializer circuit 420-4. The serializer circuits 420-1, 420-2, 420-3, 420-4 are configured to serialize data using the single-ended clock signals received from their respective single-ended clock input nodes and from their respective clock driver circuits 424-1, 424-2, 424-3, 424-4. As described above for the clock driver circuits 414-1, 414-2, 414-3, 414-4, each clock driver circuit 424-1, 424-2, 424-3, 424-4 includes two clock driver circuits, although not explicitly shown in the illustrated embodiment.

[0049] As described above, the signal driver circuit 428 has input nodes electrically connected to data lanes and clock lanes from various serializer circuits and S2D converter circuits. The signal driver circuit 428 includes signal driver circuits for each input node and corresponding lane, and is configured to drive corresponding signals on the corresponding physical channels of the physical channels 204-12. Each signal driver that drives a data signal (e.g., a signal based on serialized data on a data lane from a serializer circuit) can be configured to drive a single-ended data signal, such as a single-ended NRZ data signal, on the corresponding physical channel. Using such single-ended signaling can reduce the number of physical channels (e.g., metal lines) within the WLFO package 100 and can reduce power consumption compared to differential signaling. Further, each signal driver that drives a clock signal can be configured to drive a differential clock signal on a corresponding pair of physical channels. Each signal driver circuit can be configured to provide equalization for the channel response of the corresponding physical channel that the signal driver circuit is configured to drive. Additionally, the signal driver circuit can be programmable to provide equalization. Further details of equalization and programmability are described later.

[0050] In the operation of the illustrated embodiment, buffer circuits 402 and 404 receive parallel data from each of the 64 data lanes from the interface circuits of IC die 102-1. Buffer circuits 402 and 404 each output the received parallel data onto corresponding 64 data lanes. Of the parallel data on the 64 data lanes from buffer circuit 402, the parallel data on 16 data lanes is input to serializer circuit 410-1, the parallel data on another 16 data lanes is input to serializer circuit 410-2, and the parallel data on 32 data lanes is input to retimer circuit 418. Of the parallel data on the 64 data lanes from buffer circuit 404, the parallel data on 16 data lanes is input to serializer circuit 410-3, the parallel data on another 16 data lanes is input to serializer circuit 410-4, and the parallel data on 32 data lanes is input to retimer circuit 418.

[0051] The clock driver circuit 406 receives a single-ended clock signal from the interface circuit of the IC die 102-1 and drives the single-ended clock signal on the clock lane to the S2D converter circuits 412-1, 412-2 and the retimer circuit 418. Each of the S2D converter circuits 412-1, 412-2 generates a differential clock signal from the single-ended clock signal received from the clock lane. The S2D converter circuit 412-1 provides a differential clock signal to the signal driver circuit 428 via two clock lanes, and provides the single-ended clock signal from the clock lane to the clock driver circuits 414-1, 414-3. The S2D converter circuit 412-2 provides a differential clock signal to the signal driver circuit 428 via two clock lanes, and provides the single-ended clock signal from the clock lane to the clock driver circuits 414-2, 414-4. The clock driver circuits 414-1, 414-2, 414-3, 414-4 buffer the received single-ended clock signal and output the buffered single-ended clock signal to the respective serializer circuits 410-1, 410-2, 410-3, 410-4. In some embodiments, the clock driver circuits 414-1, 414-2, 414-3, 414-4 can adjust the duty cycle of the received single-ended clock signal to generate the buffered single-ended clock signal.

[0052] The retimer circuit 418 receives parallel data from 32 data lanes from the buffer circuit 402 and 32 data lanes from the buffer circuit 404. The retimer circuit 418 also receives a signal end clock signal from the clock lane from the clock driver circuit 406. The retimer circuit 418 can buffer or drive the single-ended clock signal and realign or synchronize the parallel data with the clock signal. The retimer circuit 418 outputs each parallel data on the corresponding 64 data lanes. Among these 64 data lanes, the parallel data output on 32 data lanes corresponds to the parallel data received on the 32 data lanes from the buffer circuit 402, and the parallel data output on 32 data lanes corresponds to the parallel data received on the 32 data lanes from the buffer circuit 404. Among the parallel data output on the 32 data lanes corresponding to the buffer circuit 402, the parallel data on 16 data lanes is input to the serializer circuit 420-1, and the parallel data on another 16 data lanes is input to the serializer circuit 420-2. Among the parallel data output on the 32 data lanes corresponding to the buffer circuit 404, the parallel data on 16 data lanes is input to the serializer circuit 420-3, and the parallel data on another 16 data lanes is input to the serializer circuit 420-4. The retimer circuit 418 drives the single-ended clock signal on the clock lane to the S2D converter circuits 422-1, 422-2.

[0053] The S2D converter circuits 422-1 and 422-2 each generate a differential clock signal from a single-ended clock signal received from a clock lane of the retimer circuit 418. The S2D converter circuit 422-1 provides the differential clock signal to the signal driver circuit 428 via two clock lanes, and provides the single-ended clock signal to the clock driver circuits 424-1 and 424-3 from the clock lane. The S2D converter circuit 422-2 provides the differential clock signal to the signal driver circuit 428 via two clock lanes, and provides the single-ended clock signal to the clock driver circuits 424-2 and 424-4 from the clock lane. The clock driver circuits 424-1, 424-2, 424-3, and 424-4 buffer the received single-ended clock signal and output the buffered single-ended clock signal to the respective serializer circuits 420-1, 420-2, 420-3, and 420-4. In some embodiments, the clock driver circuits 424-1, 424-2, 424-3, and 424-4 can adjust the duty cycle of the received single-ended clock signal to generate a buffered single-ended clock signal.

[0054] Each serializer circuit 410-1, 410-2, 410-3, 410-4, 420-1, 420-2, 420-3, and 420-4 serializes the parallel data received on its respective 16 data lanes based on the received single-ended clock signal and outputs the serialized data on 8 data lanes to the signal driver circuit 428. The signal driver circuit 428 drives each data or clock signal received from the corresponding data or clock lane on the corresponding physical channel of the physical channel 204-12. The signal driver circuit 428 drives the serialized data on each data lane as a respective single-ended data signal (e.g., a single-ended NRZ data signal) on the corresponding physical channel 204-12 and drives each differential clock signal on the corresponding pair of clock lanes of the corresponding pair of the physical channels. The signal driver circuit 428 can also equalize the signals on the physical channel 204-12.

[0055] The receiver circuit 202-2R includes a first bank of deserializers 450-1, 450-2, 450-3, 450-4, a first bank of differential-to-single-ended (D2S) converter circuits 452-1, 452-2, a first bank of clock driver circuits 454-1, 454-2, 454-3, 454-4, a buffer circuit 458, a second bank of deserializers 460-1, 460-2, 460-3, 460-4, a second bank of D2S converter circuits 462-1, 462-2, a second bank of clock driver circuits 464-1, 464-2, 464-3, 464-4, and buffer circuits 470, 472.

[0056] In the illustrated embodiment, each deserializer circuit 450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4 includes a pair of 4-to-8 ("4:8") deserializers. Each 4-to-8 deserializer is configured to receive data from four data lanes, deserialize the received data, and output the deserialized parallel data on eight data lanes. Each 4-to-8 deserializer is configured to deserialize data based on a single-ended clock signal. Each 4-to-8 deserializer is further configured to output a single-ended clock signal used to deserialize the data. Other embodiments may implement different deserializer circuits that may have different serialization ratios and / or different numbers of deserializers.

[0057] Each of the deserialization circuits 450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, and 460-4 has an input node electrically connected to a respective physical channel of the physical channel 204-12. In the illustrated embodiment, each of the deserialization circuits 450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, and 460-4 has an input node electrically connected to eight physical channels (" / 8") of the physical channel 204-12. The physical channel to which the input node of the deserialization circuit 450-1 is electrically connected carries the data signal generated from the serializer circuit 410-1. Thus, the deserialization circuit 450-1 is communicatively coupled to the serializer circuit 410-1. Similarly, the deserialization circuit 450-2 is communicatively coupled to the serializer circuit 410-2, the deserialization circuit 450-3 is communicatively coupled to the serializer circuit 410-3, the deserialization circuit 450-4 is communicatively coupled to the serializer circuit 410-4, the deserialization circuit 460-1 is communicatively coupled to the serializer circuit 420-1, the deserialization circuit 460-2 is communicatively coupled to the serializer circuit 420-2, the deserialization circuit 460-3 is communicatively coupled to the serializer circuit 420-3, and the deserialization circuit 460-4 is communicatively coupled to the serializer circuit 420-4.

[0058] In some embodiments, the first bank of serializer circuits 410-1, 410-2, 410-3, 410-4 is disposed physically farthest from the lateral sidewall 152-1 of the IC die 102-1 in the transmitter circuit 202-1T, and the second bank of serializer circuits 420-1, 420-2, 420-3, 420-4 is disposed physically closest to the lateral sidewall 152-1 of the IC die 102-1 in the transmitter circuit 202-1T. The first bank of deserialzier circuits 450-1, 450-2, 450-3, 450-4 is disposed physically closest to the lateral sidewall 152-2 of the IC die 102-2 in the receiver circuit 202-2R, and the second bank of deserialzier circuits 460-1, 460-2, 460-3, 460-4 is disposed physically farthest from the lateral sidewall 152-2 of the IC die 102-2 in the receiver circuit 202-2R. Accordingly, the banks of serializer circuits are communicatively coupled to the banks of deserialzier circuits through the physical channel 204-12, which can generally be matched and balanced because the lengths of the physical channels 204-12 are the same or similar. This matching and balancing can collectively reduce the load on the physical channels, and thus reduce the collective power consumption for driving signals through the physical channels.

[0059] Each deserialization circuit 450-1, 450-2, 450-3, 450-4 has an output node electrically connected to each input node of buffer circuit 458. Therefore, each of deserialization circuits 450-1, 450-2, 450-3, 450-4 has an output node electrically connected to the data lanes to buffer circuit 458. In the illustrated embodiment, each of deserialization circuits 450-1, 450-2, 450-3, 450-4 has an output node electrically connected to 16 data lanes (" / 16") to buffer circuit 458. Each deserialization circuit 460-1, 460-2 has an output node electrically connected to each input node of buffer circuit 470. Therefore, each of deserialization circuits 460-1, 460-2 has an output node electrically connected to the data lanes to buffer circuit 470. In the illustrated embodiment, each of deserialization circuits 460-1, 460-2 has an output node electrically connected to 16 data lanes (" / 16") to buffer circuit 470. Each deserialization circuit 460-3, 460-4 has an output node electrically connected to each input node of buffer circuit 472. Therefore, each of deserialization circuits 460-3, 460-4 has an output node electrically connected to the data lanes to buffer circuit 472. In the illustrated embodiment, each of deserialization circuits 460-3, 460-4 has an output node electrically connected to 16 data lanes (" / 16") to buffer circuit 472.

[0060] Each D2S converter circuit 452-1, 452-2, 462-1, 462-2 is configured to receive a differential clock signal from each physical channel of physical channel 204-12, generate a single-ended clock signal from the received differential clock signal, and output the single-ended clock signal. Any differential-to-single-ended converter circuit can be implemented as D2S converter circuits 452-1, 452-2, 462-1, 462-2.

[0061] Each of the clock driver circuits 454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4 is configured to receive a single-ended clock signal, buffer the single-ended clock signal, and output the buffered single-ended clock signal. In some embodiments, each of the clock driver circuits 454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4 can adjust the duty cycle of the single-ended clock signal and, further, can be programmable to adjust the duty cycle of the single-ended clock signal. In some embodiments, each of the clock driver circuits 454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4 can deskew the single-ended clock signal and, further, can be programmable to deskew the single-ended clock signal. Further details of this programmability, duty cycle adjustment, and deskewing are described later. The clock driver circuits 454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4 are shown independently of the D2S converter circuit and the deserialization circuit in FIG. 4B, but in practice, the clock driver circuits 454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4 may be embedded in and / or be part of the corresponding D2S converter circuit and / or deserialization circuit. Additionally, a single clock driver circuit is shown for the corresponding D2S converter circuit and deserialization circuit, but multiple clock driver circuits may be implemented for the corresponding D2S converter circuit and deserialization circuit.

[0062] Each of the D2S converter circuits 452-1, 452-2, 462-1, and 462-2 has a differential input node electrically connected to the physical channel of the physical channel 204-12. In the illustrated embodiment, each of the D2S converter circuits 452-1, 452-2, 462-1, and 462-2 has a differential input node electrically connected to two physical channels (" / 2") of the physical channel 204-12. The D2S converter circuit 452-1 includes one or more single-ended output nodes electrically connected to the respective input nodes of the clock driver circuits 454-1 and 454-3. The D2S converter circuit 452-2 includes one or more single-ended output nodes electrically connected to the respective input nodes of the clock driver circuits 454-2 and 454-4. The D2S converter circuit 462-1 includes one or more single-ended output nodes electrically connected to the respective input nodes of the clock driver circuits 464-1 and 464-3. The D2S converter circuit 462-2 includes one or more single-ended output nodes electrically connected to the respective input nodes of the clock driver circuits 464-2 and 464-4.

[0063] The clock driver circuit 454-1 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the deserialization circuit 450-1. The clock driver circuit 454-2 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the deserialization circuit 450-2. The clock driver circuit 454-3 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the deserialization circuit 450-3. The clock driver circuit 454-4 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the deserialization circuit 450-4. The clock driver circuit 464-1 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the deserialization circuit 460-1. The clock driver circuit 464-2 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the deserialization circuit 460-2. The clock driver circuit 464-3 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the deserialization circuit 460-3. The clock driver circuit 464-4 includes one or more single-ended output nodes electrically connected to one or more single-ended clock input nodes of the deserialization circuit 460-4.

[0064] In the illustrated embodiment, as described above, each of the deserialization circuits 450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4 includes a pair of 4-to-8 ("4:8") deserializers. Each 4:8 deserializer has a clock driver circuit. Thus, each of the clock driver circuits 454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4, although not explicitly shown, includes two clock driver circuits. The D2S converter circuits 452-1, 452-2, 462-1, 462-2 are configured to generate and provide a single-ended clock signal to each of the two clock driver circuits of each of the clock driver circuits 454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4. Each of the clock driver circuits 454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4 drives a single-ended clock signal and, in some cases, is configured to deskew the single-ended clock signal and / or adjust the duty cycle of the single-ended clock signal for each of the respective 4:8 deserializers. For example, the D2S converter circuit 452-1 is configured to provide a single-ended clock signal to the two clock driver circuits of the clock driver circuit 454-1, and each of those clock driver circuits can drive a respective single-ended clock signal output to each of the 4:8 deserializers of the deserializer circuit 450-1.

[0065] The deserialization circuits 450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4 are configured to deserialize data using the single-ended clock signals received from their respective clock driver circuits 454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4 on their respective single-ended clock input nodes. Each of the deserialization circuits 450-1, 450-2, 450-3, 450-4 has a clock output node electrically connected to a respective input node of the buffer circuit 458. Thus, each of the deserialization circuits 450-1, 450-2, 450-3, 450-4 has a clock output node electrically connected to a clock lane to the buffer circuit 458. In the illustrated embodiment, each of the deserialization circuits 450-1, 450-2, 450-3, 450-4 has a clock output node electrically connected to two data lanes (" / 2") to the buffer circuit 458. Each of the deserialization circuits 460-1, 460-2 has a clock output node electrically connected to a respective input node of the buffer circuit 470. Thus, each of the deserialization circuits 460-1, 460-2 has a clock output node electrically connected to a clock lane to the buffer circuit 470. In the illustrated embodiment, each of the deserialization circuits 460-1, 460-2 has a clock output node electrically connected to two data lanes (" / 2") to the buffer circuit 470. Each of the deserialization circuits 460-3, 460-4 has a clock output node electrically connected to a respective input node of the buffer circuit 472. Thus, each of the deserialization circuits 460-3, 460-4 has a clock output node electrically connected to a clock lane to the buffer circuit 472. In the illustrated embodiment, each of the deserialization circuits 460-3, 460-4 has a clock output node electrically connected to two data lanes (" / 2") to the buffer circuit 472.As described above, each deserialization circuit includes a pair of 4-to-8 deserializers, and each of the 4-to-8 deserializers is configured to output a clock signal that each of the respective 4-to-8 deserializers uses to deserialize data. Thus, in the illustrated embodiment, each deserialization circuit is shown to output two clock signals to two respective clock lanes.

[0066] Buffer circuit 458 has input nodes electrically connected to the respective output nodes of deserialization circuits 450-1, 450-2, 450-3, 450-4. Thus, buffer circuit 458 has input nodes electrically connected to the data lanes and clock lanes from deserialization circuits 450-1, 450-2, 450-3, 450-4. In the illustrated embodiment, buffer circuit 458 has input nodes electrically connected to 16 data lanes (" / 16") and two clock lanes (" / 2") from each of deserialization circuits 450-1, 450-2, 450-3, 450-4. Buffer circuit 458 can include, for example, a buffer circuit or driver circuit for further driving the data signals and clock signals received from the data lanes and clock lanes, respectively.

[0067] Buffer circuit 458 has output nodes electrically connected to the respective data lanes and clock lanes. In the illustrated embodiment, a total of 64 data lanes (" / 32" and " / 32") electrically coupled to the output nodes of buffer circuit 458 are shown, and a total of eight clock lanes (" / 4" and " / 4") electrically coupled to the output nodes of buffer circuit 458 are shown.

[0068] In the illustrated embodiment, buffer circuit 470 can include 72 buffer circuits, and each buffer circuit has an input node electrically connected to a data lane or a clock lane from deserialization circuits 460-1, 460-2, or buffer circuit 458, and an output node electrically connected to an interface circuit (not shown) of IC die 102-2. Thus, a total of 64 data lanes electrically coupled to the input nodes of buffer circuit 470 are shown (" / 32", " / 16", and " / 16"), and 64 data lanes electrically coupled to the output nodes of buffer circuit 470 are shown (" / 64"). Further, a total of 8 clock lanes electrically coupled to the input nodes of buffer circuit 470 are shown (" / 4", " / 2", and " / 2"), and 8 clock lanes electrically coupled to the output nodes of buffer circuit 470 are shown (" / 8"). Similarly, buffer circuit 472 can include 72 buffer circuits in the illustrated embodiment, and each buffer circuit has an input node electrically connected to a data lane or a clock lane from deserialization circuits 460-3, 460-4, or buffer circuit 458, and an output node electrically connected to the interface circuit of IC die 102-2. Thus, a total of 64 data lanes electrically coupled to the input nodes of buffer circuit 472 are shown (" / 32", " / 16", and " / 16"), and 64 data lanes electrically coupled to the output nodes of buffer circuit 472 are shown (" / 64"). Further, a total of 8 clock lanes electrically coupled to the input nodes of buffer circuit 472 are shown (" / 4", " / 2", and " / 2"), and 8 clock lanes electrically coupled to the output nodes of buffer circuit 472 are shown (" / 8"). Buffer circuits 470 and 472 are configured to receive parallel data and single-ended clock signals from their respective 64 data lanes and 8 clock lanes, and output parallel data and single-ended clock signals to their respective 64 data lanes and 8 clock lanes to the interface circuit of IC die 102-2.

[0069] In the operation of the illustrated embodiment, each deserialization circuit 450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4 receives single-ended data signals from each of eight physical channels of the physical channel 204-12, and each D2S converter circuit 452-1, 452-2, 462-1, 462-2 receives differential clock signals from each of two physical channels of the physical channel 204-12. Each D2S converter circuit 452-1, 452-2, 462-1, 462-2 converts the received differential clock signals into single-ended clock signals and provides the single-ended clock signals to the respective clock driver circuits 454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4. The D2S converter circuit 452-1 provides the single-ended clock signal to the clock driver circuits 454-1, 454-3. The D2S converter circuit 452-2 provides the single-ended clock signal to the clock driver circuits 454-2, 454-4. The D2S converter circuit 462-1 provides the single-ended clock signal to the clock driver circuits 464-1, 464-3. The D2S converter circuit 462-2 provides the single-ended clock signal to the clock driver circuits 464-2, 464-4. The clock driver circuits 454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4 buffer the received single-ended clock signals and output the buffered single-ended clock signals to the respective deserialization circuits 450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4. In some embodiments, each clock driver circuit 454-1, 454-2, 454-3, 454-4, 464-1, 464-2, 464-3, 464-4 may deskew the received single-ended clock signal and / or adjust the duty cycle of the received single-ended clock signal, and the output single-ended clock signal may have a deskewed and / or adjusted duty cycle.

[0070] Each deserialization circuit 450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4 captures and deserializes the data received from each of the eight physical channels of the physical channel 204-12 based on the received single-ended clock signal, outputs the parallel data on the 16 data lanes to the buffer circuits 458, 470, or 472, and outputs the single-ended clock signal used to deserialize the data on each clock lane to the buffer circuits 458, 470, or 472. As described above, in the illustrated embodiment, each deserialization circuit 450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4 includes two 4-to-8 deserializers, and each of the 4-to-8 deserializers outputs a single-ended clock signal. Thus, in the illustrated embodiment, each deserialization circuit 450-1, 450-2, 450-3, 450-4, 460-1, 460-2, 460-3, 460-4 outputs two single-ended clock signals on each clock lane. Each deserialization circuit 450-1, 450-2, 450-3, 450-4 outputs the parallel data and the single-ended clock signal to the buffer circuit 458. Each deserialization circuit 460-1, 460-2 outputs the parallel data and the single-ended clock signal to the buffer circuit 470. Each deserialization circuit 460-3, 460-4 outputs the parallel data and the single-ended clock signal to the buffer circuit 472.

[0071] The buffer circuit 458 receives parallel data from 16 data lanes and two single-ended clock signals from two clock lanes from each of the deserialization circuits 450-1, 450-2, 450-3, 450-4. The buffer circuit 458 buffers or drives the data and the single-ended clock signals, and outputs the respective parallel data and single-ended clock signals on the corresponding 64 data lanes and 8 clock lanes to the buffer circuits 470, 472. Among these 64 data lanes and 8 clock lanes, the parallel data output on 32 data lanes to the buffer circuit 470 and the single-ended clock signals on 4 clock lanes correspond to the parallel data received on 16 data lanes and the single-ended clock signals on 2 clock lanes from the deserialization circuit 450-1, and the parallel data and single-ended clock signals on 16 data lanes and 2 clock lanes from the deserialization circuit 450-2. Further, among these 64 data lanes and 8 clock lanes, the parallel data output on 32 data lanes to the buffer circuit 472 and the single-ended clock signals on 4 clock lanes correspond to the parallel data received on 16 data lanes and the single-ended clock signals on 2 clock lanes from the deserialization circuit 450-3, and the parallel data and single-ended clock signals on 16 data lanes and 2 clock lanes from the deserialization circuit 450-4.

[0072] Buffer circuits 470 and 472 receive parallel data from their respective 64 data lanes and single-ended clock signals from 8 clock lanes, and output the parallel data and clock signals on the corresponding 64 data lanes and 8 clock lanes to the interface circuit of IC die 102-2. Among the parallel data on the 64 data lanes and the single-ended clock signals on the 8 clock lanes input to buffer circuit 470, the parallel data on 16 data lanes and the single-ended clock signals on 2 clock lanes are input from deserialization circuit 460-1, the parallel data on 16 data lanes and the single-ended clock signals on 2 clock lanes are input from deserialization circuit 460-2, and the parallel data on 32 data lanes and the single-ended clock signals on 4 clock lanes are input from buffer circuit 458. Among the parallel data on the 64 data lanes and the single-ended clock signals on the 8 clock lanes input to buffer circuit 472, the parallel data on 16 data lanes and the single-ended clock signals on 2 clock lanes are input from deserialization circuit 460-3, the parallel data on 16 data lanes and the single-ended clock signals on 2 clock lanes are input from deserialization circuit 460-4, and the parallel data on 32 data lanes and the single-ended clock signals on 4 clock lanes are input from buffer circuit 458.

[0073] In the foregoing embodiment, receiver circuit 202-2R receives a differential clock signal from transmitter circuit 202-1T, and uses the received differential clock signal (by conversion to a single-ended clock signal) to capture the data transmitted from transmitter circuit 202-1T via physical channel 204-12. Thus, the above-described communication is source-synchronous communication. Implementing source-synchronous communication can obviate the need to implement a clock data recovery (CDR) circuit within the receiver circuit, which can increase power efficiency.

[0074] Additionally, in the foregoing embodiments, a plurality of single-ended data signals are generated, and then data is captured from those plurality of single-ended data signals with respect to a single clock signal. In the illustrated embodiment, 16 single-ended data signals (transmitted through 16 physical channels) share a single clock signal. For example, parallel data is serialized by serializer circuits 410-1, 410-3 based on a single-ended clock signal from S2D converter circuit 412-1, and 16 single-ended data signals are transmitted on 16 physical channels from signal driver circuit 428 based on the serialized data on each of 8 data lanes from serializer circuits 410-1, 410-3. One differential clock signal from S2D converter circuit 412-1 is transmitted on 2 physical channels via signal driver circuit 428. D2S converter circuit 452-1 receives the differential clock signal and generates a single-ended clock signal used by deserialization circuits 450-1, 450-3 to capture data from 16 single-ended data signals on 16 physical channels. Other ratios of data signals to clock signals can be implemented. Using a high ratio of data signals to clock signals can improve area efficiency for the physical channels within WLFO package 100 and can improve power efficiency since a reduced number of clock signals are implemented per data signal.

[0075] More or fewer bank serializer circuits and corresponding S2D converter circuits and clock driver circuits may be included in the transmitter circuit. A retimer circuit may be included or omitted as needed for the timing of signals propagated across the transmitter circuit. For example, one or more retimer circuits may be implemented for additional banks included in the transmitter circuit. Similarly, more or fewer bank deserialzer circuits and corresponding D2S converter circuits and clock driver circuits may be included in the receiver circuit. A buffer circuit (such as buffer circuit 458) may be included or omitted as needed for signals propagated across a receiver circuit having more or fewer bank deserialzer circuits.

[0076] FIG. 5 is a circuit diagram of a clock driver circuit 500 according to some embodiments. The clock driver circuit 500 may be implemented as any clock driver circuit within the transmitter circuits of FIGS. 4A and 4B. As described above, the clock driver circuit 500 may be separated from the corresponding S2D converter circuit and serializer circuit and interposed therebetween, or may be embedded in or implemented with the corresponding S2D converter circuit and / or corresponding serializer circuit. The clock driver circuit 500 is programmable to adjust the duty cycle of a single-ended clock signal.

[0077] The clock driver circuit 500 includes p-type transistors 502, 504 (e.g., p-type field effect transistors (FETs)) and n-type transistors 506, 508 (e.g., n-type FETs). The source node of the p-type transistor 502 is electrically connected to a first power supply node (e.g., the VDD power supply node), and the drain node of the p-type transistor 502 is electrically connected to the source node of the p-type transistor 504. The drain node of the p-type transistor 504 is electrically connected to the drain node of the n-type transistor 506, and the source node of the n-type transistor 506 is electrically connected to the drain node of the n-type transistor 508. The source node of the n-type transistor 508 is electrically connected to a second power supply node (e.g., the ground node). The gate nodes of the p-type transistor 504 and the n-type transistor 506 are electrically connected to the input node 510 and / or form at least a part of the input node 510. The drain nodes of the p-type transistor 504 and the n-type transistor 506 are electrically connected to the output node 512 and / or form at least a part of the output node 512. The gate node of the p-type transistor 502 is electrically connected to a first control node 514, and the gate node of the n-type transistor 508 is electrically connected to a second control node 516.

[0078] The single-ended input clock signal (Clkin) is input to the clock driver circuit 500 on the input node 510 in operation, and the complementary single-ended output clock signal (Clkout_b) is output from the clock driver circuit 500 on the output node 512. Generally, the complementary single-ended output clock signal (Clkout_b) is the logical complement of the single-ended input clock signal (Clkin). Each control signal (Ctl_1 and Ctl_2) is applied to the first control node 514 and the second control node 516 in operation. The control signal biases the clock driver circuit 500 to adjust the switching threshold of an inverter (for example, p-type transistor 504 and n-type transistor 506) electrically connected between the p-type transistor 502 and the n-type transistor 508. By adjusting the switching threshold, the voltage on the output node 512 (for example, the complementary single-ended output clock signal (Clkout_b)) changes when transitioning from logic low to logic high, or from logic high to logic low, with respect to the voltage on the input node 510 (for example, the single-ended input clock signal (Clkin)). Therefore, biasing the clock driver circuit 500 using the control signal can cause the complementary single-ended output clock signal (Clkout_b) to have a duty cycle adjusted with respect to the single-ended input clock signal (Clkin).

[0079] In some embodiments, the first control node 514 and the second control node 516 are electrically connected to the output nodes of respective digital-to-analog converters (DACs). The DACs can be electrically coupled to programmable memory elements (e.g., registers, electronic fuses (eFuses), or other memories). The memory elements can be programmed or written using digital values corresponding to the voltages of respective control signals (Ctl_1, Ctl_2) applied to the first control node 514 or the second control node 516. The memory elements are configured to provide the digital values to the respective DACs, and the DACs convert the digital values to analog voltages that the DACs apply to the first control node 514 and the second control node 516, respectively. Different values programmed or written to the memory elements cause different analog voltages to be applied to the first control node 514 and the second control node 516, respectively, which can in turn cause the duty cycle of the single-ended clock to be adjusted differently. Thus, in such embodiments, the clock driver circuit 500 can be programmable to adjust the duty cycle of the single-ended clock signal.

[0080] The clock driver circuit 500 can include additional components in other embodiments. For example, the clock driver circuit 500 can include an inverter having an input node electrically connected to the drains of a p-type transistor 504 and an n-type transistor 506, and an output node electrically connected to the output node 512 (e.g., the inverter can be electrically connected between the drain and the output node 512). In such embodiments, the single-ended output clock signal can generally logically correspond to the single-ended input clock signal (Clkin) using a duty cycle that may be adjusted (e.g., not the logical complement of the single-ended input clock signal (Clkin)).

[0081] FIG. 6 is a circuit diagram of a clock driver circuit 600 according to some embodiments. The clock driver circuit 600 can be implemented as any clock driver circuit within the receiver circuits of FIGS. 4A and 4B. As described above, the clock driver circuit 600 can be separated from the corresponding D2S converter circuit and deserialization circuit and can be an intervening circuit therebetween, or can be embedded or implemented within the corresponding D2S converter circuit and / or the corresponding deserialization circuit. The clock driver circuit 600 is programmable to deskew and adjust the duty cycle of a single-ended clock signal.

[0082] The clock driver circuit 600 includes a deskew stage and a duty cycle adjustment stage. The deskew stage includes buffers 602-1, 602-2, 602-3, 602-4, 602-5, 602-6, 602-7, inverters 610-0, 610-2, 610-4, 610-6, 620-1, 620-3, 620-5, 620-7, 630, 632, multiplexers 612, 622, and programmable inverters 614, 624. The buffers 602-1, 602-2, 602-3, 602-4, 602-5, 602-6, 602-7 are connected in series. The input node of buffer 602-1 is the input node of the clock driver circuit 600, which is the tap 0 node 604-0. The output node of buffer 602-1 is the tap 1 node 604-1, which is electrically connected to the input node of buffer 602-2. The output node of buffer 602-2 is the tap 2 node 604-2, which is electrically connected to the input node of buffer 602-3. The output node of buffer 602-3 is the tap 3 node 604-3, which is electrically connected to the input node of buffer 602-4. The output node of buffer 602-4 is the tap 4 node 604-4, which is electrically connected to the input node of buffer 602-5. The output node of buffer 602-5 is the tap 5 node 604-5, which is electrically connected to the input node of buffer 602-6. The output node of buffer 602-6 is the tap 6 node 604-6, which is electrically connected to the input node of buffer 602-7. The output node of buffer 602-7 is the tap 7 node 604-7.

[0083] The even tap nodes (e.g., tap 0 node 604-0, tap 2 node 604-2, etc.) are electrically connected to the respective input nodes of inverters 610-0, 610-2, 610-4, 610-6, and the odd tap nodes (e.g., tap 1 node 604-1, tap 3 node 604-3, etc.) are electrically connected to the respective input nodes of inverters 620-1, 620-3, 620-5, 620-7. The output nodes of inverters 610-0, 610-2, 610-4, 610-6 are electrically connected to the respective input nodes of multiplexer 612, and the output nodes of inverters 620-1, 620-3, 620-5, 620-7 are electrically connected to the respective input nodes of multiplexer 622.

[0084] More specifically, the tap 0 node 604-0 is electrically connected to the input node of inverter 610-0, and the output node of inverter 610-0 is electrically connected to the input node of multiplexer 612. The tap 2 node 604-2 is electrically connected to the input node of inverter 610-2, and the output node of inverter 610-2 is electrically connected to the input node of multiplexer 612. The tap 4 node 604-4 is electrically connected to the input node of inverter 610-4, and the output node of inverter 610-4 is electrically connected to the input node of multiplexer 612. The tap 6 node 604-6 is electrically connected to the input node of inverter 610-6, and the output node of inverter 610-6 is electrically connected to the input node of multiplexer 612.

[0085] The tap 1 node 604-1 is electrically connected to the input node of the inverter 620-1, and the output node of the inverter 620-1 is electrically connected to the input node of the multiplexer 622. The tap 3 node 604-3 is electrically connected to the input node of the inverter 620-3, and the output node of the inverter 620-3 is electrically connected to the input node of the multiplexer 622. The tap 5 node 604-5 is electrically connected to the input node of the inverter 620-5, and the output node of the inverter 620-5 is electrically connected to the input node of the multiplexer 622. The tap 7 node 604-7 is electrically connected to the input node of the inverter 620-7, and the output node of the inverter 620-7 is electrically connected to the input node of the multiplexer 622.

[0086] The output node of the multiplexer 612 is electrically connected to the input node of the programmable inverter 614, and the output node of the multiplexer 622 is electrically connected to the input node of the programmable inverter 624. The output nodes of the programmable inverter 614 and the programmable inverter 624 are electrically connected to each other and are electrically connected to the input node of the inverter 630. The output node of the inverter 630 is electrically connected to the input node of the inverter 632, and the output node of the inverter 632 is the output node of the dequeue stage and is electrically connected to the input node 510 of the duty cycle adjustment stage.

[0087] The multiplexers 612 and 622 can each have a respective selection control node electrically coupled to a respective memory element. The memory element can be programmed or written using the digital value provided to the selection control nodes of the multiplexers 612 and 622. Accordingly, the multiplexers 612 and 622 can be configured to selectively output the signal input to a given input node of each of the multiplexers 612 and 622 based on the digital value programmed or written to the memory element.

[0088] Before describing the operation of the illustrated embodiment of FIG. 6, FIG. 7 is a circuit diagram of a programmable inverter 700 according to some embodiments. Each of the programmable inverters 614, 624 of FIG. 6 can be implemented like the programmable inverter 700 of FIG. 7. The programmable inverter 700 includes n inverter stages 702-1, 702-2, ... 702-n (individually or collectively, inverter stages 702).

[0089] Each inverter stage 702 includes p-type transistors 704, 706 and n-type transistors 708, 710. The source node of the p-type transistor 704 is electrically connected to a first power supply node (e.g., a VDD power supply node), and the drain node of the p-type transistor 704 is electrically connected to the source node of the p-type transistor 706. The drain node of the p-type transistor 706 is electrically connected to the drain node of the n-type transistor 708, and the source node of the n-type transistor 708 is electrically connected to the drain node of the n-type transistor 710. The source node of the n-type transistor 710 is electrically connected to a second power supply node (e.g., a ground node). The gate nodes of the p-type transistor 706 and the n-type transistor 708 are electrically connected to the input node 712 and / or form at least a part of the input node 712. The drain nodes of the p-type transistor 706 and the n-type transistor 708 are electrically connected to the output node 714 and / or form at least a part of the output node 714. The gate node of the p-type transistor 704 is electrically connected to the respective complementary enable node (ENBx) 716, and the gate node of the n-type transistor 710 is electrically connected to the enable node (ENx) 718, where x indicates the corresponding inverter stage 702 (e.g., in the case of inverter stage 702-1, x is 1).

[0090] In some embodiments, each enable node (ENx) 718 is electrically coupled to a programmable memory element (e.g., a register, eFuse, or other memory). The memory element can be programmed or written using a digital value that is either logic high or logic low, and that logic high or logic low value is applied to each enable node (ENx) 718 of a given inverter stage 702. An inverter is electrically coupled between the memory element and each complementary enable node (ENBx) 716 of the given inverter stage 702 to logically complement the value programmed or written to the memory element, and this logically complemented value is applied to each complementary enable node (ENBx) 716.

[0091] The inverter stage 702 includes an inverter that can be selectively operably coupled within the programmable inverter 700 based on the value written to the memory element of the inverter stage 702. For a given inverter stage 702-x, when the signal on the enable node (ENx) 718 is logic high (e.g., the supply voltage VDD) and the signal on the complementary enable node (ENBx) 716 is correspondingly logic low (e.g., the ground potential), the p-type transistor 704 and the n-type transistor 710 are in a conducting state, which operably couples the inverter formed by the p-type transistor 706 and the n-type transistor 708 to the programmable inverter 700. Conversely, when the signal on the enable node (ENx) 718 is logic low and the signal on the complementary enable node (ENBx) 716 is correspondingly logic high, the p-type transistor 704 and the n-type transistor 710 are non-conducting or open, which operably separates the inverter formed by the p-type transistor 706 and the n-type transistor 708 from the programmable inverter 700.

[0092] By programming a desired number of inverters of inverter stage 702 operably coupled in programmable inverter 700, the driveability of the signal output by programmable inverter 700 can be programmed. Assuming that the inverters of each inverter stage 702 have the same driveability (e.g., the corresponding transistors 706, 708 have the same width and length for each channel), increasing the number of inverters of inverter stage 702 operably coupled in programmable inverter 700 increases the driveability of programmable inverter 700, and conversely, decreasing the number of inverters of inverter stage 702 operably coupled in programmable inverter 700 decreases the driveability of programmable inverter 700.

[0093] Referring back to FIG. 6, in operation, the clock signal (Clk0) is input to tap 0 node 604-0 of clock driver circuit 600. This clock signal propagates through buffers 602-1 to 602-7 connected in series. The latency of the clock signal propagating through the buffer delays the clock signal output by that buffer. Thus, the clock signal (Clk1) output by buffer 602-1 on tap 1 node 604-1 is delayed once. The clock signal (Clk2) output by buffer 602-2 to tap -2 node 604-2 is delayed twice. The clock signal (Clk3) output by buffer 602-3 on tap 3 node 604-3 is delayed three times. The clock signal (Clk4) output by buffer 602-4 on tap 4 node 604-4 is delayed four times. The clock signal (Clk5) output by buffer 602-5 on tap 5 node 604-5 is delayed five times. The clock signal (Clk6) output by buffer 602-6 on tap 6 node 604-6 is delayed six times. The clock signal (Clk7) output by buffer 602-7 on tap 7 node 604-7 is delayed seven times.

[0094] Various clock signals are input to respective inverters 610-0 to 610-6 and 620-1 to 620-7, and these inverters invert the clock signals and output the inverted clock signals to respective multiplexers 612, 622. Multiplexer 612 selectively outputs a clock signal having an even multiple of delay (e.g., clock signals (Clk0, Clk2, Clk4, Clk6)) based on a digital value programmed or written in a memory element provided to a selection control node of multiplexer 612. Multiplexer 622 selectively outputs a clock signal having an odd multiple of delay (e.g., clock signals (Clk1, Clk3, Clk5, Clk7)) based on a digital value programmed or written in a memory element provided to a selection control node of multiplexer 622. Generally, although different in some cases, the clock signals output by multiplexers 612, 622 have a delay difference of one delay (e.g., a delay resulting from propagation through one buffer). For example, when a four-times delayed inverted clock signal (Clk4) is selectively output from multiplexer 612, a three-times delayed inverted clock signal (Clk3) or a five-times delayed inverted clock signal (Clk5) is generally output from multiplexer 622.

[0095] The inverted clock signals output from multiplexers 612, 622 are input to respective programmable inverters 614, 624. The clock signals output from programmable inverters 614, 624 to an input node of inverter 630 are based on the respective driving capabilities of programmable inverters 614, 624. To clarify the description herein, the clock signal output by multiplexer 612 has a phase difference θ EVEN with respect to the phase of the clock signal (Clk0) input to clock driver circuit 600, and the clock signal output by multiplexer 622 has a phase difference θ ODD with respect to the phase of the clock signal (Clk0). Further, programmable inverter 612 has a driving strength D EVENand the programmable inverter 622 has a drive strength D ODD The resulting clock signal input to inverter 630 has a phase difference θ with respect to the phase of the clock signal (Clk0). deskew The phase difference θ deskew is generally expressed as: (i)(a) driving strength D EVEN and drive strength D ODD Driving strength D for the sum of EVEN and (b) phase difference θ EVEN and (ii)(a) the driving strength D EVEN and driving strength D ODD Driving strength D for the sum of ODD and (b) phase difference θ ODD This can be mathematically rephrased as follows:

[0096]

number

[0097] The resulting clock signal passes through inverters 630, 632, which act as buffer circuits, and is input to a duty cycle adjustment stage. As can be seen from the above, the phase difference θ can be adjusted by programmatically selecting which clock signal is output from multiplexers 612, 622. EVEN , θ ODD can be programmatically selected, and drivability and drive strength D can be programmatically operably coupled to the inverter stages in the programmable inverters 614, 624. EVEN , D ODD can be programmatically selected. Thus, the resulting phase difference θ of the clock signals output from the deskew stage of the clock driver circuit 600 deskew can be selected according to the program.

[0098] In the illustrated embodiment, multiplexers 612, 622, programmable inverters 614, 624, and inverters 630, 632 form and / or are included in a complementary metal oxide semiconductor based (CMOS based) phase interpolator. Being CMOS based enables the phase interpolator to be power efficient and consume low power.

[0099] The duty cycle adjustment stage of clock driver circuit 600 includes p-type transistors 502, 504 and n-type transistors 506, 508 as described above with respect to FIG. 5. The duty cycle adjustment stage (e.g., p-type transistors 502, 504 and n-type transistors 506, 508) is configured to adjust the duty cycle of the clock signal as described above with respect to FIG. 5, and thus the detailed description of the duty cycle adjustment stage in FIG. 6 is omitted for brevity.

[0100] The clock driver circuit 600 can include additional components in other embodiments. For example, the clock driver circuit 600 can include an additional inverter having an input node electrically connected to the drains of p-type transistor 504 and n-type transistor 506 and an output node electrically connected to output node 512 (e.g., the inverter can be electrically connected between the drain and output node 512). In such embodiments, the single-ended output clock signal can generally logically correspond to the single-ended input clock signal (Clkin) using an optionally adjusted duty cycle (e.g., not the logical complement of the single-ended input clock signal (Clkin)).

[0101] FIG. 8 is a circuit diagram of a signal driver circuit 800 according to some embodiments. The signal driver circuit 428 of FIG. 4A can include an instance of the signal driver circuit 800 for each physical channel of the physical channels 204-12 driven by the signal driver circuit 428. The signal driver circuit 800 can be configured to provide equalization to the offset signals, for example, by varying the attenuation of signals at different frequencies through the corresponding physical channels.

[0102] The signal driver circuit 800 includes inverters 802, 804, 806, 810, 814, 818, programmable impedance circuits 808, 812, 816, a p-type transistor 820, an n-type transistor 822, and an electrostatic discharge (ESD) protection circuit 824. The input node of the inverter 802, which is the input node 840 of the signal driver circuit 800, is electrically connected to a lane 842 (e.g., a data lane). The signal driver circuit 800 includes a primary path and a feedforward path from the output node of the inverter 802 to the output node 844 of the signal driver circuit 800 that is electrically connected to a physical channel 846 (e.g., a physical channel of the physical channels 204-12). The primary path includes the inverter 804. The input node of the inverter 804 is electrically connected to the output node of the inverter 802, and the output node of the inverter 804 is electrically connected to the output node 844 of the signal driver circuit 800.

[0103] The feedforward path includes inverters 806, 810, 814, 818, and programmable impedance circuits 808, 812, 816. The input node of inverter 806 is electrically connected to the output node of inverter 802. The output node of inverter 806 is electrically connected to the first terminal of programmable impedance circuit 808 and the input node of inverter 810. The output node of inverter 810 is electrically connected to the first terminal of programmable impedance circuit 812 and the input node of inverter 814. The output node of inverter 814 is electrically connected to the first terminal of programmable impedance circuit 816 and the input node of inverter 818. The output node of inverter 818 is electrically connected to the output node 844 of signal driver circuit 800. The second terminal (opposite to the first terminal) of each of programmable impedance circuits 808, 812, 816 is electrically connected to a second power node (e.g., a ground node).

[0104] The p-type transistor 820 is electrically connected between a first power node (e.g., the VDD power node) and the power input node of inverter 818, and the n-type transistor 822 is electrically connected between another power input node of inverter 818 and a second power node (e.g., a ground node). The source node of the p-type transistor 820 is electrically connected to the first power node (e.g., the VDD power node), and the drain node of the p-type transistor 820 is electrically connected to the power input node of inverter 818. The other power input node of inverter 818 is electrically connected to the drain node of the n-type transistor 822. The source node of the n-type transistor 822 is electrically connected to the second power node (e.g., a ground node). The gate node of the p-type transistor 820 is electrically connected to the complementary enable node (ENB) 848, and the gate node of the n-type transistor 822 is electrically connected to the enable node (EN) 850.

[0105] In some embodiments, the enable node (EN) 850 is electrically coupled to a programmable memory element (e.g., a register, eFuse, or other memory). The memory element can be programmed or written using a digital value that is either logic high or logic low, and that logic high or logic low value is applied to the enable node (EN) 850. An inverter can be electrically coupled between the memory element and the complementary enable node (ENB) 848 to logically complement the value programmed or written to the memory element, and this logically complemented value is applied to the complementary enable node (ENB) 848.

[0106] The inverter 818 can be selectively operably coupled between power nodes based on the value written to the memory element. When the signal on the enable node (EN) 850 is logic high (e.g., the power supply voltage VDD) and the signal on the complementary enable node (ENB) 848 is correspondingly logic low (e.g., the ground potential), the p-type transistor 820 and the n-type transistor 822 are in a conducting state, which operably couples the inverter 818 between the power nodes. Conversely, when the signal on the enable node (EN) 850 is logic low and the signal on the complementary enable node (ENB) 848 is correspondingly logic high, the p-type transistor 820 and the n-type transistor 822 are in a non-conducting or open state, which operably decouples the inverter 818 from the power nodes.

[0107] Operating the inverter 818 operably separated in the feedforward path turns off the equalization in the signal driver circuit 800. When operably coupled, the inverter 818 provides the output node 844 with a current that is summed with the current output by the inverter 804. In the illustrated embodiment, the feedforward path is configured subtractively such that the current output from the inverter 818 is inverted and effectively subtracted from the current output by the inverter 804. In the illustrated embodiment, the inverters 806, 810, 814, 818 within the feedforward path are configured to generate the opposite polarity of the signal in the primary path. In some embodiments, the feedforward path is configured to be additive such that the current output from the inverter 818 is not logically inverted and is added to the current output by the inverter 804. By operably separating the inverter 818 from between the power nodes, generally no current is output from the inverter 818, and generally, no equalization is provided by the feedforward path.

[0108] When the inverter 818 is operably coupled, the signal driver circuit 800 can provide equalization of the sub-UI type. In the illustrated embodiment, the feedforward path can generate an inversion with respect to the primary path. The feedforward path generates a delay difference with respect to the primary path that may be equal to 1 UI, where 1 UI is the reciprocal of the data rate of the data passing through the signal driver circuit 800. In this way, the low-frequency component of the signal at the output node 844 can be attenuated, while the high-frequency component of the signal at the output node 844 can be amplified. The programmable impedance circuits 808, 812, 816 enable adjustment of the delay introduced by the feedforward path to approach 1 UI where the equalization can be more effective. The signal driver circuit 800 can implement a finite impulse response (FIR) filter when the inverter 818 is operably coupled between the power nodes.

[0109] Additionally, an ESD protection circuit 824 is electrically connected to an output node 844. The ESD protection circuit 824 includes diodes 826, 828. Diode 826 has a cathode electrically connected to a first power node (e.g., a VDD power node) and an anode electrically connected to the output node 844. Diode 828 has a cathode electrically connected to the output node 844 and an anode electrically connected to a second power node (e.g., a ground node).

[0110] FIG. 9 is a circuit diagram of an impedance array 900 according to some embodiments. The impedance array 900 includes q impedance elements 902-1, 902-2 to 902-q (individually or collectively, impedance element 902) and q switches 904-1, 904-2 to 904-q (individually or collectively, switch 904). The impedance element 902 is electrically connected in series with the corresponding switch 904. The series-connected pairs of the impedance element 902 and the switch 904 are electrically connected in parallel between a first terminal 906 of the impedance array 900 and a second terminal 908 of the impedance array 900.

[0111] Each switch 904 further has a control (C x ) node, where x is an indication of the corresponding switch 904 (e.g., for switch 904-1, x is 1). Each switch 904 is configured to be selectively opened and closed based on a signal received at the control (C x ) node. Each switch 904 can be a transistor (e.g., a p-type or n-type transistor), a transmission gate, or other switch. Each impedance element 902 can be a resistor, a capacitor, an inductor, or any combination or series thereof, or can include them.

[0112] The impedance array 900 is configured to selectively electrically connect or disconnect impedance elements in parallel based on the state of the switches 904 (e.g., open or closed). The impedance array 900 is programmable. In some embodiments, the control signal (C x ) can be stored in a memory element (e.g., a register, eFuse, or other memory). The output nodes of the memory elements are electrically coupled to their respective control (C x ) nodes to provide the control signal (C x ) to the control (C x ) nodes and thereby control the state of the corresponding switches 904.

[0113] FIG. 10 is a circuit diagram of an impedance array 1000 according to some embodiments. The impedance array 1000 includes r impedance elements 1002-1, 1002-2 to 1002-r (individually or collectively, impedance elements 1002) and r switches 1004-1, 1004-2 to 1004-r (individually or collectively, switches 1004). The impedance elements 1002 are electrically connected in parallel with the corresponding switches 1004. The parallel-connected pairs of impedance elements 1002 and switches 1004 are electrically connected in series between a first terminal 1006 of the impedance array 1000 and a second terminal 1008 of the impedance array 1000.

[0114] Each switch 1004 further has a control (C x ) node, where x is an indication of the corresponding switch 1004 (e.g., for switch 1004-1, x is 1). Each switch 1004 is configured to be selectively opened and closed based on a signal received at the control (C x ) node. Each switch 1004 can be a transistor (e.g., a p-type or n-type transistor), a transmission gate, or other switch. Each impedance element 1002 can be a resistor, a capacitor, an inductor, or any combination or series thereof, or can include them.

[0115] The impedance array 1000 is configured to selectively electrically connect or disconnect impedance elements in series based on the state of the switch 1004 (e.g., open or closed). When the switch 1004 is open, the corresponding impedance elements 1002 of the parallel-connected pair are electrically coupled in series with any other impedance element within the impedance array 1000. When the switch 1004 is closed, the corresponding impedance elements 1002 of the parallel-connected pair are electrically short-circuited and bypassed by the closed switch 1004, and thus, that impedance element 1002 is not coupled in series with any other impedance element within the impedance array 1000. The impedance array 1000 is programmable. In some embodiments, a control signal (C x ) can be stored in a storage element such as a memory, register, etc. The output nodes of the storage element are electrically coupled to respective control (C x ) nodes to provide the control signal (C x ) to the control (C x ) nodes to control the state of the corresponding switch 1004.

[0116] The impedance arrays 900, 1000 of FIGS. 9 and 10 can be implemented together or individually, in any configuration, arrangement, or permutation, as any or each of the programmable impedance circuits 808, 812, 816 of FIG. 8. Thus, the programmable impedance circuits 808, 812, 816 can be made programmable to achieve a number of impedances, which allows the signal driver circuit 800 to be programmable to achieve a number of different delays for equalization.

[0117] According to some embodiments, the structures of the WLFO package 100 and the IC die 102 (and the circuits therein) are co-designed, which can achieve high bandwidth density and high power efficiency. In certain embodiments, the WLFO package 100 is an InFO package. A single-ended source synchronous data link (e.g., a physical channel) operating at 13.25 Gbps is connected through the redistribution structure 110 of the InFO package. Utilizing the fine dimensions of the InFO packaging technology (e.g., a 2-μm metal line width, a 2-μm spacing between adjacent metal lines, and a 4-μm pitch of adjacent metal lines), the total throughput can be 2.53 Tbps over 2.5 mm along the lateral sidewalls 152-1, 152-2 of the IC dies 102-1, 102-2, and thus a high bandwidth density of 1 Tbps / mm or more can be achieved. In some embodiments, a high bandwidth density of 2 Tbps / mm or more can be achieved. Co-designing the IC die and the WLFO package 100 can provide additional degrees of freedom. For example, the wire spacing and shielding (e.g., as illustrated in FIG. 3) can be implemented to reduce crosstalk noise and improve the signal-to-noise ratio (SNR) of the received signal while achieving a power efficiency of 0.13 pJ / bit or better.

[0118] In some embodiments, a single-ended signaling scheme (e.g., a single-ended NRZ signaling scheme) is implemented to transmit data signals between transceiver circuits 202 on different IC dies 102. The single-ended NRZ signaling scheme can have high pin efficiency and low power requirements. The single-ended NRZ signaling scheme can be enabled at least in part by co-designing the IC die 102 and the WLFO package 100, which allows dealing with channel characteristics (e.g., crosstalk) and electrical performance together in consideration. In some embodiments, the supply voltage (e.g., the power supply voltage VDD) is selected to be 0.65 V, which can reduce power consumption while achieving a bit error rate (BER) of 1×10 -12 and reducing power consumption while achieving a bit error rate (BER) of 1×10

[0119] Various embodiments implement a source synchronous transceiver. A transmitter circuit (e.g., transmitter circuit 202-1T) transmits a clock signal that a corresponding receiver circuit (e.g., receive circuit 202-1R) uses to capture data transmitted from each transmitter circuit and received by the receiver circuit. As described above, data can be transmitted as each single-ended signal, and the clock signal can be transmitted as a differential signal. The received clock signal can optionally be deskewed and then used to capture data. The receiver circuit can use a single clock signal to capture data from data signals on multiple physical channels. In the illustrated embodiments of FIGS. 4A and 4B, as described above, one clock signal is used to capture data from 16 physical channels. Thus, in the illustrated embodiments, the data lane to clock signal ratio is 16:1. Transferring the clock signal in this way can simplify the design of clock generation in the receiver circuit and improve power efficiency. A high data lane to clock ratio can minimize the number of clock signals to be transferred from the transmitter circuit to the receiver circuit, which can improve bandwidth density and power efficiency.

[0120] In some cases, a high clock sharing ratio can degrade the horizontal eye margin. Thus, in such cases, low clock and data skew may be desirable. To reduce such skew, the characteristics of the physical channels through the redistribution structure of the WLFO package can be well matched. For example, the metal wire length of the physical channel that transmits the data signal sharing the clock signal can be made substantially equal to the metal wire length of the physical channel that transmits the clock signal. For example, if the metal wire lengths are not well matched, the clock signal or data signal may experience more latency in transmission, such as due to the larger resistance-capacitance (RC) time constant of the metal wire, which can generate a larger skew. Such matching can illustrate another reason for the co-design of the IC die and the WLFO package.

[0121] In some embodiments, the clock signal used in the receiver circuit to capture data may need to be adjusted to capture data with a relatively large eye opening. To adjust the clock signal, a clock driver circuit 600 can be implemented. In some embodiments, the clock driver circuit 600 implements a CMOS-based phase interpolator that is power efficient, such as 0.018 pJ / bit, and can be easily scaled with frequency. The CMOS-based phase interpolator can have a step size of about 3 ps. Additionally, the duty cycle distortion of the clock signal can be corrected or adjusted for better eye margin. In some embodiments, the clock driver circuit 600 can have a correction range of about 3 ps for both the rising edge and the falling edge.

[0122] In some cases, in order to maximize bandwidth density, it may be desirable to operate each physical channel such that data is transmitted at the highest possible data rate, provided that doing so is within a given power constraint. Thus, in some embodiments, the transmitter circuit implements the signal driver circuit 800 of FIG. 8 in which equalization is selectively enabled. Performing equalization can equalize channel loss and, in some cases, enable a data rate of 13.25 Gbps at the expense of 0.01 pJ / bit. It has been found that performing equalization increases the margin of the eye opening at the receiver circuit.

[0123] The various components of the embodiments described above have been described as being programmable. In some embodiments, the transceiver circuits implemented within the WLFO package are not programmable. In other embodiments that implement various programmable components, such components can be programmed once or multiple times. For example, the channel characteristics of the WLFO package are mostly static once the WLFO package is manufactured. Once manufactured, tests can be performed, for example, to achieve a clock signal with an appropriate duty cycle and / or skew, and / or to implement appropriate equalization, and appropriate memory elements can be programmed based on the results of the tests. The memory element can be, for example, an eFuse that can be blown to program the memory element. Since the channel characteristics are mostly static, the eFuse can be blown once to achieve the appropriate functionality of the WLFO package. In other embodiments, the channel characteristics can change over the life of the WLFO package, such as due to process-voltage-temperature (PVT) variations. In such cases, the IC die can implement a processor or controller that can implement an adaptive algorithm based on, for example, a PVT monitor, BER, or any other criterion that allows for dynamic programming of memory elements. In such embodiments, the memory element can be, for example, a static random access memory (SRAM) or another latch circuit.

[0124] FIG. 11 is a flowchart of a method 1100 for operating an electronic device according to some embodiments. Method 1100 is described in the context of the above-described embodiments and figures, particularly FIGS. 4A and 4B. A subset of the functions of the above-described embodiments and figures is described with respect to method 1100, and those skilled in the art will readily understand the applicability to each complete embodiment of method 1100. The following description in the context of FIGS. 4A and 4B is provided from the perspective of the transmitter circuit 202-1T in the transceiver circuit 202-1 that transmits a data signal to the receiver circuit 202-2R within the transceiver circuit 202-2. It should be understood that the transceiver circuit 202-1 can include a receiver circuit 202-1R, the transceiver circuit 202-2 can include a transmitter circuit 202-2T, and the transmitter circuit 202-2T transmits a data signal to the receiver circuit 202-1R.

[0125] In block 1102, a first single-ended clock signal and parallel data are received in the transmitter circuit of the transceiver circuit of the first IC die. For example, the parallel data is received by the buffer circuit 402 of the transmitter circuit 202-1T, and the single-ended clock signal is received by the clock driver circuit 406 of the transmitter circuit 202-1T.

[0126] In block 1104, a differential clock signal is generated based on the first single-ended clock signal by a single-ended-to-differential converter circuit of the transmitter circuit. For example, the S2D converter circuit 412-1 generates a differential clock signal based on the single-ended clock signal received in the clock driver circuit 406.

[0127] In block 1106, optionally, a second single-ended clock signal is generated by adjusting the duty cycle of the first single-ended clock signal by a clock driver circuit of the transmitter circuit. For example, clock driver circuit 414-1 can adjust the duty cycle of the single-ended clock signal from clock driver circuit 406. In other embodiments, clock driver circuit 414-1 buffers the single-ended clock signal received at clock driver circuit 406 without adjusting the duty cycle.

[0128] In block 1108, parallel data is serialized based on the second single-ended clock signal by a serializer circuit of the transmitter circuit. For example, serializer circuit 410-1 serializes the parallel data received from buffer circuit 402 based on the single-ended clock signal generated by clock driver circuit 414-1.

[0129] In block 1110, the serialized data from the serializer circuit and the differential clock signal are transmitted through a physical channel to a transceiver circuit of a second IC die. For example, the serialized data output by serializer circuit 410-1 and the differential clock signal output by S2D converter circuit 412-1 are transmitted by signal driver circuit 428 through physical channel 204-12 to transceiver circuit 202-2. Signal driver circuit 428 can drive the serialized data (e.g., as a single-ended data signal) and the differential clock signal on the physical channel. Signal driver circuit 428 can also equalize the single-ended data signal and the differential clock signal.

[0130] In block 1112, a third single-ended clock signal is generated based on the differential clock signal by the differential-single-ended converter circuit of the receiver circuit. For example, the D2S converter circuit 452-1 receives the differential clock signal generated by the S2D converter circuit 412-1 and generates a single-ended clock signal based on the differential clock signal.

[0131] In block 1114, optionally, a fourth single-ended clock signal is generated by the clock driver circuit of the receiver circuit by deskewing the third single-ended clock signal and adjusting its duty cycle. For example, the clock driver circuit 454-1 can generate a single-ended clock signal by deskewing the single-ended clock signal generated by the D2S converter circuit 452-1 and adjusting its duty cycle. In other embodiments, the clock driver circuit 454-1 buffers the single-ended clock signal generated by the D2S converter circuit 452-1 without deskewing and / or adjusting the duty cycle.

[0132] In block 1116, the serialized data is captured and deserialized based on the fourth single-ended clock signal by the deserialization circuit of the receiver circuit. For example, the deserialization circuit 450-1 captures the serialized data serialized by the serializer circuit 410-1 from the data signal on the physical channel 204-12 and deserializes the data based on the single-ended clock signal generated by the clock driver circuit 454-1.

[0133] In block 1118, the deserialized parallel data is output from the receiver circuit. For example, the deserialized parallel data from the deserialization circuit 450-1 is output from the receiver circuit 202-2R via the buffer circuits 458, 470.

[0134] Other functions of the embodiments, as well as the structures of the embodiments, have been described above, and those skilled in the art will readily understand such functions and structures from the foregoing.

[0135] The foregoing is directed to specific embodiments, but other and further embodiments may be devised without departing from the basic scope thereof, which is determined by the following claims.

Claims

1. An electronic device, a wafer-level fan-out package, comprising a first integrated circuit (IC) die including a transmitter circuit, a second IC die including a receiver circuit, a redistribution structure electrically connected to the transmitter circuit and the receiver circuit and having a physical channel therebetween, wherein the transmitter circuit is configured to transmit a plurality of single-ended data signals and a differential clock signal through the physical channel to the receiver circuit, and the receiver circuit is configured to capture data from the plurality of single-ended data signals using a first single-ended clock signal based on the differential clock signal; and the physical channel includes channel metal lines within the redistribution structure, and the channel metal lines are arranged alternately with shield metal lines within the redistribution structure.

2. The transmitter circuit includes a single-ended to differential converter circuit configured to generate the differential clock signal based on a second single-ended clock signal; and a serializer circuit configured to receive parallel data and serialize the parallel data based on the second single-ended clock signal or a third single-ended clock signal based on the second single-ended clock signal, and output the serialized data, wherein the transmitter circuit is configured to transmit the serialized data as the plurality of single-ended data signals. The electronic device according to claim 1.

3. The transmitter circuit according to claim 2 includes a clock driver circuit configured to generate the third single-ended clock signal by adjusting a duty cycle of the second single-ended clock signal.

4. The transmitter circuit according to claim 1 includes a signal driver circuit configured to drive the plurality of single-ended data signals and the differential clock signal on the physical channel.

5. The electronic device according to claim 4, wherein each of the signal driver circuits is configured to equalize the plurality of single-ended data signals.

6. Each of the signal driver circuits respectively includes a primary path electrically connected between a first node and a driver output node, the primary path including a first inverter; and a secondary path electrically connected between the first node and the driver output node, the secondary path including a second inverter and an impedance circuit, the second inverter being configured to generate an opposite polarity of the signal of the primary path. The electronic device according to claim 4, comprising a secondary path.

7. The impedance circuit is programmable, The electronic device according to claim 6, wherein at least one of the second inverters is configured to be selectively operably coupled in the secondary path according to a program.

8. The receiver circuit includes a differential-single-ended converter circuit configured to generate a second single-ended clock signal based on the differential clock signal; and a deserialization circuit configured to receive at least some of the plurality of single-ended data signals and deserialize data from at least some of the plurality of single-ended data signals based on the second single-ended clock signal or the first single-ended clock signal based on the second single-ended clock signal. The electronic device according to claim 1, comprising:

9. The electronic device according to claim 8, wherein the receiver circuit includes a clock driver circuit configured to deskew the second single-ended clock signal and generate the first single-ended clock signal by adjusting a duty cycle of the second single-ended clock signal.

10. An electronic device, comprising a first transceiver circuit within a first integrated circuit (IC) die, the first IC die being disposed within a wafer-level fan-out package. A second transceiver circuit within a second IC die, wherein the second IC die is disposed within the wafer-level fan-out package, the second transceiver circuit; A physical channel within a redistribution structure of the wafer-level fan-out package; The first transceiver circuit is configured to transmit a plurality of first single-ended data signals and a first differential clock signal to the second transceiver circuit through a first subset of the physical channels; The second transceiver circuit is configured to transmit a plurality of second single-ended data signals and a second differential clock signal to the first transceiver circuit through a second subset of the physical channels; The second transceiver circuit is configured to capture data from the plurality of first single-ended data signals using a first single-ended clock signal based on the first differential clock signal; The first transceiver circuit is configured to capture data from the plurality of second single-ended data signals using a second single-ended clock signal based on the second differential clock signal; The physical channel is within the redistribution structure and includes channel metal lines disposed laterally between the first IC die and the second IC die, the channel metal lines being alternately disposed with shield metal lines within the redistribution structure, an electronic device. **Claim 11** The first transceiver circuit, A first single-ended to differential converter circuit configured to generate the first differential clock signal based on a third single-ended clock signal; A first serializer circuit configured to receive first parallel data and serialize the first parallel data based on the third single-ended clock signal or a fourth single-ended clock signal based on the third single-ended clock signal, and output first serialized data, wherein the first transceiver circuit is configured to transmit the first serialized data as the plurality of first single-ended data signals; A first differential-single-ended converter circuit configured to generate a fifth single-ended clock signal based on the second differential clock signal; A first deserialization circuit configured to deserialize data from the plurality of second single-ended data signals based on the fifth single-ended clock signal or a second single-ended clock signal based on the fifth single-ended clock signal; and The second transceiver circuit includes A second single-ended-differential converter circuit configured to generate the second differential clock signal based on a sixth single-ended clock signal; A second serializer circuit configured to receive second parallel data, serialize the second parallel data based on the sixth single-ended clock signal or a seventh single-ended clock signal based on the sixth single-ended clock signal, and output second serialized data, wherein the second transceiver circuit is configured to transmit the second serialized data as the plurality of second single-ended data signals; A second differential-single-ended converter circuit configured to generate an eighth single-ended clock signal based on the first differential clock signal; The electronic device according to claim 10, further comprising a second deserialization circuit configured to deserialize data from the plurality of first single-ended data signals based on the eighth single-ended clock signal or a first single-ended clock signal based on the eighth single-ended clock signal. **Claim 12** The first transceiver circuit includes a first signal driver circuit configured to drive the plurality of first single-ended data signals and the first differential clock signal on the first subset of the physical channels, and the first signal driver circuit is configured to equalize the plurality of first single-ended data signals. The second transceiver circuit includes a second signal driver circuit configured to drive the plurality of second single-ended data signals and the second differential clock signal on the second subset of the physical channels, and the second signal driver circuit is configured to equalize the plurality of second single-ended data signals. The electronic device according to claim 10.

13. A method of operating an electronic device, the method comprising: generating, by a single-ended to differential converter circuit of a first transceiver circuit of a first integrated circuit (IC) die, a differential clock signal based on a first single-ended clock signal, wherein the first IC die is disposed within a wafer level fan-out package; serializing parallel data based on the first single-ended clock signal by a serializer circuit of the first transceiver circuit; transmitting the serialized data from the serializer circuit and the differential clock signal to a second transceiver circuit of a second IC die through a physical channel of the wafer level fan-out package, wherein the second IC die is disposed within the wafer level fan-out package; deserializing the serialized data based on the differential clock signal by a deserialization circuit of the second transceiver circuit.

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