Display device

Abstract

To provide higher shock resistance to a semiconductor device having a transistor using an oxide semiconductor; and provide a semiconductor device which can meet diverse uses to achieve improved convenience and high reliability.SOLUTION: A semiconductor device has on a substrate, a gate electrode, a first insulation layer, an oxide semiconductor layer, a second insulation layer and a conductive layer. Each of the gate electrode and the conductive layer extends beyond both ends of the oxide semiconductor layer in a channel width direction of a transistor and in a cross section of the transistor in the channel width direction, the oxide semiconductor layer is surrounded by the gate electrode, the first insulation layer, the second insulation layer and the conductive layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Generally speaking, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. [Background technology]

[0003] Thin film transistors (TFTs) are fabricated using semiconductor thin films formed on substrates with insulating surfaces. Thin-film transistors are used in integrated circuits (ICs) and image display devices ( It is widely used in electronic devices such as LCDs.

[0004] Metal oxides have been attracting attention as materials that exhibit semiconducting properties that can be applied to thin-film transistors. A thin film transistor having a channel formation region made of a metal oxide exhibiting such semiconductor properties is It is known (see Patent Documents 1 and 2).

[0005] In addition, electronic devices using thin-film transistors are used in a variety of places and for a variety of purposes. As a result, the characteristics and shapes required, such as light weight, thinness, and impact resistance, are becoming more diverse. Therefore, development of electronic devices with functionality suited to the purpose is underway.

[0006] For example, as a semiconductor device to be provided in a gaming machine, A display having a curved surface has been reported (see, for example, Patent Document 3). [Prior art documents] [Patent documents]

[0007] Patent Document 1 Japanese Patent Application Laid-Open No. 2007-123861 Patent Document 2 Japanese Patent Application Laid-Open No. 2007-96055 Patent Document 3 Japanese Patent Application Laid-Open No. 7-114347 SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] When a semiconductor device is used in various shapes as described above, it is required to impart high resistance to the semiconductor device against external impacts.

[0009] Therefore, one aspect of the present invention aims to impart higher impact resistance to a semiconductor device having a transistor using an oxide semiconductor.

[0010] Another aspect of the present invention aims to provide a highly reliable semiconductor device that can cope with more diverse applications and has improved convenience. MEANS FOR SOLVING THE PROBLEMS

[0011] One aspect of the configuration of the invention disclosed in this specification is a bottom gate structure transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer on a substrate, an insulating layer on the transistor, and a conductive layer on the insulating layer. The insulating layer covers the oxide semiconductor layer and is provided in contact with the gate insulating layer. In the channel width direction of the oxide semiconductor layer, the ends of the gate insulating layer and the insulating layer coincide on the gate electrode layer. The conductive layer covers the channel formation region of the oxide semiconductor layer, the ends of the gate insulating layer and the insulating layer, and is provided in contact with the gate electrode layer.

[0012] One form of the configuration of the invention disclosed in this specification is for a drive circuit with a bottom gate structure on the same substrate. It has a drive circuit section including a transistor and a pixel section including a pixel transistor. The transistor for the drive circuit includes a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer. An insulating layer is provided on the oxide semiconductor layer, and a conductive layer is provided on the insulating layer. The insulating layer covers the oxide semiconductor layer and is provided in contact with the gate insulating layer. In the channel width direction of the oxide semiconductor layer, the ends of the gate insulating layer and the insulating layer coincide on the gate electrode layer. The conductive layer covers the channel formation region of the oxide semiconductor layer, the ends of the gate insulating layer and the insulating layer, and is provided in contact with the gate electrode layer. It is a semiconductor device. In the above configuration, the source electrode layer and the drain electrode layer may be provided between the oxide semiconductor layer and the insulating layer, or may be provided between the gate insulating layer and the oxide semiconductor layer. In the above configuration, the channel formation region of the oxide semiconductor layer is surrounded by the gate insulating layer and the insulating layer laminated one above the other in the channel width direction, and further by the gate electrode layer and the conductive layer, so it has excellent shock resistance and the shape can be freely processed using a flexible substrate for the substrate. When a transistor including an oxide semiconductor layer is provided on a flexible substrate, a flexible semiconductor device can be manufactured. The transistor including the oxide semiconductor layer may be directly manufactured on the flexible substrate, or the transistor including the oxide semiconductor layer may be manufactured on another manufacturing substrate and then peeled off and transferred to the flexible substrate. Note that in order to peel off and transfer from the manufacturing substrate to the flexible substrate, an adhesive layer may be provided between the manufacturing substrate and the oxide semiconductor layer.

[0013] In the above configuration, the source electrode layer and the drain electrode layer may be provided between the oxide semiconductor layer and the insulating layer, or may be provided between the gate insulating layer and the oxide semiconductor layer.

[0014] In the above configuration, the channel formation region of the oxide semiconductor layer is surrounded by the gate insulating layer and the insulating layer laminated one above the other in the channel width direction, and further by the gate electrode layer and the conductive layer, so it has excellent shock resistance and the shape can be freely processed using a flexible substrate for the substrate.

[0015] When a transistor including an oxide semiconductor layer is provided on a flexible substrate, a flexible semiconductor device can be manufactured.

[0016] The transistor including the oxide semiconductor layer may be directly manufactured on the flexible substrate, or the transistor including the oxide semiconductor layer may be manufactured on another manufacturing substrate and then peeled off and transferred to the flexible substrate. For peeling off and transferring from the manufacturing substrate to the flexible substrate, an adhesive layer may be provided between the manufacturing substrate and the oxide semiconductor layer.​​​​​​​ It is preferable to provide a peeling layer between the transistor including the layer.

[0017] One embodiment of the configuration of the invention disclosed in this specification is to form a gate electrode layer on a flexible substrate, and form a gate insulating layer on the gate electrode layer, form an oxide semiconductor layer on the gate insulating layer, form an insulating layer covering the oxide semiconductor layer, form an opening in the gate insulating layer and the insulating layer to expose the gate electrode layer, cover the upper part of the stack of the gate insulating layer and the insulating layer and the end of the stack of the gate insulating layer and the insulating layer at the opening, and form a conductive layer in contact with the gate electrode layer, which is a manufacturing method of a semiconductor device. One embodiment of the configuration of the invention disclosed in this specification is to form a peeling layer on a manufacturing substrate, form a gate electrode layer on the peeling layer, form a gate insulating layer on the gate electrode layer, form an oxide semiconductor layer on the gate insulating layer, form an insulating layer covering the oxide semiconductor layer, form an opening in the gate insulating layer and the insulating layer to expose the gate electrode layer, cover the upper part of the stack of the gate insulating layer and the insulating layer and the end of the stack of the gate insulating layer and the insulating layer at the opening, and form a conductive layer in contact with the gate electrode layer to manufacture a transistor, transfer the transistor from the manufacturing substrate to a support substrate using the peeling layer, and transfer the transistor transferred to the support substrate onto a flexible substrate, which is a manufacturing method of a semiconductor device. Note that the ordinal numbers attached as the first and second are used for convenience and do not indicate the process order or the stacking order. Also, they do not indicate specific names unique to the matters for specifying the invention in this specification.

Effect of the Invention

[0018]

[0019]

[0020] ​​​​​​​​​​​​​​One aspect of the present invention is to laminate the channel formation region of the oxide semiconductor layer in the channel width direction by a gate insulating layer, an insulating layer, a gate electrode layer, and a conductive layer, and surround it, so that impact resistance can be added.

[0021] One aspect of the present invention can provide a highly reliable semiconductor device with improved convenience by imparting flexibility to cope with more diverse applications.

Brief Description of the Drawings

[0022]

Figure 1

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Figure 11

Embodiments for Carrying Out the Invention

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can make various changes to its form and details. ​This can be easily understood. Further, the present invention is not construed as being limited to the description of the embodiments shown below. It is not so construed.

[0024] (Embodiment 1) In this embodiment, one form of a semiconductor device and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 and 3. In this embodiment, a transistor is shown as an example of the semiconductor device. Note that in the semiconductor device disclosed in the specification, an oxide semiconductor layer can be preferably used as the semiconductor layer.

[0025] As shown in FIGS. 1(A) to (C), the channel formation region of the oxide semiconductor layer 403 of the transistor 410 has a channel length (L) direction and a channel width (W) direction.

[0026] FIG. 1(A) is a plan view of the transistor 410, FIG. 1(B) is a cross-sectional view taken along line A1 - A2 in the channel length (L) direction of the transistor 410 shown in FIG. 1(A), and FIG. 1(C) is a cross-sectional view taken along line B1 - B2 in the channel width (W) direction.

[0027] As shown in FIGS. 1(A) to (C), the transistor 410 includes a gate electrode layer 401, a gate insulating layer 402, an oxide semiconductor layer 403, a source electrode layer 405a, and a drain electrode layer 405b on a substrate 400 having an insulating surface. An insulating layer 407 and a conductive layer 411 are sequentially stacked on the transistor 410.

[0028] Also, in the cross-sectional view in the channel width direction of FIG. 1(C), the oxide semiconductor layer 403 is surrounded by the gate insulating layer 402 and the insulating layer 407 at the top, bottom, and ends, and the gate insulating layer 402 and the insulating layer 407 are in contact with each other at both ends. A gate electrode layer 401 is provided below the gate insulating layer 402. ​​​​​​​​​Thus, an oxide semiconductor layer 403, a gate insulating layer 402, and an insulating layer are formed on the insulating layer 407. A conductive layer 411 is provided to cover the upper part of the insulating layer 407, both ends of the gate insulating layer 402 and the insulating layer 407, and is in contact with the gate electrode layer 401.

[0029] Therefore, in the channel width direction, the oxide semiconductor layer 403 is surrounded by the gate insulating layer 402, the insulating layer 407, the gate electrode layer 401, and the conductive layer 411.

[0030] In this way, when the periphery of the oxide semiconductor layer 403 is protected by the stack of the gate insulating layer, the gate electrode layer, the insulating layer, and the conductive layer, even if a force (an externally applied force) in the channel width (W) direction as shown by the arrow 445 in Fig. 1(C) is applied, the thick stack structure is difficult to bend, so the force applied to the oxide semiconductor layer 403 located at the center of the stack can be reduced. Therefore, breakage of the oxide semiconductor layer 403 due to an external impact can be prevented.

[0031] In addition, an opening is formed in the gate insulating layer 402 and the insulating layer 407 so that the gate electrode layer 401 is widely exposed, and the gate electrode layer 401 and the conductive layer 411 are in contact with each other in the opening. If a conductive film with good adhesion is used for the gate electrode layer 401 and the conductive layer 411, peeling of the film at the interface of the gate electrode layer 401, the gate insulating layer 402, the oxide semiconductor layer 403, the insulating layer 407, or the conductive layer 411 due to the force shown by the arrow 445 can be prevented.

[0032] In order to increase the adhesion between the gate electrode layer 401 and the conductive layer 411, it is preferable to provide a wide contact area. As shown in Fig. 1(A), the gate electrode layer 401 and the conductive layer 411 are in contact with each other. ​​​​​​​​​​The distance in the channel length direction of the oxide semiconductor layer 403 in the region is preferably longer than the distance of the channel length of the oxide semiconductor layer 403 is preferably longer than the distance of the channel length of the oxide semiconductor layer 403

[0033] Further, the oxide semiconductor layer 403 is disposed in the center, and both ends thereof are sealed in contact with the gate insulating layer 402 and the insulating layer 407, and further, both ends thereof are sealed in contact with the gate electrode layer 401 and the conductive layer 411, so that a structure symmetric with respect to the line C1 - C2 can be obtained. Therefore, the force shown by the arrow 4 45 is evenly distributed, and it is possible to prevent a locally large force from being applied to the oxide semiconductor layer 403 from being applied to the oxide semiconductor layer 403 from being applied to the oxide semiconductor layer 403

[0034] Therefore, in the transistor 410, the bending resistance in the channel width direction of the oxide semiconductor layer 403 can be increased, and impact resistance can be imparted to the oxide semiconductor layer 403, and impact resistance can be imparted

[0035] In a drive circuit, it is preferable to provide a longer channel width of the transistor in order to allow a larger current to flow. However, in a transistor with a long channel width, the influence of an external force in the channel width direction also increases. Therefore, it is more effective to use a transistor having bending resistance in the channel width direction as shown in the present embodiment, and a semiconductor device with excellent impact resistance and high reliability can be obtained and high reliability can be obtained and high reliability can be obtained

[0036] Since it has impact resistance, a flexible substrate can be used for the substrate 400, and it can also be applied to applications as a flexible semiconductor device, corresponding to more diversified applications, and improving convenience and providing a highly reliable semiconductor device with improved convenience and providing a highly reliable semiconductor device with improved convenience

[0037] Note that the transistor disclosed in this specification is particularly in the channel width direction of the oxide semiconductor layer Since it has excellent bending resistance, when manufacturing a semiconductor device, it is preferable to fabricate a transistor with the channel width direction aligned in the direction where it is easily bent (the direction with a high bending frequency). High direction).

[0038] FIGS. 3(A1)(A2) to (E1)(E2) show an example of a method for fabricating a transistor 410. Note that FIGS. 3(A1) to (E1) correspond to FIG. 1(B), and FIGS. 3(A2) to ( E2) correspond to FIG. 1(C).

[0039] First, after forming a conductive film on a substrate 400 having an insulating surface, a gate electrode layer 401 is formed by a first photolithography process. Note that a resist mask may be formed by an inkjet method. When a resist mask is formed by an inkjet method, since a photomask is not used the manufacturing cost can be reduced.

[0040] As the substrate 400 having an insulating surface, a flexible substrate can be used, for example, polyethylene tere phthalate (PET), polyester resins such as polyethylene naphthalate (PEN), polyacrylonitrile resin, polyimide resin, polymethyl methacrylate resin, polycar bonate resin (PC), polyethersulfone resin (PES), polyamide resin, cyclo olefin resin, polystyrene resin, polyamideimide resin, polyvinyl chloride resin, etc. can be preferably used. As the flexible substrate, a structure in which a fibrous body is impregnated with an organic resin (so-called prepreg) may be used. Further, on the substrate 400, a film having low water permeability such as a film containing nitrogen and silicon such as silicon nitride or silicon oxynitride or a film containing nitrogen and aluminum such as aluminum nitride can be formed in advance as a protective film.

[0041] ​When the fibrous body is included in the material of the substrate 400, the fibrous body uses high-strength fibers of organic compounds or inorganic compounds. The high-strength fiber specifically refers to a fiber with a high tensile elastic modulus or Young's modulus. Representative examples include polyvinyl alcohol-based fibers, polyester-based fibers, polyamide-based fibers, polyethylene-based fibers, aramid-based fibers, polyphenylene benzobisoxazole fibers, glass fibers, or carbon fibers. Examples of glass fibers include glass fibers using E glass, S glass, D glass, Q glass, etc. These are used in the state of woven fabric or non-woven fabric, and an organic resin is impregnated into this fibrous body and the organic resin is cured to obtain a structure, which may be used as the substrate 400. Using a structure composed of a fibrous body and an organic resin as the substrate 400 is a preferable configuration because the reliability against breakage due to bending or local pressing is improved.

[0042] In addition, a glass substrate thinned to have flexibility (for example, barium borosilicate glass or aluminoborosilicate glass) or a metal substrate formed into a film may be used. There is no particular limitation on the material constituting the metal substrate, but alloys of metals such as aluminum, copper, nickel, aluminum alloys, or stainless steel can be preferably used.

[0043] To fabricate a flexible semiconductor device, the transistor 410 including the oxide semiconductor layer 403 may be directly fabricated on the flexible substrate, or the transistor 410 including the oxide semiconductor layer 403 may be fabricated on another fabrication substrate and then peeled and transferred to the flexible substrate. In addition, in order to peel and transfer from the fabrication substrate to the flexible substrate, it is preferable to provide a peeling layer between the fabrication substrate and the transistor including the oxide semiconductor layer. ​​​​​​​​​​

[0044] An insulating film serving as an underlayer film may be provided between the substrate 400 and the gate electrode layer 401. The underlayer film has a function of preventing diffusion of impurity elements from the substrate 400, and is formed by a stacked structure of one or more films selected from a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film.

[0045] Further, the material of the gate electrode layer 401 can be formed as a single layer or by stacking using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or an alloy material mainly composed of these.

[0046] Next, a gate insulating layer 402 is formed on the gate electrode layer 401. The gate insulating layer 402 can be formed as a single layer or by stacking a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, an aluminum oxide layer, an aluminum nitride layer, an aluminum oxynitride layer, an aluminum nitride oxide layer, or a hafnium oxide layer using a plasma CVD method, a sputtering method, or the like.

[0047] The oxide semiconductor of the present embodiment is purified to a high purity so that impurities are removed and impurities serving as carrier donors other than the main component of the oxide semiconductor are contained as little as possible, thereby becoming intrinsic (type I) or substantially intrinsic (type I)-typed oxide semiconductor is used.

[0048] In the highly purified oxide semiconductor layer, carriers are extremely few (close to zero), and the carrier concentration is less than 1×10 14 / cm 3 , preferably less than 1×10 12 / cm 3 , more preferably ​​​​is less than 1×10 11 / cm 3 .

[0049] Since there are extremely few carriers in the oxide semiconductor layer, in a transistor, the off-current can be reduced . The smaller the off-current, the more preferable it is.

[0050] Such highly purified oxide semiconductors are extremely sensitive to interface states and interface charges . Therefore, the interface between the oxide semiconductor layer and the gate insulating layer is important. For this reason, the gate insulating layer in contact with the highly purified oxide semiconductor is required to be of high quality.

[0051] For example, high-density plasma CVD using microwaves (for example, a frequency of 2.45 GHz) is preferable because it can form a high-quality insulating layer with high density and high breakdown voltage. By closely contacting the highly purified oxide semiconductor with the high-quality gate insulating layer, the interface states can be reduced and the interface characteristics can be made good . Of course, as long as a high-quality insulating layer can be formed as the gate insulating layer, other film-forming methods such as sputtering

[0052] method and plasma CVD method can be applied. Also, an insulating layer whose film quality and interface characteristics with the oxide semiconductor are modified by heat treatment after film formation is also good. In any case, it is needless to say that the film quality as the gate insulating layer is good, and as long as it can reduce the interface state density with the oxide semiconductor and form a good interface. In addition, in order to minimize the inclusion of hydrogen, hydroxyl groups, and moisture in the gate insulating layer 402 and the oxide semiconductor film 440, as a pretreatment for forming the oxide semiconductor film 440, sputtering

[0053] is performed ​A substrate 400 on which a gate electrode layer 401 is formed in a preheating chamber of a device, or a substrate 400 on which a gate insulating layer 4 up to 02 is formed is preheated to desorb and exhaust impurities such as hydrogen and moisture adsorbed on the substrate 400. The exhaust means provided in the preheating chamber is preferably a cryo pump. Note that this preheating process can also be omitted. Also, this preheating can be similarly performed on the substrate 400 on which the source electrode layer 405a and the drain electrode layer 405b are formed before the formation of the insulating layer 407. Next, an oxide semiconductor film 440 having a film thickness of 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less, is formed on the gate insulating layer 402 (see FIGS. 3(A1) and (A2)).

[0054] Before forming the oxide semiconductor film 440 by sputtering, it is preferable to perform reverse sputtering in which argon gas is introduced to generate plasma to remove powdery substances (also called particles and dust) adhering to the surface of the gate insulating layer 402. Reverse sputtering is

[0055] a method of forming plasma near the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere without applying a voltage to the target side to modify the surface. Note that nitrogen, helium, oxygen, etc. may be used instead of the argon atmosphere.

[0056] As the oxide semiconductor used for the oxide semiconductor film 440, a quaternary metal oxide such as an In-Sn-Ga-Zn-O-based oxide semiconductor, or a ternary metal oxide such as an In-Ga-Zn-O-based oxide semiconductor, an In-Sn-Zn-O-based oxide semiconductor, an In-Al-Zn-O-based oxide semiconductor, a Sn-Ga-Zn-O-based oxide semiconductor, an Al-Ga-Zn-O-based oxide semiconductor, S n-Ga-Zn-O-based oxide semiconductor, or a Sn-Ga-Zn-O-based oxide semiconductor, an Al-Ga-Zn-O-based oxide semiconductor, etc. n-Al-Zn-O oxide semiconductors and In-Zn-O oxides, which are binary metal oxides Semiconductors, Sn-Zn-O oxide semiconductors, Al-Zn-O oxide semiconductors, Zn-Mg- O-based oxide semiconductors, Sn-Mg-O-based oxide semiconductors, In-Mg-O-based oxide semiconductors, In-O oxide semiconductors, Sn-O oxide semiconductors, Zn-O oxide semiconductors, etc. The oxide semiconductor may contain SiO2. In-Ga-Zn-O oxide semiconductors are made of indium (In), gallium (Ga), and zinc. It means an oxide film containing lead (Zn), and the stoichiometric ratio is not important. In addition, elements other than In, Ga, and Zn may be included.

[0057] The oxide semiconductor film 440 is formed of a compound represented by the chemical formula InMO3(ZnO). m (m>0) A thin film can be used. Here, M is one selected from Ga, Al, Mn, and Co. Or it represents multiple metal elements. For example, M can be Ga, Ga and Al, Ga and Mn, or or Ga and Co.

[0058] In this embodiment, the oxide semiconductor film 440 is an In—Ga—Zn—O-based oxide target. The oxide semiconductor film 440 is formed by a sputtering method using a rare gas ( Typically, in an argon atmosphere, an oxygen atmosphere, or a mixture of rare gas and oxygen. The film can be formed by a sputtering method.

[0059] Examples of targets for forming the oxide semiconductor film 440 by a sputtering method include The composition ratio is In2O3:Ga2O3:ZnO=1:1:1 [molar ratio] Using a target, an In-Ga-Zn-O film is formed. Also, the material and composition of this target are not limited. For example, an oxide target with In2O3:Ga2O3:ZnO = 1:1:2 [mole ratio] may be used.

[0060] Also, the filling rate of the oxide target is 90% or more and 100% or less, preferably 95% or more and 99 .9% or less. By using a metal oxide target with a high filling rate, the formed oxide semiconductor film can be made dense.

[0061] For the oxide semiconductor film 440, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups, or hydrogen compounds have been removed as the sputtering gas used during film formation.

[0062] A substrate is held in a film formation chamber maintained in a reduced-pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the film while heating the substrate, the impurity concentration in the formed oxide semiconductor film can be reduced. Also, the damage caused by sputtering is reduced. Then, while removing the residual moisture in the film formation chamber, a sputtering gas from which hydrogen and moisture have been removed is introduced, and an oxide semiconductor film 440 is formed on the substrate 400 using the above target. To remove the residual moisture in the film formation chamber, it is preferable to use an adsorption-type vacuum pump, for example, a cryopump, an ion pump, or a titanium sublimation pump. Also, as the exhaust means, a turbo pump (turbo molecular pump) with a cold trap added may be used. The film formation chamber evacuated using a cryopump contains, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H2O) (more preferably compounds containing carbon atoms Therefore, since (e.g.,) is exhausted, the concentration of impurities contained in the oxide semiconductor film formed in the film formation chamber can be reduced.

[0063] As an example of the film formation conditions, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 Pa , and conditions under an atmosphere of a direct current (DC) power source of 0.5 kW and oxygen (oxygen flow rate ratio: 100%) are applied Note that when a pulsed DC power source is used, it is preferable because powdery substances (also called particles or dust) generated during film formation can be reduced and the film thickness distribution becomes uniform.

[0064] Next, the oxide semiconductor film 440 is processed into island-shaped oxide semiconductor layers by a second photolithography process. Further, a resist mask for forming the island-shaped oxide semiconductor layer may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0065] Also, when forming a contact hole in the gate insulating layer 402, the process can be performed simultaneously during the processing of the oxide semiconductor film 440.

[0066] Note that the etching of the oxide semiconductor film 440 here may be dry etching, wet etching, or both may be used. For example, as the etching solution used for wet etching of the oxide semiconductor film 440, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, ammonia peroxide (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2), etc. can be used. Also, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0067] Next, a first heat treatment is performed on the oxide semiconductor layer. By this first heat treatment, the oxide semi The conductor layer can be dehydrated or dehydrogenated. The temperature of the first heat treatment is 400° C. The temperature is set to 750°C or higher, or 400°C or higher but lower than the distortion point of the substrate. The substrate was placed in an electric furnace, which is one of the equipment used for the deposition of oxide semiconductor layers, and the temperature was raised to 450°C in a nitrogen atmosphere. After the heat treatment for 1 hour, the oxide semiconductor layer was exposed to air and water or moisture was not allowed to enter the oxide semiconductor layer. Thus, the oxide semiconductor layer 441 is obtained while preventing recontamination of elements (see FIGS. 3B1 and 3B2).

[0068] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heating element such as a resistance heating element. A device that heats the workpiece by radiation may be used. For example, a GRTA (Gas Reactor Transformer) apid Thermal Anneal) equipment, LRTA (Lamp Rapid T RTA (Rapid Thermal Anneal) equipment, etc. al) equipment can be used. The LRTA equipment can be a halogen lamp, a metal halide lamp, lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure mercury lamp This is a device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp or other light source. The GRTA device is a device that uses high-temperature gas to perform heat treatment. Inert gases such as argon or nitrogen that do not react with the workpiece during heat treatment An active gas is used.

[0069] For example, the first heat treatment is performed by subjecting the substrate to a base in an inert gas heated to a high temperature of 650° C. to 700° C. The plate is moved and placed in the oven, heated for a few minutes, and then the substrate is moved and placed in an inert gas atmosphere heated to a high temperature. A GRTA may be conducted from the

[0070] In the first heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain water, hydrogen, etc. Alternatively, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

[0071] Also, after heating the oxide semiconductor layer in the first heat treatment, high-purity oxygen gas, high-purity N2O gas, or ultra-dry air (dew point of -40°C or lower, preferably -60°C or lower) may be introduced into the same furnace. It is preferable that oxygen gas or N2O gas does not contain water, hydrogen, etc. Alternatively, the purity of oxygen gas or N2O gas introduced into the heat treatment apparatus is 6N or higher, preferably 7N or higher (that is, the impurity concentration in oxygen gas or N2O gas is 1 ppm or lower, preferably 0.1 ppm or lower). By the action of oxygen gas or N2O gas, oxygen, which is the main component material constituting the oxide semiconductor and has decreased simultaneously due to the impurity elimination step by dehydration or dehydrogenation treatment, is supplied, thereby purifying the oxide semiconductor layer to a high purity and making it electrically type-I (intrinsic).

[0072] Also, the first heat treatment of the oxide semiconductor layer can be performed on the oxide semiconductor film 440 before processing it into an island-shaped oxide semiconductor layer. In that case, after the first heat treatment, the substrate is taken out from the heating apparatus, and a photolithography process is performed.

[0073] In addition to the above, the first heat treatment can be performed on the oxide semiconductor After laminating a source electrode layer and a drain electrode layer on the layer, or after forming an insulating layer on the source electrode layer and the drain electrode layer, either method may be used. After forming an insulating layer on the layer, either method may be used.

[0074] Also, when forming a contact hole in the gate insulating layer 402, the process may be performed before or after performing the first heat treatment on the oxide semiconductor film 440. After forming an insulating layer on the layer, either method may be used.

[0075] Also, by forming the oxide semiconductor layer in two parts and performing heat treatment in two parts, regardless of the material of the base member being oxide, nitride, metal, etc., an oxide semiconductor layer having a thick crystal region (single crystal region), that is, a crystal region with c-axis orientation perpendicular to the film surface, may be formed. For example, a first oxide semiconductor film with a thickness of 3 nm or more and 15 nm or less is formed, and a first heat treatment is performed at 450 °C or more and 850 °C or less, preferably 550 °C or more and 750 °C or less, in an atmosphere of nitrogen, oxygen, noble gas, or dry air to form a first oxide semiconductor film having a crystal region (including plate-like crystals) in the region including the surface. Then, a second oxide semiconductor film thicker than the first oxide semiconductor film is formed, and a second heat treatment is performed at 450 °C or more and 850 °C or less, preferably 600 °C or more and 700 °C or less. Using the first oxide semiconductor film as a seed for crystal growth, crystal growth is performed upward to crystallize the entire second oxide semiconductor film, and as a result, an oxide semiconductor layer having a thick crystal region may be formed. After forming an insulating layer on the layer, either method may be used. After forming an insulating layer on the layer, either method may be used. For example, a first oxide semiconductor film with a thickness of 3 nm or more and 15 nm or less is formed, and a first heat treatment is performed at 450 °C or more and 850 °C or less, preferably 550 °C or more and 750 °C or less, in an atmosphere of nitrogen, oxygen, noble gas, or dry air to form a first oxide semiconductor film having a crystal region (including plate-like crystals) in the region including the surface. Then, a second oxide semiconductor film thicker than the first oxide semiconductor film is formed, and a second heat treatment is performed at 450 °C or more and 850 °C or less, preferably 600 °C or more and 700 °C or less. Using the first oxide semiconductor film as a seed for crystal growth, crystal growth is performed upward to crystallize the entire second oxide semiconductor film, and as a result, an oxide semiconductor layer having a thick crystal region may be formed. After forming an insulating layer on the layer, either method may be used. After forming an insulating layer on the layer, either method may be used. After forming an insulating layer on the layer, either method may be used. After forming an insulating layer on the layer, either method may be used. After forming an insulating layer on the layer, either method may be used. After forming an insulating layer on the layer, either method may be used.

[0076] Next, a conductive film to be a source electrode layer and a drain electrode layer (including wirings formed of the same layer) is formed on the gate insulating layer 402 and the oxide semiconductor layer 441. As the conductive film used for the source electrode layer and the drain electrode layer, for example, Al, Cr, Cu, Ta, T After forming an insulating layer on the layer, either method may be used. As the conductive film used for the source electrode layer and the drain electrode layer, for example, Al, Cr, Cu, Ta, T Metal film containing an element selected from i, Mo, and W, or a metal containing the above elements as components Nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) can be used. In addition, Ti, Mo, W can be applied to either or both of the upper and lower sides of the metal film such as Al or Cu. High melting point metal films or their metal nitride films (titanium nitride film, molybdenum nitride film, nitrogen The source electrode layer and the drain electrode layer may be formed of a tungsten oxide film. The conductive film used for the electrode layer may be formed of a conductive metal oxide. The oxides are indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ), indium oxide tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide Indium zinc oxide alloy (In2O3-ZnO) or these metal oxide materials with silicon oxide Containing kon can be used.

[0077] A resist mask is formed on the conductive film by a third photolithography process, and selective etching is performed. After forming the source electrode layer 405a and the drain electrode layer 405b by etching, a resist The mask is removed.

[0078] In the third photolithography process, ultraviolet light or KrF laser is used for exposure when forming the resist mask. The source electrodes adjacent to each other on the oxide semiconductor layer 441 are preferably irradiated with a laser beam or an ArF laser beam. The width of the gap between the bottom end of the drain electrode layer and the bottom end of the drain electrode layer determines the width of the gap between the bottom end of the drain electrode layer and the bottom end of the drain electrode layer. The channel length L is determined. Note that when performing exposure with a channel length L of less than 25 nm, Extreme ultraviolet rays have extremely short wavelengths of several nm to several tens of nm. et) is used to perform exposure during resist mask formation in the third photolithography process. Good. Exposure using extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length L of the transistor formed later to be 10 nm or more and 1000 nm or less, and the operating speed of the circuit can be increased.

[0079] In addition, in order to reduce the number of photomasks and the number of processes used in the photolithography process, an etching process may be performed using a resist mask formed by a multi-tone mask, which is an exposure mask in which the transmitted light has multiple intensities. The resist mask formed using the multi-tone mask has a shape with multiple film thicknesses, and the shape can be further deformed by performing etching. Therefore, it can be used in a plurality of etching processes for processing into different patterns. Thus, a resist mask corresponding to at least two or more different patterns can be formed using a single multi-tone mask. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced, enabling simplification of the process.

[0080] Note that during the etching of the conductive film, it is desired to optimize the etching conditions so that the oxide semiconductor layer 441 is not etched and separated. However, it is difficult to obtain a condition where only the conductive film is etched and the oxide semiconductor layer 441 is not etched at all. During the etching of the conductive film, only a part of the oxide semiconductor layer 441 may be etched, resulting in an oxide semiconductor layer having a groove (concave portion).

[0081] In this embodiment, a Ti film is used as the conductive film, and an In-Ga- Zn-O-based oxide semiconductor is used for the oxide semiconductor layer 441. Therefore, as the etchant, aqueous ammonia peroxide (aqueous ammonia ​, a mixture of water and hydrogen peroxide solution) is used.

[0082] Next, plasma treatment is performed using a gas such as N2O, N2, or Ar to remove adsorbed water or the like adhering to the surface of the exposed oxide semiconductor layer. When the plasma treatment is performed, an insulating layer 407 in contact with a part of the oxide semiconductor layer is formed without being exposed to the atmosphere. In the case of performing plasma treatment, an insulating layer 407 in contact with a part of the oxide semiconductor layer is formed without being exposed to the atmosphere. When the plasma treatment is performed, an insulating layer 407 in contact with a part of the oxide semiconductor layer is formed without being exposed to the atmosphere.

[0083] The insulating layer 407 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into the insulating layer 407, such as sputtering. If hydrogen is contained in the insulating layer 407, the hydrogen may penetrate into the oxide semiconductor layer or oxygen in the oxide semiconductor layer may be extracted by hydrogen, resulting in a decrease in the resistance of the back channel of the oxide semiconductor layer (N-type conversion) and the formation of a parasitic channel. Therefore, it is important not to use hydrogen in the film formation method so that the insulating layer 407 becomes a film that does not contain hydrogen as much as possible. In the case of performing plasma treatment, an insulating layer 407 in contact with a part of the oxide semiconductor layer is formed without being exposed to the atmosphere. If hydrogen is contained in the insulating layer 407, the hydrogen may penetrate into the oxide semiconductor layer or oxygen in the oxide semiconductor layer may be extracted by hydrogen, resulting in a decrease in the resistance of the back channel of the oxide semiconductor layer (N-type conversion) and the formation of a parasitic channel. Therefore, it is important not to use hydrogen in the film formation method so that the insulating layer 407 becomes a film that does not contain hydrogen as much as possible. Therefore, it is important not to use hydrogen in the film formation method so that the insulating layer 407 becomes a film that does not contain hydrogen as much as possible. Therefore, it is important not to use hydrogen in the film formation method so that the insulating layer 407 becomes a film that does not contain hydrogen as much as possible.

[0084] As the insulating layer 407, typically, an inorganic insulating film such as a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film can be used. In this embodiment, a silicon oxide film with a film thickness of 200 nm is formed as the insulating layer 407 using a sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is set to 100 °C. The film formation of the silicon oxide film by sputtering can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. Also, as the target, a silicon oxide target or a silicon target

[0085] In this embodiment, a silicon oxide film with a film thickness of 200 nm is formed as the insulating layer 407 using a sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is set to 100 °C. In this embodiment, it is set to 100 °C. The film formation of the silicon oxide film by sputtering can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. In this embodiment, it is set to 100 °C. The film formation of the silicon oxide film by sputtering can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. In this embodiment, it is set to 100 °C. The film formation of the silicon oxide film by sputtering can be performed in an atmosphere of a rare gas (typically argon), an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. Also, as the target, a silicon oxide target or a silicon target For example, a silicon target can be used in an atmosphere containing oxygen. A silicon oxide film can be formed by a sputtering method under atmospheric pressure. The insulating layer 407 formed by the above process is resistant to moisture, hydrogen ions, OH - It does not contain impurities such as An inorganic insulating film is used to block the intrusion of these elements from the outside, typically a silicon oxide film. A silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or the like is used. do.

[0086] In the same manner as in the formation of the oxide semiconductor film 440, moisture remaining in the deposition chamber for the insulating layer 407 is removed. For this purpose, it is preferable to use an adsorption type vacuum pump (such as a cryopump). The concentration of impurities contained in the insulating layer 407 formed in a deposition chamber evacuated using an opamp was reduced. In addition, the following exhaust means can be used to remove residual moisture in the deposition chamber for the insulating layer 407: A turbo pump (turbomolecular pump) with a cold trap added may also be used.

[0087] The insulating layer 407 is formed using a sputtering gas such as hydrogen, water, a hydroxyl group, or a hydride. It is preferable to use a high-purity gas from which impurities have been removed.

[0088] Next, a second heat treatment (preferably a second heat treatment) is performed under an inert gas atmosphere or an oxygen gas atmosphere. For example, the heating is performed in a nitrogen atmosphere. The second heat treatment is performed at 250° C. for 1 hour under atmospheric pressure. A part of the layer (channel formation region) is heated in a state where the part is in contact with the insulating layer 407 .

[0089] Through the above steps, the oxide semiconductor film is subjected to the first heat treatment to remove hydrogen, Impurities such as moisture, hydroxyl groups, or hydrides (also referred to as hydrogen compounds) are intentionally removed from the oxide semiconductor layer, and oxygen, which is one of the main component materials constituting the oxide semiconductor that would otherwise be reduced simultaneously during the impurity removal process, can be supplied. Thus, the oxide semiconductor layer is purified to high purity and electrically made into the I-type (intrinsic) state. See (FIGS. 3(C1)(C2)) for the formation of the transistor 410 in the above process. Moreover, when using a silicon oxide layer with many defects in the insulating layer 407, impurities such as hydrogen, moisture, hydroxyl groups, or hydrides contained in the oxide semiconductor layer are diffused into the silicon oxide layer by the heat treatment after the formation of the silicon oxide layer, achieving the effect of further reducing the impurities contained in the oxide semiconductor layer. A protective insulating layer may be further formed on the insulating layer 407. For example, a silicon nitride film is formed using the RF sputtering method. Since the RF sputtering method has good mass productivity, it is preferable as the film formation method for the protective insulating layer. The protective insulating layer uses an inorganic insulating film that does not contain impurities such as moisture and blocks these from entering from the outside, such as a silicon nitride film or an aluminum nitride film.

[0090] After the formation of the protective insulating layer, heat treatment may be further performed in the atmosphere at a temperature of 100°C or higher and 200°C or lower for 1 hour or more and 30 hours or less. This heat treatment may be carried out while maintaining a constant heating temperature, or the temperature may be increased from room temperature to a heating temperature of 100°C or higher and 200°C or lower, and the temperature may be decreased from the heating temperature to room temperature multiple times.

[0091]

[0092]

[0093]

[0094] ​​​​​​​​​​​​​Next, the gate insulating layer 402 and the insulating layer 407 are selectively removed to form openings 412a and 412b through which the gate electrode layer 401 is exposed (see FIGS. 3(D1) and (D2)). As shown in FIG. 3(D 2), in the channel width direction of the oxide semiconductor layer 403, openings 412a and 412b are formed in the gate insulating layer 402 and the insulating layer 407 so that the gate insulating layer 402 and the insulating layer 407 surround and seal the oxide semiconductor layer 403 at the center. In this embodiment, since the gate insulating layer 402 and the insulating layer 407 are etched using the same mask, the ends of the gate insulating layer 402 and the insulating layer 407 substantially coincide.

[0095] Next, a conductive film is formed on the insulating layer 407, and the conductive film is etched using a photolithography process to form a conductive layer 411 (see FIGS. 3(E1) and (E2)). The conductive layer 411 is formed so as to cover at least the channel formation region of the oxide semiconductor layer 403.

[0096] As shown in FIG. 3(E2), the conductive layer 411 covers the gate insulating layer 402 surrounding the oxide semiconductor layer 403 provided on the gate electrode layer 401, the upper part of the insulating layer 407, and both ends of the gate insulating layer 402 and the insulating layer 407, and is in contact with the gate electrode layer 401 exposed in the opening to form the conductive layer 411. Since the conductive layer 411 is in contact with the gate electrode layer 401, it has the same potential as the gate electrode layer 401.

[0097] By adopting a structure in which a conductive layer 411 having the same potential as the gate electrode layer 401 is provided, it is possible to prevent a parasitic channel due to leakage current from being formed in the back channel of the transistor 4 10.

[0098] ​​​​In addition, the conductive layer 411 shields an external electric field, that is, it has a function (particularly an electrostatic shielding function against static electricity) to prevent the external electric field from acting on the inside (the circuit portion including the transistor). By the shielding function of the conductive layer 411, it is possible to prevent the electrical characteristics of the transistor 410 from fluctuating due to the influence of an external electric field such as static electricity. The transistor 410 using the highly purified oxide semiconductor layer 403 fabricated using this embodiment can reduce the current value in the off state (off-current value) to less than 10 zA / μm per channel width of 1 μm and less than 100 zA / μm at 85°C.

[0099] The transistor 410 using the oxide semiconductor layer 403 fabricated using this embodiment can reduce the current value in the off state (off-current value) to less than 10 zA / μm per channel width of 1 μm and less than 100 zA / μm at 85°C.

[0100] In addition, since the transistor 410 using the oxide semiconductor layer 403 can obtain a relatively high field-effect mobility, it can be driven at high speed. Therefore, by using the above transistor in the pixel portion of the liquid crystal display device, a high-quality image can be provided. Also, since the transistor including the highly purified oxide semiconductor layer can be fabricated by separately forming the drive circuit portion or the pixel portion on the same substrate, the number of components of the semiconductor device can be reduced.

[0101] As described above, by surrounding the channel formation region of the oxide semiconductor layer in the channel width direction with the gate insulating layer, the insulating layer, the gate electrode layer, and the conductive layer, impact resistance can be added.

[0102] In addition, by imparting flexibility, it is possible to provide a semiconductor device with higher reliability that can cope with more diverse applications and has improved convenience.

[0103] (Embodiment 2) In this embodiment, another form of the semiconductor device will be described with reference to FIG. 2. In this embodiment, , a transistor is shown as an example of the semiconductor device. Note that the same parts or parts having similar functions, and processes can be carried out in the same manner as in the above-described Embodiment 1, and repeated descriptions are omitted. Also, detailed descriptions of the same locations are omitted.

[0104] FIGS. 2(A) and (B) show transistors 420a, 420b, and 420c connected in parallel. . By connecting the plurality of transistors 420a, 420b, and 420c in parallel, it has the same effect as widening the effective channel width, and a large amount of current can flow. In this way, by combining configurations such as providing a plurality of transistors in parallel so as to divide the channel width, the degree of freedom in circuit design can be improved. A configuration such as that of transistors 420a , 420b, and 420c that can allow a large amount of current to flow can be suitably used as the drive circuit transistor of the drive circuit section.

[0105] The channel formation regions of the oxide semiconductor layers 423a, 423b, and 42 3c of the transistors 420a, 420b, and 420c have a channel length (L) direction and a channel width (W) direction. .

[0106] FIG. 2(A) is a plan view of the transistors 420a, 420b, and 420c, and FIG. 2(B) is a cross-sectional view taken along line B3 - B4 in the channel width (W) direction of the transistors 420a, 420b, and 420c shown in FIG. 2(A).

[0107] As shown in FIGS. 2(A) and (B), the transistors 420a, 420b, and 420c are on an insulating surface On a substrate 400 having a surface, a gate electrode layer 421, a gate insulating layer 422 (gate insulating layers 4 22a, 422b, 422c), oxide semiconductor layers 423a, 423b, 423c, a source electrode layer 425a, and a drain electrode layer 425b are included. On transistors 420a, 420b, 4 20c, an insulating layer 427 (insulating layers 427a, 427b, 427c) and a conductive layer 43 1 are sequentially stacked.

[0108] Transistors 420a, 420b, 420c are connected in parallel, and the gate electrode layer 4 21, the source electrode layer 425a, and the drain electrode layer 425b are provided in common.

[0109] Also, in the cross-sectional view in the channel width direction of FIG. 2(B), the oxide semiconductor layers 423a, 423b , 423c are respectively surrounded by the gate insulating layers 422a, 422b, 422c and the insulating layers 427a, 427b, 427c at the top, bottom, and ends, and the gate insulating layers 422a, 422b , 422c and the insulating layers 427a, 427b, 427c are in contact at both ends. The gate insulating layers 422a, 422b, 422c are provided with the gate electrode layer 421 on the lower side, and on the insulating layers 42 7a, 427b, 427c, the oxide semiconductor layers 423a, 423b, 423c, the gate insulating layers 422a, 422b, 422c, and the insulating layers 427a, 427b, 427c on the top and the gate insulating layers 422a, 422b, 422c, and the insulating layers 427a, 427b, 4 27c at both ends are covered, and a conductive layer 431 is provided in contact with the gate electrode layer 421 .

[0110] Therefore, in the channel width direction, the oxide semiconductor layers 423a, 423b, 423c are, respectively, These are the gate insulating layers 422a, 422b, 422c and the insulating layers 427a, 427b, 427c , and are surrounded by the gate electrode layer 421, the conductive layer 431, and the like.

[0111] In this way, when the periphery of the oxide semiconductor layers 423a, 423b, 423c is protected by the lamination of the gate electrode layer, the gate insulating layer, the insulating layer, and the conductive layer, even if a force in the channel width direction is applied, the thick laminated structure is difficult to bend, so the force applied to the oxide semiconductor layers 423a, 423b, 423c located at the center of the lamination can be reduced. Thus, breakage of the oxide semiconductor layers 423a, 423b, 423c due to external impact can be prevented.

[0112] Also, openings are formed in the gate insulating layer 422 (gate insulating layers 422a, 422b, 422c) and the insulating layer 4 27 (insulating layers 427a, 427b, 427c) where the gate electrode layer 421 is widely exposed, and the gate electrode layer 421 and the conductive layer 431 are in contact with each other at the openings . By using conductive films with good adhesion as the gate electrode layer 421 and the conductive layer 431, film peeling at the interfaces of the gate electrode layer 421, the gate insulating layers 422a, 422b, 422c, the oxide semiconductor layers 423a, 423b, 423c, the insulating layers 427a, 427b, 427c, or the conductive layer 431 due to an external force can be prevented.

[0113] In order to increase the adhesion between the gate electrode layer 421 and the conductive layer 431, it is preferable to provide a wide contact area. As shown in Fig. 2(A), the distance in the channel length direction of the oxide semiconductor layers 423a, 423b, 423c in the region where the gate electrode layer 421 and the conductive layer 431 are in contact is as shown in Fig. 2(A), and the distance in the channel length direction of the oxide semiconductor layers 423a, 423b, 423c in the region where the gate electrode layer 421 and the conductive layer 431 are in contact is 、It is preferable to make it longer than the channel length distance of the oxide semiconductor layers 423a, 423b, and 423c. Preferably.

[0114] Also, in the transistors 420a, 420b, and 420c, the oxide semiconductor layers 4 23a, 423b, and 423c are arranged in the center, and both ends thereof are in contact with the gate insulating layers 422a, 42 2b and 422c and the insulating layers 427a, 427b, and 427c to be sealed. Further, both ends are sealed by the contact of the gate electrode layer 421 and the conductive layer 431. Therefore, a line-symmetric structure can be formed. Thus, the external force applied can be evenly distributed, and it is possible to prevent a locally large force from being applied to the oxide semiconductor layers 423a , 423b, and 423c.

[0115] Therefore, in the transistors 420a, 420b, and 420c, the bending resistance in the channel width direction of the oxide semiconductor layers 423a, 423b, and 423c can be increased, and impact resistance can be imparted. It can be done.

[0116] Since it has impact resistance, a flexible substrate can be used for the substrate 400, and it is possible to cope with applications as a flexible semiconductor device, and it is possible to cope with more diversified applications, and a highly reliable semiconductor device with improved convenience can be provided. It can be provided.

[0117] As described above, by surrounding the channel formation region of the oxide semiconductor layer in the channel width direction with the stacked gate insulating layer, the insulating layer, and further the gate electrode layer and the conductive layer, impact resistance can be added. It can be done.

[0118] Also, by imparting flexibility, it is possible to cope with more diversified applications, and a highly reliable semiconductor device with improved convenience can be provided.

[0119] This embodiment can be implemented in appropriate combination with other embodiments.

[0120] (Embodiment 3) In this embodiment, another form of the semiconductor device will be described with reference to FIG. 5. In this embodiment , a transistor is shown as an example of the semiconductor device. It is an example in which the formation process and structure of the transistor shown in Embodiment 1 and the source electrode layer and the drain electrode layer are different. Therefore, the same parts or parts having similar functions, and the processes as in the above embodiment can be carried out in the same manner as in the above embodiment, and repeated explanations are omitted. Also, detailed explanations of the same parts are omitted.

[0121] In Embodiment 1 and Embodiment 2, examples in which the source electrode layer 405a and the drain electrode layer 405b are provided between the oxide semiconductor layer 403 and the insulating layer 407 were shown. In this embodiment, examples in which the source electrode layer 405a and the drain electrode layer 405b are provided between the gate insulating layer 402 and the oxide semiconductor layer 403 are shown.

[0122] FIG. 5(A) is a plan view of the transistor 430, FIG. 5(B) is a cross-sectional view taken along line A5 - A6 in the channel length (L) direction of the transistor 430 shown in FIG. 5(A), and FIG. 5(C) is a cross-sectional view taken along line B5 - B6 in the channel width (W) direction.

[0123] The transistor 430 shown in FIGS. 5(A) to (C) is a bottom gate type transistor, and includes a gate electrode layer 401, a gate insulating layer 402, a source electrode layer 405a, a drain electrode layer 405b, and an oxide semiconductor layer 403 on a substrate 400. Further, an insulating layer 407 that covers the transistor 430 and is in contact with the oxide semiconductor layer 403 is provided. ​

[0124] In the transistor 430, the gate insulating layer 402 is provided in contact with the substrate 400 and the gate electrode layer 40 1, and the source electrode layer 405a and the drain electrode layer 405b are provided in contact with the gate insulating layer 402. Then, an oxide semiconductor layer 403 is provided on the gate insulating layer 402, and the source electrode layer 40 5a and the drain electrode layer 405b.

[0125] Also, in the cross-sectional view in the channel width direction of FIG. 5(C), the oxide semiconductor layer 403 is surrounded by the gate insulating layer 402 and the insulating layer 407 at the top, bottom, and ends, and the gate insulating layer 402 and the insulating layer 407 are in contact at both ends. A gate electrode layer 401 is provided below the gate insulating layer 402, and on the insulating layer 407, the oxide semiconductor layer 403, the gate insulating layer 402, and the insulating layer 407 at the top and both ends of the gate insulating layer 402 and the insulating layer 407 are covered, and a conductive layer 411 is provided in contact with the gate electrode layer 401.

[0126] Therefore, in the channel width direction, the oxide semiconductor layer 403 is surrounded by the gate insulating layer 402, the insulating layer 4 07, the gate electrode layer 401, and the conductive layer 411.

[0127] Thus, when the structure is such that the periphery of the oxide semiconductor layer 403 is protected by the lamination of the gate insulating layer, the gate electrode layer, the insulating layer, and the conductive layer, even if a force (a force applied from the outside) is applied in the channel width (W) direction, the thick laminated structure is difficult to bend, so the force applied to the oxide semiconductor layer 403 located at the center of the lamination can be reduced. Therefore, damage to the oxide semiconductor layer 403 due to an external impact can be prevented. impact can be prevented. impact can be prevented.

[0128] In addition, an opening is formed in the gate insulating layer 402 and the insulating layer 407, through which the gate electrode layer 401 is widely exposed such that the gate electrode layer 401 and the conductive layer 411 are in contact with each other in the opening . If conductive films with good adhesion are used for the gate electrode layer 401 and the conductive layer 411, peeling of the films at the interfaces of the gate electrode layer 401, the gate insulating layer 402, the oxide semiconductor layer 403, the insulating layer 407, or the conductive layer 411 due to an externally applied force can be prevented . To enhance the adhesion between the gate electrode layer 401 and the conductive layer 411, it is preferable to provide a wide contact area. As shown in Fig. 5(A), the distance in the channel length direction of the oxide semiconductor layer 403 in the region where the gate electrode layer 401 and the conductive layer 411 are in contact is preferably longer than the distance of the channel length of the oxide semiconductor layer 403 .

[0129] In addition, the oxide semiconductor layer 403 is disposed in the center, and both ends thereof are sealed in contact with the gate insulating layer 402 and the insulating layer 407. Further, both ends thereof are sealed in contact with the gate electrode layer 401 and the conductive layer 411, so that a line-symmetric structure can be formed. Therefore, the externally applied force is evenly dispersed, and it is possible to prevent a locally large force from being applied to the oxide semiconductor layer 403 . . .

[0130] Accordingly, in the transistor 430, the bending resistance in the channel width direction of the oxide semiconductor layer 403 can be enhanced, and impact resistance can be imparted . . . .

[0131] Since it has impact resistance, a flexible substrate can be used for the substrate 400, enabling it to be applicable to a semiconductor device having flexibility, corresponding to more diverse applications, and improving convenience and reliability .

[0132] . . A highly reliable semiconductor device can be provided.

[0133] This embodiment can be implemented in appropriate combination with other embodiments.

[0134] (Embodiment 4) In this embodiment, an example of a method for manufacturing a semiconductor device is shown, in which a transistor is provided on a flexible substrate through a peeling and transfer process from another manufacturing substrate. The semiconductor device according to one aspect of the present invention will be described with reference to FIG. 4. Note that this embodiment is the same as Embodiment 1 except that some of the steps are different. Therefore, the same reference numerals are used for the same parts, and detailed descriptions of the same parts are omitted. An example of a method for manufacturing a semiconductor device will be described in detail with reference to FIG. 4. A release layer 302 is formed on a first manufacturing substrate 300, and a first insulating layer 301 is formed on the release layer 302. Preferably, the first insulating layer 301 is continuously formed without exposing the formed release layer 302 to the atmosphere. By continuously forming, it is possible to prevent the entry of dust and impurities between the release layer 302 and the first insulating layer 301. As the first manufacturing substrate 300, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, or the like can be used. As the glass substrate, barium borosilicate glass, aluminosilicate glass, or the like can be used. Also, a plastic substrate having heat resistance capable of withstanding the processing temperature of this embodiment may be used. In the manufacturing process of the semiconductor device, the manufacturing substrate can be appropriately selected according to the steps to be performed.

[0135] An example of a method for manufacturing a semiconductor device will be described in detail with reference to FIG. 4.

[0136] A release layer 302 is formed on a first manufacturing substrate 300, and a first insulating layer 301 is formed on the release layer 302. Preferably, the first insulating layer 301 is continuously formed without exposing the formed release layer 302 to the atmosphere. By continuously forming, it is possible to prevent the entry of dust and impurities between the release layer 302 and the first insulating layer 301. As the first manufacturing substrate 300, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, or the like can be used.

[0137] As the glass substrate, barium borosilicate glass, aluminosilicate glass, or the like can be used. Also, a plastic substrate having heat resistance capable of withstanding the processing temperature of this embodiment may be used. In the manufacturing process of the semiconductor device, the manufacturing substrate can be appropriately selected according to the steps to be performed.

[0138] ​​Note that, in this step, the case where the release layer 302 is provided on the entire surface of the first production substrate 300 is shown. However, if necessary, after providing the release layer 302 on the entire surface of the first production substrate 300, the release layer 302 may be selectively removed, and the release layer may be provided only in a desired region. Further, in FIG. 4, the release layer 302 is formed in contact with the first production substrate 300. However, if necessary, an insulating layer such as a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, or a silicon nitride oxide layer may be formed between the first production substrate 300 and the release layer 302.

[0139] The release layer 302 is made of an element selected from tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr ), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os) , iridium (Ir), silicon (Si), or an alloy material mainly composed of the element, or a compound material mainly composed of the element, and is a single-layer or laminated layer. The crystal structure of the layer containing silicon may be any of amorphous, microcrystalline, and polycrystalline.

[0140] The release layer 302 can be formed by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like. Note that the coating method includes a spin coating method, a droplet discharge method, and a dispensing method.

[0141] When the release layer 302 has a single-layer structure, preferably, a layer containing a tungsten layer, a molybdenum layer, or a mixture of tungsten and molybdenum is formed. Alternatively, a layer containing an oxide or oxynitride of tungsten, a layer containing an oxide or oxynitride of molybdenum, or a layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum is formed. Note that tan ​ The mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

[0142] When the release layer 302 has a laminated structure, preferably, a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum is formed as the first layer, and as the second layer, an oxide, nitride, oxynitride, or nitroxide of tungsten, molybdenum, or a mixture of tungsten and molybdenum is formed.

[0143] When forming a laminated structure of a layer containing tungsten and a layer containing an oxide of tungsten as the release layer 302, a layer containing tungsten is formed, and an insulating layer formed of an oxide is formed on the upper layer thereof, and a layer containing an oxide of tungsten is formed at the interface between the layer containing tungsten and the insulating layer. This may be utilized.

[0144] In addition, when forming a transistor on a production substrate by forming a release layer, the release layer is also heated by heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer, and when peeling from the production substrate to the support substrate in a later process, peeling at the release layer interface becomes easy.

[0145] Further, the surface of the layer containing tungsten may be treated by heat oxidation treatment, oxygen plasma treatment, treatment with a solution having a strong oxidizing power such as ozone water, etc. to form a layer containing an oxide of tungsten. Also, plasma treatment and heat treatment may be performed in an atmosphere of oxygen, nitrogen, dinitrogen monoxide alone, or a mixed gas of the gas and other gases. This is the same when forming a layer containing a nitride, oxynitride, and nitroxide of tungsten. When forming a layer containing tungsten, ​​​​​​​​​​​​​Subsequently, a silicon nitride layer, a silicon oxynitride layer, and a silicon nitride oxide layer are formed on the upper layer thereof. This is preferable.

[0146] A layer to be peeled 304 is formed on the peeling layer 302 (see Fig. 4(A)). The layer to be peeled 304 has the first insulating layer 301 and the transistor 410.

[0147] First, the first insulating layer 301 is formed on the peeling layer 302. The first insulating layer 301 is preferably formed of a single layer or multiple layers of an insulating film containing nitrogen and silicon, such as silicon nitride, silicon oxynitride, or silicon nitride oxide.

[0148] The first insulating layer 301 can be formed using a sputtering method, a plasma CVD method, a coating method, a printing method, etc. For example, by forming the film at a film formation temperature of 250°C to 400°C by the plasma CVD method, a dense and very low water-permeable film can be obtained. Note that the thickness of the first insulating layer 301 is preferably 10 nm or more and 1000 nm or less, more preferably 100 nm or more and 700 nm or less.

[0149] By providing the first insulating layer 301, peeling at the interface with the peeling layer 302 becomes easier in the subsequent peeling process. Furthermore, it is possible to prevent cracks and damage from occurring in the semiconductor element and wiring in the subsequent peeling process. Also, the first insulating layer 301 functions as a protective layer of the semiconductor device.

[0150] The transistor 410 is formed on the first insulating layer 301, and the layer to be peeled 304 is formed. Since the layer to be peeled 304 can be formed by applying the method described in Embodiment 1, detailed description is omitted here.

[0151] In addition, in this embodiment, an example of a laminated structure with a protective insulating layer 409 on the insulating layer 407 is shown. In this embodiment, as the protective insulating layer 409, the substrate 400 formed up to the insulating layer 407 is heated to a temperature of 100°C to 400°C, and sputtering gas containing high-purity nitrogen from which hydrogen and moisture have been removed is introduced, and a silicon nitride film is formed using a silicon semiconductor target (see Fig. 4 (A)). Also in this case, similar to the insulating layer 407, it is preferable to form the protective insulating layer 409 while removing residual moisture in the processing chamber.

[0152] Furthermore, a planarizing insulating film may be formed on the transistor 410 to reduce surface irregularities caused by the transistor. As the planarizing insulating film, organic materials such as polyimide, acrylic, benzocyclobutene, etc. can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), etc. can also be used. Note that a planarizing insulating film may be formed by laminating a plurality of insulating films formed of these materials.

[0153] Next, the second production substrate 306 is temporarily bonded to the peelable layer 304 using a removable adhesive layer 305. By bonding the second production substrate 306 to the peelable layer 304, the peelable layer 304 can be easily peeled from the release layer 302. Also, the stress applied to the peelable layer 304 during the peeling process is relaxed, and the transistor can be protected. In addition, since the removable adhesive layer 305 is used, the second production substrate 306 can be easily removed when it becomes unnecessary.

[0154] Examples of the removable adhesive layer 305 include, for example, water-soluble resins. The applied water-soluble resin relaxes the irregularities of the peelable layer 304 and improves the bonding with the second production substrate 306. ​ This facilitates [the process]. Also, as the removable adhesive layer 305, a laminate obtained by laminating a pressure-sensitive adhesive that can be peeled off by light or heat on a water-soluble resin may be used.

[0155] Next, the layer to be peeled 304 is peeled from the first production substrate 300 (see Fig. 4(B)). Various methods can be used as the peeling method.

[0156] For example, when a metal oxide film is formed on the side of the first insulating layer 301 as the peeling layer 302, the metal oxide film can be made fragile by crystallization, and the layer to be peeled 304 can be peeled from the first production substrate 300. Also, after the metal oxide film is made fragile by crystallization, a part of the peeling layer 302 can be further etched and removed by a solution or a fluorinated halogen gas such as NF3, BrF3, or ClF3, and peeling can be performed on the fragile metal oxide film.

[0157] Also, when a film containing nitrogen, oxygen, hydrogen, etc. (for example, an amorphous silicon film containing hydrogen, a hydrogen-containing alloy film, an oxygen-containing alloy film, etc.) is used as the peeling layer 302 and a substrate having optical transparency is used as the first production substrate 300, a method can be used in which laser light is irradiated on the peeling layer 302 from the first production substrate 300 to vaporize nitrogen, oxygen, or hydrogen contained in the peeling layer, and peeling is performed between the first production substrate 300 and the peeling layer 302.

[0158] Also, by removing the peeling layer 302 by etching, the layer to be peeled 304 may be peeled from the first production substrate 300.

[0159] Also, a method of mechanically polishing and removing the first production substrate 300, or removing the first production substrate 300 by etching with a fluorinated halogen gas such as NF3, BrF3, or ClF3 or HF ​ Methods such as this can be used. In this case, it is not necessary to use the release layer 302.

[0160] Also, by irradiating with a laser beam, etching with a gas or solution, or using a sharp knife or scalpel, etc., a groove is formed to expose the release layer 302, and using the groove as a trigger, the layer to be peeled 304 is peeled from the first production substrate 300 at the interface with the first insulating layer 301 that functions as a protective layer. It can also be peeled off.

[0161] As the peeling method, for example, applying mechanical force (such as peeling treatment with human hands or gripping jigs, or separation treatment while rotating a roller, etc.) can be used. Also, liquid is dropped into the groove, and the liquid is allowed to penetrate the interface between the release layer 302 and the first insulating layer 301 to peel the layer to be peeled 304 from the release layer 302. It may also be peeled off. Also, a fluorinated gas such as NF3, BrF3, or ClF3 is introduced into the groove, and the release layer 302 is etched and removed with the fluorinated gas to peel the layer to be peeled 304 from the first production substrate 300 having an insulating surface. A method may also be used. Also, when peeling, peeling may be performed while applying a liquid such as water.

[0162]

[0162]

[0163]

[0163]

[0164]

[0164]

[0165] As the resin layer 307, photocurable adhesives such as ultraviolet curable adhesives, reaction curable adhesives, thermosetting adhesives, or anaerobic adhesives and other various curable adhesives can be used. These adhesives can use epoxy resins, acrylic resins, silicone resins, phenolic resins, etc. as their materials.

[0166] When a prepreg is used as the substrate 400, the directly peelable layer 30 4 and the substrate 400 are directly pressure-bonded and bonded without using an adhesive. At this time, as the organic resin of the structure, those that progress in curing by additional treatment such as reaction curable type, thermosetting type, ultraviolet curable type, etc. are preferably used.

[0167] After providing the substrate 400, the second production substrate 306 and the removable adhesive layer 305 are removed, and the transistor 410 is exposed (see Fig. 4(D)).

[0168] Through the above steps, using the transfer process, the transistor 410 can be formed on the substrate 400.

[0169] In addition, in this embodiment, a method of providing up to a transistor in the peelable layer is exemplified, but the invention disclosed in this specification is not limited to this, and peeling and transfer may be performed after forming up to other display elements (for example, light emitting elements, etc.).

[0170] According to this embodiment, a transistor manufactured using a substrate with high heat resistance can be transferred to a thin and lightweight flexible substrate. Therefore, a semiconductor device having flexibility can be formed without being restricted by the heat resistance of the substrate.

[0171] This embodiment can be implemented in appropriate combination with other embodiments.

[0172] (Embodiment 5) A semiconductor device having a display function ( also referred to as a display device) can be fabricated using the transistors exemplified in Embodiments 1 to 4. The transistors exemplified in Embodiments 1 to 4 are more effective when used in the drive circuit section. Further, part or all of the drive circuit can be integrally formed on the same substrate as the pixel section to form a system-on-panel.

[0173] In FIGS. 6(A) and 6(B), a sealing material 4005 is provided so as to surround a pixel section 4002 provided on a first substrate 4001 and a scanning line drive circuit 4004. Also, a second substrate 4006 is provided on the pixel section 4002 and the scanning line drive circuit 4004. Thus, the pixel section 4002 and the scanning line drive circuit 4004 are sealed together with the display elements by the first substrate 4001, the sealing material 4 005, and the second substrate 4006. In FIGS. 6(A) and 6(B), a signal line drive circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. In FIGS. 6(A) and 6(B), various signals and potentials supplied to the separately formed signal line drive circuit 4003 and the scanning line drive circuit 4004 or the pixel section 4002 are supplied from an FPC 4018. Also, in FIGS. 6(A) and 6(B), an example is shown in which the signal line drive circuit 4003 is separately formed and mounted on the first substrate 4 001, but the configuration is not limited to this. The scanning line drive circuit may be separately

[0174] formed and mounted on the first substrate 4 001, but the present invention is not limited to this configuration.​​​​​ It may be formed and implemented separately, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and implemented.

[0175] Note that the connection method of the separately formed driving circuit is not particularly limited, and COG (Ch ip On Glass) method, wire bonding method, or TAB (Tape A utomated Bonding) method, etc. can be used. Fig. 6(A) is an example of implementing the signal line driving circuit 4003 by the C OG method, and Fig. 6(B) is an example of implementing the signal line driving circuit 4003 by the TAB method is an example.

[0176] In addition, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel.

[0177] Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a module to which a connector, for example, an FPC or a TAB tape or a TCP is attached, a module provided with a printed wiring board at the tip of the TAB tape or the TCP, or a module in which an IC (integrated circuit) is directly mounted on the display element by the COG method shall all be included in the display device. shall all be included in the display device.

[0178] Also, the pixel portion and the scanning line driving circuit provided on the first substrate have a plurality of transistors and, as the transistors of the scanning line driving circuit 4004, the transistors shown as an example in Embodiments 1 to 4 can be applied.

[0179] As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element), a light emitting element ( (also referred to as a light-emitting display element) can be used. The light-emitting element includes, within its scope, an element whose luminance is controlled by current or voltage. Specifically, it includes inorganic EL (Electro Luminescence), organic EL, etc. Further, a display medium whose contrast changes by an electrical action, such as electronic ink, can also be applied.

[0180] A form of the semiconductor device will be described with reference to FIGS. 7 to 9. FIGS. 7 to 9 correspond to a cross-sectional view taken along M-N of FIG. 6(A).

[0181] As shown in FIGS. 7 to 9, the semiconductor device has connection terminal electrodes 4015 and terminal electrodes 4016, and the connection terminal electrodes 4015 and the terminal electrodes 4016 are electrically connected via an anisotropic conductive film 4019 to the terminals of the FPC 4018.

[0182] The connection terminal electrode 4015 is formed of the same conductive film as the first electrode layer 4030, and the terminal electrode 4 016 is formed of the same conductive film as the source electrode layer and the drain electrode layer of the transistors 4010 and 4011.

[0183] Further, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 have a plurality of transistors. In FIGS. 7 to 9, the transistor 4010 included in the pixel portion 4002 and the transistor 4011 included in the scanning line driving circuit 4004 are illustrated. In FIG. 7, an insulating layer 4020 is provided on the transistors 4010 and 4011, and in FIGS. 8 and 9, an insulating layer 4021 is further provided. Note that the insulating film 4023 is an insulating film that functions as an underlayer film.

[0184] ​​​​​​​​​In this embodiment, as the transistor 4011 of the scanning line driving circuit 4004, the transistor shown as an example in Embodiment 1 is applied. The transistor 4011 has a structure in which the channel formation region is surrounded by upper and lower gate insulating layers, a gate electrode layer, an insulating layer, and a conductive layer in the channel width direction of the oxide semiconductor layer. In the driving circuit, in order to allow more current to flow , it is preferable to provide a longer channel width for the transistor. Therefore, a transistor having bending resistance in the channel width direction as shown in Embodiments 1 to 4 can be used to provide a semiconductor device with excellent shock resistance and high reliability. The transistor 4010 provided in the pixel portion 4002 is electrically connected to the display element to form a display panel. The display element is not particularly limited as long as it can perform display, and various display elements can be

[0185] used. An example of a liquid crystal display device using a liquid crystal element as the display element is shown in FIG. 7. In FIG. 7, the liquid crystal element 4013, which is the display element , includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer

[0186] 4008. Insulating films 4 032 and 4033 that function as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4006 side , and the first electrode layer 4030 and the second electrode layer 4031 are stacked via the liquid crystal layer 4008. In addition, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Note that a spherical s pacer may be used.

[0187] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film and is provided to control the film thickness (cell gap) of the liquid crystal layer 4008. Note that a spherical spacer may be used. The film thickness (cell gap) of the liquid crystal layer 4008 is controlled. Note that a spherical spacer may be used. It may be used.

[0188] When using a liquid crystal element as the element, thermotropic liquid crystals, low-molecular liquid crystals, high-molecular liquid crystals, polymer-dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions. Also, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer to improve the temperature range. A liquid crystal composition containing a liquid crystal that exhibits a blue phase and a chiral agent has a short response time of 1 msec or less and is optically isotropic, so alignment treatment is not required and the viewing angle dependence is small. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device. A transistor using an oxide semiconductor layer may have its electrical characteristics significantly fluctuated due to the influence of static electricity and deviate from the design range. Therefore, it is more effective to use a liquid crystal material with a blue phase in a liquid crystal display device having a transistor using an oxide semiconductor layer. Moreover, the intrinsic resistance of the liquid crystal material is 1×10

[0189] Ω·cm or more, preferably 1×10 Ω·cm or more, and more preferably 1×10 Ω·cm or more. Also, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer to improve the temperature range. A liquid crystal composition containing a liquid crystal that exhibits a blue phase and a chiral agent has a short response time of 1 msec or less and is optically isotropic, so alignment treatment is not required and the viewing angle dependence is small. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device. A transistor using an oxide semiconductor layer may have its electrical characteristics significantly fluctuated due to the influence of static electricity and deviate from the design range. Therefore, it is more effective to use a liquid crystal material with a blue phase in a liquid crystal display device having a transistor using an oxide semiconductor layer. Moreover, the intrinsic resistance of the liquid crystal material is 1×10 Ω·cm or more, preferably 1×10 Ω·cm or more, and more preferably 1×10 Ω·cm or more. Also, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases and is the phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the cholesteric liquid crystal is heated. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral agent is used for the liquid crystal layer to improve the temperature range. A liquid crystal composition containing a liquid crystal that exhibits a blue phase and a chiral agent has a short response time of 1 msec or less and is optically isotropic, so alignment treatment is not required and the viewing angle dependence is small. Also, since an alignment film does not need to be provided, rubbing treatment is not required, so electrostatic breakdown caused by the rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. Therefore, it is possible to improve the productivity of the liquid crystal display device. A transistor using an oxide semiconductor layer may have its electrical characteristics significantly fluctuated due to the influence of static electricity and deviate from the design range. Therefore, it is more effective to use a liquid crystal material with a blue phase in a liquid crystal display device having a transistor using an oxide semiconductor layer. Moreover, the intrinsic resistance of the liquid crystal material is 1×10 Ω·cm or more, preferably 1×10 Ω·cm or more, and more preferably 1×10

[0190] Ω·cm or more. 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, and more preferably 1×10 12It is 1 Ω·cm or more. Note that the resistivity value in this specification is the value measured at 20°C. The resistivity value in this specification is the value measured at 20°C.

[0191] The size of the holding capacitance provided in the liquid crystal display device is set so that it can hold electric charges for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion. The size of the holding capacitance may be set in consideration of the off-current of the transistor. By using a transistor having a high-purity oxide semiconductor layer, a holding capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, with respect to the liquid crystal capacitance in each pixel is sufficient. The size of the holding capacitance provided in the liquid crystal display device is set so that it can hold electric charges for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion. The size of the holding capacitance may be set in consideration of the off-current of the transistor. By using a transistor having a high-purity oxide semiconductor layer, a holding capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, with respect to the liquid crystal capacitance in each pixel is sufficient. The size of the holding capacitance provided in the liquid crystal display device is set so that it can hold electric charges for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion. The size of the holding capacitance may be set in consideration of the off-current of the transistor. By using a transistor having a high-purity oxide semiconductor layer, a holding capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, with respect to the liquid crystal capacitance in each pixel is sufficient. By using a transistor having a high-purity oxide semiconductor layer, a holding capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, with respect to the liquid crystal capacitance in each pixel is sufficient. By using a transistor having a high-purity oxide semiconductor layer, a holding capacitance having a size of 1 / 3 or less, preferably 1 / 5 or less, with respect to the liquid crystal capacitance in each pixel is sufficient.

[0192] For the liquid crystal display device, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Bend) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. For the liquid crystal display device, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Bend) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. For the liquid crystal display device, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Bend) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. For the liquid crystal display device, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Bend) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. For the liquid crystal display device, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Bend) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. For the liquid crystal display device, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Bend) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used. For the liquid crystal display device, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Bend) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, etc. can be used.

[0193] Also, a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be used. Examples of the vertical alignment mode include, but are not limited to, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode. Also, a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be used. Examples of the vertical alignment mode include, but are not limited to, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode. Also, a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be used. Examples of the vertical alignment mode include, but are not limited to, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode. Also, a normally black type liquid crystal display device, for example, a transmissive liquid crystal display device adopting a vertical alignment (VA) mode may be used. Examples of the vertical alignment mode include, but are not limited to, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode. , the ASV mode or the like can be used. It can also be applied to a VA type liquid crystal display device. The VA type liquid crystal display device is a method of controlling the alignment of liquid crystal molecules in a liquid crystal display panel. It is a type of method. In a VA type liquid crystal display device, when no voltage is applied, the liquid crystal molecules are oriented in the vertical direction with respect to the panel surface. Also, pixels (picture elements) are divided into several regions (sub-pixels), and a method called multi-domain conversion or multi-domain design, which is devised to tilt the molecules in different directions, can be used. multi-domain conversion or multi-domain design can be used.

[0194] In addition, in the display device, optical members (optical substrates) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, and an anti-reflection member are appropriately provided. For example, circular polarization by a polarizing substrate and a retardation plate may be used. Also, a backlight, a side light, or the like may be used as the light source. For example, circular polarization using a polarizing substrate and a retardation plate may be used. Also, a backlight, a side light, or the like may be used as the light source. backlight, a side light, or the like may be used as the light source.

[0195] In addition, as the display method in the pixel portion, a progressive method, an interlace method, or the like can be used. Also, when performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, there are RGBW (W represents white), or RGB with one or more additional colors such as yellow, cyan, and magenta added. Note that the size of the display area may be different for each dot of the color elements. However, the present invention is not limited to a color display device, and can also be applied to a monochrome display device. In addition, as the display method in the pixel portion, a progressive method, an interlace method, or the like can be used. Also, when performing color display, the color elements controlled by the pixels are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, there are RGBW (W represents white), or RGB with one or more additional colors such as yellow, cyan, and magenta added. Note that the size of the display area may be different for each dot of the color elements. However, the present invention is not limited to a color display device, and can also be applied to a monochrome display device. RGBW (W represents white), or RGB with one or more additional colors such as yellow, cyan, and magenta added. Note that the size of the display area may be different for each dot of the color elements. However, the present invention is not limited to a color display device, and can also be applied to a monochrome display device. Note that the size of the display area may be different for each dot of the color elements. However, the present invention is not limited to a color display device, and can also be applied to a monochrome display device. However, the present invention is not limited to a color display device, and can also be applied to a monochrome display device.

[0196] In addition, as the display element included in the display device, a light-emitting element utilizing electroluminescence can be applied. The light-emitting element utilizing electroluminescence is a light-emitting material. electroluminescence is a light-emitting material.​​ It is distinguished according to whether it is an organic compound or an inorganic compound. Generally, the former is an organic E L element, and the latter is called an inorganic EL element.

[0197] In an organic EL element, by applying a voltage to a light-emitting element, electrons and holes are respectively injected into a layer containing a light-emitting organic compound, and a current flows. Then, these carriers (electrons and holes) recombine to form an excited state of the light-emitting organic compound and emit light when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0198] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element structures. Dispersed inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder and the light-emitting mechanism is donor-acceptor recombination type light emission that utilizes donor levels and acceptor levels. Thin-film inorganic EL elements have a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transitions of metal ions. Here, an organic EL element is used for explanation as the light-emitting element.

[0199] For a light-emitting element, at least one of a pair of electrodes may be transparent in order to extract light emission. Then, a transistor and a light-emitting element are formed on a substrate, and light emission is extracted from the surface opposite to the substrate side such as top emission, light emission is extracted from the surface on the substrate side such as bottom emission, or there is a light-emitting element with a double-sided emission structure in which light emission is extracted from the surface on the substrate side and the surface opposite to the substrate, and any light-emitting element with an emission structure can be applied.

[0200] ​​ FIG. 8 shows an example of a light-emitting device using a light-emitting element as a display element. The light-emitting element 4513 which is the display element is electrically connected to a transistor 4010 provided in a pixel portion 4002. Note that the light-emitting element 4513 has a stacked structure of a first electrode layer 4030, an electroluminescent layer 4511, and a second electrode layer 4031, but is not limited to the illustrated structure. The structure of the light-emitting element 4513 can be appropriately changed according to the direction of light emitted from the light-emitting element 4513 and the like.

[0201] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030, and to form the side wall of the opening as an inclined surface formed with a continuous curvature.

[0202] The electroluminescent layer 4511 may be composed of a single layer or may be configured such that a plurality of layers are stacked.

[0203] A protective film may be formed on the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting element 4513. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, or the like can be formed. Further, a filler 4514 is provided and sealed in a space sealed by the first substrate 4001, the second substrate 4006, and the sealing material 4005. In this way, it has high airtightness so as not to be exposed to the outside air, and it is preferable to perform packaging (encapsulation) with a protective film (laminating film, ultraviolet curable resin film, etc.) having little outgassing or a cover material.

[0204] ​​​​​​​​As the filling material 4514, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, poly imide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. For example, nitrogen can be used as the filling material. That's fine.

[0205] Moreover, if necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light emitting surface of the light emitting element. Also, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to the surface unevenness and reduce the reflection.

[0206] In addition, as a display device, it is also possible to provide an electronic paper that drives electronic ink. The electronic paper is also called an electrophoretic display device (electrophoretic display), and has the advantages of being as easy to read as paper, having lower power consumption compared to other display devices, and being able to be made thin and light.

[0207] Although various forms of electrophoretic display devices can be considered, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or a solute, and by applying an electric field to the microcapsule, the particles in the microcapsule are moved in opposite directions to each other and only the color of the particles aggregated on one side is displayed. Note that the first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless). ​​​​​​ ) shall be used.

[0208] In this way, the electrophoretic display device is a display that utilizes the so-called weak dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region.

[0209] A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is also possible by using color filters or particles having dyes.

[0210] Note that the first particles and the second particles in the microcapsules may be made of a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof.

[0211] Also, as an electronic paper, a display device using a twist ball display method can also be applied. The twist ball display method is a method of performing display by arranging spherical particles painted white and black between a first electrode layer and a second electrode layer, which are electrode layers used in a display element, and controlling the orientation of the spherical particles by generating a potential difference between the first electrode layer and the second electrode layer.

[0212] Fig. 9 shows an active matrix type electronic paper as one form of a semiconductor device. Fig. 9 shows an example of a display device using the twist ball display method.

[0213] A first electrode layer 4030 connected to a transistor 4010 and provided on a second substrate 4006 ​​​​It has a black region 4615a and a white region 4615b between it and the second electrode layer 4031 and spherical particles 4613 including a cavity 4612 filled with liquid around it are provided and the periphery of the spherical particles 4613 is filled with a filler 4614 such as resin. The second electrode layer 4031 corresponds to a common electrode (opposing electrode). The second electrode layer 4031 is electrically connected to the common potential line and electrically connected.

[0214] In addition, in FIGS. 7 to 9, as the first substrate 4001 and the second substrate 4006, a flexible substrate can be used, for example, a plastic substrate having translucency can be used and so on. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can also be used and so on.

[0215] The insulating layer 4020 functions as a protective film for the transistor.

[0216] In addition, the protective film is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the air and a dense film is preferable. The protective film can be formed by a single layer or a laminate of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film a silicon nitride film, an aluminum oxynitride film, or a silicon nitride aluminum oxide film using a sputtering method and so on. or a laminate.

[0217] Also, the insulating layer 4021 that functions as a planarizing insulating film is acrylic, polyimide, benzocyclo ​Organic materials with heat resistance, such as chlorbuten, polyamide, and epoxy, can be used. . In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, PS G (phosphorus glass), BPSG (borophosphorus glass), etc. can be used. Note that an insulating layer may be formed by laminating a plurality of insulating films formed of these materials.

[0218] The method for forming the insulating layer 4020 and the insulating layer 4021 is not particularly limited, and depending on the material, sputtering method, SOG method, spin coating, dipping, spray coating, droplet discharge method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used.

[0219] The display device performs display by transmitting light from a light source or a display element. Therefore, all thin films such as the substrate, insulating film, and conductive film provided in the pixel portion through which light passes are made transparent to light in the wavelength region of visible light.

[0220] In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, etc.) to which a voltage is applied to the display element, the light transmissivity and reflectivity may be selected according to the direction of the light to be extracted, the location where the electrode layer is provided, and the pattern structure of the electrode layer.

[0221] The first electrode layer 4030 and the second electrode layer 4031 are indium oxides containing tungsten oxide , indium zinc oxides containing tungsten oxide, indium oxides containing titanium oxide , indium tin oxides containing titanium oxide, indium tin oxides (hereinafter referred to as ITO. ), indium zinc oxides, indium tin oxides added with silicon oxide, etc., having light transmissivity ​A conductive material that can be used.

[0222] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) or molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b) Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag), It can be formed by using one or more of the following metals: Cut.

[0223] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer may be a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or a copolymer or derivative thereof consisting of two or more of aniline, pyrrole and thiophene Examples include the body.

[0224] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the driver circuit is also required. It is preferable that the protection circuit is configured using a non-linear element.

[0225] As described above, by using the transistors described in any of Embodiments 1 to 4, various functions can be achieved. It is possible to provide a display device having the above structure.

[0226] This embodiment mode can be implemented in appropriate combination with other embodiment modes.

[0227] (Embodiment 6) The semiconductor device disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of the electronic devices include, for example, television devices (also referred to as televisions or television receivers), monitors for computers, cameras such as digital cameras, digital video cameras, digital photo frames, mobile phones (also referred to as mobile phones or mobile phone devices), portable game machines, portable information terminals, audio playback devices, large gaming machines such as pachinko machines, etc. ) are included.

[0228] Figs. 10(A) and (B) are examples of applying the flexible semiconductor device formed by applying the above embodiment to an e-book. Fig. 10(A) shows the state where the e-book is opened, and Fig. 10(B) shows the state where the e-book is closed. The flexible semiconductor device formed by applying the above embodiment can be used for the first display panel 4311, the second display panel 4312, and the third display panel 4313. The first housing 4305 has a first display panel 4311 having a first display portion 4301. The second housing 4306 has a second display panel 4312 having an operation portion 4304 and a second display portion 4307.

[0229] The third display panel 4313, which is a double-sided display panel, has a third display portion 4302 and a fourth display portion 4310, and the third display panel 4313 is inserted between the first display panel 4311 and the second display panel 4312. The first housing 4305, the first display panel 4311, the third display panel 4313, the second display panel 4312, and the second housing 4306 are connected by a binding portion 4308 in which a drive circuit is provided inside. ​​​​​​exists. The e-book in FIG. 10 has four display screens: a first display unit 4301, a second display unit 4307, a third display unit 4302, and a fourth display unit 4310.

[0230] The first housing 4305, the first display panel 4311, the third display panel 4313, the second display panel 4312, and the second housing 4306 have flexibility and high flexibility. In addition, if a plastic substrate is used for the first housing 4305 and the second housing 4306, and a thin film is used for the third display panel 4313, a thin e-book can be obtained. .

[0231] The third display panel 4313 is a dual-sided display panel having the third display unit 4302 and the fourth display unit 4310. The third display panel 4313 may use a dual-sided injection type display panel, or may use a single-sided injection type display panel bonded together.

[0232] FIG. 11 shows an example in which a semiconductor device formed by applying the above embodiment is used as an indoor lighting device 3001. Since the semiconductor device shown in the above embodiment can be made large in area, it can be used as a large-area lighting device. In addition, the semiconductor device shown in the above embodiment can also be used as a desktop lighting fixture 3000. Note that lighting fixtures include ceiling-fixed standard lighting fixtures, desktop lighting fixtures, as well as wall-mounted lighting fixtures, in-vehicle lighting, induction lights, etc. are also included.

[0233] As described above, the semiconductor devices shown in Embodiments 1 to 5 can be arranged in various electronic devices as described above, and reliable electronic devices can be provided.

Claims

1. A display device having a pixel portion and a scanning line driving circuit on a substrate, wherein the scanning line driving circuit includes a first transistor having a first oxide semiconductor layer and a second transistor having a second oxide semiconductor layer, the channel width direction of the first transistor is the same as that of the second transistor, a first conductive layer having a region functioning as one of the source electrode and the drain electrode of the first transistor extends in the channel width direction of the first transistor and has a region functioning as one of the source electrode and the drain electrode of the second transistor, a second conductive layer having a region functioning as the gate electrode layer of the first transistor extends in the channel width direction of the first transistor and has a region functioning as the gate electrode layer of the second transistor, in the channel width direction of the first transistor, each of both ends of the first oxide semiconductor layer and both ends of the second oxide semiconductor layer has a portion overlapping with the second conductive layer, in each of the first transistor and the second transistor, the channel width is larger than the channel length, each of the first oxide semiconductor layer and the second oxide semiconductor layer contains In, Ga, and Zn, each of the lower surface of the first oxide semiconductor layer and the lower surface of the second oxide semiconductor layer has a region in contact with a first silicon oxide film, each of the upper surface of the first oxide semiconductor layer and the upper surface of the second oxide semiconductor layer has a region in contact with a second silicon oxide film. A display device.

2. A display device having a pixel portion and a scanning line driving circuit on a substrate, wherein the scanning line driving circuit includes a first transistor having a first oxide semiconductor layer and a second transistor having a second oxide semiconductor layer, the channel width direction of the first transistor is the same as that of the second transistor, a first conductive layer having a region functioning as one of the source electrode and the drain electrode of the first transistor extends in the channel width direction of the first transistor and has a region functioning as one of the source electrode and the drain electrode of the second transistor, The second conductive layer having a region that functions as the gate electrode layer of the first transistor extends in the channel width direction of the first transistor and has a region that functions as the gate electrode layer of the second transistor. In the channel width direction of the first transistor, each of both ends of the first oxide semiconductor layer and both ends of the second oxide semiconductor layer has a portion overlapping with the second conductive layer. In each of the first transistor and the second transistor, the channel width is larger than the channel length. Each of the first oxide semiconductor layer and the second oxide semiconductor layer contains In, Ga, and Zn. Each of the lower surface of the first oxide semiconductor layer and the lower surface of the second oxide semiconductor layer has a region in contact with the first silicon oxide film. Each of the upper surface of the first oxide semiconductor layer and the upper surface of the second oxide semiconductor layer has a region in contact with the second silicon oxide film. The substrate has a region bent in the channel width direction of the first transistor. The substrate contains glass, a display device. **Claim 3**: A display device having a pixel portion and a scanning line driving circuit on a substrate, wherein the scanning line driving circuit includes a first transistor having a first oxide semiconductor layer and a second transistor having a second oxide semiconductor layer. The channel width direction of the first transistor is the same as the channel width direction of the second transistor. The first conductive layer having a region that functions as one of the source electrode and the drain electrode of the first transistor extends in the channel width direction of the first transistor and has a region that functions as one of the source electrode and the drain electrode of the second transistor. The second conductive layer having a region that functions as the gate electrode layer of the first transistor extends in the channel width direction of the first transistor and has a region that functions as the gate electrode layer of the second transistor. The third conductive layer having a region that functions as the other of the source electrode and the drain electrode of the first transistor extends in the channel width direction of the first transistor and has a region that functions as the other of the source electrode and the drain electrode of the second transistor. In the channel width direction of the first transistor, each of both ends of the first oxide semiconductor layer and both ends of the second oxide semiconductor layer has a portion overlapping with the second conductive layer. In each of the first transistor and the second transistor, the channel width is larger than the channel length. Each of the first oxide semiconductor layer and the second oxide semiconductor layer contains In, Ga, and Zn. Each of the lower surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer has a region in contact with a first silicon oxide film. A display device, wherein each of the upper surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer has a region in contact with a second silicon oxide film. A display device according to claim 4, comprising a pixel portion and a scanning line driving circuit on a substrate, wherein the scanning line driving circuit includes a first transistor having a first oxide semiconductor layer and a second transistor having a second oxide semiconductor layer, wherein the channel width direction of the first transistor is the same as the channel width direction of the second transistor, a first conductive layer having a region functioning as one of a source electrode and a drain electrode of the first transistor extends in the channel width direction of the first transistor and has a region functioning as one of a source electrode and a drain electrode of the second transistor, a second conductive layer having a region functioning as a gate electrode layer of the first transistor extends in the channel width direction of the first transistor and has a region functioning as a gate electrode layer of the second transistor, a third conductive layer having a region functioning as the other of the source electrode and the drain electrode of the first transistor extends in the channel width direction of the first transistor and has a region functioning as the other of the source electrode and the drain electrode of the second transistor, In the channel width direction of the first transistor, each of both ends of the first oxide semiconductor layer and both ends of the second oxide semiconductor layer has a portion overlapping with the second conductive layer, In each of the first transistor and the second transistor, the channel width is larger than the channel length. Each of the first oxide semiconductor layer and the second oxide semiconductor layer contains In, Ga, and Zn. Each of the lower surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer has a region in contact with a first silicon oxide film. Each of the upper surfaces of the first oxide semiconductor layer and the second oxide semiconductor layer has a region in contact with a second silicon oxide film. The substrate has a region bent in the channel width direction of the first transistor. The substrate is a display device having glass.

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