System and method for chirp generation of digital signals using a frequency multiplier

Abstract

A system and method for digitally synthesizing a chirp signal in a low intermediate frequency (IF) band and generating a higher frequency signal for radar applications using frequency multipliers is described. An embodiment includes a chirp signal generator including a direct digital frequency synthesizer (DDFS) configured to receive an input synchronization signal and a frequency reference signal and generate a number of chirp signals at a first frequency that is in the low intermediate frequency (IF) band, a number of frequency multipliers configured to increase the chirp signal to a higher frequency, and a number of bandpass filter circuits configured to remove nonlinearities from the chirp signal and generate a clean output signal.

Description

Technical Field

[0001] (Cross - Reference to Related Applications) This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 63 / 146,261, filed on February 5, 2021, entitled "Systems and Methods for Digital Signal Chirp Generation Using Frequency Multipliers", which is incorporated herein by reference in its entirety.

[0002] (Field of the Invention) The present invention relates to a chirp generator, and more particularly, to using a digitally synthesized chirp signal, processing the signal using a frequency multiplier, and generating a higher - frequency signal for radar applications.

Background Art

[0003] (Background) A chirp is a signal in which the frequency increases (up - chirp) or decreases (down - chirp) over time. In some sources, the term "chirp" can be used synonymously with a sweep signal. It can be applied to, among other various applications, sonar, radar, and laser systems. For automotive radar applications, this is typically referred to as a linear frequency - modulated waveform (LFMW). The LFMW signal can be defined by the following equation.

[0004] (Equation 1):

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[0005] A chirp signal can be generated using an analog circuit network via a voltage controlled oscillator (VCO) and a linear or exponential ramp control voltage.

SUMMARY OF THE INVENTION

MEANS FOR SOLVING THE PROBLEM

[0006] (SUMMARY OF THE INVENTION) Disclosed is a chirp generator that utilizes a digitally synthesized chirp signal within a low intermediate frequency (IF) band according to an embodiment of the present invention, processes the chirp signal using a frequency multiplier, and can generate a higher frequency signal for radar applications. In an embodiment of the present invention, the chirp signal generator is configured to receive an input synchronization signal and a frequency reference signal and generate several chirp signals at a first frequency within a low intermediate frequency (IF) band, a direct digital frequency synthesizer (DDFS), and several frequency multipliers configured to increase a chirp signal present within the IF band to a higher frequency that is a multiple of the first frequency, and several band-pass filter circuits configured to remove non-linearity from a plurality of chirp signals and generate a clean output signal.

[0007] In a further embodiment, the chirp generator further includes a first frequency doubler circuit that receives the first frequency, doubles the first frequency, and generates a second frequency that is twice the first frequency, a second frequency doubler circuit that receives the second frequency, doubles the second frequency, and generates a third frequency that is twice the second frequency, a third frequency doubler circuit that receives the third frequency, doubles the third frequency, and generates a fourth frequency that is twice the third frequency, and a fourth frequency doubler circuit that receives the fourth frequency, doubles the fourth frequency, and generates a fifth frequency that is twice the fourth frequency.

[0008] In a further embodiment, the first frequency is in the range of 1,562.5 to 1,750 MHz, the second frequency is in the range of 3,125 to 3,500 MHz, the third frequency is in the range of 6,250 to 7,000 MHz, the fourth frequency is in the range of 12.5 to 14 GHz, and the fifth frequency is in the range of 25 to 28 GHz.

[0009] In a further embodiment, some of the band - pass filter stages include a first band - pass filter circuit after the first frequency doubler circuit, a second band - pass filter circuit after the second frequency doubler circuit, and a third band - pass filter circuit after the third frequency doubler circuit.

[0010] In a further embodiment, the direct frequency synthesizer includes a high - speed resonator that generates a frequency signal, and an oscillator that receives the frequency signal and generates an output signal.

[0011] In a further embodiment, the chirp signal generator further includes several amplifier circuits that amplify an input chirp signal and generate an amplified output signal.

[0012] In a further embodiment, the chirp signal is denoted as x(t),

Number

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[0013] In a further embodiment, the bandpass filter is used to select a desired second harmonic from the frequency doubler, and the bandpass filter output is z(t), and

Number

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[0014] In a further embodiment, the chirp signal generator further includes a first frequency quadrupler circuit that receives a first frequency, quadruples the first frequency, and generates a second frequency that is four times the first frequency, and a second frequency quadrupler circuit that receives the second frequency, quadruples the second frequency, and generates a third frequency that is four times the second frequency.

[0015] In a further embodiment, the chirp signal generator further includes filtering out harmonics and intermodulation components that do not fall within a specific frequency band in order to preserve the linearity of the signal between frequency doubling stages. The present invention provides, for example, the following. (Item 1) A chirp signal generator comprising: a direct digital frequency synthesizer (DDFS) configured to receive an input synchronization signal and a frequency reference signal and generate a plurality of chirp signals at a first frequency within a low intermediate frequency (IF) band; a plurality of frequency multipliers configured to increase the plurality of chirp signals to a higher frequency that is a multiple of the first frequency; a plurality of band-pass filter circuits configured to remove non-linearity from the plurality of chirp signals and generate a clean output signal A chirp signal generator comprising. (Item 2) a first frequency doubler circuit configured to receive the first frequency, double the first frequency, and generate a second frequency that is twice the first frequency; a second frequency doubler circuit configured to receive the second frequency, double the second frequency, and generate a third frequency that is twice the second frequency; a third frequency doubler circuit configured to receive the third frequency, double the third frequency, and generate a fourth frequency that is twice the third frequency; a fourth frequency doubler circuit configured to receive the fourth frequency, double the fourth frequency, and generate a fifth frequency that is twice the fourth frequency The chirp generator according to Item 1, further comprising. (Item 3) The first frequency is in the range of 1,562.5 to 1,750 MHz, the second frequency is in the range of 3,125 to 3,500 MHz, the third frequency is in the range of 6,250 to 7,000 MHz, the fourth frequency is in the range of 12.5 to 14 GHz, and the fifth frequency is in the range of 25 to 28 GHz. The chirp generator according to Item 2. (Item 4) The plurality of band-pass filter stages include a first band-pass filter circuit after the first frequency doubler circuit, a second band-pass filter circuit after the second frequency doubler circuit, and a third band-pass filter circuit after the third frequency doubler circuit. The chirp generator according to Item 2. (Item 5) The direct frequency synthesizer includes a high-speed resonator that generates a frequency signal, and an oscillator that receives the frequency signal and generates an output signal. The chirp signal generator according to Item 1. (Item 6) The chirp signal generator according to item 1, further comprising a plurality of amplifier circuits that amplify an input chirp signal and generate an amplified output signal. (Item 7) The chirp signal is represented as x(t),

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[0016]

Figure 1

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Figure 2

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[0020]

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Figure 8

[0024]

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Figure 10

[0026] (Detailed Description) Turning now to the drawings, systems and methods are illustrated for generating higher frequency RF chirp signals for various applications, including radar, using digitally synthesized chirp signals and frequency multipliers as needed, according to various embodiments of the present invention. In many embodiments, the digital chirp signal can be generated using a digital direct frequency synthesizer (DDFS) in a relatively low intermediate frequency (IF) band, and the signal can be increased to a higher frequency using multiple stages of frequency multipliers as needed for radar applications.

[0027] In many embodiments, a direct digital frequency synthesizer that provides a clean input signal, as described in U.S. Patent No. 10,530,372 (the Yu et al. patent), filed on March 27, 2017, and titled "Systems and Methods for Digital Synthesis of Output Signals Using Resonators" by Yu et al., and incorporated herein by reference, can be utilized. In many embodiments, utilizing DDFS as described by the Yu et al. patent can provide ultra-low phase noise and an output signal in an initial state. In many embodiments, a direct digital frequency synthesizer (DDFS) can include a high-speed resonator that generates a frequency signal, an oscillator that receives the frequency signal and generates an output signal, a clock generator that receives the output signal of the oscillator and generates a clock signal from the output signal, a controller that generates a frequency control word that describes a desired output digital signal, and a direct digital frequency synthesizer that receives the clock signal and the frequency control word and generates a desired digital output signal based on the clock signal and the frequency control word.

[0028] According to some embodiments, the output frequency may be controlled by a frequency control word (FCW) provided to the DDFS. According to many embodiments, the frequency synthesizer can be comparable to a voltage controlled oscillator (VCO) and can be used within a PLL for clock generation and / or jitter attenuation applications. In many embodiments, a direct digital frequency synthesizer (DDFS) block according to various embodiments of the present invention may be used for frequency and phase tracking.

[0029] According to some embodiments of the present invention, a direct frequency synthesizer may provide a programmable oscillator. The programmable oscillator can be used to replace many existing standard crystal and quartz-based oscillators and can provide a number of benefits, including, but not limited to, significant cost savings. In particular, the programmable oscillator can be used to replace many of the existing high-performance crystal oscillators (XOs) and voltage-controlled oscillators (VCXOs) available on the market.

[0030] According to some embodiments of the present invention, the programmable frequency of the programmable oscillator provided by the direct frequency synthesizer is in the range of 1 MHz to 2 GHz (or higher), can be programmable using a frequency control word (FCW), which can be at least 32 bits in length. According to some embodiments of the present invention, the frequency of the programmable oscillator provided by the direct frequency synthesizer may be programmable at the factory as a single frequency and / or limited to a plurality of selectable frequencies. In some embodiments, the programmable oscillator may be programmable using an Inter-Integrated Circuit (I2C) and / or any other suitable interface. In one embodiment, the programmable frequency may be voltage-controlled. The programmable oscillator has a jitter of less than 100 fs, is integrated from 12 KHz to 20 MHz, has a frequency drift of + / - 10 ppm, and the operating range can be from -40 to 85 degrees Celsius.

[0031] Furthermore, according to some embodiments of the present invention, a programmable oscillator provided by a direct frequency synthesizer can provide ultra-low phase noise (e.g., <=50 fs and integrated from 12 KHz to 20 MHz). The programmable oscillator may have a single voltage supply source (e.g., 3.3V, 2.5V, or 1.8V) and may use an industry standard package (e.g., 5×7, 3.2×5). As can be easily understood, the specific characteristics of the programmable oscillator provided by the direct frequency synthesizer according to some embodiments of the present invention are not limited to any specific characteristics and can be determined based on the requirements of specific applications according to the embodiments of the present invention.

[0032] In many embodiments, the DDFS circuit may include a look-up table that stores sine and cosine values. Further, a control word may be used to set the output frequency of the DDFS circuit according to some embodiments. The DDFS circuit can provide a very high tuning range because DDFS is used to set the frequency. Further, the programmable oscillator can provide low phase noise by using the ability to adjust the output frequency of the programmable oscillator. According to some embodiments, the DDFS circuit may use logic and memory to digitally construct a desired output signal, and an HS DAC may be used to convert the output signal of the DDFS circuit from the digital domain to the analog domain. Therefore, the DDFS method of constructing a signal can be almost completely digital, and precise amplitude, frequency, and phase can always be grasped and controlled.

[0033] In many embodiments, the chirp signal can be generated digitally by a digital signal processor (DSP) and a digital-to-analog converter (DAC) using a direct digital frequency synthesizer (DDFS) and varying the steps in a numerically controlled oscillator. For example, the digital codeword x n can be defined in the following equation.

[0034] Equation 2: [Number] -T s : Sampling period of the DAC clock -f n : Time t = nT s Frequency at

[0035] The digital codeword can be converted into an analog signal using a high-speed DAC. The digital frequency synthesis architecture can provide many advantages over analog VCO implementations, including up to full linear frequency modulation, ultra-low phase noise, and ultra-high frequency modulation rates.

[0036] According to the Nyquist sampling theorem, the sample rate for a high-speed DAC may need to be at least twice the highest frequency contained within the signal. For example, for automotive radar applications operating within the 77 GHz band, the sample rate for a digital synthesis DAC can be near 200 GHz. Implementing a design with these specifications can be difficult and may be power inefficient. Thus, many embodiments of the present invention provide for digitally synthesizing a chirp signal within a low intermediate frequency (IF) band and converting this low IF signal into a higher frequency RF signal through a series of frequency multipliers. The system architecture according to many embodiments of the present invention provides substantial power savings without sacrificing the advantages of digital frequency synthesis.

[0037] In some embodiments, a chirp signal at a relatively low frequency (e.g., 1.5 - 2 GHz) is generated by a DDFS and can be processed through several stages of frequency doublers to convert the chirp signal to a higher frequency range, e.g., from 1.75 GHz to 25 - 28 GHz, which may be suitable for many radar applications, including automotive radar. By comparison, many current existing radar applications may utilize an LC oscillator analog signal generated, for example, at 28 GHz, or may use a phase - locked loop (PLL) mixed with a 28 GHz signal to generate a chirp signal. However, these signals generally suffer from non - linearity and have problems related to phase noise. Thus, to improve phase noise and increase the linearity of the chirp signal, many embodiments use a digitally synthesized chirp signal rather than an analog signal and maintain the linearity of the digital signal by filtering phase noise and non - linearity at each stage of frequency multiplication. Thus, many embodiments can preserve the linearity of the frequency of chirp generation, thereby increasing the accuracy of many radar applications.

[0038] The low - IF chirp signal is denoted as x(t).

[0039] Equation 3:

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[0040] To generate a chirp signal that is twice the carrier frequency of x(t), x(t) is passed through a frequency doubler. The frequency doubler output is denoted as y(t).

[0041] Equation 4:

Number

[0042] As shown in Equation 4 above, the frequency doubler output includes a chirp signal with a carrier frequency, bandwidth, and chirp rate that are twice those of the input chirp signal, as well as a DC component. In some embodiments, the output may also have an attenuated input signal due to signal leakage and a chirp signal at three times the carrier frequency due to circuit non-linearity. This can be illustrated in FIG. 6 in accordance with an embodiment of the present invention and can be shown in the following equation.

[0043] Equation 5:

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[0044] In many embodiments, a bandpass filter can be used to select the desired second harmonic from the frequency doubler. Let the bandpass filter output be denoted as z(t).

[0045] Equation 6:

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[0046] For a frequency multiplier including four doublers, let the output of each stage be denoted as z i (t), (i = 1, 2, 3, 4), and they are represented in the following equation.

[0047] Equation 7:

Number

[0048] As shown in these equations, the filtered frequency multiplier output consists of the desired chirp output. The phase noise at higher frequencies can be the phase noise at the IF frequency multiplied by the ratio of the frequency multiplier. In many embodiments, there is no additional phase noise within the frequency multiplier data path.

[0049] During the frequency multiplication stage, to preserve the linearity of the signal, many embodiments filter out any harmonics and intermodulation components that do not fall within a specific frequency band. In many embodiments, since the artifacts and non - linearities during digital synthesis are known in advance and can be planned during the filtering stage, the frequency band can be pre - planned. Many embodiments use band - pass filtering at each frequency multiplier stage to filter out noise and preserve the linearity of the signal. A chirp generator with a frequency multiplier according to an embodiment of the present invention is illustrated in FIG. 1.

[0050] As shown, the IF chirp generator, which can be a direct digital frequency synthesizer (DDFS), synthesizes a low intermediate frequency (IF) chirp signal and converts it into an analog signal through a high - speed DAC at a specific frequency centered, for example, around approximately 1.6 GHz. In many embodiments, the DDFS can be a frequency synthesizer that provides a clean input signal as described in U.S. Patent No. 10,530,372 (Yu et al.'s patent) filed on March 27, 2017, titled "Systems and Methods for Digital Synthesis of Output Signals Using Resonators" and incorporated herein by reference in its relevant parts. In many embodiments, the low IF chirp signal is up - converted to a higher RF frequency with multiple stages, for example, a four - stage frequency multiplication operation. In one embodiment, the four - stage frequency multiplication operation can be implemented as two frequency quadruplers.

[0051] The signal can be processed through several stages of frequency multipliers and amplifiers to obtain frequencies in a specific desired range, e.g., in the range of 25 - 28 GHz. In many embodiments, the architecture can include a two - stage frequency quadrupler that converts a chirp signal, e.g., from 1.75 GHz to 28 GHz. In many embodiments, after each stage of frequency multiplication, the second - harmonic of the signal can be selected for further multiplication. In many embodiments, the chirp generator architecture does not add IQ imbalance and there is no degradation of phase noise due to the charge pump.

[0052] As shown in FIG. 1, the IF chirp generator can receive a sync_in signal and a reference signal, e.g., a 40 MHz reference signal, and generate chirp #1 provided to an amplifier and chirp #2 provided to an amplifier. Each chirp can be provided to a quadrupler (×4) and a subsequent amplifier. After the first stage, the signal can be increased, e.g., from a range of 1,562.5 - 1,750 MHz to a range of 6,250 - 7,000 MHz. The signal can be provided to another quadrupler to increase the frequency, e.g., to a range of 25 - 28 GHz.

[0053] FIG. 1 illustrates a specific chirp generator architecture with a two - stage frequency quadrupler at specific frequencies, but any of a variety of chirp generator architectures and frequencies, including, inter alia, a chirp generator with a four - stage frequency doubler, suitable for the requirements of a specific application according to embodiments of the present invention, can be utilized. Filtering and pre - planning techniques for preserving the linearity of the signal according to many embodiments of the present invention include using band - pass filtering to remove non - linearity after each stage of frequency multiplication.

[0054] FIG. 2 illustrates a chirp generator architecture with band - pass filtering for removing non - linearity according to an embodiment of the present invention. As shown, the chirp generator can include a DDFS, several frequency doublers, and several band - pass filters. As shown, the IF chirp generator can be a frequency synthesizer that provides a clean input signal as described in U.S. Patent No. 10,530,372 (the Yu et al. patent), filed on March 27, 2017, entitled "Systems and Methods for Digital Synthesis of Output Signals Using Resonators", the relevant portions of which are incorporated herein by reference. As shown, the chirp signal is provided to a four - stage frequency doubler (×2), and each stage can include an amplifier circuit and a band - pass filter circuit for harmonic filtering and capable of removing non - linearity at each stage. Thus, the chirp signal can be increased in each of four stages as follows: for example, from 1,562.5 - 1,750 MHz to 3,125 - 3,500 MHz, from 3,125 - 3,500 MHz to 6,250 - 7,000 MHz, from 6,250 - 7,000 MHz to 12.5 - 14 GHz, and from 12.5 - 14 GHz to 25 - 28 GHz.

[0055] FIG. 2 illustrates a particular chirp generator architecture with a band - pass filter for removing non - linearity, but any of various chirp generator architectures can be utilized as appropriate for the requirements of a specific application according to an embodiment of the present invention.

[0056] FIG. 3 illustrates a first - stage amplifier noise architecture according to an embodiment of the present invention. In many embodiments, the DAC output power = - 10 dBm and has a noise floor of - 154 dBc / Hz. In many embodiments, the amplifier output noise floor in dBc / Hz is

Equation

[0057] Figure 3 illustrates a specific first-stage amplifier noise architecture, but any of various amplifier noise architectures can be utilized as appropriate for the requirements of a specific application according to embodiments of the present invention.

[0058] Figure 4 illustrates a chirp generator with bandpass filtering according to an embodiment of the present invention. As shown, the chirp generator includes a DDFS, a four-stage frequency doubler, several low-pass filters, and several bandpass filters. In particular, the chirp generator can receive a sync_in signal and a frequency_ref signal and generate several chirp signals including chirp_out1 and chirp_out2. The chirp signals can be amplified, passed through a low-pass filter stage, and then provided to a four-stage frequency doubler circuit. The chirp signals can also be provided to a series of bandpass filter circuits as shown in Figure 4.

[0059]

[0060] Figure 4 illustrates a specific chirp generator with bandpass filtering architecture, but any of various chirp generator architectures can be utilized as appropriate for the requirements of a specific application according to embodiments of the present invention.

[0061] FIG. 5 illustrates a model of a frequency doubler with intermodulation, according to an embodiment of the present invention. In many embodiments, intermodulation can generate unwanted harmonics in a frequency multiplication operation. In many embodiments, the doubler can be modeled as the sum of an IM2 product and an IM3 product with gain passing through a tilt filter. In many embodiments, the gain models the third-order non-linearity of the doubler. In some embodiments, the tilt filter models the power delta between the fundamental tone and the third harmonic tone. FIG. 6 illustrates a specific doubler modeling, but any of various doubler models can be utilized as appropriate for the requirements of a specific application, according to an embodiment of the present invention.

[0062] FIG. 6 illustrates several graphs of the doubler output spectrum, according to an embodiment of the present invention. As shown, each graph corresponds to a specific input (1.65 GHz, 3.3 GHz, 6.6 GHz, and 13.2 GHz), the X-axis corresponds to a specific frequency, and the Y-axis corresponds to dB. As shown, each graph shows the output spectrum simulated in each frequency doubler. As shown, these output spectra are in good agreement with the specifications of a certain component used in a chirp generator design, according to various embodiments of the present invention.

[0063] FIG. 7 illustrates several graphs of the bandpass filter frequency response, according to an embodiment of the present invention. Each graph corresponds to a specific simulated bandpass filter frequency response (e.g., 2,975, 5,540, 1,262, and 2,582). These frequency responses can be in good agreement with the specifications of a certain component used in a chirp generator design, according to some embodiments of the present invention.

[0064] FIG. 8 illustrates a graph of the RF output spectrum according to an embodiment of the present invention. As shown, the graph shows the output spectrum of the chirp signal generated at the RF frequency. As shown, the RF chirp signal is from 26 GHz to 26.75 GHz. The synthesized RF chirp signal can be evaluated with respect to signal generation performance.

[0065] FIG. 9 illustrates a graph of the chirp output frequency according to an embodiment of the present invention. The X-axis of the graph corresponds to time, and the Y-axis corresponds to frequency. As shown, the graph illustrates the output frequency offset of the synthesized RF chirp signal. The offset frequency 0 corresponds to the center of the chirp frequency band. The center of the chirp frequency band is 26.8 GHz. In this embodiment, there are two chirps. The first chirp frequency ranges from 26.4 GHz to 27.2 GHz, or from -400 MHz to 400 MHz, at a frequency offset from 26.8 GHz. The second chirp frequency ranges from 26.56 GHz to 27.36 GHz or from -240 MHz to 560 MHz at a frequency offset from 26.8 GHz. Since the low IF chirp signal is digitally synthesized and has a perfectly linear frequency ramp, the corresponding RF chirp signal also has a perfectly linear frequency ramp, as shown in FIG. 9. Furthermore, the digitally synthesized chirp can instantaneously change the frequency ramp direction. Therefore, the same property can be preserved within the RF chirp signal.

[0066] FIG. 10 illustrates a graph of the RF carrier phase noise according to an embodiment of the present invention. The X-axis of the graph corresponds to the offset frequency (Hz), and the Y-axis corresponds to dBc / Hz. As shown, there is a 24 dB difference between the RF output @25.6 GHz and the DAC output @1.6 GHz. As shown, the graph shows the carrier phase noise of the low IF signal and the RF signal. The delta between the two phase noises is approximately 24 dB or 20×log10(16). In the example shown in FIG. 10, 16 is the frequency multiplication ratio. As shown, the phase noise performance of the low IF chirp is also preserved within the RF chirp signal.

[0067] Although the present invention has been described in a certain specific aspect, many additional modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that the present invention may be practiced otherwise than as specifically described and may include various changes in implementation. Therefore, the embodiments of the present invention should be regarded as illustrative in every respect and not restrictive.

Claims

1. A chirp signal generator, wherein the chirp signal generator comprises: A direct digital frequency synthesizer (DDFS) configured to receive an input synchronization signal and a frequency reference signal and generate a plurality of chirp signals at a first frequency within a low intermediate frequency (IF) band; A plurality of frequency multipliers configured to increase the frequencies of the plurality of chirp signals to a higher frequency that is a multiple of the first frequency; A plurality of band-pass filter circuits configured to generate a clean output signal by removing non-linearity from the plurality of chirp signals and comprising: The plurality of frequency multipliers include: A first frequency doubler circuit configured to receive the first frequency and generate a second frequency that is twice the first frequency by doubling the first frequency; A second frequency doubler circuit configured to receive the second frequency and generate a third frequency that is twice the second frequency by doubling the second frequency; A third frequency doubler circuit configured to receive the third frequency and generate a fourth frequency that is twice the third frequency by doubling the third frequency; A fourth frequency doubler circuit configured to receive the fourth frequency and generate a fifth frequency that is twice the fourth frequency by doubling the fourth frequency and comprising a chirp signal generator.

2. The chirp generator according to claim 1, wherein the first frequency is in the range of 1,562.5 MHz to 1,750 MHz, the second frequency is in the range of 3,125 MHz to 3,500 MHz, the third frequency is in the range of 6,250 MHz to 7,000 MHz, the fourth frequency is in the range of 12.5 GHz to 14 GHz, and the fifth frequency is in the range of 25 GHz to 28 GHz.

3. The chirp generator according to claim 1, wherein the plurality of band-pass filter circuits include a first band-pass filter circuit after the first frequency doubler circuit, a second band-pass filter circuit after the second frequency doubler circuit, and a third band-pass filter circuit after the third frequency doubler circuit.

4. The direct digital frequency synthesizer according to claim 1 includes a high-speed resonator that generates a frequency signal, and an oscillator that receives the frequency signal and generates an output signal.

5. The chirp signal generator according to claim 1 further includes a plurality of amplifier circuits, and the plurality of amplifier circuits generate an amplified output signal by amplifying an input chirp signal.

6. The chirp signal is represented as x(t), 【Number 21】 f ０ : The initial frequency of the chirp signal, α: the frequency ramp rate of the chirp signal, θ ０ : The initial phase of the chirp signal, 【Number 22】 is the phase noise added in the digital-to-analog (DAC) process, By passing x(t) through the frequency doubler circuit of the plurality of frequency doublers, a chirp signal that is twice the carrier frequency of x(t) is generated, and the output of the frequency doubler circuit is y(t), 【Number 23】 is the chirp signal generator according to claim 1.

7. The bandpass filter is used to select a desired second harmonic from the frequency doubler, and the bandpass filter output is z(t), [Number 24] k: is a scale factor, The plurality of frequency multipliers includes four frequency doubler stages, and the band-pass filter output of each stage is z ｉ (t), (i = 1, 2, 3, 4) as shown, 【Number 25】 is the chirp signal generator according to claim 1.

8. The plurality of frequency doublers A first frequency quadrupler circuit that receives the first frequency and generates a second frequency that is four times the first frequency by quadrupling the first frequency; A second frequency quadrupler circuit that receives the second frequency and generates a third frequency that is four times the second frequency by quadrupling the second frequency is further provided, and is the chirp signal generator according to claim 1.

9. The chirp signal generator further includes filtering out harmonic and intermodulation components that do not fall within a specific frequency band in order to preserve the linearity of the signal during the frequency doubling stage, according to claim 1. The chirp signal generator described.

10. A method for generating a chirp signal, the method comprising: Using a direct digital frequency synthesizer (DDFS) to receive an input synchronization signal and a frequency reference signal, and generate a plurality of chirp signals at a first frequency within a low intermediate frequency (IF) band; Increasing the plurality of chirp signals to a higher frequency that is a multiple of the first frequency using a plurality of frequency multipliers, wherein the plurality of frequency multipliers comprises a first frequency doubler circuit, a second frequency doubler circuit, a third frequency doubler circuit, and a fourth frequency doubler circuit, Generating a clean output signal by removing non-linearity from the plurality of chirp signals using a plurality of band-pass filter circuits, In the first frequency doubler circuit, receiving the first frequency and generating a second frequency that is twice the first frequency by doubling the first frequency, In the second frequency doubler circuit, receiving the second frequency and generating a third frequency that is twice the second frequency by doubling the second frequency, In the third frequency doubler circuit, receiving the third frequency and generating a fourth frequency that is twice the third frequency by doubling the third frequency, In the fourth frequency doubler circuit, receiving the fourth frequency and generating a fifth frequency that is twice the fourth frequency by doubling the fourth frequency A method comprising.

11. The method according to claim 10, wherein the first frequency is in the range of 1,562.5 MHz to 1,750 MHz, the second frequency is in the range of 3,125 MHz to 3,500 MHz, the third frequency is in the range of 6,250 MHz to 7,000 MHz, the fourth frequency is in the range of 12.5 GHz to 14 GHz, and the fifth frequency is in the range of 25 GHz to 28 GHz.

12. The method according to claim 10, wherein the plurality of band-pass filter circuits comprises a first band-pass filter circuit after the first frequency doubler circuit, a second band-pass filter circuit after the second frequency doubler circuit, and a third band-pass filter circuit after the third frequency doubler circuit.

13. The method according to claim 10, wherein the direct digital frequency synthesizer comprises a high-speed resonator that generates a frequency signal and an oscillator that receives the frequency signal and generates an output signal. **Claim 14**: The method according to claim 10, further comprising generating an amplified output signal by amplifying the plurality of chirp signals using a plurality of amplifier circuits. **Claim 15** The chirp signal is denoted as x(t), 【Number 26】 f ０ : The initial frequency of the chirp signal, α: the frequency ramp rate of the chirp signal, θ ０ : The initial phase of the chirp signal, 【Number 27】 is the phase noise added in the digital - analog (DAC) process, By passing x(t) through the frequency doubler circuit of the plurality of frequency doublers, a chirp signal that is twice the carrier frequency of x(t) is generated, and the output of the frequency doubler circuit is y(t), 【Number 28】 The method according to claim 10. **Claim 16** The band - pass filter is used to select the desired second - order harmonic from the frequency doubler, and the band - pass filter output is z(t), 【Number 29】 k: is a scale factor, The plurality of frequency multipliers includes four frequency doubling stages, and the band-pass filter output of each stage is z ｉ (t), (i = 1, 2, 3, 4) and is shown as 【30 numbers】 The method according to claim 10. **Claim 17**: The plurality of frequency doublers further comprises a first frequency quadrupler circuit and a second frequency quadrupler circuit, The method comprises In the first frequency quadrupler circuit, receiving the first frequency and generating a second frequency that is four times the first frequency by quadrupling the first frequency; In the second frequency quadrupler circuit, receiving the second frequency and generating a third frequency that is four times the second frequency by quadrupling the second frequency The method according to claim 10, further comprising. **Claim 18**: The method according to claim 10, further comprising filtering out harmonics and intermodulation components that do not fall within a specific frequency band in order to preserve the linearity of the signal during the frequency doubling stage.

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