Gap filling deposition process

Abstract

In one embodiment, a method for forming an interconnect structure in a substrate in a cluster processing system and a method for thermally treating the interconnect structure are provided. In one embodiment, the method for device formation of a semiconductor device includes forming a barrier layer in an opening formed in a material layer disposed on a substrate, forming an interface layer on the barrier layer, forming a gap fill layer on the interface layer, and subjecting the substrate to an annealing process performed at a pressure range greater than 5 bar.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to a method for forming a metal-containing material. More specifically, embodiments of the present disclosure generally relate to a method for forming a metal-containing material in a small-sized opening in a device structure of a semiconductor device.

Background Art

[0002]

[0002] Ensuring the manufacture of features below sub-half micron is one of the important technical challenges in very large scale integration (VLSI) and ultra very large scale integration (ULSI) of next-generation semiconductor devices. However, while the limits of circuit technology are being raised, the requirements for processing power are further increasing due to the dimensional scaling of the interconnect technology in VLSI and ULSI. Reliably forming a gate structure on a substrate is important for the success of VLSI and ULSI and for continuing efforts to increase the circuit density and quality of individual substrates and dies.

[0003]

[0003] As the dimensions of integrated circuit components become smaller (e.g., down to deep submicron dimensions), the materials used in the manufacture of such components must be carefully selected to obtain a satisfactory level of electrical performance. To enable the manufacture of next-generation devices and structures, semiconductor chips are often stacked three-dimensionally (3D) to improve the performance of transistors. By arranging transistors three-dimensionally instead of in the conventional two dimensions, multiple transistors can be placed in close proximity to each other in an integrated circuit (IC). Stacking semiconductor chips three-dimensionally (3D) reduces the wiring length and keeps the wiring delay low. As the width of the trench shrinks, the aspect ratio (depth divided by width) during stacking of semiconductor chips continues to increase. One challenge regarding the manufacture of high aspect ratio trenches is to avoid the formation of voids during the deposition of the desired material in the trench.

[0004]

[0004] To fill the trench, a layer of a material such as a dielectric material or a metal layer is deposited. The material layer typically covers not only the field but also the walls and bottom of the trench. If the trench is wide and shallow, it is relatively easy to completely fill the trench. However, as the aspect ratio of the trench increases, the opening of the trench is more likely to "pinch off", resulting in a higher possibility of voids (e.g., defects) being formed within the trench.

[0005]

[0005] To reduce the possibility of voids being formed within the trench or seams being formed within the trench, many different process techniques have been developed to fill the trench with the desired material layer while minimizing defects. Poor process control during the deposition process can result in an irregular structure profile or the trench closing prematurely, creating voids, seams, or voids within the trench while filling it with a dielectric material.

[0006]

[0006] Therefore, there is a need to improve the deposition process for forming a material layer within a trench having a desired profile with minimal defects.

SUMMARY OF THE INVENTION

[0007]

[0007] A method of forming an interconnect structure on a substrate in a cluster processing system and a method of heat-treating the interconnect structure are provided. In one embodiment, a method of forming a device structure of a semiconductor device includes forming a barrier layer in an opening formed in a material layer disposed on the substrate, forming an interface layer on the barrier layer, forming a gap-fill layer on the interface layer, and performing an annealing process executed in a pressure range higher than 5 bar on the substrate.

[0008]

[0008] In another embodiment, the interconnect structure includes a barrier layer formed in an opening defined in a material layer disposed on the substrate, an interface layer disposed on the barrier layer, and a gap-fill layer disposed on the interface layer and having an average particle size greater than 10 nm.

[0009]

[0009] In yet another embodiment, the method of forming the interconnect structure includes performing a gap filling layer forming process by repeatedly executing a deposition process and a plasma treatment process until a gap filling layer of a predetermined thickness is obtained, and after the gap filling layer forming process is completed, performing an annealing process on the gap filling layer at a pressure higher than 5 bar while supplying a hydrogen or hydrogen isotope-containing gas.

[0010]

[0010] To understand the features of the present disclosure described above in detail, the present disclosure summarized above will be described more specifically with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings merely show typical embodiments of the present disclosure and should not be regarded as limiting the scope of the present disclosure, and the present disclosure may also admit other equally effective embodiments.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Embodiments for Carrying Out the Invention

[0012]

[0019] For ease of understanding, the same reference numbers are used as much as possible to indicate the same elements common to the drawings. It is considered that the elements and features of one embodiment can be beneficially incorporated into other embodiments without further detailed description.

[0013]

[0020] However, it should be noted that the accompanying drawings merely show exemplary embodiments of the present disclosure and should not be regarded as limiting the scope of the present disclosure, and the present disclosure may also admit other equally effective embodiments.

[0014]

[0021] A method of forming a metal-containing interconnect structure having good gap filling performance on a substrate in a semiconductor device is provided. In one example, a pre-cleaning process, a barrier layer deposition process, an interface layer deposition process, a gap filling layer deposition process, and a high-pressure annealing process are performed to fill the openings of a material layer disposed on the substrate with good gap filling performance. Further, the pre-cleaning process, the barrier layer deposition process, the interface layer deposition process, and the gap filling layer deposition process can be formed in a cluster processing system without breaking the vacuum (for example, without exposing the substrate in the cluster processing system to the atmosphere), so that the possibility of contamination and pollution from the atmosphere or the environment can be substantially eliminated. The high-pressure annealing process performed after the barrier layer, the interface layer, and the gap filling layer are formed can assist in strengthening the crystal grain structure of the gap filling layer, and thus can improve the film quality and purity of the gap filling layer.

[0015]

[0022] FIG. 1 is a cross-sectional view of an exemplary processing chamber 100 suitable for performing a substrate pre-cleaning process described further below. The processing chamber 100 can be configured to remove native oxides or surface contaminants from the substrate surface. The processing chamber 100 is particularly useful for performing a remote plasma surface cleaning process. The processing chamber 100 can be a Frontier™, PCxT Reactive Preclean™ (RPC), AKTIV Pre-Clean™, Siconi™ or Capa™ chamber available from Applied Materials, Inc. of Santa Clara, California. Note that other vacuum processing chambers available from other manufacturers can also be adapted for practicing the present disclosure.

[0016]

[0023] The processing chamber 100 includes a chamber body 112, a lid assembly 123, and a support assembly 180. The lid assembly 123 is disposed at the upper end of the chamber body 112, and the support assembly 180 is disposed at least partially within the chamber body 112.

[0017]

[0024] The chamber body 112 includes a slit valve opening 114 formed in its sidewall to provide access to the interior of the processing chamber 100. The slit valve opening 114 is selectively opened and closed to allow access to the interior of the chamber body 112 by a wafer handling robot (not shown).

[0018]

[0025] In one or more implementations, the chamber body 112 includes channels 115 formed therein for flowing a heat transfer fluid therethrough. The chamber body 112 may further include a liner 120 that surrounds the support assembly 180. The liner 120 is removable for servicing and cleaning. In one or more embodiments, the liner 120 includes one or more apertures 125 and pumping channels 129 formed therein that are in fluid communication with a vacuum system. The apertures 125 provide a flow path for gas to the pumping channels 129 that provide an outlet for gas within the processing chamber 100.

[0019]

[0026] The vacuum system may include a vacuum pump 130 and a throttle valve 132 for regulating the flow of gas through the processing chamber 100. The vacuum pump 130 is coupled to a vacuum port 131 disposed on the chamber body 112 and is thus in fluid communication with the pumping channels 129 formed within the liner 120.

[0020]

[0027] The remote plasma system 110 can process a halogen-containing precursor, such as a fluorine-containing precursor, which then moves through the gas inlet assembly 111. Inside the gas inlet assembly 111, two separate gas supply channels (the first channel 109 and the second channel 113) can be seen. The first channel 109 carries the gas passing through the remote plasma system 110 (RPS), and the second channel 113 bypasses the remote plasma system 110. Both channels 109, 113 can be used for the halogen-containing precursor. On the other hand, the first channel 109 can be used as the process gas, and the second channel 113 can be used as the treatment gas. The lid assembly (or conductive top) 123 and the perforated partition 153 (or showerhead) are shown with an insulating ring 124 sandwiched therebetween, whereby an AC potential can be applied to the lid assembly 123 with respect to the perforated partition 153. The AC potential impinges on the plasma in the chamber plasma region 121. The process gas can move through the first channel 109 into the chamber plasma region 121 and can be excited only by the plasma in the chamber plasma region 121 or in combination with the remote plasma system 110. When the process gas flows through the second channel 113, only the chamber plasma region 121 is used for excitation. The combination of the chamber plasma region 121 and / or the remote plasma system 110 can be referred to as the remote plasma system herein. The perforated partition (also called the showerhead) 153 separates the chamber plasma region 121 from the substrate processing region 141 below the perforated partition 153. The perforated partition 153 avoids the plasma present in the chamber plasma region 121 from directly exciting the gas in the substrate processing region 141, while enabling the excited species to move from the chamber plasma region 121 to the substrate processing region 141.

[0021]

[0028] The perforated partition 153 is positioned between the chamber plasma region 121 and the substrate processing region 141, allowing plasma emissions (precursor excitation derivatives or other gases) generated within the remote plasma system 110 and / or the chamber plasma region 121 to pass through a plurality of through-holes 156. The perforated partition 153 also has one or more hollow volumes 151 that are filled with precursors in the form of vapor or gas and enter the substrate processing region 141 through the through-holes 156 but do not enter the chamber plasma region 121 directly. To maintain a significant concentration of excited species penetrating from the chamber plasma region 121 to the substrate processing region 141, the length 126 of the through-holes 156 is limited as necessary and can be configured in different ways.

[0022]

[0029] As shown in FIG. 1, the perforated partition 153 can be configured to act as an ion suppressor. Alternatively, it may include a separate process chamber element (not shown) that suppresses the ion concentration moving into the substrate processing region 141. The lid assembly 123 and the perforated partition 153 can function as a first electrode and a second electrode, respectively, such that the lid assembly 123 and the perforated partition 153 receive different voltages. In these configurations, power (e.g., RF power) can be applied to the lid assembly 123, the perforated partition 153, or both. For example, power can be applied to the lid assembly 123 while the perforated partition 153 (functioning as an ion suppressor) is grounded. The substrate processing chamber 100 can include an RF generator that supplies power to the lid assembly 123 and / or the perforated partition 153 as needed. The voltage applied to the lid assembly 123 can promote a uniform distribution of the plasma within the chamber plasma region 121 (i.e., reduce local plasma). To enable the formation of plasma in the chamber plasma region 121, the insulating ring 124 can electrically insulate the lid assembly 123 from the perforated partition 153. The insulating ring 124 can be made of ceramic and may have a high breakdown voltage to avoid sparks. The portion of the substrate processing chamber 100 close to the capacitively coupled plasma component described above may further include a cooling unit (not shown) including one or more cooling fluid channels for cooling the surface exposed to the plasma with a circulating coolant (e.g., water).

[0023]

[0030] In the illustrated embodiment, the perforated partition 153 can distribute a process gas containing hydrogen and fluorine and / or plasma emissions of the process gas (through the through holes 156) during excitation by plasma in the chamber plasma region 121. In an embodiment, the process gas introduced into the remote plasma system 110 and / or the chamber plasma region 121 can contain fluorine (such as F2 or HF). The process gas can also contain a carrier gas such as helium, argon, hydrogen (H2), etc. The plasma emissions may include ionized or neutral derivatives of the process gas, and in this specification, they can also be referred to as radical-fluorine with reference to the atomic components of the introduced process gas.

[0024]

[0031] The through holes 156 are configured to suppress the outflow of ionized charged species from the chamber plasma region 121 while allowing non-charged neutral or radical species to pass through the perforated partition 153 and enter the substrate processing region 141. These non-charged species can include highly reactive species transported together with a low-reactive carrier gas through the through holes 156. As described above, the outflow of ion species through the through holes 156 can be reduced and, in some cases, completely suppressed. By controlling the amount of ion species passing through the perforated partition 153, the control of the mixed gas contacting the underlying wafer substrate is enhanced, and as a result, the control of the deposition and / or etching characteristics of the mixed gas is enhanced. For example, by adjusting the ion concentration of the mixed gas, the etching selectivity (e.g., the etching ratio of silicon nitride / silicon oxide: silicon) can be significantly changed.

[0025]

[0032] In an embodiment, the number of through-holes 156 may be from about 60 to about 2000. The through-holes 156 can have various shapes, but can most easily be made circular. Also, there is a free range in the selection of the cross-sectional shape of the through-holes, and they can be conical, cylindrical, or a combination of the two shapes. The through-holes 156 can be configured to control the passage of plasma-activated gas (i.e., ion species, radical species, and / or neutral species) through the perforated partition 153. For example, the aspect ratio of the holes (i.e., the diameter of the holes relative to the length) and / or the shape dimensions of the holes can be controlled so that the flow of ionized charged species in the activated gas passing through the perforated partition 153 is reduced. The through-holes 156 of the perforated partition 153 can include a tapered portion facing the chamber plasma region 121 and a cylindrical portion facing the substrate processing region 141. The cylindrical portion can be sized and proportioned to control the flow of ion species passing into the substrate processing region 141. As an additional means for controlling the flow of ion species through the perforated partition 153, an adjustable electrical bias can also be applied to the perforated partition 153.

[0026]

[0033] Alternatively, the through-hole 156 may have a smaller inner diameter (ID) toward the upper surface of the perforated partition 153 and a larger ID toward the bottom surface. Further, the bottom edge of the through-hole 156 may be chamfered to help evenly distribute the plasma emissions into the substrate processing region 141 when the plasma emissions exit the showerhead, and to promote the even distribution of the plasma emissions and the precursor gas. The smaller ID may be disposed at various locations along the through-hole 156, yet still enable the perforated partition 153 to reduce the ion density within the substrate processing region 141. The reduction in ion density is due to an increased number of collisions with the walls before entering the substrate processing region 141. Each collision increases the probability that the ions are neutralized by the gain or loss of electrons from the walls. Generally, the smaller ID of the through-hole 156 may be from about 0.2 mm to about 20 mm. In other embodiments, the smaller ID may be from about 1 mm to 6 mm, or from about 0.2 mm to about 5 mm. Further, the aspect ratio of the through-hole 156 (i.e., the smaller ID relative to the length of the hole) may be from about 1 to 20. The smaller ID of the through-hole 156 may be the smallest ID seen along the length of the through-hole. The cross-sectional shape of the through-hole 156 may generally be cylindrical, conical, or any combination thereof.

[0027]

[0034] The support assembly 180 may include a support member 185 for supporting a substrate (not shown in FIG. 1) to be processed within the chamber body 112. The support member 185 may be coupled to a lift mechanism 183 via a shaft 187 that extends through an opening 116 located at the center formed in the bottom surface of the chamber body 112. The lift mechanism 183 may be flexibly sealed to the chamber body 112 by a bellows 188 that prevents vacuum leakage around the shaft 187.

[0028]

[0035] The support member 185 may include a bore 192 formed through the support member 185 to accommodate a lift pin 193, one of which is shown in FIG. 1. Each lift pin 193 is made of ceramic or a ceramic-containing material and is used for substrate handling and transportation. The lift pin 193 is movable within its respective bore 192 when it engages an annular lift ring 195 disposed within the chamber body 112. The support assembly 180 may further include an edge ring 196 disposed around the support member 185.

[0029]

[0036] The temperature of the support assembly 180 may be controlled by a fluid circulating through a fluid channel 198 embedded in the body of the support member 185. In one or more implementation modes, the fluid channel 198 is in fluid connection with a heat transfer conduit 199 disposed through the shaft 187 of the support assembly 180. The fluid channel 198 is positioned relative to the support member 185 to provide uniform heat transfer to the substrate receiving surface of the support member 185. The fluid channel 198 and the heat transfer conduit 199 may carry a heat transfer fluid for either heating or cooling the support member 185. Any suitable heat transfer fluid such as water, nitrogen, ethylene glycol, or a mixture thereof may be used. The support assembly 180 may further include an embedded thermocouple (not shown) for monitoring the temperature of the support surface of the support member 185. For example, the signal from the thermocouple may be used in a feedback loop to control the temperature or flow rate of the fluid circulating through the fluid channel 198.

[0030]

[0037] The support member 185 may move vertically within the chamber body 112 so as to be able to control the distance between the support member 185 and the lid assembly 140. A sensor (not shown) may provide information regarding the position of the support member 185 within the processing chamber 100.

[0031]

[0038] A system controller (not shown) can be used to adjust the operation of the processing chamber 100. The system controller can operate under the control of a computer program stored in the memory of the controller or other memory sources. The computer program can include instructions that enable the pre-cleaning process described below to be executed in the processing chamber 100. For example, the computer program can instruct the sequence and timing of the process, the mixing of gases, the chamber pressure, the RF power level, the positioning of the susceptor, the opening and closing of the slit valve, the cooling of the wafer, and other parameters of a particular process.

[0032]

[0039] FIG. 2 is a schematic cross-sectional view of an embodiment of an atomic layer deposition (ALD) processing chamber 200. The ALD processing chamber 200 includes a gas supply device 230 adapted for periodic deposition such as ALD or chemical vapor deposition (CVD). As used herein, the terms ALD and CVD refer to the sequential introduction of reactants for depositing thin layers on a substrate structure. The sequential introduction of reactants can be repeated to deposit multiple thin layers to form a conformal layer of a desired thickness. Also, the chamber 200 can be adapted for other deposition techniques in conjunction with a lithography process.

[0033]

[0040] The chamber 200 includes a chamber body 229 having a bottom 234. A slit valve tunnel 233 formed through the chamber body 229 provides access for a robot (not shown) to transfer and retrieve a substrate 201, such as a semiconductor substrate or a glass substrate, of 200 mm, 300 mm, or 450 mm, from and to the chamber 200.

[0034]

[0041] The substrate support 292 is disposed in the chamber 200 and supports the substrate 201 during processing. The substrate support 292 is attached to the lift 214 to raise and lower the substrate support 292 and the substrate 201 disposed thereon. The lift plate 216 is connected to a lift plate actuator 218 that controls the raising of the lift plate 216. The lift plate 216 can move up and down to raise and lower pins 220 movably disposed through the substrate support 292. The pins 220 are used to raise and lower the substrate 201 on the surface of the substrate support 292. The substrate support 292 may include a vacuum chuck, an electrostatic chuck, or a clamping ring for fixing the substrate 201 to the surface of the substrate support 292 during processing.

[0035]

[0042] The substrate support 292 can be heated to heat the substrate 201 disposed thereon. For example, the substrate support 292 can be heated using an embedded heating element such as a resistance heater, or can be heated using radiant heat such as a heating lamp disposed above the substrate support 292. A purge ring 222 can be disposed on the substrate support 292 to define a purge channel 224 for supplying a purge gas to the peripheral portion of the substrate 201 to prevent deposition thereon.

[0036]

[0043] The gas supply device 230 is disposed at the upper part of the chamber body 229 and supplies gases such as process gas and / or purge gas to the chamber 200. The pumping system 278 communicates with the pumping channel 279, discharges any desired gas from the chamber 200, and helps maintain a desired pressure or a desired pressure range inside the pumping zone 266 of the chamber 200.

[0037]

[0044] In one embodiment, the gas supply device 230 includes a chamber lid 232. The chamber lid 232 includes an extension channel 237 extending from the central portion of the chamber lid 232 and a bottom surface 260 extending from the extension channel 237 to the peripheral portion of the chamber lid 232. The bottom surface 260 is sized and shaped to substantially cover the substrate 201 disposed on the substrate support 292. The chamber lid 232 may have a choke 262 at the peripheral portion of the chamber lid 232 adjacent to the periphery of the substrate 201. The cap portion 272 includes a part of the extension channel 237 and gas inlets 236A, 236B. The extension channel 237 has gas inlets 236A, 236B for providing gas flow from two similar valves 242A, 242B. The gas flows from the valves 242A, 242B may be provided together and / or separately.

[0038]

[0045] In one configuration, valves 242A and 242B are coupled to separate reaction gas sources but are coupled to the same purge gas source. For example, valve 242A is coupled to reaction gas source 238, valve 242B is coupled to reaction gas source 239, and both valves 242A and 242B are coupled to purge gas source 240. Each of valves 242A and 242B includes supply lines 243A and 243B having valve seat assemblies 244A and 244B, and purge lines 245A and 245B having valve seat assemblies 246A and 246B. Supply lines 243A and 243B communicate with reaction gas sources 238 and 239 and communicate with gas inlets 237A and 237B of expansion channel 290. Valve seat assemblies 244A and 244B of supply lines 243A and 243B control the flow of reaction gas from reaction gas sources 238 and 239 to expansion channel 290. Purge lines 245A and 245B communicate with purge gas source 240 and intersect supply lines 243A and 243B downstream of valve seat assemblies 244A and 244B of supply lines 243A and 243B. Valve seat assemblies 246A and 246B of purge lines 245A and 245B control the flow of purge gas from purge gas source 240 to supply lines 243A and 243B. If a carrier gas is used to supply reaction gas from reaction gas sources 238 and 239, the same gas can be used as both the carrier gas and the purge gas (i.e., argon gas can be used as both the carrier gas and the purge gas).

[0039]

[0046] Each valve 242A, 242B may be a zero dead volume valve that allows for flushing of the reaction gas from the supply lines 243A, 243B when the valve seat assemblies 244A, 244B of the valves are closed. For example, the purge lines 245A, 245B may be positioned adjacent to the valve seat assemblies 244A, 244B of the supply lines 243A, 243B. When the valve seat assemblies 244A, 244B are closed, the purge lines 245A, 245B may supply purge gas to flush the supply lines 243A, 243B. In the illustrated embodiment, the purge lines 245A, 245B are arranged at a slight distance from the valve seat assemblies 244A, 244B of the supply lines 243A, 243B so that purge gas is not sent directly to the valve seat assemblies 244A, 244B when open. The zero dead volume valve used herein is defined as a valve having a very small dead volume (i.e., not necessarily zero dead volume). Each valve 242A, 242B may be adapted to provide a composite gas flow and / or a separated gas flow of the reaction gas from the sources 238, 239 and the purge gas from the source 240. Pulses of the purge gas may be provided by opening and closing the diaphragm of the valve seat assembly 246A of the purge line 245A. Pulses of the reaction gas from the reaction gas source 238 may be provided by opening and closing the valve seat assembly 244A of the supply line 243A.

[0040]

[0047] The control unit 280 can be coupled to the chamber 200 to control processing conditions. The control unit 280 includes a central processing unit (CPU) 282, support circuits 284, and a memory 286 that includes associated control software 283. The control unit 280 can be one of any form of general-purpose computer processor that can be used in an industrial environment to control various chambers and sub-processors. The CPU 282 can use any suitable memory 186, such as random access memory, read-only memory, floppy disk drive, compact disk drive, hard disk, or any other form of local or remote digital storage. To support the chamber 200, various support circuits can be coupled to the CPU 282. The control unit 280 can be coupled to another controller located adjacent to individual chamber components, such as programmable logic controllers 248A, 248B of valves 242A, 242B. Bidirectional communication between the control unit 280 and various other components of the chamber 200 is processed through a number of signal cables collectively referred to as a signal bus 288, some of which are illustrated in FIG. 2. In addition to controlling process gases and purge gases from gas sources 238, 239, 240 and from programmable logic controllers 248A, 248B of valves 242A, 242B, the control unit 280 can be configured to undertake automatic control of other activities used in substrate processing, such as substrate transport, temperature control, chamber evacuation, some of which are described elsewhere in this document.

[0041]

[0048] FIG. 3 is a cross-sectional view of a processing chamber 300 suitable for performing a plasma deposition process (e.g., plasma CVD or metal organic CVD) that can be utilized as a semiconductor interconnect structure for semiconductor device manufacturing. The processing chamber 300 may be a suitably adapted CENTURA®, PRODUCER® SE or PRODUCER® GT or PRODUCER® XP processing system available from Applied Materials, Inc. of Santa Clara, Calif. Other processing systems, including those manufactured by other manufacturers, are contemplated to be able to benefit from the embodiments described herein.

[0042]

[0049] The processing chamber 300 includes a chamber body 351. The chamber body 351 includes a lid 325, sidewalls 303, and a bottom wall 322 that define an internal volume 326.

[0043]

[0050] A substrate support pedestal 350 is provided in the internal volume 326 of the chamber body 351. The pedestal 350 can be made from aluminum, ceramic, aluminum nitride, and other suitable materials. In one embodiment, the pedestal 350 is made of a ceramic material such as aluminum nitride, which is a material suitable for use in a high temperature environment such as a plasma process environment without causing thermal damage to the pedestal 350. Note that the pedestal 350 can be moved vertically within the chamber body 351 using a lift mechanism (not shown).

[0044]

[0051] The pedestal 350 may include an embedded heater element 370 suitable for controlling the temperature of the substrate 301 supported on the pedestal 350. In one embodiment, the pedestal 350 may be resistively heated by applying a current from the power supply 306 to the heater element 370. In one embodiment, the heater element 370 may be made of nickel-chromium wire encapsulated in a nickel-iron-chromium alloy (e.g., INCOLOY®) sheath tube. The current supplied from the power supply 306 is adjusted by the controller 310 to control the heat generated by the heater element 370, whereby the substrate 301 and the pedestal 350 are maintained at a substantially constant temperature within any suitable temperature range during film deposition. In another embodiment, the pedestal may be maintained at room temperature as needed. In yet another embodiment, the pedestal 350 may also include a chiller (not shown) as needed to cool the pedestal 350 in a range lower than room temperature as needed. The supplied current may be adjusted to selectively control the temperature of the pedestal 350 from about 20°C to about 700°C.

[0045]

[0052] A temperature sensor 372 such as a thermocouple can be embedded in the substrate support pedestal 350 to monitor the temperature of the pedestal 350 in a conventional manner. The measured temperature is used by the controller 310 to control the power supplied to the heater element 370 to maintain the substrate at the desired temperature.

[0046]

[0053] The pedestal 350 generally includes a plurality of lift pins (not shown) disposed therethrough and configured to lift the substrate 301 from the pedestal 350 to facilitate replacement of the substrate 301 using a robot (not shown) in a conventional manner.

[0047]

[0054] The pedestal 350 includes at least one electrode 392 for holding the substrate 301 on the pedestal 350. The electrode 392 is driven by a chucking power supply 308 to generate an electrostatic force for holding the substrate 301 on the pedestal surface, as is well known in the art. Alternatively, the substrate 301 can be held on the pedestal 350 by a clamp, vacuum, or gravity.

[0048]

[0055] In one embodiment, the pedestal 350 is configured as a cathode having an electrode 392 embedded therein and coupled to at least one RF bias power supply shown as two RF bias power supplies 384, 386 in FIG. 3. In the example shown in FIG. 3, two RF bias power supplies 384, 386 are shown, but it should be noted that the number of RF bias power supplies can be any number as required. The RF bias power supplies 384, 386 are coupled between the electrode 392 disposed on the pedestal 350 and another electrode such as the gas distribution plate 342 or the lid 325 of the processing chamber 300. The RF bias power supplies 384, 386 excite and sustain a plasma discharge formed from the gas disposed in the processing region of the processing chamber 300.

[0049]

[0056] In the embodiment shown in FIG. 3, the dual RF bias power supplies 384, 386 are coupled to the electrode 392 disposed on the pedestal 350 through a matching circuit 304. The signals generated by the RF bias power supplies 384, 386 are sent in a single supply to the pedestal 350 through the matching circuit 304 to ionize the mixed gas provided to the processing chamber 300, thereby providing the ion energy required to perform a deposition or other plasma process. The RF bias power supplies 384, 386 can generally generate RF signals having a frequency from about 50 kHz to about 200 MHz and a power from about 0 watts to about 5000 watts.

[0050]

[0057] It should be noted that in one example shown herein, the plasma is only turned on when a cleaning process is performed in the processing chamber 300 as required.

[0051]

[0058] The vacuum pump 302 is coupled to a port formed at the bottom 322 of the chamber body 351. The vacuum pump 302 is used to maintain a desired gas pressure in the chamber body 351. Further, the vacuum pump 302 discharges the processed gas and process by-products from the chamber body 351.

[0052]

[0059] The processing chamber 300 includes one or more gas supply passages 344 coupled through the lid 325 of the processing chamber 300. The gas supply passage 344 and the vacuum pump 302 are positioned at opposite ends of the processing chamber 300 so as to induce a laminar flow within the internal volume 326 to minimize particulate contamination.

[0053]

[0060] The gas supply passage 344 is coupled to a gas panel 393 through a remote plasma source (RPS) 348 and supplies a mixed gas to the internal volume 326. In one embodiment, the mixed gas supplied through the gas supply passage 344 may be further supplied through a gas distribution plate 342 disposed below the gas supply passage 344. In one example, the gas distribution plate 342 having a plurality of apertures 343 is coupled to the lid 325 of the chamber body 351 above the pedestal 350. The apertures 343 of the gas distribution plate 342 are utilized to introduce the process gas from the gas panel 393 into the chamber body 351. The apertures 343 may have different sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various process gases for different process requirements. Plasma is formed from the process mixed gas exiting the gas distribution plate 342, promoting the thermal decomposition of the process gas that results in the deposition of material on the surface 391 of the substrate 301.

[0054]

[0061] The gas distribution plate 342 and the substrate support pedestal 350 can form a pair of electrodes spaced apart within the internal volume 326. One or more RF sources 347 supply a bias potential to the gas distribution plate 342 through the matching network 345, facilitating the generation of plasma between the gas distribution plate 342 and the pedestal 350. Alternatively, the RF source 347 and the matching network 345 can be coupled to the gas distribution plate 342, the substrate support pedestal 350, or both the gas distribution plate 342 and the substrate support pedestal 350, or can be coupled to an antenna (not shown) disposed outside the chamber body 351. In one embodiment, the RF source 347 can supply from about 10 watts to about 3000 watts at a frequency from about 30 kHz to about 13.6 MHz. Alternatively, the RF source 347 can be a microwave generator that supplies microwave power to the gas distribution plate 342 that aids in the generation of plasma within the internal volume 326.

[0055]

[0062] In one embodiment, a remote plasma source (RPS) 348 can instead be coupled to the gas supply passage 344 to assist in the formation of plasma from the gas supplied into the internal volume 326 from the gas panel 393. The remote plasma source 348 supplies plasma formed from the mixed gas supplied by the gas panel 393 to the processing chamber 300.

[0056]

[0063] The controller 310 includes a central processing unit (CPU) 312, a memory 316, and support circuits 314 that are used to control the process sequence and regulate the gas flow from the gas panel 393. The CPU 312 may be any form of general-purpose computer processor that can be used in an industrial environment. Software routines may be stored in the memory 316 such as random access memory, read-only memory, floppy, or hard disk drives, or other forms of digital storage. The support circuits 314 are conventionally coupled to the CPU 312 and may include a cache, a clock circuit, an input / output system, a power supply, etc. The bidirectional communication between the controller 310 and the various components of the processing chamber 300 is processed through a number of signal cables collectively referred to as the signal bus 318, some of which are illustrated in FIG. 3.

[0057]

[0064] FIG. 4 is a simplified front cross-sectional view of a single-substrate processing chamber 400 for a high-pressure annealing process of a single substrate 401. The single-substrate processing chamber 400 has a body 410 having an outer surface 412 and an inner surface 413 that enclose an internal volume 425. In some embodiments such as FIG. 4, the body 410 has an annular cross-section, but in other embodiments, the cross-section of the body 410 may be rectangular or any closed shape. The outer surface 412 of the body 410 may be made of corrosion-resistant steel (CRS) such as stainless steel, but is not limited thereto. One or more thermal shields 415 are disposed on the inner surface 413 of the body 410 to prevent heat loss from the single-substrate processing chamber 400 to the external environment. The inner surface 413 of the body 410 and the thermal shields 415 may be made of nickel-based steel alloys that exhibit high corrosion resistance such as HASTELLOY®, ICONEL®, and MONEL®, but are not limited thereto.

[0058]

[0065] The substrate support 430 is disposed within the internal volume 425. The substrate support 430 has a stem 434 and a substrate support member 432 held by the stem 434. The stem 434 passes through a passage 422 formed through the chamber body 410. A rod 439 connected to an actuator 438 passes through a second passage 423 formed through the chamber body 410. The rod 439 is coupled to a plate 435 having an aperture 436 that houses the stem 434 of the substrate support 430. A lift pin 437 is connected to the substrate support member 432. The actuator 438 operates the rod 439 to move the plate 435 up and down to connect and disconnect from the lift pin 437. When the lift pin 437 moves up and down, the substrate support member 432 moves up and down within the internal volume 425 of the chamber 400. The substrate support member 432 has a resistance heating element 431 embedded in the center thereof. A power source 433 is configured to supply power to the resistance heating element 431. The operation of not only the power source 433 but also the actuator 438 is controlled by a controller 480.

[0059]

[0066] The single-substrate processing chamber 400 has an opening 411 in the main body 410 through which one or more substrates 401 can be loaded and unloaded with respect to a substrate support 430 disposed in the internal volume 425. The opening 411 forms a tunnel 421 in the main body 410. The slit valve 418 is configured to sealably close the tunnel 421 such that access to the opening 411 and the internal volume 425 is possible only when the slit valve 418 is open. The high-pressure seal 427 is used to seal the slit valve 418 to the main body 410 in order to seal the internal volume 425 for processing. The high-pressure seal 427 may be made of a polymer, such as a fluoropolymer such as perfluoroelastomer and polytetrafluoroethylene (PTFE), but is not limited thereto. The high-pressure seal 427 may further include a spring member for biasing the seal to improve the sealing performance. A cooling channel 424 is disposed in the tunnel 421 adjacent to the high-pressure seal 427 in order to maintain the high-pressure seal 427 below its maximum safe operating temperature during processing. A coolant from a coolant source 426, such as an inert, dielectric, and high-performance heat transfer fluid, may circulate within the cooling channel 424. The flow of coolant from the coolant source 426 is controlled by a controller 480 through feedback received from a temperature sensor 416 or a flow sensor (not shown). An annular thermal choke 419 is formed around the tunnel 421 to prevent the flow of heat from the internal volume 425 through the opening 411 when the slit valve 418 is open.

[0060]

[0067] The single substrate processing chamber 400 has a port 417 that penetrates the body 410, and this port 417 is fluidly connected to a gas panel 450, a condenser 460, and a fluid circuit 490 that connects the port 417. The fluid circuit 490 has a gas conduit 492, a supply conduit 457, an inlet isolation valve 455, an exhaust conduit 463, and an outlet isolation valve 465. A number of heaters 496, 458, 452, 454, 464, 466 are joined to different parts of the fluid circuit 490. A number of temperature sensors 451, 453, 459, 467, 469 are also arranged at different parts of the fluid circuit 490 to perform temperature measurements and transmit the information to the controller 480. The controller 480 uses the temperature measurement information to control the operation of the heaters 452, 454, 458, 496, 464, and 466 so that the temperature of the fluid circuit 490 is maintained at a temperature exceeding the condensation point of the processing fluid arranged in the fluid circuit 490 and the internal volume 425.

[0061]

[0068] The gas panel 450 is configured to supply a pressurized processing fluid to the internal volume 425. The pressure of the processing fluid introduced into the internal volume 425 is monitored by a pressure sensor 414 coupled to the body 410. The condenser 460 is fluidly coupled to a cooling fluid source (not shown) and is configured to condense the vapor-phase processing fluid exiting the internal volume 425 through the gas conduit 492. The condensed processing fluid is then removed by a pump 476. One or more heaters 440 are arranged in the body 410 and are configured to heat the internal volume 425 within the single substrate processing chamber 400. The heaters 440, 452, 454, 458, 496, 464, and 466 maintain the processing fluid within the fluid circuit 490 in the vapor phase while the outlet isolation valve 465 to the condenser 460 is open to prevent condensation within the fluid circuit.

[0062]

[0069] The controller 480 controls the operation of the single-substrate processing chamber 400. The controller 480 controls the operations of the gas panel 450, the condenser 460, the pump 470, the inlet isolation valve 455, the outlet isolation valve 465, and the power supplies 433, 445. Further, the controller 480 is communicatively connected to the temperature sensor 416, the pressure sensor 414, the actuator 438, the coolant source 426, and the temperature reading devices 456, 462.

[0063]

[0070] The processing fluid may include an oxygen-containing gas and / or a nitrogen-containing gas, and / or a gas or vapor of a chalcogen or tellurium (such as S, Se, Te, etc.), for example, oxygen, dry steam, water, hydrogen peroxide, hydrogen, deuterium, tritium, ammonia, S vapor, Se vapor, H2S, H2Se, etc. The processing fluid may react with the metal material on the substrate to purify the metal or form a metal oxynitride, a metal oxide, a metal oxychalcogenide, or a metal chalcogenide.

[0064]

[0071] During the processing of the substrate 401, the environment of the internal volume 425 is maintained at a temperature and pressure that keep the processing fluid in the high-pressure region in the gas phase. Such pressure and temperature are selected based on the composition of the processing fluid. In the case of steam, the temperature and pressure are maintained at conditions that keep the steam in the dry steam state. In one embodiment, the internal volume 425 is pressurized to a pressure higher than atmospheric pressure, for example, higher than about 5 bar. In another embodiment, the internal volume 425 is pressurized to a pressure of about 10 bar to about 100 bar, for example, about 20 bar to about 80 bar. In another embodiment, the internal volume 425 is pressurized to a maximum pressure of about 100 bar. During processing, the internal volume 425 is also maintained at a high temperature, for example, a temperature exceeding about 425°C such as about 300°C to about 500°C (limited by the thermal budget of the substrate 401 disposed on the substrate support member 432).

[0065]

[0072] FIG. 5 is a schematic top view of an exemplary cluster processing system 500 that includes one or more of processing chambers 100, 200, 300, 400 incorporated and integrated therein. In one embodiment, cluster processing system 500 may be a CENTURA® or ENDURA® integrated processing system commercially available from Applied Materials, Inc. located in Santa Clara, California. Other processing systems (including those from other manufacturers) are contemplated to be adaptable to benefit from the present disclosure.

[0066]

[0073] Cluster processing system 500 includes a vacuum-tight processing platform 504, a factory interface 502, and a system controller 544. Platform 504 includes a plurality of processing chambers 100, 200, 300, 400 and at least one load lock chamber 522 coupled to a vacuum substrate transfer chamber 536. Two load lock chambers 522 are shown in FIG. 5. Factory interface 502 is coupled to transfer chamber 536 by load lock chamber 522.

[0067]

[0074] In one embodiment, factory interface 502 includes at least one docking station 508 and at least one factory interface robot 514 to facilitate transfer of substrates. Docking station 508 is configured to receive one or more front opening unified pods (FOUPs). Two FOUPs 506A - B are illustrated in the embodiment of FIG. 5. Factory interface robot 514 having blades 516 disposed at one end thereof is configured to transfer substrates from factory interface 502 to processing platform 504 through load lock chamber 522 for processing. Optionally, one or more measurement stations 518 may be connected to terminals 526 of factory interface 502 to facilitate measurement of substrates from FOUPS 506A - B.

[0068]

[0075] Each load lock chamber 522 has a first port coupled to the factory interface 502 and a second port coupled to the transfer chamber 536. The load lock chamber 522 is coupled to a pressure control system (not shown) that pumps down and vents the load lock chamber 522 to facilitate passage of the substrate between the vacuum environment of the transfer chamber 536 and the substantially ambient (e.g., atmospheric) environment of the factory interface 502.

[0069]

[0076] The transfer chamber 536 has a vacuum robot 530 disposed therein. The vacuum robot 530 has blades 534 capable of transferring the substrate 524 between the load lock chamber 522, the measurement system 510, and the processing chambers 100, 200, 300, 400.

[0070]

[0077] In one embodiment of the cluster processing system 500, the cluster processing system 500 may include one or more processing chambers 100, 200, 300, 400, which may be deposition chambers (e.g., physical vapor deposition chambers, chemical vapor deposition, atomic layer deposition, or other deposition chambers), annealing chambers (e.g., high pressure annealing chambers, RTP chambers, laser annealing chambers), etching chambers, cleaning chambers, pre - cleaning chambers, curing chambers, lithography exposure chambers, or other similar types of semiconductor processing chambers. In some embodiments of the cluster processing system 500, at least one of one or more of the processing chambers 100, 200, 300, 400, the transfer chamber 536, the factory interface 502, and / or the load lock chamber 522 is present.

[0071]

[0078] The system controller 544 is coupled to the cluster processing system 500. The system controller 544, which may include or be included within the computing device 501, controls the operation of the cluster processing system 500 using direct control of the processing chambers 100, 200, 300, 400 of the cluster processing system 500. Alternatively, the system controller 544 may control the processing chambers 100, 200, 300, 400 and the computer (or controller) associated with the cluster processing system 500. In the process, the system controller 544 also enables data collection and feedback from each chamber to optimize the performance of the cluster processing system 500.

[0072]

[0079] Similar to the computing device 501 described above, the system controller 544 generally includes a central processing unit (CPU) 538, a memory 540, and support circuitry 542. The CPU 538 may be one of any form of general-purpose computer processor that can be used in an industrial environment. The support circuitry 542 is conventionally coupled to the CPU 538 and may include a cache, a clock circuit, an input / output subsystem, a power supply, and the like. Software routines convert the CPU 538 into a special-purpose computer (controller) 544. Also, the software routines may be stored and / or executed by a second controller (not shown) located remotely from the cluster processing system 500.

[0073]

[0080] FIG. 6 is a flow diagram of an embodiment for forming an interconnect structure such as a barrier layer (or liner layer), an interface layer, and a gap filling material formed in an opening formed in a material layer for a semiconductor structure. Note that the barrier layer referred to in this specification can be replaced with a liner layer as needed. The structure can be any suitable structure formed on a semiconductor substrate, for example, a device or channel structure having conductive and non-conductive regions, a fin structure, a gate structure, a contact structure, a front-end structure, a back-end structure, or any other suitable structure used for manufacturing a semiconductor device or the like. FIGS. 7A-7D are schematic cross-sectional views of a portion of a substrate 702 corresponding to various stages of process 600. Process 600 can be used to form a contact or back-end interconnect structure that requires a gap filling layer formed in an opening having a small dimension (e.g., the width of a feature) of less than 20 nm.

[0074]

[0081] Process 600 begins in step 602 by providing a substrate, such as substrate 702 shown in FIG. 7A, for processing. In one embodiment, substrate 702 can have an interconnect structure 750 formed thereon. Substrate 702 can have a substantially planar surface, a non-planar surface, or a substantially planar surface having structures formed thereon. The embodiment shown in FIGS. 7A-7D can be a portion of a surface, such as bottom surface 822 of substrate 702, exposed by an opening 850 formed in a material layer 802, as further shown in FIG. 8. Process 600 can assist in forming multiple layers (e.g., two or more layers) in an opening 850 having a small dimension such as less than 20 nm. Thus, the multiple layers can provide a high gap filling capability to fill the opening 850 with a minimum of defects such as voids, seams, or gaps.

[0075]

[0082] The substrate 702 shown in FIG. 8 includes a structure or material layer 802 formed on the substrate 702. An opening 850 is formed in the material layer 802. In one embodiment, the substrate 702 may be made of materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon on insulator (SOI) wafers and patterned or unpatterned wafers, silicon oxide doped with carbon, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, etc. The substrate 702 can have various dimensions, such as wafers with a diameter of 200 mm, 300 mm, or 450 mm, and rectangular or square panels. Unless otherwise specified, the embodiments and examples described herein are implemented on substrates with a diameter of 300 mm or 450 mm.

[0076]

[0083] In one embodiment, the material layer 802 may be a dielectric layer. The material layer 802 has an opening 850 that exposes a portion (e.g., the bottom surface) 822 of the substrate 702. The opening 850 described herein may include trenches, vias, holes, apertures, etc. In one embodiment, the material layer 802 may be a dielectric material such as a silicon-containing material, a carbon-containing material, or other suitable materials. Suitable silicon-containing materials include silicon, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. Suitable carbon-containing materials include silicon carbide, silicon oxycarbide, amorphous carbon, etc. In the exemplary embodiment illustrated herein, the material layer 802 is a SiOC layer.

[0077]

[0084] In step 604, the substrate 702 is then transferred to a processing chamber, such as the pre-cleaning chamber 100 shown in FIG. 1, which can be incorporated into the cluster processing system 500 shown in FIG. 5, to perform a pre-cleaning process on the substrate 702. It should be noted that the pre-cleaning process in step 604 is an option based on the surface condition of the substrate. In some embodiments, the pre-cleaning process performed in step 604 may assist in removing surface contamination or surface native oxide from the substrate surface. In some embodiments, the pre-cleaning step may not be necessary.

[0078]

[0085] In one example, the pre-cleaning process can be performed by supplying a pre-cleaning mixed gas containing a hydrogen-containing gas with or without an inert gas such as Ar or He gas. In one example, a hydrogen-containing gas may be supplied into the pre-cleaning mixed gas, and an inert gas may also be optionally supplied during the pre-cleaning process. Suitable examples of the hydrogen-containing gas include H2, H2O, H2O2, NH3, etc. Also, suitable examples of the inert gas can be supplied into the pre-cleaning mixed gas as needed. Examples of the inert gas supplied into the mixed gas include Ar, He, Ne, Kr, Xe, etc. In a specific example, the pre-cleaning mixed gas contains H2.

[0079]

[0086] While supplying the pre-cleaning mixed gas, the substrate support temperature can be controlled to maintain the substrate at a temperature higher than 250°C, such as higher than 300°C, for example, from 300°C to about 600°C, for example, 400°C. Relatively high substrate temperature control during the pre-cleaning process is considered to assist in removing surface contamination from the substrate surface and / or the substrate surface native oxide. To remove surface contaminants and native oxide, a remote plasma source is formed in the chamber plasma region 121 from the pre-cleaning mixed gas, and the pre-cleaning mixed gas is supplied to the substrate processing region 141 through the chamber plasma region 121. The amount of gas introduced into the processing chamber 100 from the pre-cleaning mixed gas can be varied and adjusted, for example, corresponding to the thickness of the native oxide or the amount of surface contaminants to be removed.

[0080]

[0087] Remote plasma power is supplied from a power source to form plasma in the chamber plasma region 121 from the pre-cleaning mixed gas supplied in process 604. The plasma remotely generated in the chamber plasma region 121 during the pre-cleaning process in process 604 dissociates the etching solution to form a relatively mild and gentle etching solution so as to slowly, gently, and gradually etch surface contaminants and native oxides (e.g., an isotropic etching process). The remote plasma process provides good control for interface cleaning and promotes high etching selectivity.

[0081]

[0088] In process 606, as shown in FIG. 7A, a first deposition process is performed to form a barrier layer 704 (e.g., a liner layer) on substrate 702. The deposition process may be an atomic layer deposition (ALD) process performed in the ALD processing chamber 200 shown in FIG. 2, or a chemical vapor deposition (CVD) process performed in the CVD processing chamber 300 shown in FIG. 3, or another suitable processing chamber incorporated in a cluster processing system 500 such as a PVD Endura® system. In one embodiment, the barrier layer 704 is formed to prevent metal diffusion from a conductive layer to be formed thereon later to a surrounding dielectric layer such as the material layer 802 in the vicinity. Thus, the barrier layer 704 is selected to have good barrier properties to block ion diffusion therethrough during subsequent thermal cycles and processes. In another embodiment, the barrier layer 704 is formed to promote the nucleation of metal elements formed subsequent to the material layer 802. Thus, the barrier layer 704 can be considered as a liner. In one embodiment, the barrier layer (and / or liner layer) 704 is made of a metal-containing layer such as a Ta-containing layer, a Ti-containing layer, a Co-containing material, a Ru-containing material, a Mn-containing material, etc. In the embodiment illustrated herein, the barrier layer 704 is TaN, TiN, TaON, TiON, a Ti alloy, or a Ta alloy.

[0082]

[0089] In one embodiment, the first deposition process can be carried out by supplying a deposition mixed gas containing a metal-containing precursor into the processing chamber 200. Suitable examples of the metal-containing precursor include a Ta-containing gas or a Ti-containing gas, etc. Also, some reactive gases can be supplied into the deposition mixed gas. Suitable examples of the reactive gases include N2, NH3, O2, N2O, NO2, etc. Also, if necessary, other purge gases such as Ar, He, N2, N2O, NO2, NH3, etc., and / or dilution gases can also be supplied together with the deposition mixed gas.

[0083]

[0090] In one embodiment, the barrier layer 704 is a TaN, TiN, TaO, TiO, TaON, or TiON layer.

[0084]

[0091] In the optional step 607, a plasma treatment process can be carried out to treat the barrier layer 704 (or the liner layer). The plasma treatment process is considered to reduce the surface roughness of the deposited barrier layer 704 by reducing impurities and densifying the barrier layer 704. Exemplary plasma-forming gases for the plasma treatment process in step 607 include hydrogen (H2), nitrogen (N2), ammonia (NH3), and combinations thereof. During the plasma treatment process, several process parameters are also adjusted. In one implementation, the process pressure is controlled from about 0.1 Torr to about 100 Torr (for example, from about 0.1 Torr to about 80 Torr; from about 1 Torr to about 20 Torr or from about 7 Torr to about 30 Torr). In one implementation, the processing temperature is from about 100 °C to about 900 °C (for example, from about 125 °C to about 350 °C, for example, from about 200 °C to about 300 °C, for example, from about 250 °C to about 340 °C). The RF power can be controlled from about 100 watts to about 800 watts, for example, about 400 watts. The plasma-forming gas such as H2 gas can be supplied from about 3000 sccm to about 5000 sccm, for example, about 4000 sccm. The H2 gas supplied from the substrate edge / substrate bottom can be controlled from about 200 sccm to about 1000 sccm. Also, argon gas can be supplied from about 200 sccm to about 1000 sccm from the substrate edge / substrate bottom.

[0085]

[0092] In operation 608, as shown in FIG. 7B, a second deposition process is performed to form an interface layer 706 on the barrier layer 704. The interface layer 706 may also be a metal-containing layer formed by a CVD process, an ALD process, or a PVD process. The interface layer 706 provides good interfacial adhesion that bridges the gap-fill layer 708 to the barrier layer 704 (as shown in FIG. 7C), thereby enhancing and promoting high interfacial adhesion.

[0086]

[0093] In one embodiment, the interface layer 706 may be a tungsten-containing material, a nickel-containing material, an aluminum-containing material, a ruthenium-containing material, or a manganese-containing material. In one embodiment, the interface layer 706 is a ruthenium-containing layer.

[0087]

[0094] In one example, the interface layer 706 has a thickness of from about 0.3 nm to about 3 nm and is deposited by a metalorganic chemical vapor deposition (MOCVD) process such as in the CVD processing chamber 300 shown in FIG. 3.

[0088]

[0095] In operation 610, as shown in FIG. 7C, a gap-fill deposition process is performed to form the gap-fill layer 708. As further shown in the example of FIG. 8, the gap-fill layer 708 fills the space defined in the opening 850 with a minimum of defects such as a minimum of seams or voids and is formed in the opening 850. In one example, the gap-fill layer 708 is a Co layer or a Co alloy. In one example, the gap-fill layer 708 is formed by cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), etc. In the example shown in this document, the gap-fill layer 708 is formed by a CVD process.

[0089]

[0096] The CVD process executed in step 610 includes a plurality of sub-steps (for example, different processes along the CVD process). For example, the CVD process for forming the gap-fill layer 708 in step 610 may include at least one cycle of a deposition process and a plasma treatment. The number of cycles can be repeated any number of times until the desired thickness of the gap-fill layer 708 is achieved. Approximately, each cycle of the deposition process and the plasma treatment process can form a thickness of about 20 Å to about 200 Å, for example, a portion of the gap-fill layer 708 on the interface layer 706. In each cycle, the deposition process is executed for about 60 seconds to about 600 seconds, and then the plasma treatment process can be executed for a period of about 10 seconds to about 120 seconds.

[0090]

[0097] In one embodiment, the deposition process can be executed by supplying a deposition precursor mixed gas containing a cobalt precursor. The deposition precursor mixed gas can be supplied together with a reactive mixed gas as needed. The reactive mixed gas can be hydrogen gas (H2) or NH3 gas as needed. Suitable cobalt precursors can include, but are not limited to, cobalt carbonyl complexes, cobalt amidinate compounds, cobaltocene compounds, cobalt dienyl complexes, cobalt nitrosyl complexes, their derivatives, their complexes, their plasmas, or combinations thereof. In one embodiment, examples of cobalt precursors that can be used herein include dicobalt hexacarbonyl butylacetylene (CCTBA, (CO)6Co2(HC≡C t Bu)), dicobalt hexacarbonyl methylbutylacetylene ((CO)6Co2(MeC≡C tExamples include dicobalt hexacarbonyl phenylacetylene ((CO)6Co2(HC≡CPh)). Also included are hexacarbonyl methylphenylacetylene ((CO)6Co2(MeC≡CPh)), dicobalt hexacarbonyl methylacetylene ((CO)6Co2(HC≡CMe)), dicobalt hexacarbonyl dimethylacetylene ((CO)6Co2(MeC≡CMe)), their derivatives, their complexes, their plasmas, or combinations thereof. Other exemplary cobalt carbonyl complexes include cyclopentadienylcobalt bis(carbonyl) (CpCo(CO)2), tricarbonylallylcobalt ((CO)3Co(CH2CH=CH2)), their derivatives, their complexes, their plasmas, or combinations thereof. One specific example of a cobalt precursor used herein is dicobalt hexacarbonyl butylacetylene (CCTBA, (CO)6Co2(HC≡C t Bu)).

[0091]

[0098] After the deposition process, a plasma treatment process is performed in the same chamber. The plasma treatment process can assist in densifying portions of the gap-fill layer 708 formed on the substrate 702 so as to eliminate defects such as voids, air, and impurities from the gap-fill layer 708. The plasma treatment process is performed in the same processing chamber as the processing chamber in which the deposition of the gap-fill layer is performed, such as the plasma treatment chamber 300 shown in FIG. 3. Similarly, the plasma treatment process can be performed in other suitable plasma treatment chambers incorporated in the cluster processing system 500 shown in FIG. 5 in which the plasma treatment chamber 300 is also incorporated. Alternatively, the plasma treatment process can be performed in other independent processing chambers not incorporated in the cluster processing system 500 in which the plasma treatment chamber 300 is incorporated. In one embodiment, the plasma treatment process is performed globally and ubiquitously to remove loose bonding structures, voids, or air from the gap-fill layer 708 formed over the entire substrate 702.

[0092]

[0099] In one embodiment, the plasma treatment process is performed in a processing chamber 300 in which the gap fill layer 708 is formed. The plasma treatment process uses an RF source or bias power applied to either or both of the showerhead assembly or the substrate support assembly to generate plasma. RF source power, bias power, or a remote plasma source is applied to generate plasma in the presence of a process gas mixture.

[0093]

[0100] In one example, the process gas mixture may include at least a hydrogen-containing gas such as H2, NH3, etc. In some examples, an inert gas such as Ar or He may also be supplied into the process gas mixture. In one embodiment, the hydrogen-containing gas is H2 with a volume flow rate of about 1000 sccm to about 6000 sccm. In one embodiment, the inert gas or carrier gas is Ar or He with a volume flow rate of about 3000 sccm to about 5000 sccm.

[0094]

[0101] During the plasma treatment process, several process parameters can be adjusted to control the plasma treatment process. In one exemplary embodiment, the process pressure in the processing chamber 100 is adjusted to be from about 10 mTorr to about 5000 mTorr, for example, from about 300 mTorr to about 3000 mTorr. The substrate temperature can be maintained in the range of about 80°C to about 400°C, for example, from about 150°C to about 250°C. The plasma treatment process can be performed for a period of from about 5 seconds to about 600 seconds, for example, from about 20 seconds to about 120 seconds.

[0095]

[0102] After the plasma treatment process, one cycle of the deposition process and the plasma treatment process is completed. Each cycle of the deposition process and the plasma treatment process can form a portion of the gap fill layer 708 having a thickness of from about 20 Å to about 200 Å.

[0096]

[0103] The number of cycles (e.g., alternating steps of a deposition process and a plasma treatment process) used to form the gap fill layer 708 may be as many as necessary. In the embodiment shown in FIG. 7C, to obtain a total thickness of the gap fill layer 708 in the range of about 10 nm to about 40 nm, the cycles of the deposition process and the plasma treatment process may be performed about 2 to about 15 times.

[0097]

[0104] In step 612, a post-anneal process is performed. The post-anneal process is an anneal process performed at a high process pressure higher than 5 bar, for example higher than 5 bar but lower than 70 bar. The high-pressure anneal process may assist in repairing voids, deposition by-products and / or residues, smoothing the surface roughness of the gap fill layer 708, and forming an annealed gap fill layer 712, as shown in FIG. 7D. In some embodiments, the high process pressure may be up to 70 bar. The high-pressure anneal process may be performed in a processing chamber such as the processing chamber 400 shown in FIG. 4, or other suitable processing chambers that process substrates one by one at a time.

[0098]

[0105] The high-pressure anneal process performed in step 612 maintains the processing pressure in the high-pressure region in the vapor phase, for example, in a dry vapor phase substantially free of liquid droplets. For example, it is in a superheated state. The processing pressure and temperature are controlled to densify the film structure in order to repair film defects, eliminate impurities, and smooth the surface roughness. In one embodiment, the internal volume 425 (shown in FIG. 4) is pressurized to a pressure higher than the atmosphere, for example, a pressure higher than about 2 bar. In another embodiment, the internal volume 425 is pressurized to a pressure of about 5 to about 70 bar, for example, about 5 to about 50 bar, for example, about 25 bar to about 55 bar.

[0099]

[0106] During processing, the internal volume 425 is maintained at a relatively low temperature by the heater 440, for example, a temperature exceeding 250 °C, for example, a temperature of about 300 °C to about 500 °C.

[0100]

[0107] By means of a high-pressure process, a driving force for eliminating impurities and connecting the dangling bonds of the gap-fill layer 708 is obtained. Therefore, the possibility of forming defects such as voids is reduced, the film quality is improved, and the surface roughness can be smoothed. In one embodiment, during the annealing process, a hydrogen-containing gas, hydrogen gas, and / or a hydrogen isotope-containing gas, such as H2, D2, T2, H2O, H2O2, NH3, and dry steam, may be supplied. Also, an inert gas such as He or Ar may be supplied during the annealing process. In one embodiment, hydrogen gas (H2) is supplied during the annealing process. In another embodiment, hydrogen gas (H2) or a hydrogen isotope-containing gas is supplied during the annealing process.

[0101]

[0108] In an exemplary implementation, the process pressure is adjusted to a pressure higher than 2 bar, such as higher than 5 bar, for example, a pressure from 5 bar to 70 bar, such as from 20 bar to about 50 bar. The process temperature can be controlled to a temperature higher than 250°C, such as from about 250°C to about 700°C, for example, from about 300°C to about 500°C.

[0102]

[0109] After the annealing process at high pressure, the gap-fill layer 708 can provide a relatively robust film structure with high purity, a large grain structure, a smooth surface roughness, and few grain boundaries, and a high film density and a low film resistivity can be obtained. In an embodiment where the gap-fill layer 708 is a Co-containing material, the film resistivity of the Co-containing material can be reduced by about 10% to about 50% after the high-pressure annealing process. The gap-fill layer 708 formed in the opening 850 can have a high gap-filling ability and be substantially void-free. The gap-fill layer 708 has an average particle size from about 80 Å to about 400 Å.

[0103]

[0110] Accordingly, a method and apparatus for forming a gap-fill layer, such as a metal-containing material, for a device structure such as a channel structure, an interconnect structure, or a contact structure are provided. Since the interconnect structure includes a barrier layer, an interface layer, and a gap-fill layer in one cluster processing system without impairing the vacuum, the possibility of surface contamination is eliminated and good interface control can be obtained. The annealing process improves the film quality of the interconnect structure so that the device structure including the interconnect structure can achieve desired electrical performance, and the annealing process is performed in a pressure range higher than 5 bar in an environment containing hydrogen or hydrogen isotopes.

[0104]

[0111] Although the foregoing content is directed to embodiments of the present disclosure, it is possible to devise other further embodiments of the present disclosure without departing from its basic scope as determined by the following claims.

Claims

1. A method of forming a device structure of a semiconductor device, comprising: forming a barrier layer in an opening formed in a material layer disposed on a substrate; performing a first plasma treatment process on the barrier layer; after performing the first plasma treatment process, forming an interface layer having a thickness of about 0.3 nm to about 3 nm on the barrier layer; forming a gap filling layer on the interface layer; performing an annealing process on the substrate in a pressure range higher than 5 bar; and forming the gap filling layer includes: (a) performing a deposition process for forming a part of the gap filling layer; (b) performing a second plasma treatment process on the part of the gap filling layer. A method further comprising the steps of:

2. The method according to claim 1, wherein the interface layer is a metal-containing layer.

3. The method according to claim 2, wherein the interface layer is at least one of a tungsten-containing material, a nickel-containing material, an aluminum-containing material, a ruthenium-containing material, or a manganese-containing material.

4. The method according to claim 1, wherein the gap filling layer is a Co layer or a Co alloy.

5. further comprising repeating (a) and (b). The method according to claim 1.

6. The second plasma treatment process further includes: supplying a treatment gas mixture containing a hydrogen-containing gas. The method according to claim 1.

7. The method according to claim 1, wherein the deposition process is a CVD process.

8. Performing the annealing process further includes: maintaining the substrate temperature higher than 250°C. The method according to claim 1.

9. Performing the annealing process further includes: during the annealing process, supplying an annealing gas mixture containing a hydrogen-containing gas. The method according to claim 1.

10. The method according to claim 1, wherein the barrier layer is a Ta-containing layer or a Ti-containing layer.

11. The method according to claim 1, wherein the barrier layer, the interface layer, and the gap filling layer are formed in a cluster system without breaking vacuum.

12. further comprising performing a pre-cleaning process before forming the barrier layer. The method according to claim 1.

13. A method of forming a device structure of a semiconductor device, comprising: forming a barrier layer in an opening formed in a material layer disposed on a substrate; Before forming the barrier layer, performing a pre-cleaning process; Performing a first plasma treatment process on the barrier layer; After performing the first plasma treatment process, forming an interface layer with a thickness of about 0.3 nm to about 3 nm on the barrier layer; Forming a gap filling layer on the interface layer; Performing an annealing process on the substrate in a pressure range higher than 5 bar; including; Performing the pre-cleaning process; further includes maintaining the substrate temperature higher than 250 °C; A method.

14. Performing the annealing process; further includes increasing the particle size of the gap filling layer; The method according to claim 1, further comprising.

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