Horizontal RRAM device and method for manufacturing the same

Abstract

A resistive random access memory (RRAM) device, particularly for a crossbar array, comprises a dielectric layer (115) positioned between a first electrode (110A) and a second electrode (110B), a resistive switching layer (RSL) (120), and a third electrode (125) positioned between the first electrode (110A) and the second electrode (110B), the first electrode being separated from a first side of the third electrode by a first portion of the RSL, and the second electrode being separated from a second side of the third electrode by a second portion of the RSL. Corresponding fabrication methods are also provided.

Description

Technical Field

[0001] The present invention generally relates to the field of RRAM arrays, and more particularly to the formation of RRAM arrays for reducing resistance variations.

Background Art

[0002] Resistive random access memory (RRAM) is a non-volatile memory structure that relies on the formation and control of filamentous conductive paths within a dielectric. Filament conduction is controlled by the movement of oxygen vacancies. The movement of oxygen vacancies is a fundamentally stochastic process that results in high variability in the resistance of the device.

Summary of the Invention

[0003] Additional aspects or advantages, or both, are in part described in the following description, in part will become apparent from the description, or can be learned by practice of the present invention.

[0004] Viewed from one aspect, the present invention provides an apparatus comprising a dielectric layer positioned between a first electrode and a second electrode, and a third electrode positioned on the dielectric layer between the first electrode and the second electrode, wherein the first electrode is separated from a first side of the third electrode by a first portion of the dielectric layer, and the second electrode is separated from a second side of the third electrode by a second portion of the dielectric layer.

[0005] According to another aspect of the present invention, the third electrode is composed of a first layer and a second layer, and the first layer is in direct contact with the first electrode and the second electrode.

[0006] According to another aspect of the present invention, the second layer is in direct contact with the first layer and in direct contact with an upper metal component.

[0007] According to another aspect of the present invention, the material of the first layer is HfO xIt is selected from the group consisting of HfO2, ZrO2, AnO, TiO2, Al2O3, NiO, MnO2, or TaO2.

[0008] According to another aspect of the present invention, the material of the second layer is selected from the group consisting of TiN, Al, Ti, Cu, Ag, W, Pt, Au, Ni, TaN, conductive oxides such as indium tin oxide, Al-doped or Ga-doped ZnO, p-type doped Si, n-type doped Si, or any combination thereof.

[0009] According to another aspect of the present invention, the top surfaces of the first layer and the second layer are planar with the top surfaces of the first electrode and the second electrode.

[0010] According to another aspect of the present invention, the third electrode is disposed directly on the dielectric layer.

[0011] According to another aspect of the present invention, the first layer is in direct contact with the dielectric layer.

[0012] According to another aspect of the present invention, the material of the dielectric layer is selected from the group consisting of SiO2, SiCOH, TEOS, SiN, low-k dielectrics, or ultra-low-k dielectrics.

[0013] According to another aspect of the present invention, the third electrode is composed of a separation layer, a first layer, and a second layer, and the separation layer is in direct contact with the first electrode and the second electrode.

[0014] According to another aspect of the present invention, the first layer is in direct contact with the separation layer, the second layer is in direct contact with the first layer, and is in direct contact with the upper metal component.

[0015] According to another aspect of the present invention, the third electrode is disposed directly on the dielectric layer.

[0016] According to another aspect of the present invention, the separation layer and the first layer are in direct contact with the dielectric layer.

[0017] According to another aspect of the present invention, the first material for the first electrode is selected from the group consisting of Cu, Ru, Co, Rh, Mo, W, or Ta, the second material for the second electrode is selected from the group consisting of Cu, Ru, Co, Rh, Mo, W, or Ta, the third material for the separation layer is selected from the group consisting of Cu, Ru, Co, Rh, Mo, W, or Ta, the third material is different from the first material, and the third material is different from the second material.

[0018] According to another aspect of the present invention, there is provided an apparatus comprising: a plurality of lower electrodes spaced apart from each other; a plurality of dielectric layers, one of the plurality of dielectric layers being located between two adjacent lower electrodes of the plurality of lower electrodes; a plurality of connection electrodes, each of the plurality of connection electrodes being located on a dielectric layer located between two adjacent lower electrodes of the plurality of lower electrodes, one of the two adjacent lower electrodes being separated from the first side of the connection electrode by a first portion of the dielectric layer, and the other of the two adjacent lower electrodes being separated from the second side of the connection electrode by a second portion of the dielectric layer.

[0019] According to another aspect of the present invention, each of the plurality of connection electrodes is composed of a first layer and a second layer, and the first layer is in direct contact with at least two adjacent lower electrodes of the plurality of lower electrodes.

[0020] According to another aspect of the present invention, the second layer is in direct contact with the first layer and in direct contact with an upper metal component.

[0021] According to another aspect of the present invention, the material of the first layer is selected from the group consisting of HfO x , HfO2, ZrO2, AnO, TiO2, Al2O3, NiO, MnO2, or TaO2.

[0022] According to another aspect of the present invention, the material of the second layer is selected from the group consisting of TiN, Al, Ti, Cu, Ag, W, Pt, Au, Ni, TaN, conductive oxides such as indium tin oxide, Al-doped or Ga-doped ZnO, p-type doped Si, n-type doped Si, or any combination thereof.

[0023] According to another aspect of the present invention, the top surfaces of the first layer and the second layer are flush with the top surfaces of the plurality of lower electrodes.

[0024] Viewed from another aspect, the present invention provides a method of forming a resistive random access memory (RRAM) structure including forming a first electrode and a second electrode. A first dielectric layer is formed between the first electrode and the second electrode. The first dielectric layer is etched to form a trench between the first electrode and the second electrode. A third electrode is formed in the trench, and the first electrode is separated from a first side of the third electrode by a first portion of the dielectric layer, and the second electrode is separated from a second side of the third electrode by a second portion of the dielectric layer.

[0025] According to another aspect of the present invention, the third electrode is composed of a first layer and a second layer, and the first layer is in direct contact with the first electrode and the second electrode.

[0026] According to another aspect of the present invention, the second layer is in direct contact with the first layer and in direct contact with the upper metal component.

[0027] According to another aspect of the present invention, the material of the first layer is HfO x , selected from the group consisting of HfO2, ZrO2, AnO, TiO2, Al2O3, NiO, MnO2, or TaO2.

[0028] According to another aspect of the present invention, the material of the second layer is selected from the group consisting of TiN, Al, Ti, Cu, Ag, W, Pt, Au, Ni, TaN, conductive oxides such as indium tin oxide, Al-doped or Ga-doped ZnO, p-type doped Si, n-type doped Si, or any combination thereof.

[0029] The above and other aspects, features, and advantages of specific exemplary embodiments of the present invention will become more apparent from the following description in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0030]

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DETAILED DESCRIPTION OF THE INVENTION

[0031] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the present invention defined by the claims and their equivalents. The following description includes various specific details for the purpose of assisting in that understanding, but these should be regarded merely as examples. Accordingly, those skilled in the art will recognize that various changes and modifications to the embodiments described herein can be made without departing from the scope and spirit of the present invention. In addition, descriptions of well-known functions or configurations may be omitted for clarity and brevity.

[0032] The terms and words used in the following description and claims are not limited to their bibliographical meanings, but are used merely to enable a clear and consistent understanding of the present invention. Thus, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention is provided for illustrative purposes only and not for the purpose of limiting the invention defined by the appended claims and their equivalents.

[0033] The singular forms "a", "an", and "the" are to be understood to include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a component surface" includes reference to one or more such surfaces unless the context clearly dictates otherwise.

[0034] Detailed embodiments of the claimed structures and methods are disclosed herein. However, it should be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. In the description, well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0035] References to "one embodiment", "an embodiment", "an exemplary embodiment", etc. in this specification indicate that the described embodiment can include a particular feature, structure, or characteristic, but not all embodiments need to include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure, or characteristic is described in relation to an embodiment, it is presented that it is within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in relation to other embodiments, whether explicitly described or not.

[0036] For the purposes of the following description, the terms "above", "below", "right", "left", "vertical", "horizontal", "top", "bottom", and their derivatives are related to the disclosed structures and methods as oriented in the figures of the drawings. The terms "overlying", "atop", "on top", "positioned on", or "positioned atop" mean that a first element, such as a first structure, is present over a second element, such as a second structure, and intervening elements, such as an interface structure, may be present between the first element and the second element. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive, insulating, or semiconductor layer at the interface of the two elements.

[0037] To avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and illustration, and in some cases, may not be described in detail. In other instances, some process steps or operations known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.

[0038] Various embodiments of the present invention are described herein with reference to the accompanying drawings. Alternative embodiments can be devised without departing from the scope of the present invention. Note that in the following description and drawings, various connections and positional relationships between elements (e.g., above, below, adjacent, etc.) are described. These connections or positional relationships or both may be direct or indirect, and the present invention is not intended to be limited in this regard. Thus, the coupling of entities can refer to either direct or indirect coupling, and the positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, a reference herein to forming layer "A" on layer "B" includes a situation where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", provided that the relevant characteristics and functionality of layer "A" and layer "B" are not substantially changed by the intermediate layer.

[0039] The following definitions and abbreviations are used for the interpretation of the claims and this specification. As used herein, the terms "comprise", "comprising", "include", "including", "has", "having", "contains" or "containing" or any other variation thereof are intended to cover non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that includes a list of elements is not necessarily limited to only those elements, but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0040] Furthermore, as used herein, the term "exemplary" is used to mean "an example, instance, or serving as an illustration." Any embodiment or design described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" can be understood to include any integer greater than or equal to 1, i.e., 1, 2, 3, 4, etc. The term "a plurality" can be understood to include any integer greater than or equal to 2, i.e., 2, 3, 4, 5, etc. The term "connected" can include both indirect "connection" and direct "connection."

[0041] As used herein, the term "about" modifying the amount of an ingredient, component, or reactant of the invention being used refers to the variation in numerical amounts that can occur by, for example, the typical measuring procedures and liquid handling procedures used in making concentrates or solutions. Further, the variation can occur from inadvertent error in the measuring procedures, differences in the manufacture, source, or purity of the components used to make the compositions or to carry out the methods. The terms "about" or "substantially" are intended to include the degree of error associated with the measurement of a particular quantity based on the equipment available at the time of filing of the present application. For example, about can include a range of ±8% or 5% or 2% of a given value. In another aspect, the term "about" means within 5% of the reported numerical value. In another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

[0042] The various processes used to form microchips packaged in integrated circuits (ICs) are classified into four general categories: namely, film deposition, removal / etching, semiconductor doping, and patterning / lithography. Deposition is any process of growing, coating, or otherwise transferring a material onto a wafer. Available techniques include, among others, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently atomic layer deposition (ALD). Removal / etching is any process of removing material from a wafer. Examples include etching processes (either wet or dry), reactive ion etching (RIE), and chemical mechanical planarization (CMP). Semiconductor doping generally involves changing the electrical properties, for example, by doping the source and drain of a transistor, typically by diffusion or ion implantation or both. Following these doping processes, furnace annealing or rapid thermal annealing (RTA) is performed. Annealing serves to activate the implanted dopants. Films of both conductors (e.g., aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and insulate electrical components. By selectively doping various regions of a semiconductor substrate, the conductivity of the substrate can be changed by applying a voltage.

[0043] Here, embodiments of the present invention will be referred to in detail, examples of which are shown in the accompanying drawings, and like reference numerals refer to like elements throughout. Embodiments of the present invention generally target a RRAM crossbar array having an upper electrode positioned between two of the lower electrodes, and thus each of the two lower electrodes is connected to a different side of the upper electrode. Thereby, the lower metal electrodes can be operated in parallel. The reduction of resistance variation in the RRAM crossbar array is brought about by operating the two lower electrodes in parallel. For example, the variance of a RRAM program pair (RPP) in which two lower electrodes share a signal upper electrode is, for example, 1 / 8 of the resistance variation of a single RRAM device in which the upper electrode is positioned over the lower electrode.

[0044] FIG. 1 shows a RRAM crossbar device 100 according to an embodiment of the present invention. FIG. 1 shows a crossbar device having a plurality of lower metal bars 101 and a plurality of upper metal bars 102. FIGS. 2-9 show forming a shared electrode between two of the lower metal bars 110A and 110B.

[0045] FIG. 2 shows the formation of first lower bars 110A and 110B along section A of the crossbar device 100 according to an embodiment of the present invention.

[0046] The first metal layer 110 is formed on the substrate 105. The substrate 105 can be of any type of material, for example, a substrate, a silicon wafer, a sapphire wafer, a metal layer, a conductor layer, an insulator, or any other type of material used in creating a multilayer device. The lower metal layer 110 can be formed, for example, by physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD), or other deposition techniques. The lower metal layer 110 is etched to form each of the plurality of lower bars 101. The lower metal layer 110 can be etched, for example, by deposition of a hard mask material, lithography, pattern transfer, and finally by reactive ion etching (RIE) or other etching techniques. FIG. 2 shows the first lower bar 110A and the second lower bar 110B resulting from the etching of the lower metal layer 110. The lower bars 110A, 110B are formed of a material selected from the group consisting of copper (Cu), ruthenium (Ru), cobalt (Co), rhodium (Rh), molybdenum (Mo), tungsten (W), and tantalum (Ta). Each of the lower bars 110A and 110B functions as an electrode, where the lower bar 110A is the first electrode and the lower bar 110B is the second electrode. The space between each of the lower bars 110A and 110B is filled with a dielectric material 115. The dielectric material 115 can be selected from the group consisting of SiO2, SiCOH, TEOS, SiN, a low-k dielectric, or an ultra-low-k dielectric.

[0047] FIG. 3 shows the removal of the dielectric material 115 along cross-section A of the crossbar device 100 according to an embodiment of the present invention. The dielectric material 115 is etched to form a trench between the lower bars 110A and 110B. This trench enables the formation of a third electrode between the lower bars 110A and 110B. By disposing the third electrode, both the first electrode and the second electrode are connected to the third electrode, thereby enabling the lower bar 110A (i.e., the first electrode) and the lower bar 110B (i.e., the second electrode) to be connected in parallel.

[0048] Figure 4 shows the formation of the first layer 120 along the exposed surface along cross-section A of the crossbar device according to an embodiment of the present invention. The first layer 120 is formed on the exposed surfaces of the lower bars 110A and 110B and the dielectric material 115. The first layer 120 is HfO x It can be formed of a material selected from the group consisting of HfO2, ZrO2, AnO, TiO2, Al2O3, NiO, MnO2, and TaO2. The first layer 120 can be formed, for example, by physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD), or other deposition techniques.

[0049] Figure 5 shows the formation of the third electrode (second layer 125) along cross-section A of the crossbar device according to an embodiment of the present invention.

[0050] The second layer 125 is formed on the exposed surface of the first layer 120. The second layer 125 can be formed, for example, by physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD), or other deposition techniques. The second layer 125 can be formed of a material selected from the group consisting of TiN, Al, Ti, Cu, Ag, W, Pt, Au, Ni, TaN, conductive oxides such as indium tin oxide, Al-doped or Ga-doped ZnO, p-type doped Si, n-type doped Si, or combinations thereof.

[0051] Figure 6 shows the planarization along cross-section A of the crossbar device 100 according to an embodiment of the present invention. The second layer 125 and the first layer 120 are planarized to expose the top surfaces of the lower bars 110A and 110B. The trenches are filled with the first layer 120 and the second layer 125. The exposed surfaces of the first layer 120 and the second layer 125 are flush with the exposed surfaces of the lower bars 110A and 110B.

[0052] FIG. 7 shows the formation of the etch stop 130 and the dielectric layer 135 on the exposed surface along the cross-section A of the crossbar device 100 according to an embodiment of the present invention. An optional etch stop 130 can be formed on the exposed surfaces of the first layer 120, the second layer 125, and the lower bars 110A and 110B. The etch stop 130 can be formed of a material selected from the group consisting of NBLOK, SiN, and Al2O3. The dielectric layer 135 can be formed directly on the etch stop 130 or on the exposed surfaces of the first layer 120, the second layer 125, and the lower bars 110A and 110B. The dielectric layer 135 can be selected from the group consisting of SiO2, SiCOH, TEOS, SiN, low-k dielectrics, or ultra-low-k dielectrics.

[0053] FIG. 8 shows the patterning and etching for forming a via into the dielectric layer 135 up to the third electrode (i.e., the second layer 125) along the cross-section A of the crossbar device 100 according to an embodiment of the present invention. The dielectric layer 135 is patterned and etched to form a via into the dielectric layer 135 up to the second layer 125 that forms the third electrode. The via is formed between two portions of the dielectric layers 135A and 135B. The etch stop 130 functions as a barrier to the etching process of the dielectric layer 135. The etch stop 130 prevents the etching process from damaging the second layer 125. A second etching process is utilized to remove the etch stop 130 located within the via.

[0054] FIG. 9 shows the formation of the upper metal layer 140 in the crossbar device 100 along the cross-section A according to an embodiment of the present invention.

[0055] The upper metal layer 140 can be formed, for example, by physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD), or other deposition techniques. The upper metal layer 140 is formed on the exposed surfaces of the dielectric layers 135A and 135B and fills vias extending to the top surface of the second layer 125. The upper metal layer 140 can be formed of a material selected from the group consisting of copper (Cu), ruthenium (Ru), cobalt (Co), rhodium (Rh), molybdenum (Mo), tungsten (W), and tantalum (Ta).

[0056] The two lower electrodes (lower bars 110A and 110B) share a common upper electrode (second layer 125). The parallel connection between the lower electrodes is achieved by disposing the upper electrode between the lower electrodes, thus enabling both lower electrodes to be electrically connected to the same upper electrode. The resistance variation in the RRAM crossbar array is reduced by operating the electrodes in parallel. The RRAM program pair (RPP), i.e., the variation of two lower electrodes sharing a signal upper electrode, is 1 / 8 of the resistance variation of a single RRAM device.

[0057] FIG. 10 shows the formation of the first and second electrodes along section A of the crossbar device 100 according to an embodiment of the present invention.

[0058] The first metal layer is formed on substrate 205. The substrate 205 can be of any type of material, for example, a substrate, a silicon wafer, a sapphire wafer, a metal layer, a conductor layer, an insulator, or any other type of material used in creating a multilayer device. The lower metal layer can be formed, for example, by physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD), or other deposition techniques. The lower metal layer is etched, including, for example, deposition of a hard mask material, lithography, pattern transfer, and finally reactive ion etching (RIE), to form each of the plurality of lower bars 101. FIG. 10 shows a first lower bar 210A and a second lower bar 210B. The lower bar 210A or 210B is formed of a material selected from the group consisting of copper (Cu), ruthenium (Ru), cobalt (Co), rhodium (Rh), molybdenum (Mo), tungsten (W), and tantalum (Ta). Each of the lower bars 210A and 210B functions as an electrode, where the lower bar 210A is the first electrode and the lower bar 210B is the second electrode. The space between each of the lower bars 210A and 210B is filled with a dielectric material 215. The dielectric material 215 can be selected from the group consisting of SiO2, SiCOH, TEOS, SiN, a low-k dielectric, or an ultra-low-k dielectric.

[0059] Figure 11 shows the removal of the dielectric material 215 and the formation of the separation layer 222 along the cross-section A of the crossbar device according to an embodiment of the present invention. The dielectric material 215 is etched to form a trench between the lower bars 210A and 210B. This trench enables the formation of a third electrode between the lower bars 210A and 210B. By arranging the third electrode, it becomes possible to connect the lower bar 210A (i.e., the first electrode) and the lower bar 210B (i.e., the second electrode) in parallel. The separation layer 222 is formed on the exposed surfaces of the lower bars 210A and 210B and on the exposed surface of the dielectric material 215. The separation layer can be selected from the group consisting of conductive oxides such as Cu, Ru, Co, Rh, Mo, W, Ta, Al, Ti, Cu, Ag, W, Pt, Au, Ni, TaN, indium tin oxide, A or Ga-doped ZnO, n-type doped Si, p-type doped Si, or other suitable materials. The material of the separation layer 222 is different from the materials of the lower bars 210A and 210B. The reason for the separation layer 222 is to provide a different bonding surface for the first layer 220. Depending on the materials selected for the lower bars 210A and 210B, problems (such as electrical connection problems, bonding problems, etc.) may occur regarding the connection to the first layer 220. The separation layer 222 functions as an intermediate layer to prevent connection problems between the lower bars 210A and 210B and the first layer 220.

[0060] Figure 12 shows the removal of a part of the separation layer 222 and the formation of the first layer 220 along the exposed surface along the cross-section A of the crossbar device 100 according to an embodiment of the present invention. The separation layer 222 is etched such that a part of the separation layer 222 remains on the sidewalls within the trenches of each of the lower bars 210A and 210B. The etching can be achieved by reactive ion etching (RIE) or other suitable etching means. The first layer 220 is formed on the exposed surfaces of the lower bars 210A and 210B, the dielectric material 215, and the separation layer 222. The first layer 220 is HfO x、It can be formed of a material selected from the group consisting of HfO2, ZrO2, AnO, TiO2, Al2O3, NiO, MnO2, and TaO2. The first layer 220 can be formed, for example, by physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD), or other deposition techniques.

[0061] FIG. 13 shows the formation of a third electrode (second layer 225) along cross-section A of a crossbar device according to an embodiment of the present invention.

[0062] The second layer 225 is formed on the exposed surface of the first layer 220. The second layer 225 can be formed, for example, by physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD), or other deposition techniques. The second layer 225 can be formed of a material selected from the group consisting of TiN, Al, Ti, Cu, Ag, W, Pt, Au, Ni, TaN, conductive oxides such as indium tin oxide, Al-doped or Ga-doped ZnO, p-type doped Si, n-type doped Si, or combinations thereof.

[0063] FIG. 14 shows planarization along cross-section A of a crossbar device according to an embodiment of the present invention. The second layer 225 and the first layer 220 are planarized to expose the top surfaces of the lower bars 210A and 210B and the top surface of the isolation layer 222. The trench between the lower bars 210A and 210B is filled with the first layer 220, the second layer 225, and the isolation layer 222. The exposed surfaces of the first layer 220, the second layer 225, and the isolation layer 222 are flush with the exposed surfaces of the lower bars 210A and 210B.

[0064] FIG. 15 shows the formation of an etch stop 230 and a dielectric layer 235 on an exposed surface along cross-section A of a crossbar device according to an embodiment of the present invention. An optional etch stop 230 can be formed on the exposed surfaces of the first layer 220, the second layer 225, the isolation layer 222, and the lower bars 210A and 210B. The etch stop 230 can be formed of a material selected from the group consisting of NBLOK, SiN, and Al2O3. The dielectric layer 235 can be formed directly on top of the etch stop 230 or on the exposed surface of the first layer 220, the second layer 225, the isolation layer 222, and the lower bars 210A and 210B. The dielectric layer 235 can be selected from the group consisting of SiO2, SiCOH, TEOS, SiN, a low-k dielectric, or an ultra-low-k dielectric.

[0065] FIG. 16 shows the patterning and etching for forming a via into the dielectric layer up to a third electrode (i.e., the second layer 225) along cross-section A of a crossbar device according to an embodiment of the present invention. The dielectric layer 235 is patterned and etched to form a via into the dielectric layer 235 up to the second layer 225 that forms the third electrode. The via is formed between two portions of the dielectric layers 235A and 235B. The etch stop 230 functions as a barrier to the etching process of the dielectric layer 235. The etch stop 230 prevents the etching process from damaging the surface of the second layer 225. A second etching process is utilized to remove the etch stop 230 located within the via to expose the top surface of the second layer 225.

[0066] FIG. 17 shows the formation of an upper metal layer in a crossbar device along cross-section A according to an embodiment of the present invention.

[0067] The upper metal layer 240 can be formed, for example, by physical vapor deposition (PVD), atomic layer deposition (ALD), and chemical vapor deposition (CVD), or other deposition techniques. The upper metal layer 240 is formed on the exposed surfaces of the dielectric layers 235A and 235B and fills vias extending to the top surface of the second layer 225. The upper metal layer 240 can be formed of a material selected from the group consisting of copper (Cu), ruthenium (Ru), cobalt (Co), rhodium (Rh), molybdenum (Mo), tungsten (W), and tantalum (Ta).

[0068] The two lower electrodes (lower bars 210A and 210B) share a common upper electrode (second layer 225). The parallel connection between the lower electrodes is achieved by placing the upper electrode between the lower electrodes, thus enabling both lower electrodes to be electrically connected to the same upper electrode. The resistance variation in the RRAM crossbar array is reduced by operating the electrodes in parallel. The RRAM program pair (RPP), i.e., the variation of two lower electrodes sharing a signal upper electrode, is 1 / 8 of the resistance variation of a single RRAM device.

[0069] Although the present invention has been shown and described with reference to its specific exemplary embodiments, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.

[0070] The description of the various embodiments of the present invention is presented for purposes of illustration and is not intended to be exhaustive or to be limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of one or more embodiments, the practical application to the technologies found in the market, or the technical improvements, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A dielectric layer positioned between a first electrode and a second electrode, On the dielectric layer, HfO ｘ , HfO ２ , ZrO ２ , TiO ２ , Al ２ O ３ , NiO, MnO ２ , or TaO ２ and a first oxide layer selected from the group consisting of and a third electrode positioned on the first oxide layer between the first electrode and the second electrode, comprising: the first oxide layer being in direct contact with the first electrode, the second electrode, and the third electrode, and a top surface of the third electrode being flush with a top surface of the first electrode and a top surface of the second electrode, a resistive random access memory (RRAM) program pair.

2. The RRAM program pair according to claim 1, wherein the third electrode is in direct contact with an upper metal component.

3. The RRAM program pair according to claim 1, wherein a material of the first electrode is selected from the group consisting of Cu, Ru, Co, Rh, Mo, W, or Ta.

4. The RRAM program pair according to claim 1, wherein a material of the second electrode is selected from the group consisting of Cu, Ru, Co, Rh, Mo, W, or Ta.

5. The material of the first oxide layer is HfO ｘ The RRAM program pair according to claim 1, wherein the material is HfO

6. The RRAM program pair according to claim 1, wherein a material of the third electrode is selected from the group consisting of TiN, Al, Ti, Cu, Ag, W, Pt, Au, Ni, TaN, a conductive oxide of indium tin oxide, Al-doped or Ga-doped ZnO, p-type doped Si, n-type doped Si, or any combination thereof.

7. The material of the dielectric layer is SiO ２ , SiCOH, TEOS, SiN, a low-k dielectric, or an ultra-low-k dielectric, the RRAM program pair according to claim 1, selected from the group consisting of.

8. The RRAM program pair according to claim 1, including a conductive separation layer, the separation layer being in direct contact with the first electrode, the second electrode, and the first oxide layer.

9. The RRAM program pair according to claim 8, wherein the separation layer and the first oxide layer are in direct contact with the dielectric layer.

10. A first material for the first electrode is selected from the group consisting of Cu, Ru, Co, Rh, Mo, W, or Ta, a second material for the second electrode is selected from the group consisting of Cu, Ru, Co, Rh, Mo, W, or Ta, a third material for the separation layer is selected from the group consisting of Cu, Ru, Co, Rh, Mo, W, or Ta, the third material being different from the first material, the third material being different from the second material, the RRAM program pair according to claim 8.

11. An RRAM array including a plurality of the RRAM program pairs according to any one of claims 1 to 10.

12. A method of forming a resistance change type RAM (RRAM) program pair, comprising: forming a first electrode and a second electrode on a substrate; forming a dielectric layer between the first electrode and the second electrode; etching the dielectric layer to form a trench between the first electrode and the second electrode; On the exposed surfaces of the dielectric layer, the first electrode, and the second electrode, HfO ｘ , HfO ２ , ZrO ２ , TiO ２ , Al ２ O ３ , NiO, MnO ２ , or TaO ２ to form a first oxide layer selected from the group consisting of: forming a third electrode layer on an exposed surface of the first oxide layer; planarizing the first oxide layer and the third electrode layer to expose top surfaces of the first electrode and the second electrode; forming a dielectric layer on exposed surfaces of the first oxide layer, the third electrode layer, the first electrode, and the second electrode; etching the dielectric layer to form a via in the dielectric layer down to the third electrode layer; A method comprising the above steps.

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