Hole integrated sensor and its manufacturing process

Abstract

An integrated Hall sensor is provided, comprising: a main wafer (10) of semiconductor material including a substrate (101) having a first surface (101a) and a second surface (101b) opposite the first surface (101a) along a vertical axis (y); Hall sensor terminals (1, 2, 3, 4; 1', 2', 3', 4') arranged on at least one of the first and second surfaces (101a, 101b) of the substrate (101); and an isolation structure (109) in the substrate (101) that defines a Hall sensor plate (103) of the integrated Hall sensor, the Hall sensor terminals being arranged within the isolation structure (109). The integrated Hall sensor further comprises at least one test and calibration coil (C1) integrated within the main wafer (10), the test and calibration coil (C1) having a plurality of windings formed at least in part by metal portions (130b, 170b; 130a, 170a) disposed on the first and second surfaces (101a, 101b) of the substrate (101) and defining an internal volume that encompasses the entire Hall sensor plate (103).

Description

Technical Field

[0001] Cross - reference to related applications This application claims the priority of European Patent Application No. 19185046.0 filed on July 8, 2019, the entire disclosure of which is incorporated herein by reference.

[0002] Technical field The present invention relates to a Hall integrated sensor having at least an integrated coil for final testing and calibration, and a corresponding manufacturing process.

Background Art

[0003] Magnetic sensor ICs (magnetic circuits) typically use silicon - based Hall sensor elements integrated together with the electrical circuits necessary for signal conditioning and amplification. Typical products with an integrated Hall sensor are Hall switch ICs, Hall ICs for linear position measurement, Hall ICs for angular position sensors, Hall ICs for current detection, and 3D Hall sensor ICs. Depending on the type of product, the Hall integrated sensor may include horizontal Hall elements, vertical Hall elements, or both. Horizontal Hall elements sense the strength of a magnetic field perpendicular to the silicon surface. They are used in many applications where it is sufficient to determine the strength of the magnetic field in one spatial dimension. Examples are unipolar and bipolar Hall switch ICs and Hall sensor ICs for linear position measurement along one axis. Vertical Hall elements that sense the strength of a magnetic field in the plane of the silicon surface are used in angular position sensor Hall ICs and, together with horizontal Hall elements, in 3D Hall sensor ICs.

[0004] Since Hall sensors can be manufactured in a standard CMOS manufacturing process, the electronics for operation and readout and the Hall sensor can be integrated on the same chip. Alternatively, a dedicated Hall sensor wafer can be laminated on a second wafer containing the necessary circuits. WO2020 / 104998A1 in the name of the present applicant discloses a method of laminating two wafers to form such a Hall sensor IC product.

[0005] The magnetic sensitivity of a Hall sensor depends on stress, temperature, elapsed time, and thermal shock. Manufacturing defects such as optical orientation errors, non-uniform dopant density, or defects may cause an offset in the Hall voltage. Even more seriously, the plastic package used for the Hall sensor IC may generate stress in the silicon and cause an offset in the Hall voltage. Therefore, Hall sensor ICs are subject to extensive testing. In the case of many products, such as linear Hall ICs, each Hall sensor is calibrated and the resulting calibration data is stored in the IC. To characterize the magnetic response of the Hall sensor, the packaged chip is placed in an external Helmholtz coil. Naturally, 3D Hall sensor ICs need to be characterized in all three spatial dimensions. As can be understood from the above, the final testing and calibration effort for Hall sensor ICs is substantial, and the associated costs account for a large portion of the overall manufacturing cost.

[0006] As described below, for example, it has been proposed to equip Hall sensor ICs with integrated coils for testing and calibration. -P.L.C. Simon, P.H.S. de Vries, S. Middelhoek, “Autocalibration of silicon Hall devices”, Transducers 95, 291-A12, pages 237 - 240, 1995 -R.S. Popovic, T.J.A. Flanagan, P.A. Besse, “The future of magnetic sensors”, Sensors and Actuators A56, pages 39 - 55, 1996

[0007] The integrated coil used for the final test and calibration of horizontal and / or vertical Hall sensors needs to induce a magnetic field large enough in the range of at least several mT. Coil efficiency is defined as the ratio of the induced magnetic field strength divided by the coil current. The maximum coil current applied to the integrated coil during the final test or calibration procedure can be limited by the electromigration performance of the CMOS metal layer used for the coil. More importantly, it is necessary to consider the self-heating of the Hall sensor element during the test. For these reasons, it is important to achieve a high coil efficiency for the integrated coil.

[0008] Furthermore, the magnetic field induced by the integrated coil must be uniform in the region of the Hall sensor element to be tested. This can be achieved to some extent for horizontal Hall sensors (by using a standard metal layer for coil formation), but no method is known for forming an inductor coil for vertical Hall sensors such that a uniform and homogeneous magnetic field is generated in the Hall plate of the vertical Hall sensor.

Summary of the Invention

Problems to be Solved by the Invention

[0009] Therefore, an object of the present invention is to provide an improved Hall integrated sensor, particularly having at least one integrated coil for final test and calibration.

Means for Solving the Problems

[0010] According to the present invention, a Hall integrated sensor and a corresponding manufacturing process are provided as defined in the appended claims.

[0011] To better understand the present invention, here, by way of merely non-limiting example, its preferred embodiments will be described with reference to the accompanying drawings.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0013] As will be described in detail below, the present invention contemplates the manufacture of an integrated Hall sensor using fully CMOS-compatible process steps and materials.

[0014] Figures 1A, 1B, and 1C show a first embodiment of the present invention. The Hall sensor product 100 includes a vertical Hall sensor with coils for calibration and testing. Figure 1A shows a spatial view of the Hall sensor product 100 in the x-z plane. A cut parallel to the x direction from 1B to 1B' is shown as 1B-1B'. Figure 1B shows a cross-section of the Hall sensor product 100 along the cut 1B-1B'. Two cuts are shown in Figure 1B. A first cut from 1A to 1A' shown as 1A-1A' and a second cut from 1C to 1C' shown as 1C-1C'. Each of the two cuts corresponds to a plane parallel to the x-z plane shifted along the y direction from the origin. Figure 1A shows the Hall sensor product 100 in the plane of the cut 1A-1A'. Figure 1C is another spatial view of the Hall sensor product 100 in the plane of the cut 1C-1C'. The Hall sensor product 100 includes a vertical Hall element and an on-chip coil dedicated to testing and calibration of the vertical Hall element. Referring to Figure 1B, the vertical Hall element is formed on a wafer 10 having a semiconductor substrate 101. The semiconductor substrate 101 is preferably a silicon substrate, but other semiconductors can also be considered. The semiconductor substrate 101 has a first conductivity type and is preferably n-type. Further referring to Figure 2, the semiconductor substrate has a first surface indicated by 101a. In the first 101a, two highly doped regions 1 and 2 having the first conductivity type are formed. The two highly doped regions 1 and 2 extend from the surface 101a into the semiconductor substrate 101. The highly doped regions 1 and 2 can be formed by common CMOS manufacturing techniques such as photomask ion implantation and subsequent rapid thermal annealing. A dielectric layer 104 is disposed on the first surface 101a. The dielectric layer 104 constitutes a pre-metal dielectric layer and can be made of silicon nitride, silicon oxide, phosphosilicate glass, borophosphosilicate glass, or other suitable dielectric materials. The dielectric layer 104 can also include a stack of dielectric layers having a material composition as described above. Within the portion of the surface 101a occupied by the highly doped region 1, the dielectric layer 104 has an opening extending to the substrate surface 101a. Similarly, a second opening is provided in the dielectric layer 104 located within the portion of the semiconductor surface 101a occupied by the highly doped region 2.The second opening also extends to the substrate surface 101a. The first metal layer 110 is disposed on the dielectric layer 104. The first metal layer 110 can be an aluminum-based metal layer, as is common in many CMOS manufacturing processes. As shown in FIG. 2, the aluminum-based metal layer fills two openings in the dielectric layer 104. Alternatively, the two openings may be filled with a tungsten-based layer, while the metal layer 110 is aluminum-based or alternatively copper-based. Different metallization schemes can be employed for the metal layer 110, which is well known in the art. The metal layer 110 is structured to leave portions 110b, 112, 111, and 111b, as shown in FIG. 1B. The metal portions 111 and 112 are in contact with the highly doped regions 1 and 2, respectively. The highly doped regions 1 and 2 define two terminals of the vertical Hall sensor, and both are formed on the first surface 101a of the substrate 101. The metal portions 111 and 112 provide electrical contacts and wiring for accessing the Hall terminals 1 and 2, respectively. The respective metal wirings of the two Hall terminals disposed on the dielectric layer 104 are oriented in the x direction within and in proximity to the region of the vertical Hall sensor. The metal portions 110b and 111b are parts of a metal coil that surrounds the vertical Hall sensor, as will become more apparent below. The metal layer 110 is embedded in a second dielectric layer 105 that forms a first inter-metal dielectric. A material suitable for the dielectric layer 105 is silicon oxide or a high-k dielectric material. A via 121b is formed in the dielectric layer 105. A second metal layer 130 is disposed on the dielectric layer 105 and is structured to leave a metal portion 130b. A common metallization scheme can be employed for the second metal layer. The via 121b can be filled with a tungsten-based layer, and the metal layer 130 can be aluminum-based or copper-based. The via 121b can also be filled with an aluminum-based metal layer 130 disposed on the inter-metal dielectric 105. A common manufacturing process can be applied to form the metal structure shown in FIG. 1B. The second metal layer is embedded in a dielectric layer 106, which can consist of a stack including silicon oxide or a high-k dielectric and silicon oxide.Via 121b is in contact with the metal part 111b. The metal part 110b, the metal part 111b, the via 121b, and the metal part 130b constitute a part of a coil surrounding the vertical via element on the first surface of the substrate 101. The wafer 10 is attached to the second wafer 20 on the upper surface of the dielectric layer 106. The second wafer 20 may be a carrier wafer. For example, the second wafer 20 may be an inexpensive silicon wafer. Alternatively, the second wafer 20 may be a CMOS wafer including integrated circuits necessary for operating the vertical via element. In this case, the wafer 20 includes a silicon substrate on which CMOS devices are formed and a metallization stack. The metallization stack on the wafer 20 may include a plurality of metal layers embedded in the dielectric layer. In this case, the wafer 10 is attached on the upper surface of the dielectric layer on the upper surface of the silicon wafer 20 at the upper surface of the dielectric layer 106. Further, an electrical contact is provided between the metal layer formed on the wafer 20 and the metal layer formed on the first surface of the wafer 10. Such an electrical contact can be realized by hybrid bonding or other methods known in the art. Using the wafer 20 as a carrier, the wafer 10 is thinned from the back side, that is, from the opposite side of the first surface 101a. Most of the wafer material is removed so that only a thin layer of the semiconductor substrate 101 remains. In FIG. 1B, the surface of the resulting second substrate on the opposite side of the first surface 101a is indicated by 101b. The second surface 101b of the substrate layer 101 is parallel to the first surface 101a. The thickness of the remaining semiconductor substrate 101 may preferably be in the range of 10 micrometers to 50 micrometers, but thinner or thicker thickness values are also conceivable. The two highly doped regions 3 and 4 extend into the substrate 101 and are arranged on the second surface 101b. The highly doped regions 3 and 4 have the first conductivity type, which is the conductivity type of the substrate layer 101. In the vertical via element in the product 100, the highly doped region 3 may be formed on the opposite side of the highly doped region 2 on the first surface 101a, and the highly doped region 4 may be formed on the opposite side of the highly doped region 1 on the first surface 101a. FIG. 1A shows the hall sensor product 100 in the x-z plane of the second surface 100b along the cut 1A-1A'.As can be seen in FIG. 1A, the highly doped regions 3 and 4 form stripes along the z-direction. In the case of the vertical via elements of product 100, the highly doped regions 1 and 2 on the first surface 100a also form stripes oriented in the z-direction. The highly doped regions 1, 2, 3, and 4 can all have the same lateral dimension. The highly doped regions 3 and 4 on the second surface 100b can be formed by photomask ion implantation followed by laser thermal annealing. Laser thermal annealing can activate the doping on the second surface without adversely affecting the metallization on the first surface. The highly doped regions 3 and 4 and the highly doped regions 1 and 2 are surrounded by a dielectric structure 109. The dielectric structure 109 extends from the second surface 101b to the first surface 101a of the substrate layer 101. In FIG. 1A, the lateral enclosure of the highly doped regions 3 and 4 by the dielectric structure 109 is depicted. The portion of the substrate layer 101 that is laterally surrounded by the dielectric structure 109 is shown as 103 in FIGS. 1A and 1B. The portion 103 of the substrate layer 101 is the hall sensor region (hall plate) of the vertical via element of product 100. The dielectric structure 109 can be established by a deep trench isolation process. The dielectric material of the dielectric structure 109 can be silicon oxide. The deep trench isolation process is well known in the art. Referring again to FIG. 1B, a first dielectric layer 107 is disposed on the second surface 101b. The dielectric layer 107 provides a pre-metal dielectric layer on the second surface of the substrate layer 101. The dielectric layer 107 can be considered to have the same material or material composition as that used for the pre-metal dielectric layer 104 on the first surface. The first through-silicon via 140b is formed to extend from the upper surface of the dielectric layer 107 through the layer 107, through the substrate layer 101, through the dielectric layer 104 on the first surface 101a, and reach the metal portion 110b of the first metal disposed on the layer 104. The through-silicon via 140b is filled with a metal layer, and the metal layer can be a tungsten-based metal layer, or more preferably, a copper-based metal layer. The metal fill of the through-silicon via is electrically insulated from the semiconductor substrate 101 by a dielectric liner 181.The dielectric liner can be composed of silicon oxide or other suitable insulating materials. The second through-silicon via 141b is formed to extend from the upper surface of the dielectric layer 107 through the substrate to the metal portion 111b of the metal layer 110. The formation of through-silicon vias is known to those skilled in the art. Similar to the first side, two contact openings are formed in the dielectric layer 107 that extends to the surface 101b, providing access to the highly doped regions 3 and 4 respectively. Continuing with the description of FIG. 1B, the first metal layer 150 is disposed on the pre-metal dielectric layer 107 on the second substrate surface 101b. The two trenches are filled with the metal of layer 150. The same processes and materials as those for the metal layer 110 on the first surface can be applied. FIG. 1B shows four metal portions 150b, 153, 154, and 151b. The metal portion 150b is in contact with the metal fill of the through-silicon via 140b. The metal portion 151b is in contact with the metal fill of the through-silicon via 141b. The metal portion 153 is in contact with the highly doped region 3 that defines one of the two hole terminals disposed on the second surface 101b. The metal portion 154 is in contact with the highly doped region 4 that defines the other of the two hole terminals disposed on the second surface 101b. The metal portions 153 and 154 also include the wiring of the two hole terminals 3 and 4. The wiring is directed in the z direction. The metal layer 150 is embedded in the first inter-metal dielectric layer 108. The same processes and materials as those for the first inter-metal dielectric 105 on the first side of the substrate 101 can be applied. The via 160b formed through the inter-metal dielectric 108 provides a contact to the metal portion 150b. The second via 161b through the dielectric layer 108 provides a contact to the metal portion 151b. The second metal layer 170 is disposed on the inter-metal dielectric 108 and is structured to electrically connect the via 160b and the via 161b. The electrical connection is established by the metal portion 170b. In FIG. 1C, the metal portion 107b as well as the vias 160b and 161b are depicted in the x-z plane along the cut 1C-1C'. The processes and materials for filling the vias with metal and forming the metal portion 170b can be the same as those for the second metal layer on the first side of the substrate.Finally, a dielectric layer 182 is disposed on the second metal layer 170 and the intermetal dielectric layer 108. The dielectric layer 182 functions as a final passivation layer and may include a silicon nitride or silicon oxynitride layer.

[0015] The vertical Hall element has four terminals disposed on two opposing surfaces of the semiconductor substrate layer 101 so that four-fold symmetry is obtained. During operation, a drive current can be applied from terminal 1 to terminal 3. The current flows diagonally through the semiconductor layer 101, but the current flow is restricted by the dielectric structure 109. A Hall voltage can be captured between terminals 2 and 4. The measured Hall voltage represents the component of the magnetic field in the z direction. Similarly, the drive current can be applied from terminal 2 to terminal 4, and the Hall voltage can be captured between Hall terminals 3 and 1. In this case as well, the measured Hall voltage represents the component of the magnetic field in the z direction. Furthermore, since the drive current can be reversed, a total of four different operating stages can be established to determine exactly the same component of the magnetic field in the z direction. The operation of the vertical Hall sensor requires a complex circuit for the adjustment and amplification of the voltage signal. The required integrated circuit can be formed on the first surface 101a of the semiconductor wafer 10 or provided on the second semiconductor wafer 20. In either case, additional through-silicon vias may be required to access the Hall terminals 3 and 4 disposed on the second surface 101b from the first side. These vertical connections and the required integrated circuit are not shown in FIGS. 1A and 1B.

[0016] As shown in FIG. 1B, a rectangular coil is formed on the wafer 10 around the vertical Hall element. The coil includes a metal wire and pads 110b, through-silicon vias 140b, metal pads 150b, vias 160b, metal wires 170b, vias 161b, metal pads 151b, through-silicon vias 141b, metal pads 111b, vias 121b, and metal wires 130b. The rectangular coil lies in the x-y plane. When a current is supplied to the coil and flows counterclockwise, a magnetic field is induced, which is directed in the z direction inside the coil. The strength of the induced magnetic field depends on the supplied current and the shape of the induction coil. The magnetic field induced by the coil can be measured by a vertical Hall element sensitive to the z-direction magnetic field component.

[0017] As is apparent from FIG. 1B, the coil can be arranged in the x-y plane such that a substantially uniform magnetic field is induced inside the Hall plate 103 of the vertical Hall element. The thicknesses of the dielectric layers 107 and 108 on the second surface can be selected to have values equal to the thicknesses of the dielectric layers 104 and 105, respectively. In this way, the metal part 170b has the same vertical distance from the Hall plate 103 as the metal part 130b. Further, the through-silicon vias 140b and 141b can be arranged such that they have the same lateral distance from the Hall plate 103. Further, the distance of the through-silicon vias 140b and 141b to the Hall plate can be equal to the total thickness of the layers 104 and 105.

[0018] As shown in FIG. 1A, for example, seven inductor coils arranged in a row in the z direction can be provided in the vertical via element of the product 100. As shown in FIG. 1B, each coil lies in a plane parallel to the x-y plane. FIG. 1A, which represents the vertical via element with coils in the x-z plane along the cut 1A-1A’, shows the through-silicon vias belonging to the coils. As already explained in connection with FIG. 1B, the through-silicon vias 140b and 141b are part of the coils (shown in FIG. 1B). The through-silicon vias 140a and 141a belong to another coil, the through-silicon vias 140c and 141c belong to yet another coil, and the same applies to the through-silicon vias 140d and 141d, the through-silicon vias 140e and 141e, the through-silicon vias 140f and 141f, and the through-silicon vias 140g and 141g. The seven coils can be connected in series such that the current direction in the x-y plane is the same for all seven coils (i.e., counterclockwise or clockwise). Thus, the seven individual coils form the winding of one combined coil. Further, the magnetic fields induced by a single coil or winding have the same direction. Each coil or winding is arranged parallel to the x-y plane, and the series connection of the single coils is established at some distance in the vertical via element. Those skilled in the art will understand how to provide a series connection between the single coils. The series connection can be formed by the first and second metal layers 110 and 130 and their respective vias. As shown in FIG. 1A, the seven windings are arranged at equal intervals. The windings can be arranged such that a substantially uniform magnetic field is induced in the z direction across the region occupied by the hole plate 103.

[0019] In Hall sensor product 100, the Hall plate 103 of the vertical Hall element is inside the multi - wire coil. The inside of the coil (inner volume) is understood as the volume of the space surrounded by the coil windings. In FIG. 1B, the inside of the coil is indicated by 1001 as seen in this cross - sectional view parallel to the x - y plane. As shown, the Hall plate 103 is entirely disposed inside the inner volume 1001 of the coil. The same is true for the cross - sectional view parallel to the x - z plane as shown in FIG. 1A. The Hall plate 103 is entirely disposed inside the inner volume (also indicated by 1001 here) of the (multi - wire) coil.

[0020] FIG. 2 represents another Hall sensor product, indicated by 200, having a vertical Hall element with a coil for testing and calibration. FIG. 2 shows a 2 - D cut of the Hall sensor product parallel to the x - z plane along the second surface 101b of the substrate 101 (similar to FIG. 1B of Hall sensor product 100). The highly doped regions 3 and 4 that define the two terminals of the vertical Hall sensor are shown. The Hall sensor region 103 is laterally surrounded by the dielectric structure 109. Compared with the vertical Hall sensor of product 100, the vertical Hall sensor of product 200 has a narrower width in the z - direction. FIG. 2 shows two pairs of through - silicon vias. The first pair, including through - silicon vias 140a and 141a, belongs to the first winding. The second pair, including through - silicon vias 140b and 141b, belongs to the second winding of the coil. Both the first and second windings are in the x - y plane. Similar to the case of Hall sensor product 100, the windings are connected such that the current supplied to the coil flows in the same direction (i.e., clockwise or counter - clockwise in the x - y plane) through each winding.

[0021] In FIG. 2, the distance between the through-silicon vias 140a and 141a is denoted by a. The length a is the length inside the rectangular induction coil in the x direction. The distance between the two rectangular windings in the z direction is denoted by d in FIG. 2. When the distance d is selected to be close to a / 2, a Helmholtz configuration is approximately obtained. As is known to those skilled in the art, in the case of a secondary winding of length a, when 0.544×a is selected as the distance d between the two windings, approximately Helmholtz characteristics are obtained. Further, as is known, when a current is supplied to the Helmholtz coil, a uniform magnetic field is induced inside the Helmholtz coil. As shown in FIG. 2, the hole plate 103 of the vertical hole element of the product 200 is entirely located inside the two coils 1001.

[0022] A further Hall sensor product 300 is shown in FIGS. 3A, 3B, and 3C. The Hall sensor product 300 includes a horizontal Hall sensor with coils for calibration and testing. FIG. 3A provides a cross-sectional view of the Hall sensor product 300 parallel to the x-y plane. FIGS. 3B and 3C are spatial views of the Hall sensor product 300 at two different positions along the y direction. FIG. 3B shows the product 300 in the x-z plane of the second surface 101b of the substrate. This cut is shown at 3C-3C' and is shown in FIG. 3A. FIG. 3C shows a second cut parallel to the x-z plane, shown at 3B-3B'. FIGS. 3B and 3C show a cut line from 3A to 3A'. The cut 3A-3A' is shown in FIG. 3A. Referring to FIG. 3C, four highly doped regions 1, 2, 3, and 4 are formed on the second surface 101b of the substrate 101. Similarly, four highly doped regions 1', 2', 3', and 4' are formed on the first surface 101a of the substrate 101. As can be seen from FIG. 3A, the highly doped regions 1 and 1' formed on two opposing surfaces of the substrate 101 have the same position in the x-y plane. Further, the highly doped regions 2 and 2' have the same position in the x-z plane. The highly doped regions 3 and 3' also have the same position in the x-z plane, and the same applies to the highly doped regions 4 and 4'. Further referring to FIG. 3A, electrical contacts and wiring portions 151, 111', 152, and 112' are established to access the highly doped regions 1, 1', 2, and 2' respectively. Similar electrical contacts and wiring portions are also provided for the highly doped regions 3, 3', 4, and 4'. The dielectric structure 109 is arranged to extend from the second surface 101b of the substrate to the first surface 101a. As shown in FIG. 3C, the dielectric structure surrounds a portion 103 of the substrate 101, and the portion'103 defines the Hall plate of the horizontal Hall element. All of the highly doped regions are formed within the Hall plate 103. The highly doped regions 1 and 1' are electrically connected by the wiring portions 151 and 111' and by through-silicon vias not shown in FIGS. 3A, 3B, and 3C. One skilled in the art will readily understand, by referring to FIG. 1B, how a vertical electrical connection between the highly doped regions 1 and 1' can be established.Similarly, the highly doped regions 2 and 2' are also electrically connected. Similarly, the highly doped regions 3 and 3' are also electrically connected, and the highly doped regions 4 and 4' are electrically connected in this way. The four necessary through-silicon vias are arranged outside the hole plate 103 surrounded by the dielectric structure 109. The pair (1, 1') constitutes the first hole terminal of the horizontal hole element. The pair (2, 2') constitutes the second hole terminal of the horizontal hole element. The pair (3, 3') constitutes the third hole terminal of the horizontal hole element, and the pair (4, 4') constitutes the fourth hole terminal of the horizontal hole element. Referring further to FIG. 3C, the hole plate 103 of the horizontal hole element has a square shape. The highly doped regions 1, 2, 3, and 4 are arranged at the four corners of the square hole plate 103. Different layouts of the horizontal hole element can be considered. In particular, the hole plate can have a cross shape with four terminals arranged at the four ends of the cross.

[0023] During operation, the drive current can be supplied from the hole terminals (1, 1') to the hole terminals (3, 3'). In the x-z plane, this drive current flows diagonally across the square hole plate 103. Next, the hole voltage is captured between the hole terminals (2, 2') and (4, 4'). The hole voltage represents the magnetic field in the y direction. In another operating mode, the drive current is supplied from the hole terminals (2, 2') to the hole terminals (4, 4'), and the hole voltage is captured between the terminals (1, 1') and (3, 3'). Also in this case, the measured hole voltage represents the magnetic field directed in the y direction. Reversing the direction of the current in the above operating modes results in two further operating modes.

[0024] Returning to FIG. 3A, at least two metal layers are applied to the first side of the substrate 101 facing the carrier wafer 20. As described above, the first metal layer 110 is used to provide an electrical connection to the hole terminals formed at the first surface 101a. Also, at least two metal layers are applied to the second side 101b of the substrate 101. The first metal layer 150 is used to provide an electrical connection to the hole terminals formed at the second surface 101b. Two coils are formed so as to surround the area occupied by the hole plate 103. The first coil 130a is formed together with the second metal layer 130 on the first side of the wafer 10. The second coil 170a is formed by the second metal layer 170 on the second side of the wafer 10. In FIG. 3B, the coil 170a is shown in the x-z plane (cut 3B-3B’). The coil may have a square shape as shown in FIG. 3B, but other shapes such as hexagonal or circular are also possible. The coil 170a in FIG. 3B has one winding, but the coil may have a plurality of windings. The first coil 130a and the second coil 170a are preferably formed in the same manner. Specifically, the first inductor coil 130a and the second coil 170a are preferably formed such that they face each other and have the same number of windings, the same line width, the same inner diameter, and the same outer diameter. Further, preferably, the same process and material are used on both sides of the substrate layer 101 for the formation of the second metal layers 130 and 170, so that the series resistance of both inductor coils becomes substantially the same. Further, preferably, the total thickness of the dielectric layers 104 and 105 is the same as the total thickness of the dielectric layers 107 and 108. By means of through-silicon vias (not shown), the two coils are connected in series so as to form two windings of one coil. The connection is established such that the current direction in the x-z plane is the same for both windings. When a current is supplied to the coil counterclockwise, a magnetic field in the y direction is generated. In this way, the coil generates a magnetic field, and the magnetic field is measured by the horizontal Hall element. The Hall plate 103 of the horizontal Hall element is inside the coil including the windings 130a and 170a. For reference, the internal volume of the coil is shown as 1001 in FIGS. 3A and 3B.

[0025] As shown in FIGS. 4A and 4B, the Hall sensor product 400 includes a vertical Hall element with an on-chip coil for testing and calibration. FIG. 4A is an aerial view of the Hall sensor product, and FIG. 4B is a cross-sectional view. The cut position of this aerial view is along the first surface 101a of the substrate 101 (cut 4A-4A'). The cut position of the cross-sectional view is shown in FIG. 4A. The Hall sensor product 400 is preferably formed on a substrate having a second conductivity type (p-type). The well 701 is formed extending from the first surface 101a into the substrate. The well 701 has a conductivity type opposite to that of the substrate, that is, it has a first conductivity type (n-type). A plurality of highly doped regions 1, 2, 3, 4, and 5 having the first conductivity type are formed extending from the first surface 101a into the substrate. The highly doped regions 1, 2, 3, 4, and 5 are entirely disposed within the region of the well 701. The electrical contacts and wiring portions (111, 112, 113, 114, 115) are formed using the first metal layer 110. The well 701 constitutes the Hall plate (previously shown as 103) of the vertical Hall element, and the highly doped regions 1, 2, 3, 4, and 5 define the Hall terminals of the vertical Hall element. As shown in FIG. 4A, the Hall terminals 1, 2, 3, 4, and 5 are formed in a row along the x-axis. Such vertical Hall elements are known in the art. It is not necessary to explain their operations here. As is known, these types of vertical Hall elements can have different numbers of Hall elements, such as more than 3, 4, or 5. In any case, the vertical Hall element shown in FIG. 4B is sensitive to a magnetic field in the z direction. The coil for testing and calibration of the vertical Hall element is established in the same manner as the Hall sensor product 100. Here too, the Hall plate of the Hall element (here, the well 701) is entirely located inside the internal volume 1001 of the coil.

[0026] Another Hall sensor product denoted by reference numeral 500 is shown in FIGS. 5A and 5B. The Hall sensor product 500 includes a horizontal Hall element with an on-chip coil for testing and calibration. The Hall sensor product 500 is formed on a substrate 101 having a second conductivity type (p-type). A well 701 having a first conductivity type extends from a first surface 101a and is formed in the substrate. Four highly doped regions 1, 2, 3, and 4 having a first conductivity type extend into the well 701 and are formed on the first surface 101a. In the x-z plane, the well 701 may have a square shape as shown in FIG. 5A. Further, the four highly doped regions 1, 2, 3, and 4 that define Hall terminals may be arranged at the four corners of the square well 701. Other layouts are also known in the art. For example, the well 701 may have a shape of a plus sign, and the four Hall terminals are located at the four corners of the plus sign. The horizontal Hall element shown in FIGS. 5A and 5B is sensitive to a magnetic field in the z direction. The coil for testing and calibration of the horizontal Hall element of the Hall sensor product 500 is formed in the same manner as the Hall sensor product 300. The Hall plate of the horizontal Hall sensor is entirely disposed inside the internal volume 1001 of the coil.

[0027] FIG. 6 shows a Hall sensor product 600 that includes a vertical Hall element that may be the same as the vertical Hall element of the Hall sensor product 100. FIG. 6 shows a cross-sectional view of the Hall sensor product. The vertical Hall element with a Hall plate 103 and Hall terminals 1, 2, 3, and 4 is surrounded by two coils, an inner coil and an outer coil. The inner coil is formed by metal portions 110b, through-silicon vias 140b, metal portion 150, via 160b, metal line 170a, via 161b, metal portion 151b, through-silicon vias 141b, metal portion 111b, via 121b, and metal line 130b. This inner coil is the same as the coil shown in FIG. 1b with reference to the Hall sensor product 100. As shown in FIG. 6, the outer coil is formed by metal structures 114b, 142b, 155b, 162b, 171b, 192b, 270b, 193b, 172b, 163b, 156b, 143b, 115b, 123b, 133b, 223b, and 230b. To form the outer coil, an additional metal layer 230 is added to the first side of the substrate facing the carrier wafer 20. The metal layer 230 is disposed on the upper surface of the dielectric layer 106 and is itself embedded in the dielectric layer 206. A vertical connection to the metal layer 130 such as via 223b is provided. Along the same line, an additional metal layer 270 is added to the second side of the substrate 101. The metal layer 270 is disposed on the dielectric layer 182 and vias such as 192b and 193b are provided. The metal layer 270 is embedded in the final passivation layer 193. The inner and outer coils are connected in series such that when current is supplied, the direction of the current is the same in the inner coil and the outer coil (clockwise or counterclockwise in the x-y plane). The necessary electrical connections between the inner and outer coils are not shown in FIG. 6. As a result, a coil having one inner winding and one outer winding is created. Similar to the Hall sensor product 100, a plurality of such coils can be arranged along the z direction, each including an inner winding and an outer winding that are both in the x-y plane. When a plurality of coils are connected in series, a multi-wire coil having inner and outer winding loops is established. The Hall plate 103 of the vertical Hall element is disposed inside the resulting coil, and the interior is also shown as 1001 here in FIG. 6.

[0028] Figure 7 is a cutaway view of Hall sensor product 700. Hall sensor product 700 differs from Hall sensor product 300 in that coil winding 130a (not shown here) disposed on dielectric layer 105 is established as a spiral coil having a plurality of windings, and coil winding 170a disposed on dielectric layer 108 is established as a spiral coil having a plurality of windings. Spiral coil 170a is shown in Figure 7. Spiral coil 130a may have the same or a similar layout and number of windings. Similar to Hall sensor product 300, the two coils 130a and 170a are connected in series such that the current direction in the x-z plane is the same for the two spirals. The series connection requires through-silicon vias and possible underpasses for the internal ports or ends of spiral coils 130a and 170a. The underpasses can be formed by the first metal layers 110 and 150, respectively. Those skilled in the art will readily understand how to establish the series connection. Figure 7 also shows a horizontal Hall element. The horizontal Hall element is shown through a cut along the second surface 101b. In Figure 7, spiral coil 170a and the horizontal Hall element belong to two different cut positions along the y-axis. 1001 indicates the volume surrounded by spiral coils 130a and 170a. Hall plate 103 is entirely inside the internal volume 1001.

[0029] The Hall sensor product 800 shown in FIGS. 8A and 8B is another product with a horizontal Hall element and is, for example, similar to the Hall sensor product 300. The on-chip coil for testing and calibration is formed by through-silicon vias 140 that surround the horizontal Hall element laterally. FIG. 8B shows a cross-sectional view of the horizontal Hall element and the surrounding coil. Cut 8A-8A’ is shown, which is in the plane of the second surface 101b. In FIG. 8A, the horizontal Hall element and the surrounding coil are depicted in the x-z plane of cut 8A-8A’. As shown in FIG. 8B, the coil includes a metal portion 114 of the metal layer 110 on the first side of the substrate, a through-silicon via 140 through the substrate 101, and a metal portion 154 of the metal layer 150 on the second side of the same substrate. The through-silicon via 140 is isolated from the substrate 101 by a dielectric liner 181. In FIG. 8A, the through-silicon via 140 is shown surrounding the horizontal Hall element having a Hall plate 103 laterally. When current is supplied to the coil, a uniform magnetic field is induced inside the coil. Inside the coil, the direction of the induced magnetic field is perpendicular to the x-z plane. The coil has a square shape, but other shapes such as circular, octagonal, or hexagonal are also possible. The coil extends from the first metal layer 110 on the first side of the substrate to the first metal layer 150 on the second side of the substrate, and since the coil surrounds the Hall element laterally, a second metal layer on the first side of the substrate and a second metal layer on the second side of the substrate are required to access the Hall terminals from outside the coil. In FIG. 8B, metal lines 171 and vias 161 provide access to the metal portion 151 and thus to Hall terminal 1. Similarly, metal lines 172 and vias 162 provide access to the metal portion 152 and thus to Hall terminal 2. On the first side of the substrate 101 facing the carrier wafer 20, metal lines 131’ and vias 121’ provide access to the metal portion 111’ and thus to Hall terminal 1’. Similarly, metal lines 132’ and vias 122’ provide access to the metal portion 112’ and thus to Hall terminal 2’. The coil of the Hall sensor product 800 can also have a plurality of windings, i.e., a spiral coil can be established by the metal portion 154, the through-silicon via 140, and the metal portion 114.In that case, at least one underpass is required. As is apparent from FIG. 8B, such an underpass can be achieved by the metal layer 130 and the corresponding vias. The underpass can also be formed by the metal 170 and the corresponding vias. As can be seen from FIGS. 8A and 8B, the hall plate 103 of the horizontal hall element is entirely located inside the volume 1001 surrounded by the coil integrated on the same wafer 10.

[0030] The hall sensor product 900 shown in FIGS. 9A and 9B includes a horizontal hall element with coils for testing and calibration, which includes three coil windings in the x-z plane direction. The first coil winding is formed by the metal part 130a. This coil winding can be the same as the coil winding 130a of the hall sensor product 300. The second coil winding includes the metal part 110a, the through-silicon via 140a, and the metal part 150a. This coil winding can be the same as the coil of the hall sensor product 800. The third coil winding is formed by the metal part 170a. This coil winding can be the same as the coil winding 170a of the hall sensor product 300. The first, second, and third coil windings are connected in series so that when current is supplied, the current directions are the same in the x-z plane.

[0031] Figures 10A and 10B show a Hall sensor product 1000 with a vertical Hall element and coils for testing and calibrating the Hall element. This is different from the Hall sensor product 100 only in that the through-silicon vias 140a - g, 141a - g are arranged far from the Hall plate 103 (i.e., at a greater distance). This is indicated by the symbol 777. As a result, when current is supplied to the multi-strand coil, the magnetic field induced in the Hall plate 103 is mostly generated only by the lateral segments of the coil windings, i.e., the metal parts 130a, 170a, 130b, 170b, etc. As is known in the art, in this configuration, when the sum of the thicknesses of the dielectric layers 107 and 108 on the second side of the substrate 101 is equal to the sum of the thicknesses of the dielectric layers 104 and 105 on the first side of the substrate facing the carrier wafer 20, a uniform magnetic field can be created inside the coil. In other words, if the vertical distance between the metal wire 170b and the Hall plate 103 is equal to the vertical distance between the Hall plate 103 and the metal wire 130b, a uniform magnetic field is induced in the Hall plate 103.

[0032] The Hall sensor product 1100 shown in FIG. 11A has the same coil configuration as the Hall sensor product 1000, but a plurality of vertical Hall elements are arranged inside the coil. In FIG. 11A, it is shown that three vertical Hall elements indicated by H1, H2, and H3 are arranged inside a volume 1001 that represents the inside of the multi-strand coil. FIG. 11A shows a cut along the second surface 101b of the substrate 101. All of the vertical Hall elements H1, H2, and H3 are arranged such that the distances to the through-silicon vias 140a - g, 141a - g are large. The large spacing is indicated by the symbol 777. The vertical Hall elements H1, H2, and H3 are oriented to be sensitive to the z-component of the magnetic field. The Hall plates of the vertical Hall elements H1, H2, and H3 are entirely located inside the multi-strand coil. The multi-strand coil is oriented such that it can induce a uniform z-direction magnetic field inside the coil. FIG. 11A shows three vertical Hall elements. This is merely an example. Generally speaking, a plurality of vertical Hall elements oriented to be sensitive to the z-component of the magnetic field are arranged inside the multi-strand coil 1001, and the multi-strand coil itself is oriented such that the magnetic field induced inside it is in the z-direction. Similarly, a plurality of vertical Hall elements oriented to be sensitive to the x-component of the magnetic field are arranged inside the multi-strand coil 1001, and the multi-strand coil itself is oriented such that the magnetic field induced inside it is in the x-direction. In this way, for each of the two directions, a plurality of vertical Hall elements can be tested and calibrated with a single multi-strand coil. This technique can also be extended to the case of horizontal Hall elements. The inner diameters of the coil windings 130a and 170a of the Hall sensor product 300 (FIG. 3a) can be set to be sufficiently large, so that as a result, a plurality of horizontal Hall elements can be arranged inside the two coil windings.

[0033] This is shown in FIG. 11B. Here, as an example, four horizontal Hall elements indicated by H1, H2, H3, and H4 are arranged inside the test and calibration coil 1001. The test and calibration coil has the windings 170a and 130a (not shown).

[0034] In this way, multiple horizontal Hall elements can also be tested and calibrated with a single coil.

[0035] In the Hall sensor product 1200 of FIG. 12A, four vertical Hall elements denoted as H1, H2, H3, and H4 are arranged inside the multi-line coil 1001 such that the distances to the through-silicon vias 140a - g, 141a - g are large for all of them. The four Hall elements H1, H2, H3, and H4 are orthogonally coupled. In FIG. 12A, the orthogonal coupling of the Hall elements H1, H2, H3, and H4 is denoted as OC. By the orthogonal coupling, a new Hall element or Hall sensor H is generated. The orthogonal coupling of the four Hall elements H1, H2, H3, and H4 requires various electrical connections including an electrical connection between a metal layer on the first side of the substrate facing the carrier 20 and a metal layer on the second side of the substrate. Some of the electrical connections may be formed outside the multi-line coil. However, the Hall plates 103 of all four Hall elements are arranged inside the multi-line coil 1001. The Hall sensor H is tested and calibrated by this multi-line coil. FIG. 12A shows vertical Hall elements sensitive to the magnetic field component in the z direction. This is just an example. In FIG. 12A, although four Hall elements are orthogonally coupled, only two Hall elements may be orthogonally coupled to generate a new Hall element or Hall cell H. Further, two or four horizontal Hall elements can be orthogonally coupled and tested and calibrated by an appropriate coil as described above. This is shown in FIG. 12B.

[0036] In the Hall sensor product 1300 of FIG. 13, other devices are arranged inside the multi-line coil together with the Hall element H. As an example, a vertical Hall element H is shown in FIG. 13, where the Hall element is oriented to be sensitive to the magnetic field component along the z-axis. The through-silicon vias 140a - g, 141a - g belong to a multi-line coil suitable for inducing a uniform magnetic field in the z-direction inside thereof. The Hall plate of the Hall element H is in the internal volume 1001 of the multi-line coil. D1 and D2 represent further semiconductor devices other than the Hall element. In the Hall sensor product 1300, the space inside the large multi-line coil for testing and calibrating the Hall element is also used for other devices.

[0037] In the Hall sensor product 1400 of FIG. 14, the entire Hall IC is arranged inside the multi-line coil. In FIG. 14, the Hall IC indicated by IC includes a vertical Hall element H in which the vertical Hall element is oriented to be sensitive to the z-component of the magnetic field. The Hall IC and the Hall element H are arranged inside the multi-line coil 1001 and are oriented such that a uniform magnetic field in the z-direction is induced therein. The Hall IC may include a plurality of vertical Hall elements sensitive to the z-component of the magnetic field. The basic concept of the Hall sensor product can also be extended to the case of a Hall IC with a horizontal Hall element and its test and calibration coils.

[0038] Another Hall sensor product 1500 is shown in FIGS. 15A, 15B, 15C, and 15D. In FIG. 15A, which is a cross-sectional view of Hall sensor product 1500 parallel to the x-y plane, the vertical Hall element is shown to comprise a Hall plate 103 and Hall terminals 1, 2, 3, and 4 disposed on a substrate 101. The depicted vertical Hall element is sensitive to the z-component of an external magnetic field. The winding loops of the first coil formed by metal portions 115 (left and right), through-silicon vias 145 (left and right), metal portions 155 (left and right), vias 165 (left and right), via 125, and metal bars 175 and 135 are shown. As indicated by 777, the vertical segments of the first coil are disposed at a large distance, i.e., far away, from the vertical Hall element shown in FIG. 15A. As shown, when a current is supplied to this coil whose windings are parallel to the x-y plane, a magnetic field in the z-direction is induced inside the coil. Further, at the position of the depicted vertical Hall element, i.e., at a position far from the through-silicon via 145, the magnetic field is mainly induced by the flow of current through metal bars 135 and 175. A third metal layer 230 is disposed on the first side of the substrate 101 facing the carrier 20, and a third metal layer 270 is also disposed on the second side of the substrate. The metal layers 230 and 270 form a second multi-wire coil, and its orientation in the x-z plane is rotated 90 degrees with respect to the first coil. FIG. 15B is an aerial view showing the orientation of metal bar 175 parallel to the x-z plane (cut 15B-15B'). FIG. 15C is an aerial view showing the orientation of metal bar 275 parallel to the x-z plane (cut 15C-15C'). The vertical segments of the second coil are not shown in any of the figures, but the method of establishing the vertical segments is apparent from FIG. 6. In FIG. 15A, 1001 indicates the internal volume shared by the first (inner) and second (outer) multi-wire coils. When a current I1 is supplied to the first coil, a magnetic field in the z-direction is induced in volume 1001. When a current I2 is supplied to the second coil, a magnetic field in the x-direction is induced in volume 1001. By appropriately adjusting currents I1 and I2, the absolute value of the magnetic field in the z-direction can be made equal to the absolute value of the magnetic field in the x-direction.FIG. 15D shows another cut of the Hall sensor product 1500 parallel to the x-z plane, along the second surface 101b (cut 15D-15D’). Two perpendicular Hall elements H1 and H2 are disposed inside the two multi-line coils, one oriented to be sensitive to the magnetic field in the z direction (H1), and the other oriented to be sensitive to the magnetic field in the x direction (H2). The perpendicular Hall element H1 is tested and calibrated by the first (inner) coil, and the perpendicular Hall element H2 is tested and calibrated by the second (outer) coil.

[0039] The coil configuration of the Hall sensor product 1500 is used in the Hall sensor product 1600 (see FIG. 16) to test and calibrate circular perpendicular Hall elements. FIG. 16 shows a cut of the Hall sensor product 1600 along the second surface 101b. 145 shows a plurality of through-silicon vias belonging to the first (inner) and second (outer) multi-line coils. The internal volume shared by the two coils is indicated by 1001. The circular perpendicular Hall element CVH is disposed inside the two coils such that the entire Hall plate 103 is located within the volume 1001. The Hall plate 103 is ring-shaped and is laterally confined by two dielectric structures both indicated by 109. A plurality of Hall terminals 1, 2, 3, …, n are formed on the Hall plate on the second surface 101b of the substrate 101. A second plurality of Hall terminals 1’, 2’, 3’, …, n’ may be formed on the first surface 101a of the substrate. The circular perpendicular Hall element CVH is sensitive to an external magnetic field in the x-z plane, i.e., an external magnetic field parallel to the surfaces 101a and 101b of the substrate. This type of perpendicular Hall element is particularly useful for angular position measurement applications. The circular perpendicular Hall element CVH is tested and calibrated by the combined operation of the first (inner) and second (outer) multi-line coils.

[0040] In the Hall sensor product 1700 of FIG. 17, two coils for testing and calibrating the Hall element are arranged in series. Referring to FIG. 17, the first coil indicated by C1 is shown. The vertical Hall element H1 is arranged inside 1001 of the coil C1. The vertical Hall element is oriented to be sensitive to an external magnetic field in the z direction. The coil C1 is dedicated to the test and calibration of the vertical Hall element. Therefore, the coil windings of the coil C1 are oriented such that a magnetic field in the z direction is induced inside 1001. C2 indicates the second coil. A second vertical Hall element H2 arranged inside 1001 of the coil C2 is shown. The vertical Hall element H2 is oriented to be sensitive to an external magnetic field in the x direction. The coil C2 for testing and calibrating the vertical Hall element H2 is oriented accordingly. The two coils C1 and C2 are in series, and the Hall elements H1 and H2 can be tested or calibrated simultaneously. The basic concept of the Hall sensor product 1700 applies to the case of three or more coils in series for testing and calibration. In particular, it can be considered that there are three coils C1, C2, and C3. C1 and C2 are used for the test and calibration of the two vertical Hall elements as shown in FIG. 17, and C3 is used for the test and calibration of the horizontal Hall element. Thus, the 3D Hall sensor can be tested and calibrated by a coil setup composed of a series connection of three coils C1, C2, and C3, one for each direction in space.

[0041] The Hall sensor product 18 shown in FIG. 18 includes a plurality of identical Hall elements, and only a subset of the identical Hall elements is provided with on-chip coils for testing and calibration. Referring to FIG. 18, as an example, four vertical Hall elements H1, H2, H3, and H4 are shown. Only the vertical Hall element H3 is arranged inside 1001 of the multi-wire coil. The basic concept also applies to a plurality of identical horizontal Hall elements.

[0042] A cross-sectional view of another Hall sensor product 1900 is shown in FIG. 19. The vertical Hall element is formed on a substrate 101 belonging to wafer 10. The Hall plate 103 is disposed within the substrate 101. The dielectric structure 109 laterally confines the Hall plate. Hall terminals 1 and 2 are formed on the first surface 101a of the substrate 101, and Hall terminals 3 and 4 are formed on the second surface 101b of the substrate 101. The wafer 10 is mounted on the wafer 20 such that the first surface 101a faces the carrier 20. In the Hall sensor product 1900, the carrier 20 is also a structured wafer. For example, 20 is a CMOS wafer. In FIG. 19, the wafer 20 includes a substrate 201 and at least one metal layer 230 disposed within the dielectric layer 206. An electrical connection can be established between the metal layer 130 of the substrate 101 and the metal layer 230 of the substrate 201 by hybrid bonding. By this technique known in the art, a direct bond between the dielectric layers (oxides) 106 and 206 is achieved, while the electrical connection is established by copper-copper bonding. In FIG. 19, 2313b and 1323b indicate such copper-copper bonds. Other techniques of wafer stacking are known in the art and can be used in the Hall sensor product 1900. A third wafer 30 having at least one metal layer 370 embedded in the substrate 301 and the dielectric layer 306 is provided. The wafer 30 is mounted on the wafer 10 such that the dielectric layer 306 faces the dielectric layer 182 of the wafer 10. The electrical connection between the wafer 30 and the wafer 20 is preferably established in the same manner as the electrical connection between the wafer 20 and the wafer 10, and thus, for example, is also established here by the hybrid bonding technique shown in FIG. 19. 1737b and 3717b indicate the copper-copper bonds between the substrates 101 and 301. As further shown in FIG. 19, coils for testing and calibrating the vertical Hall element are formed, which extend across all three wafers 10, 20, and 30. In particular, the lateral segments 370b and 230b of the coil are formed by the metal layers of the wafers 30 and 20, respectively. The Hall plate 103 of the vertical Hall element is within the interior 1001 of a multi-line coil that extends across the three wafers 10, 20, and 30.The basic concept of the Hall sensor product 1900 can also be applied to the case of a horizontal Hall element. In this case, the first spiral coil can be formed by the metal layer 230 of the substrate 201. The second spiral coil can be formed by the metal layer 370 of the substrate 301. In order to connect the two spiral coils in series, an electrical connection between wafers is required, similar to a through-silicon via. This can be the same type of structure as that shown and described in connection with FIG. 19.

[0043] The Hall sensor product 2000 in FIG. 20 is another Hall sensor product, and the coils for testing and calibrating the Hall element span across three substrates. However, in contrast to the Hall sensor product 1900, the three substrates are stacked at the die level rather than the wafer level. In other words, the connections are achieved after singulation in the assembly process. Referring to FIG. 20, a vertical Hall element is formed on substrate 101. The Hall plate 103 is disposed within substrate 101. The dielectric structure 109 laterally confines the Hall plate. Hall terminals 1 and 2 are formed on the first surface 101a of substrate 101, and Hall terminals 3 and 4 are formed on the second surface 101b. For the processing on the second side of substrate 201, a carrier wafer is required. However, since this carrier wafer is a temporary carrier, it is not part of the final Hall sensor product. In FIG. 20, the temporary one is not shown. After the manufacturing process of substrate 101 is completed, substrate 101 is separated into dies. In FIG. 20, 10 indicates a single die including at least one vertical Hall element. Another die 20 is provided that includes substrate 201 and at least two metal layers 230 and 250 embedded in dielectric layer 206. Further, another die 30 is provided that includes substrate 201 and at least two metal layers 370 and 350 embedded in dielectric layer 306. The electrical connection between die 10 and die 20 is established by copper or solder bumps such as bumps 2513b and 1325b shown in FIG. 20. Similarly, the electrical connection between die 30 and die 20 is established by copper or solder bumps such as bumps 1735b and 3517b shown in FIG. 20. Such an assembly process is known in the art and may deviate from the foregoing discussion in some aspects and details. Referring to FIG. 20 again, coils for testing and calibrating the vertical Hall element are formed, and these coils span across die 30, die 10, and die 20. In particular, the lateral segments of coils 230b and 370b are formed by the metal layers of substrates 201 and 301, respectively. Similar to the Hall sensor product 1900, the basic concept of the Hall sensor product 2000 can also be applied to the case of horizontal Hall elements.In this case, the first spiral coil can be formed by the metal layer 230 of the substrate 201 (die 20). The second spiral coil can be formed by the metal layer 370 of the substrate 301 (die 30). The electrical series connection of the spiral coils has the same structure as the vertical segments of the coils shown in FIG. 20.

[0044] The manufacturing process steps of the hall sensor product 100 of FIGS. 1A - 1C are disclosed herein by way of example with reference to FIGS. 21A - 22M.

[0045] As shown in FIG. 21A, a wafer 10 is provided that includes a semiconductor substrate 101 having a first surface 101a and a second surface 101c. The substrate 101 is preferably a silicon substrate of a first conductivity type, preferably n-type. Two shallow and highly doped regions 1 and 2 having the first conductivity type are formed on the first surface 101a. The two highly doped regions 1 and 2 extend into the semiconductor substrate 101 from the surface 101a. The highly doped regions 1 and 2 are created by photo mask implantation, followed by resist removal and laser thermal annealing. The highly doped regions 1 and 2 have an n-type conductivity type and extend to the surface 10b. The doping concentration can be in the range of 1020 atoms / cm 3 to 1022 atoms / cm 3 and can be within the range. In laser thermal annealing, since the wafer is subjected to a very short thermal pulse, heat penetrates the silicon only to a limited depth depending on the pulse time, the amount of energy, and the wavelength. The depth of the highly doped region can be in the range of 50 nanometers to 200 nanometers.

[0046] As shown in FIG. 21B, a dielectric layer 104 is deposited on the surface 10b. The dielectric layer can be tetraethyl orthosilicate (TEOS) deposited by plasma enhanced chemical vapor deposition (PECVD). By a photomask etching process, first and second openings are etched through the oxide layer 104 such that the highly doped region 1 is exposed. A first metal layer 110 is deposited on the dielectric layer 104. The first metal layer 110 is structured by a photomask etching step as shown in FIG. 21B, leaving portions 110b, 112, 111, and 111b and filling two openings under portions 111 and 112 such that metal contacts the exposed highly doped silicon regions 1 and 2. The metal layer is preferably a typical aluminum-based metal stack including a titanium adhesion layer, a titanium nitride barrier layer, an aluminum layer, and a titanium nitride cap layer. A second dielectric layer 105 is deposited on the metal structure 110 and the exposed oxide layer 104. The second dielectric layer 105 is planarized by chemical mechanical polishing (CMP). A silicon via 121b is etched by anisotropic dry etching through the dielectric layer 105 and selectively stops at the titanium nitride barrier layer of the metal structure 111b. The silicon via is filled with a tungsten-based layer. A second metal layer 130, preferably an aluminum-based or copper-based layer, is deposited on the dielectric layer 105 and structured to leave a portion 130b. Next, a third dielectric layer 106 is deposited on the second metal layer 130b and the exposed second dielectric layer 105. The third dielectric layer 106 is planarized by chemical mechanical polishing (CMP).

[0047] Referring to FIGS. 21C and 21D, the wafer 10 is flipped over and attached to the surface of the second wafer 20 at the surface 106a of the third dielectric layer. The second wafer 20 may be a carrier wafer or a CMOS wafer including an integrated circuit necessary for the operation of the vertical via device. A permanent bond is achieved between the wafer 10 and the wafer 20. There are several methods known in the art for permanent wafer bonding. An example of the bonding process is described in the international application WO2020 / 104987A1 in the name of the applicant of the present application. Using the CMOS wafer 20 as a carrier wafer, the hall sensor wafer 10 is processed from its back surface 101c.

[0048] As shown in FIG. 21E, the wafer 10 has most of the silicon material removed and is thinned from the back surface. The second substrate surface of the wafer 10 obtained after thinning is denoted by 101b. The thickness of the remaining semiconductor substrate 101 can preferably be in the range of 10 to 50 micrometers.

[0049] Continuing with FIG. 21F, regions 3 and 4, which are shallow and highly doped with an n-type conductivity type, are formed on the second surface 101b in the same manner as the highly doped regions 1 and 2 of the first surface. In particular, the same implant species, implant dose, and energy used on the first surface to create the doping regions 1 and 2 are used. More specifically, after resist removal, the same laser thermal annealing conditions used on the first surface to activate the doping regions 1 and 2 are applied. As will be understood by those skilled in the art, by using laser thermal annealing for dopant activation of the second surface, as opposed to other activation methods such as furnace annealing or rapid thermal processing, the aluminum-based metallization of the first surface of the hall sensor wafer 10 can be prevented from being destroyed by the heat treatment. Further, further, the laser thermal annealing is not added to the heat budget of the devices formed on the CMOS wafer 20.

[0050] As shown in FIG. 21G, a dielectric structure 19 is created that extends from the second surface 101b to the first surface 101a of the substrate and laterally surrounds a part of the substrate layer 101 including the Hall sensor region (Hall plate) 103. The dielectric structure is created by a deep trench isolation process well known in the art.

[0051] Referring to FIG. 21H, a first dielectric layer 107 is deposited on the second surface 101b using the same process and materials as those used for the first dielectric layer 104 on the first side.

[0052] Referring to FIG. 21I, a deep silicon etching process is performed using a silicon nitride layer as a hard mask, and via openings 11 are formed. The deep silicon etching is first selectively stopped on the oxide layer 104. A thin oxide layer 181 is deposited. More specifically, the layer 181 can be tetraethyl orthosilicate (TEOS) deposited by plasma enhanced chemical vapor deposition (PECVD) at a temperature not exceeding 400°C. The oxide layer 181 functions as a dielectric liner on the silicon sidewalls exposed by the preceding deep silicon etching. The thickness of the oxide layer 181 can be, for example, 3000 angstroms, but is not limited to this value.

[0053] Next, the thin oxide 181 is etched at the bottom of the deep silicon via opening 11. The dry etching selectively stops at the titanium nitride barrier layer of the metal structure 110. The via opening 11 is filled with a metal layer, which can be a tungsten-based metal layer or, more preferably, a copper-based metal layer.

[0054] Looking at FIG. 21K, contact trenches or holes 17 are formed through the dielectric layer 107 by a photomask etching process so that the highly doped regions 3 and 4 are exposed. Thanks to the high selectivity to silicon, etching can be stopped within the shallow, highly doped regions 3 and 4, and the doping concentration on the silicon surface inside the trenches or holes 17 is 1020 atoms / cm3 from 1022 atoms / cm 3 can be in the range of.

[0055] The first metal layer 150 is deposited on the dielectric layer 107 and fills the contact trench or via 17. The same processes and materials as for the metal layer 110 on the first surface are applied. After deposition, the metal layer is structured by a photomask etching process as shown in FIG. 21L. As shown, the metal structure 150 completely covers the upper surfaces of the through-silicon vias 140b and 141b and realizes an electrical connection between the two through-silicon vias.

[0056] Next, the inter-metal dielectric layer 108 is deposited on the metal structure 150. The same processes and materials as for the first inter-metal dielectric 105 are used. As shown in FIG. 21M, a via structure is etched through the inter-metal dielectric layer 108 and filled with metal layers 160b and 161b. Next, the second metal layer 170 is deposited on top of the inter-metal dielectric layer 108 and structured to electrically connect the vias 160b and 161b by the metal portion 170b. The processes and materials for filling the vias with metal and forming the metal layer portion 170b are the same as in the case of the second metal layer 130 on the first side of the substrate. Finally, the dielectric layer 182 is deposited on top of the metal structure 170 and on the exposed inter-metal dielectric layer 108.

[0057] The advantages of the proposed solution are apparent from the foregoing description.

[0058] In particular, the hall sensor is configured such that the inductor coil for testing and calibration induces a uniform and homogeneous magnetic field in the hall plate of the vertical or horizontal hall sensor element.

[0059] Finally, it is clear that modifications and variations can be made to what is described and illustrated herein without departing from the scope of the invention as defined in the appended claims.

Description of Reference Numerals

[0060] 1, 2, 3, 4 High-doped regions 10, 20, 30 Wafers 100 Hall sensor products 101, 201 Substrates 101a, 10b Surfaces 103 Hall plates 104 Dielectric layers 105 Dielectric layers 106 Dielectric layers 107 Dielectric layers 108 Dielectric layers 109 Dielectric structures 110 Metal layers 110b, 112, 111, 111b Metal parts 115 Metal parts 121b Vias 125 Vias 130 Metal layers 130a Coils 130b Metal wires 135 Metal bars 140b, 141b Through-silicon vias 150 Metal layers 150b, 153, 154 Metal parts 160b, 161b Vias 170 Metal layers 170b Metal parts 181 Dielectric liners 182 Dielectric layers 1001 Internal volumes H1, H2, H3, H4 Vertical Hall elements C1, C2, C3 Coils D1, D2 Semiconductor devices

Claims

Claim 1: A main wafer (10) of semiconductor material comprising a substrate (101) having a first surface (101a) and a second surface (101b) opposite the first surface (101a) along a vertical axis (y), at least one vertical Hall sensor element (H1) having a first pair of Hall sensor terminals (1, 2) formed on the first surface (101a) of the substrate (101) and a second pair of Hall sensor terminals (3, 4) formed on the second surface (101b) of the substrate (101) on the opposite side of the first pair of Hall sensor terminals, a separation structure (109) in the substrate (101) defining a Hall sensor plate (103) of an integrated Hall sensor, the Hall sensor terminals being disposed inside the separation structure (109), wherein the integrated Hall sensor further comprises at least one test and calibration coil (C1) integrated in the main wafer (10) having a plurality of windings, each winding of the test or calibration coil comprising a first metal portion (130b) formed on a first dielectric layer structure (104, 105) disposed on the first surface (101a) of the substrate (101), a second metal portion (170b) formed on a second dielectric layer structure (107, 108) disposed on the second surface (101b) of the substrate (101), and a through-silicon via (140b, 141b) extending through the substrate (101) and coupled to the first and second metal portions (130b, 170b), wherein the plurality of windings define an internal volume (1001) encompassing the entire Hall sensor plate (103), wherein at least one first outer dielectric layer (106) is disposed on the first dielectric structure (104, 105), the main wafer (10) is attached to a second wafer (20) at the upper surface of the outer dielectric layer (106), the second wafer (20) being configured to thin the main wafer (10) such that the thinned second surface (101b) of the substrate (101) is defined, and the final thickness of the substrate (101) is in the range of 10 to 50 micrometers. An integrated Hall sensor. Claim 2 The hall sensor terminals (1, 2, 3, 4) extend along a first horizontal axis (z) of a plane parallel to the first and second surfaces (101a, 101b) of the substrate (101), and the first and second metal portions (130b, 170b) extend along a second horizontal axis (x) of the plane that crosses the first horizontal axis (z). The integrated hall sensor according to claim 1, wherein each of the windings of the test or calibration coil has a rectangular cross-section in a plane defined by the second horizontal axis (x) and the vertical axis (y), is connected in series, and is arranged along the first horizontal axis (z). **Claim 3** The integrated hall sensor according to claim 1 or 2, wherein the through-silicon vias (140b, 141b) have the same lateral distance with respect to the hall sensor plate (103). **Claim 4** The integrated hall sensor according to any one of claims 1 to 3, wherein the through-silicon vias (140b, 141b) defining the windings of the test or calibration coil are spaced apart from the hall sensor plate (103) so as not to contribute to the magnetic field induced in the hall sensor plate (103). **Claim 5** Further comprising an outer coil formed on the main wafer (10) having a plurality of windings, each including a first metal portion (230b) formed on a first outer dielectric layer (106) disposed on the first dielectric structures (104, 105), a second metal portion (270b) formed on a second outer dielectric layer (182) disposed on the second dielectric structures (107, 108), and through-silicon vias (142b, 143b) extending through the substrate (101) and coupled to the first and second metal portions (230b, 270b). The integrated hall sensor according to any one of claims 1 to 4, wherein the outer coil is connected in series with the test or calibration coil. **Claim 6** Further comprising an outer coil having a plurality of windings formed on the main wafer (10), each including a first metal portion (234) formed on a first outer dielectric layer (106) disposed on the first dielectric structures (104, 105), and a second metal portion (275) formed on a second outer dielectric layer (182) disposed on the second dielectric structures (107, 108). The integrated Hall sensor according to any one of claims 1 to 4, wherein the direction of the outer coil is rotated 90 degrees with respect to the test or calibration coil.

7. The integrated Hall sensor according to claim 6, wherein the vertical Hall sensor element is a circular vertical Hall element (CVH) including a Hall sensor plate (103) having a ring shape that is entirely disposed in the internal volume (1001) commonly defined by the outer coil and the test or calibration coil.

8. A method of manufacturing an integrated Hall sensor, comprising: a) providing a main wafer (10) including a first-conductivity-type semiconductor substrate (101) having a first surface (101a) and a second surface 101(c); b) forming Hall sensor terminals on a first side of the main wafer (10) by forming shallow and highly doped regions 1 and 2 having a first conductivity type on the first surface (101a) of the main wafer (10); c) contacting the Hall sensor terminals by filling contact holes formed in a first dielectric layer (104) with a first metal layer (110); d) depositing a second dielectric layer (105), forming vias (121b) that penetrate the second dielectric layer (105) and stop on the first metal layer (110), filling the vias (121b) with a metal layer, depositing a second metal layer (130) on the second dielectric layer (105), and etching the second metal layer (130) to form a first winding of a test and calibration coil; e) depositing and planarizing a third dielectric layer (106) on the second metal layer (130) and the exposed second dielectric layer (105); f) flipping the main wafer (10), attaching a second wafer (20) onto the surface of the third dielectric layer (106) by a permanent bond, and thinning the main wafer (10) from the second surface to a thickness in the range of 10 to 50 micrometers; g) forming Hall sensor terminals on the thinned second surface (101b) of the main wafer (10) by forming shallow and highly doped regions 3 and 4 having a first conductivity type on the thinned second surface (101b) of the semiconductor substrate (101) of the main wafer (10); h) forming a deep trench isolation structure (109) that extends from the thinned second surface (101b) of the semiconductor substrate (101) to the first surface (101a) and laterally surrounds a portion of the semiconductor substrate (101) including the hall sensor region (103); i) depositing a first dielectric layer (107) on the thinned second surface (101b), forming through-silicon vias (140b and 141b) that selectively stop on the first metal structure (111b) by a deep silicon etching process, and filling the through-silicon vias (140b and 141b) with a metal layer; l) contacting the hall sensor terminals on the thinned second surface (101b) of the main wafer (10) by filling contact holes (17) formed in the first dielectric layer (107) with a first metal layer (150); m) depositing a second dielectric layer (108) on the first metal layer (150), forming vias (160b and 161b) that penetrate the second dielectric layer (108) and stop on the first metal layer (150), filling the vias (160b and 161b) with a metal layer, depositing a second metal layer (170) on the second dielectric layer (108), and etching the metal layer (170) to form a second winding of a test and calibration coil; n) depositing a third dielectric layer (182) on the second metal layer (170) and the exposed second dielectric layer (108); A method of manufacturing an integrated hall sensor, comprising the steps above.

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