Error Rate Management in a Heterogeneous Memory Array

Abstract

To provide a method, apparatus and system for applying address offsets to generate offset addresses.SOLUTION: In a memory system, a plurality of control circuits are configured to individually connect to arrays that each include a plurality of non-volatile memory cells. Each non-volatile memory cell includes a programmable resistive element. Each control circuit is configured with an individual address offset. The plurality of control circuits are configured to: receive a read address from a memory controller in parallel, apply the respective individual address offsets to the read address to generate respective offset addresses, read portions of data from the respective offset addresses and send the data read from the offset addresses to the memory controller to perform Error Correction Code (ECC) decoding of the portions of data.SELECTED DRAWING: Figure 22

Description

Technical Field

[0001] (Claim of Priority) This application claims the priority of U.S. Provisional Patent Application No. 63 / 505,300, entitled "ERROR RATE MANAGEMENT IN NON-UNIFORM MEMORY ARRAYS," filed on May 31, 2023 by Houssameddine et al., which is hereby incorporated by reference in its entirety.

Background Art

[0002] Memory is widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory enables information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0003] An example of non-volatile memory is magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data, as opposed to some other memory technologies that use electric charges to store data. Generally, MRAM includes a number of magnetic memory cells formed on a semiconductor substrate, where each memory cell represents (at least) 1 bit of data. Bits of data are written to the memory cell by changing the magnetization direction of a magnetic element within the memory cell, and the bits are read by measuring the resistance of the memory cell (low resistance typically represents a "0" bit and high resistance typically represents a "1" bit). As used herein, the magnetization direction is the direction in which the magnetic moment is oriented.

[0004] MRAM is a promising technology, but various phenomena can cause errors in the data stored in MRAM. An Error Correction Code (ECC) can be used to correct such errors. Correcting errors using ECC requires significant resources and can take a significant amount of time. In some cases, the data may have too many errors to be corrected using a given ECC scheme. Such data can be considered Uncorrectable by ECC, or "UE" for short. It is difficult to manage the impact of errors in an efficient manner so that the data corrected by ECC can be reliably and efficiently generated from the data stored in MRAM.

Brief Description of the Drawings

[0005] Like-numbered elements refer to common components in different figures.

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Best Mode for Carrying Out the Invention

[0006] In a memory array having a cross-point architecture, a first set of conductive lines extends across the surface of a substrate, and a second set of conductive lines is formed over the first set of conductive lines and extends over the substrate in a direction perpendicular to the first set of conductive lines. Memory cells are disposed at the cross-point junctions of the two sets of conductive lines. Embodiments of the memory cells can include programmable resistive elements, such as MRAM memory cells, connected in series with a selector switch. Certain types of selector switches are threshold switching selectors, such as ovonic threshold switches, which can be implemented in a small area without the need for additional control lines relative to other switching elements, such as transistors. When a voltage above a particular level, i.e., a threshold voltage, is applied to the threshold switching selector, the threshold switching selector switches to a conductive state.

[0007] Data can be read from a plurality of MRAM memory cells and transmitted to an ECC circuit for decoding. In such data, errors can occur for many reasons. Data from some structured MRAM memory cells may be affected by a "snapback disturb" caused by a relatively high current called a "snapback current". The snapback current can be affected by several factors, such as the distance of a given memory cell from the word line driver and the bit line driver (e.g., the length of the electrical connection from the memory cell to the word line driver and the bit line driver), which can make the snapback-related effects non-uniform. For example, memory cells closer to the word line driver and / or the bit line driver (near cells) may have a higher snapback current than memory cells farther from the word line driver and / or the bit line driver (far cells) and may be more affected by the snapback disturb. As a result, data from near memory cells may have a higher error rate than data from far memory cells. Other phenomena can also have non-uniform effects.

[0008] In one embodiment, the data encoded by ECC and decoded together (e.g., as ECC codewords) can be located at different respective positions within different arrays (e.g., some data in nearby cells and some data in distant cells), such that the error rates of memory cells at multiple positions are combined, thereby providing an average error rate and mitigating the effects of non-uniform error rates within the memory array. This can provide a relatively uniform error rate across different ECC codewords, such that the risk to the UE is relatively low. For example, different media (e.g., different memory dies) can apply different address offsets to the address such that each media accesses its respective memory array at different positions.

[0009] FIG. 1 is a block diagram of one embodiment of a memory system 100 connected to a host 120. The memory system 100 can implement the techniques presented herein to manage error rates. Many different types of memory systems can be used with the techniques proposed herein. Examples of memory systems include solid state drives (“SSD”), memory cards including dual in-line memory modules (“DIMM”) for DRAM replacement, and embedded memory devices. However, other types of memory systems can also be used.

[0010] The memory system 100 of FIG. 1 includes a controller 102, a non-volatile memory 104 for storing data, and a local memory (e.g., DRAM / ReRAM / MRAM) 106. The controller 102 includes a front-end processor (FEP) circuit 110 and one or more back-end processor (BEP) circuits 112. In one embodiment, the FEP circuit 110 is implemented on an application-specific integrated circuit (ASIC). In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. In other embodiments, an integrated controller ASIC can combine both front-end and back-end functions. Each ASIC of the BEP circuit 112 and the FEP circuit 110 is implemented on the same semiconductor such that the controller 102 is manufactured as a system-on-chip (“SoC”). Both the FEP circuit 110 and the BEP circuit 112 include their own processors. In one embodiment, the FEP circuit 110 and the BEP circuit 112 function as a master-slave configuration where the FEP circuit 110 is the master and each BEP circuit 112 is the slave. For example, the FEP circuit 110 implements a flash translation layer (FTL) or a media management layer (MML) that performs memory management (e.g., garbage collection, wear leveling, etc.), address translation from logical addresses to physical addresses, communication with the host, management of DRAM (local volatile memory), and management of the overall operation of an SSD (or other non-volatile memory system). The BEP circuit 112 manages memory operations within the memory package / die upon request from the FEP circuit 110. For example, the BEP circuit 112 can perform read, erase, and programming processes. Further, the BEP circuit 112 can perform buffer management, setting of specific voltage levels required by the FEP circuit 110, error correction (ECC), control of the toggle mode interface to the memory package, etc. In one embodiment, each BEP circuit 112 is responsible for a set of its own memory packages.

[0011] In one embodiment, the non-volatile memory 104 includes a plurality of memory packages. Each memory package includes one or more memory dies. Accordingly, the controller 102 is connected to one or more non-volatile memory dies. In one embodiment, each memory die within the memory package 104 utilizes a NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package can include other types of memory such as resistive random access memory (ReRAM, MRAM, FeRAM, or RRAM, etc.) or storage class memory (SCM) based on phase change memory (PCM). In other embodiments, BEP or FEP can be included on the memory die.

[0012] The controller 102 communicates with the host 120 via an interface 130 that implements a protocol such as Compute Express Link (CXL) over, for example, NVM Express (NVM Express, NVMe) or PCI Express (PCI Express, PCIe), or uses a JEDEC standard Double Data Rate or Low-Power Double Data Rate (DDR or LPDDR) interface such as DDR5 or LPDDR5. To cooperate with the memory system 100, the host 120 includes a host processor 122 connected along a bus 128, a host memory 124, and a PCIe interface 126. The host memory 124 is the physical memory of the host and can be DRAM, SRAM, MRAM, non-volatile memory, or another type of storage. The host 120 is external to the memory system 100 and is separate from the memory system 100. In one embodiment, the memory system 100 is embedded within the host 120.

[0013] Figure 2 is a block diagram of an embodiment of the FEP circuit 110. Figure 2 shows a PCIe interface 150 that communicates with a host 120 and a host processor 152 that communicates with the PCIe interface. The host processor 152 can be any type of processor known in the art suitable for implementation. The host processor 152 communicates with a network-on-chip (NOC) 154. The NOC is typically a communication subsystem on an integrated circuit between cores within a SoC. The NOC can use synchronous and asynchronous clock domains or asynchronous logic that is not locked. NOC technology applies networking theory and methods to on-chip communication, resulting in significant improvements over conventional bus and crossbar interconnects. The NOC improves the scalability of the SoC and the power efficiency of complex SoCs compared to other designs. The wires and links of the NOC are shared by many signals. Since all links within the NOC can operate simultaneously on different data packets, a high level of parallelism is achieved. Thus, as the complexity of the integrated subsystem continues to increase, the NOC provides improved performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). A memory processor 156, SRAM 160, and a DRAM controller 162 are connected to and communicate with the NOC 154. The DRAM controller 162 is used to operate and communicate with a DRAM (e.g., DRAM 106). The SRAM 160 is local RAM memory used by the memory processor 156. The memory processor 156 is used to operate the FEP circuit and execute various memory operations. Also communicating with the NOC are two PCIe interfaces 164, 166. In the embodiment of Figure 2, the SSD controller includes two BEP circuits 112. Thus, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other embodiments, there may be more or fewer than two BEP circuits 112.Accordingly, there may be three or more PCIe interfaces.

[0014] The FEP circuit 110 may also include a flash translation layer (FTL), or more generally a media management layer (MML) 158, which performs memory management (e.g., garbage collection, wear leveling, load balancing, etc.), address translation from logical addresses to physical addresses, communication with the host, management of DRAM (local volatile memory), and overall operation management of the SSD (or other non-volatile storage system). The media management layer MML 158 can be integrated as part of memory management that can handle memory errors and interfaces with the host. Specifically, the MML may be a module within the FEP circuit 110 and may be in charge of the internal part of memory management. Specifically, the MML 158 can include algorithms in the memory device firmware that convert writes from the host into writes to the memory structure (e.g., 502 / 602 of FIGS. 5 and 6 below). The MML 158 may be required because 1) the durability of the memory may be limited, 2) the memory structure can only be written in multiples of pages, and / or 3) the memory structure cannot be written unless it is erased as a block. The MML 158 understands these potential constraints of the memory structure, which may not be visible to the host. Accordingly, the MML 158 attempts to convert writes from the host into writes into the memory structure.

[0015] FIG. 3 is a block diagram of one embodiment of the BEP circuit 112. FIG. 3 shows a PCIe interface 200 for communicating with the FEP circuit 110 (e.g., communicating with one of the PCIe interfaces 164 and 166 of FIG. 2). The PCIe interface 200 is communicating with two NOCs 202 and 204. In one embodiment, the two NOCs can be combined into one large NOC. Each NOC (202 / 204) is connected to an SRAM (230 / 260), a buffer (232 / 262), a processor (220 / 250), and a data path controller (222 / 252) via an XOR engine (224 / 254) and an ECC engine (226 / 256). The ECC engines 226 / 256 are used to perform error correction as is known in the art. The XOR engines 224 / 254 are used to XOR the data so that the data can be combined and stored in a way that can be restored in case of programming errors. The data path controller 222 is connected to an interface module for communicating with the memory package via four channels. Thus, the upper NOC 202 is associated with an interface 228 for four channels for communicating with the memory package, and the lower NOC 204 is associated with an interface 258 for four additional channels for communicating with the memory package. Each interface 228 / 258 includes four toggle mode interfaces (TM interfaces), four buffers, and four schedulers. For each of the channels, there is one scheduler, buffer, and TM interface. The processor can be any standard processor known in the art. The data path controllers 222 / 252 can be a processor, an FPGA, a microprocessor, or other type of controller. The XOR engines 224 / 254 and the ECC engines 226 / 256 are dedicated hardware circuits known as hardware accelerators. In other embodiments, the XOR engines 224 / 254 and the ECC engines 226 / 256 can be implemented in software.The scheduler, buffer, and TM interface are hardware circuits.

[0016] FIG. 4 is a block diagram of one embodiment of a memory package 104 that includes a plurality of memory dies 292 connected to a memory bus (data line and chip enable line) 294. The memory bus 294 is connected to a toggle mode interface 296 for communicating with the TM interface of the BEP circuit 112 (see, e.g., FIG. 3). In some embodiments, the memory package can include a small controller connected to the memory bus and the TM interface. The memory package can have one or more memory dies. In one embodiment, each memory package includes 8 or 16 memory dies, although other numbers of memory dies can also be implemented. In another embodiment, the toggle interface is instead a JEDEC standard DDR or LPDDR with or without variations such as relaxed timing sets or smaller page sizes. The techniques described herein are not limited to a particular number of memory dies.

[0017] FIG. 5 is a block diagram depicting an example of a memory system 500 that can implement the techniques described herein. The memory system 500 includes a memory array 502 that can include any of the memory cells described below. The array demarcation lines of the memory array 502 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations can also be implemented. The memory system 500 includes a row control circuit 520, whose output 508 is connected to each word line of the memory array 502. The row control circuit 520 receives a group of M row address signals and one or more various control signals from the system control logic circuit 560, and can typically include circuits such as a row decoder 522, an array termination driver 524 (e.g., a word line driver), and a block selection circuit 526 for both read and write operations. The memory system 500 also includes a column control circuit 510, whose input / output 506 is connected to each bit line of the memory array 502. Although only a single block is shown for the memory array 502, the memory die can include multiple arrays, i.e., "tiles", that can be accessed individually. The column control circuit 510 receives a group of N column address signals and one or more various control signals from the system control logic 560, and can typically include circuits such as a column decoder 512, an array termination receiver or driver 514 (e.g., a bit line driver), a block selection circuit 516, and circuits such as a read / write circuit and an I / O multiplexer.

[0018] System control logic 560 receives data and instructions from a host and provides output data and status to the host. In other embodiments, system control logic 560 receives data and instructions from a separate controller circuit, provides output data to that controller circuit, and the controller circuit communicates with the host. In some embodiments, system control logic 560 can include a state machine that provides die-level control of memory operations. In one embodiment, the state machine is programmable by software. In other embodiments, state machine 112 is implemented entirely within hardware (e.g., an electrical circuit) without using software. In another embodiment, the state machine is replaced by a microcontroller that turns the memory chip either on or off. System control logic 560 can also include a power control module that controls the power and voltage supplied to the rows and columns of memory array 502 during memory operations, and can include a charge pump and regulator circuitry for generating regulated voltages. System control logic 560 may include one or more state machines, registers, and other control logic to control the operation of memory system 500. FIG. 5 shows such a register, 561, that can be used to store data, such as an offset that can be used when accessing (e.g., reading or writing) a memory cell of memory array 502. In some embodiments, all of the elements of memory system 500 that include system control logic 560 can be formed as part of a single die. In other embodiments, some or all of system control logic 560 can be formed on different dies.

[0019] For the purposes of this specification, the phrase "one or more control circuits" can include a controller, a state machine, a microcontroller, and / or other control circuits represented by system control logic 560, or other similar circuits used to control non-volatile memory.

[0020] In one embodiment, the memory structure 502 includes a three-dimensional memory array of non-volatile memory cells in which multiple memory levels are formed on a single substrate such as a wafer. The memory structure can include any type of non-volatile memory that is monolithically formed on one or more physical levels of memory cells having an active area disposed on a silicon (or other type of) substrate. In one example, the non-volatile memory cells include vertical NAND strings having charge traps.

[0021] In another embodiment, the memory structure 502 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (e.g., NOR-type flash memory) can also be used.

[0022] The exact type of memory array architecture or memory cells included in the memory structure 502 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form the memory structure 326. For the purposes of the newly claimed embodiments proposed herein, no particular non-volatile memory technology is required. Other examples of technologies suitable for the memory cells of the memory structure 502 include ReRAM memory (resistive random access memory), magnetic resistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of technologies suitable for the memory cell architecture of the memory structure 502 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.

[0023] As an example of a ReRAM cross-point memory, there is a resistive switching element disposed in a cross-point array accessed by X and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallization cell. The conductive bridge memory element can be used as a state change element based on the physical rearrangement of ions in a solid electrolyte. In some cases, the conductive bridge memory element may include two solid metal electrodes having a thin solid electrolyte film between the two electrodes, one of which is relatively inert (e.g., tungsten) and the other of which is electrochemically active (e.g., silver or copper). As the temperature increases, the mobility of the ions also increases, and the programming threshold of the conductive bridge memory cell decreases. Thus, the conductive bridge memory element can have a wide range of programming thresholds with respect to temperature.

[0024] Another example is a magnetic random access memory (MRAM) that uses magnetic memory elements to store data. The element is formed from two ferromagnetic layers, each of which can hold magnetization, separated by a thin insulating layer. One of the two layers is a permanent magnet set to a particular polarity. The magnetization of the other layer can be changed to match the magnetization of an external field to store memory. The memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is between a pair of write lines arranged perpendicular to each other, parallel to the cell, one above the cell and one below the cell. When current passes through them, an induced magnetic field is generated. MRAM-based memory embodiments are discussed in more detail below.

[0025] Phase change memory (PCM) utilizes the unique behavior of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase change by simply changing the regulated state of germanium atoms with a programming current pulse. In this document, the use of "pulse" does not require a square pulse, but includes sound vibrations or bursts (continuous or discontinuous), current, voltage, light, or other waves. This memory element within an individual selectable memory cell or bit may include additional series elements that are selectors such as an ovonic threshold switch or a metal-insulator substrate.

[0026] Those skilled in the art will understand that this technology described herein is not limited to a single specific memory structure, memory construction, or material composition, but rather covers many related memory structures within the spirit and scope of the technology as described herein and understood by those skilled in the art.

[0027] The elements in FIG. 5 can be grouped into two parts: the structure of the memory cell's memory structure 502 and the peripheral circuits including all other elements. An important characteristic of the memory circuit is its capacity, which can be increased by increasing the area of the memory die of the memory system 500 provided to the memory structure 502. However, this reduces the area of the memory die available for the peripheral circuits. This can impose very strict limitations on these peripheral elements. For example, the need to fit a sense amplifier circuit within the available area can be a significant limitation on the sense amplifier design architecture. Regarding the system control logic 560, the reduction in area availability can limit the available functions that can be implemented on-chip. Therefore, the basic trade-off in the design of the memory die for the memory system 500 is the amount of area spent on the memory structure 502 and the amount of area spent on the peripheral circuits.

[0028] Another area where the memory structure 502 and the peripheral circuits often conflict is included in the processes involved in the formation of these areas, because these areas often involve different process technologies, which is a trade-off for having different technologies on a single die. For example, if the memory structure 502 is NAND flash, which is an NMOS structure, the peripheral circuits are often CMOS-based. For example, elements such as such sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in the system control logic 560 often use PMOS devices. The process operations for manufacturing a CMOS die are different in many aspects from the process operations optimized for NMOS flash NAND memory or other memory cell technologies.

[0029] To improve these limitations, the embodiments described below can separate the elements of FIG. 5 onto separately formed dies, and then the dies are bonded to each other. More specifically, the memory structure 502 can be formed on one die, and some or all of the peripheral circuit elements including one or more control circuits can be formed on separate dies. For example, the memory die can be formed of only memory elements such as an array of memory cells of flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory types. Some or all of the peripheral circuits can be moved to a separate die later, even if they include elements such as decoders and sense amplifiers. This allows each of the memory dies to be individually optimized according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without worrying about the CMOS elements moved onto a separate peripheral circuit die optimized for a CMOS process. This allows for more space for the peripheral elements, and thus additional features that could not be easily incorporated if limited to the margins of the same die holding the memory cell array can be incorporated. The two dies can then be bonded to each other within the bonded multi-die memory circuit, and the array on one die is connected to the peripheral elements on the other memory circuit. Below, the focus is on a bonded memory circuit of one memory die and one peripheral circuit die, but other embodiments can use more dies, such as two memory dies and one peripheral circuit die, for example.

[0030] Figures 6A and 6B show an alternative arrangement of FIG. 5 that can be implemented using wafer-to-wafer bonding to provide a bonded die pair for memory system 600. FIG. 6A shows an example of a peripheral circuit including a control circuit formed in a peripheral circuit or control die 611 coupled to a memory structure 602 formed within a memory die 601. Similar to 502 of FIG. 5, memory die 601 can include a plurality of independently accessible arrays or “tiles”. Common components are labeled the same as in FIG. 5 (e.g., 502 is 602 here, 510 is 610 here, and so on). It can be seen that system control logic 659, row control circuit 620, and column control circuit 610 (which can be formed by a CMOS process) are located within control die 611. Additional elements such as functions from controller 102 can also be moved within control die 611. System control logic 659, row control circuit 620, and column control circuit 610 can be formed by a common process (e.g., a CMOS process), whereby additional elements and functions typically found on memory controller 102 may require few or no additional process steps (i.e., system control logic 659, row control circuit 620, and column control circuit 610 can be fabricated using the same process steps used to manufacture controller 102). Thus, while moving such circuits from a die such as the memory die of memory system 500, the number of steps required to manufacture such a die can be reduced, and adding such circuits to a die such as control die 611 may not require any additional process steps.

[0031] FIG. 6A shows a column control circuit 610 on a control die 611 coupled to a memory structure 602 on a memory die 601 via an electrical path 606. For example, the electrical path 606 may provide an electrical connection between a column decoder 612, a driver circuit 614, and a block selection section 616 and the bit lines of the memory structure 602. The electrical path may extend from the column control circuit 610 within the control die 611 via pads on the control die 611 that are joined to corresponding pads of the memory die 601 connected to the bit lines of the memory structure 602. Each bit line of the memory structure 602 may have a corresponding electrical path within the electrical path 606 that includes a pair of joined pads that connect to the column control circuit 610. Similarly, a row control circuit 620, including a row decoder 622, an array driver 624, and a block selection 626, is coupled to the memory structure 602 via an electrical path 608. Each electrical path 608 may correspond to a word line, a dummy word line, or a select gate line. Further, additional electrical paths may be provided between the control die 611 and the memory die 601.

[0032] FIG. 6B is a block diagram showing in more detail the configuration of one embodiment of an integrated memory assembly 600 formed by a pair of joined dies. The memory die 601 includes an array 602 of memory cells. The memory die 601 may have additional arrays (e.g., multiple modules each including an array). For the array 602, one representative bit line (BL) and a representative word line (WL) 666 are shown. There may be thousands or tens of thousands of such bit lines for each array 602. In one embodiment, the array represents a group of connected memory cells that share a common set of unbroken word lines and unbroken bit lines.

[0033] The control die 611 includes several bit line drivers 650. Each bit line driver 650 may be connected to one bit line or, in some embodiments, to multiple bit lines. The control die 611 includes several word line drivers 660(1) - 660(n). The word line drivers 660 are configured to provide a voltage to the word lines. In this example, there are "n" word lines per array or planar memory cell. When the memory operation is a program or a read, in one embodiment, one word line within the selected block is selected for the memory operation. When the memory operation is an erase, in one embodiment, all of the word lines within the selected block are selected for the erase. The word line drivers 660 provide a voltage to the word lines within the memory die 601. As described above with respect to FIG. 6A, the control die 611 may also include a charge pump, a voltage generator, etc., not shown in FIG. 6B, that can be used to provide a voltage to the word line drivers 660 and / or the bit line drivers 650.

[0034] The memory die 601 has several bond pads 670a, 670b on a first major surface 682 of the memory die 601. There may be "n" bond pads 670a to receive a voltage from the corresponding "n" word line drivers 660(1) - 660(n). There may be one bond pad 670b for each bit line associated with the array 602. The reference numeral 670 is generally used to refer to the bond pads on the major surface 682.

[0035] In some embodiments, each data bit and each parity bit of the codeword are transferred through different bond pad pairs 670b, 674b. The bits of the codeword can be transferred in parallel through the bond pad pairs 670b, 674b. This provides a very efficient data transfer, for example, with respect to transferring data between the memory controller 102 and the integrated memory assembly 600. For example, the data bus between the memory controller 102 and the integrated memory assembly 600 can transfer 8 bits, 16 bits, or 32 bits or more in parallel. However, the data bus between the memory controller 102 and the integrated memory assembly 600 is not limited to these examples. Such ECC may be implemented on the memory die in some embodiments.

[0036] The control die 611 has several bond pads 674a, 674b on the first main surface 684 of the control die 611. There may be "n" bond pads 674a to deliver voltage from the corresponding "n" word line drivers 660(1) to 660(n) to the memory die 601. There may be one bond pad 674b for each bit line associated with the array 602. The reference numeral 674 is generally used to refer to the bond pads on the main surface 682. Note that bond pad pairs 670a / 674a and bond pad pairs 670b / 674b may exist. In some embodiments, the bond pads 670 and / or 674 are flip chip bond pads.

[0037] In one embodiment, the pattern of bond pad 670 matches the pattern of bond pad 674. Bond pad 670 is bonded (e.g., flip-chip bonded) to bond pad 674. Thus, bond pads 670 and 674 electrically and physically couple memory die 601 to control die 611. Also, bond pads 670 and 674 enable internal signal transfer between memory die 601 and control die 611. Accordingly, memory die 601 and control die 611 are joined together by the bond pads. FIG. 6A shows one control die 611 bonded to one memory die 601, but in another embodiment, one control die 611 is bonded to a plurality of memory dies 601.

[0038] As used herein, "internal signal transfer" means signal transfer between control die 611 and memory die 601. Internal signal transfer enables circuits on control die 611 to control memory operations within memory die 601. Thus, bond pads 670 and 674 can be used for memory operation signal transfer. As used herein, "memory operation signal transfer" refers to any signal related to memory operations within memory die 601. Memory operation signal transfer can include, but is not limited to, providing a voltage, providing a current, receiving a voltage, receiving a current, sensing a voltage, and / or sensing a current.

[0039] Bond pads 670 and 674 may be formed of, for example, copper, aluminum, and alloys thereof. A liner may be present between bond pads 670 - 674 and the main surfaces (682 - 684). The liner may be formed of, for example, a titanium / titanium nitride stack. Bond pads 670 and 674 and the liner may be applied by vapor deposition and / or plating techniques. The bond pads and the liner may together have a thickness of 720 nm, but in further embodiments, this thickness may be greater or smaller.

[0040] Metal interconnects and / or vias can be used to electrically connect various elements within the die to bond pads 670 - 674. Several conductive paths that can be implemented by the metal interconnects and / or vias are shown. For example, a sense amplifier can be electrically connected to bond pad 674b by path 664. With respect to FIG. 6A, electrical path 606 can correspond to path 664, bond pad 674b, and bond pad 670b. Thousands of such sense amplifiers, paths, and bond pads can exist. Note that BL does not necessarily make a direct connection to bond pad 670b. The word line driver 660 can be electrically connected to bond pad 674a by path 662. With respect to FIG. 6A, electrical path 608 can correspond to path 662, bond pad 674a, and bond pad 670a. Note that path 662 can include a separate conductive path for each word line driver 660(1) - 660(n). Similarly, a separate bond pad 674a can exist for each word line driver 660(1) - 660(n). The word lines within block 2 of memory die 601 can be electrically connected to bond pad 670a by path 664. In FIG. 6B, there are “n” paths 664 for the corresponding “n” word lines within the block. For each path 664, a separate pair of bond pads 670a, 674a can exist.

[0041] Referring to FIG. 5, the on - die control circuit of FIG. 6A can also include additional functionality within its logic elements and can include capabilities more general than those typically found in memory controller 102 and some CPU functionality, as well as application - specific functionality.

[0042] In the following, the system control logic 560 / 660, column control circuits 510 / 610, row control circuits 520 / 620, and / or controller 102 (or equivalently functioning circuits) can be regarded as part of one or more control circuits that perform the functions described herein in combination with other circuits shown in FIG. 5, or all or a subset of similar elements of FIG. 6A's control die 611 and FIG. 5. The control circuit can include only hardware, or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. The control circuit can include a processor, FGA, ASIC, integrated circuit, or other types of circuits.

[0043] In the following description, the memory arrays 502 / 602 of FIGS. 5 and 6A are mainly discussed in the context of a cross-point architecture, but much of the description can be applied more generally. In a cross-point architecture, it includes a first set of conductive lines or wires, such as word lines, running in a first direction with respect to the underlying substrate, and a second set of conductive lines or wires, such as bit lines, running in a second direction with respect to the underlying substrate. Memory cells are disposed at the intersections of the word lines and the bit lines. The memory cells at these cross-points can be formed according to any of several techniques including those described above. The following description mainly focuses on embodiments based on a cross-point architecture using MRAM memory cells.

[0044] Figure 7A shows in perspective an embodiment of a portion of a memory array forming a cross-point architecture. The memory array 502 / 602 of Figure 7A is an example of an implementation of the memory array 502 of Figure 5 or the memory array 602 of Figure 6A, and a memory die can include a plurality of such array structures. Bit lines BL1 to BL5 are arranged in a first direction (represented as extending into the page) with respect to a substrate (not shown) under the die, and word lines WL1 to WL5 are arranged in a second direction (across the page) perpendicular to the first direction. Figure 7A shows that both the word lines WL1 to WL5 and BL1 to BL5 extend horizontally with respect to the substrate, while two of them, the memory cells shown at 701, are an example of a horizontal cross-point structure oriented such that the current (I cell as shown in ) extends in the vertical direction. In a memory array having an additional layer of memory cells, as will be described below with respect to Figure 7D, there are corresponding additional layers of bit lines and word lines.

[0045] As shown in Figure 7A, the memory array 502 / 602 includes a plurality of memory cells 701. The memory cells 701 may include rewritable memory cells that can be implemented using ReRAM, MRAM, PCM, FeRAM, or other materials having programmable resistance. Although the following description focuses on MRAM memory cells, most of the description can be applied more generally. The current in the memory cells at the first memory level is shown as flowing upward as indicated by the arrow I cell but the current can flow in either direction, as will be described in more detail below.

[0046] Figures 7B and 7C show a side view and a top view, respectively, of the cross-point structure of Figure 7A. The side view of Figure 7B shows one lower wire, namely word line WL1, and upper wires, namely bit lines BL1 to BL nis shown. The cross points between each upper wire and lower wire are MRAM memory cells, although PCM, FeRAM, ReRAM, or other technologies can be used. FIG. 7C shows M lower wires WL1 to WL M and N upper wires BL1 to BL N in a top view of the cross point structure. In the binary embodiment, the MRAM cell at each cross point can be programmed to one of two resistive states, high or low. Embodiments of MRAM memory cell designs and techniques for their programming will be described in more detail below.

[0047] The cross point array of FIG. 7A shows an embodiment having one layer of word lines and bit lines, where the MRAM or other memory cells are located at the intersections of two sets of conductive lines. To increase the storage density of the memory die, multiple layers of such memory cells and conductive lines can be formed. An example of two layers is shown in FIG. 7D.

[0048] FIG. 7D shows in perspective an embodiment of a portion of a two-level memory array forming a cross point architecture. Similar to FIG. 7A, FIG. 7D shows the first layer 718 of memory cells 701 of an array 502 / 602 connected at the cross points of a first layer of word lines WL 1、1 to WL 1、4 and bit lines BL1 to BL5. The second layer of memory cells 720 is above the bit lines BL1 to BL5 and between these bit lines and the word lines WL 2、1 to WL 2、4It is formed between the second set of . FIG. 7D shows two layers 718 and 720 of memory cells, but this structure can extend upward through additional alternating layers of word lines and bit lines. Depending on the embodiment, the word lines and bit lines of the array of FIG. 7D can be biased for read or program operations such that current within each layer flows from the word line layer to the bit line layer, or vice versa. The two layers can be structured to have current flow in the same direction within each layer for a given operation, e.g., having current flow from the bit line to the word line for read, or e.g., having current flow from the word line to the bit line for read in layer 1 and from the bit line to the word line for read in layer 2.

[0049] The use of a cross-point architecture enables arrays with a small footprint, and several such arrays can be formed on a single die. The memory cells formed at each cross-point can be resistance-type memory cells, and data values are encoded as different resistance levels. Depending on the embodiment, the memory cells can be binary values having either a low resistance state or a high resistance state, or multi-level cells (MLCs) that can have additional resistance intermediate the low resistance state and the high resistance state. The cross-point arrays described herein can be used as the memory die 292 of FIG. 4, can be used to replace the local memory 106, or can be used as both. Resistance-type memory cells can be formed according to many of the above techniques, such as ReRAM, FeRAM, PCM, or MRAM. The following description is presented primarily in the context of a memory array using a cross-point architecture having binary value MRAM memory cells, but much of the description can be applied more generally.

[0050] FIG. 8 shows an embodiment of the structure of an MRAM memory cell. The voltage applied to the memory cell between the corresponding word line and bit line of the memory cell is voltage source V appIt is represented as 813. The memory cell includes a lower electrode 801, a pair of magnetic layers (reference layer 803 and free layer 807) separated by a separation layer or tunnel layer of magnesium oxide (MgO) 805 in this example, and then an upper electrode 811 separated from the free layer 807 by a spacer 809. The state of the memory cell is based on the relative orientation of the magnetization of the reference layer 803 and the free layer 807. When the two layers are magnetized in the same direction, the memory cell is in a parallel (P) low resistance state (LRS), and when the two layers have opposite orientations, the memory cell is in an anti-parallel (AP) high resistance state (HRS). Embodiments of the MLC include additional intermediate states. The orientation of the reference layer 803 is fixed and is oriented upward in the example of FIG. 15. The reference layer 803 is also known as a fixed layer or pinned layer.

[0051] Data is written to the MRAM memory cell by programming the free layer 807 to either the same or opposite orientation. The reference layer 803 is formed to maintain its orientation when programming the free layer 807. The reference layer 803 can have a more complex design that includes a synthetic antiferromagnetic layer and an additional reference layer. For simplicity, the figures and description omit these additional layers and focus only on the fixed magnetic layer that mainly contributes to the tunneling magnetoresistance within the cell.

[0052] FIG. 9 shows in more detail an embodiment of an MRAM memory cell design implemented in a cross-point array. When arranged in a cross-point array, the upper and lower electrodes of the MRAM memory cell are two of the adjacent wire layers of the array, e.g., two of the upper and lower wires of a two-level or two-deck array. In the embodiment shown herein, the lower electrode is the word line 901 and the upper electrode is the bit line 911 of the memory cell, but in some embodiments, it can be reversed by inverting the orientation of the memory element. Between the word line 901 and the bit line 911, there are a reference layer 903 and a free layer 907, which are also separated by an MgO barrier 905. In the embodiment shown in FIG. 9, an MgO cap 908 is also formed on top of the free layer 907, and a conductive spacer 909 is formed between the bit line 911 and the MgO cap 908. The reference layer 903 is separated from the word line 901 by another conductive spacer 902. There are liners 921 and 923 on both sides of the memory cell structure, which can be part of the same structure, but appear separated in the cross-section of FIG. 9. A portion of the fill materials 925, 927 used to fill the areas that would otherwise be empty in the cross-point structure is shown on both sides of the liners 921, 923.

[0053] Regarding the free layer design 907, embodiments include a CoFe or CoFeB alloy having a thickness of about 1 to 2 nm, the Ir layer can be dispersed in the free layer close to the MgO barrier 905, and the free layer 907 can be doped with Ta, W, or Mo. Embodiments of the reference layer 903 can include a bilayer of CoFeB and CoPt multilayers combined with an Ir or Ru spacer 902. The MgO cap 908 is optional but can be used to enhance the anisotropy of the free layer 907. The conductive spacer can be, among other things, a conductive metal such as Ta, W, Ru, CN, TiN, and TaN.

[0054] To sense the data state stored in the MRAM, a V is applied across the entire memory cell appA voltage represented thereby is applied to determine its resistance state. To read the MRAM memory cell, a voltage difference V app can be applied in either direction. However, since the MRAM memory cell has a directionality, depending on the situation, reading in one direction may be prioritized over the other. For example, the optimal current amplitude for writing a bit to AP (high resistance state, HRS) may be larger than writing to P (low resistance state) by 50% or more, thereby making the bit error rate (read disturb) less likely to occur in the case of reading to AP (2AP). Some of these situations and the resulting read directionality will be described below. As will be further described with respect to FIGS. 10A and 10B, the directionality of the bias is part of some embodiments, particularly for programming the MRAM memory cell.

[0055] The following description is mainly made with respect to a perpendicular spin transfer torque MRAM memory cell, and the free layers 807 / 907 in FIGS. 8 and 9 include a switchable magnetization direction perpendicular to the plane of the free layer. Spin transfer torque (STT) is the effect that the orientation of a magnetic layer within a magnetic tunnel junction can be changed using a spin-polarized current. Charge carriers (such as electrons) have a property known as spin, which is a small amount of angular momentum inherent to the carrier. A current is generally unpolarized (e.g., consisting of 50% spin-up electrons and 50% spin-down electrons). A spin-polarized current is a current in which there are more electrons of one spin or the other (e.g., a majority of spin-up electrons, or a majority of spin-down electrons). A spin-polarized current can be generated by flowing a current through a thick magnetic layer (usually called the reference layer). When this spin-polarized current is directed to a second magnetic layer (free layer), the angular momentum is transferred to this second magnetic layer and can change the magnetization direction of the second magnetic layer. This is called spin transfer torque. FIGS. 10A and 10B show the use of spin transfer torque for programming or writing to an MRAM memory. Spin transfer torque magnetic random access memory (STT MRAM) has the advantages of lower power consumption and good scalability compared to MRAM variants such as toggle MRAM. Compared to other MRAM implementations, STT switching technology requires relatively low power, substantially eliminates the problem of adjacent bit interference, and has better scalability for higher memory cell density (reduction of MRAM cell size). The latter issue is also advantageous for STT MRAM in which the free layer magnetization and the reference layer magnetization are oriented perpendicular to the film plane rather than in the plane.

[0056] Since the STT phenomenon is more easily explained in terms of electron behavior, FIGS. 10A and 10B and their discussion are given in terms of electron flow, where the direction of the write current is defined as the direction of electron flow. Thus, referring to FIGS. 10A and 10B, the term "write current" refers to electron current. Since electrons are negatively charged, the electron current is in the opposite direction to the conventionally defined current, and the electron current flows from a lower voltage level to a higher voltage level, rather than from a higher voltage level to a lower voltage level as in the case of the conventional current flow.

[0057] FIGS. 10A and 10B show the write operation of an MRAM memory cell using the STT mechanism, and show a simplified schematic diagram of an example of an STT-switching MRAM memory cell 1000 in which the magnetizations of both the reference layer and the free layer are in the vertical direction. The memory cell 1000 includes a magnetic tunnel junction (MTJ) 1002 including an upper ferromagnetic layer 1010, a lower ferromagnetic layer 1012, and a tunnel barrier (TB) 1014 as an insulating layer between these two ferromagnetic layers. In this example, the upper ferromagnetic layer 1010 is the free layer FL, and its magnetization direction is switchable. The lower ferromagnetic layer 1012 is the reference (or fixed) layer RL, and its magnetization direction is non-switchable. When the magnetization in the free layer 1010 is parallel to the magnetization in the reference layer RL 1012, the resistance between both ends of the memory cell 1000 is relatively low. When the magnetization in the free layer FL 1010 is antiparallel to the magnetization in the reference layer RL 1012, the resistance between both ends of the memory cell 1000 is relatively high. The data ("0" or "1") in the memory cell 1000 is read by measuring the resistance of the memory cell 1000. At this time, the MRAM data is read using the conductors 1006 / 1008 attached to the memory cell 1000. By design, both the parallel and antiparallel configurations maintain a stable state during the steady state and / or read operation (with a sufficiently low read current).

[0058] For both the reference layer RL1012 and the free layer FL1010, the magnetization direction is in the vertical direction (i.e., perpendicular to the plane defined by the free layer and perpendicular to the plane defined by the reference layer). FIGS. 10A and 10B show the magnetization direction of the reference layer RL1012 as upward, and the magnetization direction of the free layer FL1010 is shown as being switchable between upward and downward, both of which are also perpendicular to the plane.

[0059] In one embodiment, the tunnel barrier 1014 is made of magnesium oxide (MgO), although other materials may also be used. The free layer 1010 is a ferromagnetic metal and has the ability to change / switch its magnetization direction. Multilayers based on transition metals such as Co, Fe, and their alloys can be used to form the free layer 1010. In one embodiment, the free layer 1010 includes an alloy of cobalt, iron, and boron. The reference layer 1012 can be many different types of materials (but not limited to) including multiple layers of an alloy of cobalt and platinum and / or an alloy of cobalt and iron.

[0060] As depicted in FIG. 10A, to "set" the MRAM memory cell bit value (i.e., select the magnetization direction of the free layer), an electron write current 1050 is applied from conductor 1008 to conductor 1006. Due to the negative charge of electrons, the upper conductor 1006 is placed at a higher voltage level than the lower conductor 1008 to generate the electron write current 1050. Since the reference layer 1012 is a ferromagnetic metal, the electrons within the electron write current 1050 are spin-polarized when they pass through the reference layer 1012. When the spin-polarized electrons tunnel across the tunnel barrier 1014, angular momentum conservation can result in spin-transfer torque being applied to both the free layer 1010 and the reference layer 1012. However, this torque is (by design) insufficient to affect the magnetization direction of the reference layer 1012. In contrast, when the initial magnetization orientation of the free layer 1010 is antiparallel (AP) to the reference layer 1012, this spin-transfer torque is (by design) sufficient to switch the magnetization orientation within the free layer 1010 to be parallel (P) to the magnetization orientation of the reference layer 1012, which is called antiparallel-to-parallel (AP2P) writing. Subsequently, the parallel magnetization remains in a stable state before and after such an electron write current is turned off.

[0061] In contrast, when the free layer 1010 magnetization and the reference layer 1012 magnetization are initially parallel, the magnetization direction of the free layer 1010 can be switched to be antiparallel to the reference layer 1012 by applying an electron write current in the opposite direction as in the previous case. For example, as shown in FIG. 10B, the electron write current 1052 is applied from conductor 1006 to conductor 1008 by placing a higher voltage level on the lower conductor 1008. This writes the free layer 1010 in the P state to the AP state and is called parallel-to-antiparallel (P2AP) writing. Thus, due to the same STT physical characteristics, the magnetization method of the free layer 1010 can be deterministically set to either of the two stable orientations by a judicious choice of the electron write current direction (polarity).

[0062] The data (either "0" or "1") within memory cell 1000 can be read by measuring the resistance of memory cell 1000. A low resistance typically represents a "0" bit, and a high resistance typically represents a "1" bit, although there may be a swapped rule. The read current can be applied across the memory cell (e.g., across magnetic tunnel junction 1002) by applying an electron read current that flows from conductor 1008 to conductor 1006 as shown for 1050 in FIG. 10A ("AP2P direction"), or the electron read current can be applied such that it flows from conductor 1006 to conductor 1008 as shown for 1052 in FIG. 10B ("P2AP direction"). In a read operation, if the electron write current is too high, it may disturb the data stored in the memory cell and change its state. For example, when the electron read current uses the P2AP direction of FIG. 10B, if the current or voltage level is too high, any memory cell in the low resistance P state may be switched to the high resistance AP state. As a result, the MRAM memory cell can be read in either direction, but the write operation's directionality may make one read direction (in various embodiments, the P2AP direction) more preferable than the other direction because more current is required to write a bit in that direction.

[0063] The descriptions of FIGS. 10A and 10B were in the context of electron current for read and write currents, but the following descriptions are in the context of conventional current unless otherwise specified.

[0064] Whether reading from or writing to a selected memory cell within the array structures of FIGS. 7A-7D, the bit lines and word lines corresponding to the selected memory cell are biased to apply a voltage across the selected memory cell to induce an electron flow, as shown with respect to FIGS. 10A or 10B. This also applies a voltage across the unselected memory cells of the array and may induce a current in the unselected memory cells. This wasted power consumption can be reduced to some extent by designing the memory cells to have a relatively high resistance level for both the high resistance state and the low resistance state, but this still results in an increase in current and power consumption and imposes additional design constraints on the design of the memory cells and the array.

[0065] One approach to address this unwanted current leakage is to place a selector device in series with each MRAM or other resistive (e.g., ReRAM, PCM, and FeRAM) memory cell. For example, a selection transistor can be placed in series with each resistive memory cell element of FIGS. 7A-7D, whereby element 701 becomes a composite of a selector and a programmable resistor. However, the use of a transistor requires the introduction of additional control lines that can turn on the corresponding transistor of the selected memory cell. In addition, transistors are often not scaled in the same way as resistive memory elements, so the use of transistor-based selectors can become a limiting factor as the memory array changes to a smaller size.

[0066] An alternative approach to the selector element is the use of a threshold switching selector device in series with a programmable resistance element. The threshold switching selector has a high resistance (is in an off or non-conducting state) when biased at a voltage lower than its threshold voltage and a low resistance (is in an on or conducting state) when biased at a voltage higher than its threshold voltage. The threshold switching selector remains on until its current is reduced below a holding current or its voltage is reduced below a holding voltage. When this occurs, the threshold switching selector returns to the off state. Thus, in order to program a memory cell at a cross point, a sufficient voltage or current is applied to turn on the associated threshold switching selector to set or reset the memory cell, and in order to read the memory cell, the threshold switching selector must be turned on as well before the resistance state of the memory cell can be determined. An example of a threshold switching selector is the ovonic threshold switching material of an ovonic threshold switch (OTS).

[0067] Figures 11A and 11B show embodiments for incorporating a threshold switching selector into a MRAM memory array having a cross-point architecture. The examples of Figures 11A and 11B show two MRAM cells in a side view in a two-layer cross-point array as shown in Figure 7D. Figures 11A and 11B show a lower first conductive line which is word line 1 1100, an upper first conductive line which is word line 2 1120, and an intermediate second conductive line which is bit line 1110. In these figures, for ease of presentation, all of these lines are shown as extending left to right across the page, and in a cross-point array, these are shown more accurately as represented in the perspective view of Figure 7D, where the word lines or first conductive lines or wires extend in one direction parallel to the surface of the underlying substrate and the bit lines or second conductive lines or wires extend in a second direction parallel to the surface of the substrate which is substantially orthogonal to the first direction. The MRAM memory cells are also represented in a simplified form showing only the reference layer, the free layer, and the intermediate tunnel barrier, but in an actual implementation typically include the additional structures described above with respect to Figure 9.

[0068] The MRAM cell 1102 including the free layer 1101, the tunnel barrier 1103, and the reference layer 1105 is formed on the threshold switching selector 1109, and this series connection between the MRAM device 1102 and the threshold switching selector 1109 forms a layer 1 cell together between the bit line 1110 and the word line 11100. The series connection between the MRAM device 1102 and the threshold switching selector 1109 operates as described above with respect to FIGS. 10A and 10B substantially, except for some voltage drop across the threshold switching selector 1109 when the threshold switching selector 1109 is turned on. However, first, the threshold switching selector 1109 needs to be turned on by applying a voltage higher than the threshold voltage V th of the threshold switching selector 1109. Then, the bias current or voltage needs to be maintained sufficiently higher than the holding current or holding voltage of the threshold switching selector 1109 so that it is turned on during subsequent read or write operations.

[0069] In the second layer, the MRAM cell 1112 includes the free layer 1111 and the tunnel barrier 1113, the reference layer 1115 is formed above the threshold switching selector 1119, and a layer 2 cell is formed between the bit line 1110 and the word line 2 1120 by the series connection between the MRAM device 1112 and the threshold switching selector 1119. The layer 2 cell operates for the layer 1 cell, but the lower conductor corresponds to the bit line 1110 and the upper conductor is here the word line, which is the word line 2 1120.

[0070] In the embodiment of FIG. 11A, the threshold switching selector 1109 / 1119 is formed under the MRAM devices 1102 / 1112. However, in an alternative embodiment, the threshold switching selector may be formed on top of one or both layers of MRAM devices. As discussed with respect to FIGS. 10A and 10B, the MRAM memory cells are directional. In FIG. 11A, the MRAM devices 1102 and 1112 have the same orientation, and the free layers 1101 / 1111 are on top of the reference layers 1105 / 1115 (with respect to a substrate not shown). Forming a layer between conductive lines having the same structure can have several advantages with respect to the process, since each of the two layers, and subsequent layers in embodiments having more layers, can be formed according to the same process sequence.

[0071] FIG. 11B shows an alternative embodiment arranged similarly to FIG. 11A, but in the cells of layer 2, the positions of the reference layer and the free layer are reversed. More specifically, between a word line 1 1150 and a bit line 1160 as in FIG. 11A, layer cell 1 includes an MRAM structure 1152 having a free layer 1151 formed on top of a tunnel barrier 1153, the tunnel barrier 1153 being formed on top of a reference layer 1155, and the MRAM structure 1152 being formed on top of a threshold switching selector 1159. The second layer of the embodiment of FIG. 11B also has an MRAM device 1162 formed on top of a threshold switching selector 1169 between the bit line 1160 and a word line 2 1170. However, compared to FIG. 11A, in an inverted state of the MRAM device 1162, it here has a reference layer 1161 formed on top of a tunnel barrier 1163 and a free layer 1165 formed under the tunnel barrier 1163 here.

[0072] The embodiment of FIG. 11B requires different process sequences for forming the layers, but can have advantages in some embodiments. Specifically, when writing or reading in the same direction (with respect to the reference and free layers), the bit lines are biased in the same way with respect to both the lower and upper layers, and both word lines are biased in the same way, so the directionality of the MRAM structure can make the embodiment of FIG. 11B attractive. For example, when both the memory cells of layer 1 and layer 2 are sensed in the P2AP direction (with respect to the reference layer and free layer), the bit line layer 1160 is biased in the P2AP direction, etc., the bit line 1160 is biased low (e.g., 0V) with respect to both the upper and lower cells, and the word line 1 1150 and the word line 2 1170 are both biased to a higher voltage level. Similarly, with respect to writing, to write to the high-resistance AP state, the bit line 1160 is biased low (e.g., 0V) with respect to both the upper and lower cells, and the word line 1 1150 and the word line 2 1170 are both biased to a higher voltage level, and to write to the low-resistance P state, the bit line 1160 is biased to a high voltage level, and the word line 1 1150 and the word line 2 1170 are both biased to a low voltage level. In contrast, in the embodiment of FIG. 11A, the bit lines and word lines need to reverse their bias levels in order to perform any of these operations at the upper level with respect to the lower level.

[0073] Reading data from or writing data to an MRAM memory cell involves passing a current through the memory cell. In embodiments where a threshold switching selector is arranged in series with the MRAM device, it is necessary to turn on the threshold switching selector by applying a sufficient voltage across the series combination of the threshold switching selector and the MRAM device before the current can pass through the MRAM device. FIGS. 12 and 13 consider this activation of the threshold switching selector in more detail in the context of the read operation.

[0074] Figures 12 and 13 are each an embodiment of a set of waveforms of current and voltage of the layer 1 cell in FIGS. 11A and 11B in a read operation, and the time axes of FIGS. 12 and 13 are aligned on the same scale. In this embodiment for the read operation, the read is performed in the P2AP direction, the word lines 11100 / 1150 are biased high, and the bit lines 1110 / 1160 are set low (e.g., 0V), whereby the (conventional) current flows upward through the reference layer 1105 / 1155 before passing through the free layer 1101 / 1151. (In contrast to the conventional current, for the electron current, the electron flow is as shown in FIG. 10B.)

[0075] In the embodiments of FIGS. 12 and 13, a forced current approach is used, and the memory is driven from the reference layer side by a read current I read from a current source in the drive circuit of that line. read As shown in FIG. 12 by the solid line 1201, the current rises to the value of I th and is held there for the duration of the current read operation. This current moves through the line that supplies current to the selected memory cells such as the word lines 11100 / 1150 of the layer 1 memory cells in FIGS. 11A and 11B, and also supports leakage in the path. As shown at 1251 in FIG. 13, the voltage across the parallel combination of the threshold switching selector and the resistive MRAM element rises when the threshold switching selector is in the off state. When the voltage across the threshold switching selector reaches the threshold voltage V

[0076] of the threshold switching selector at 1253, the threshold switching selector turns on and switches to the low resistance state. read Once the threshold switching selector is in the on state, the I read current flows through the selected memory cells. This is shown by the dashed line 1203 in FIG. 12, and when the threshold switching selector switch turns on at 1253, the current is resent through the memory cells and jumps from zero to I readWhen fixed and held, the voltage across the memory cell drops to a level that depends on the series resistance of the MRAM device and the on-state resistance of the threshold switching selector. In a binary embodiment, the memory cell has a high-resistance antiparallel state and a low-resistance parallel state. The I for the high-resistance state (HRS) and the low-resistance state (LRS) read In response to the current, the resulting voltages across the series-connected MRAM device and threshold switch selector, and across the series decoder transistor that conducts current to one of the N word lines and one of the N bit lines are shown as 1255 and 1253, respectively. The resulting voltage difference can then be measured by a sense amplifier to determine the data state stored in the memory cell. The discussion herein is in the context of an MRAM-based memory cell arranged in series with a threshold switching selector, but this read technique can be similarly applied to other programmable resistive memory cells such as PCM, FeRAM, or ReRAM devices.

[0077] FIG. 13 shows that the voltage rises at 1251 until it reaches V at 1253 and then drops either to the high-resistance state (HRS) level at 1255 or to the low-resistance state (LRS) at 1253. In an actual device, due to resistance and capacitance, there is some delay as the voltage spike at 1253 drops to either 1255 or 1253. This is shown by FIG. 14 for the example of the low-resistance state. th FIG. 14 shows an example of the voltage across the MRAM device when the threshold switching selector switches from the off state to the on state. Compared to FIG. 13, FIG. 14 shows the voltage V across only the MRAM device

[0078] MRAM MRAMis shown, and FIG. 13 depicts the voltage across the series combination of the threshold switching selector and the MRAM device. First, before the threshold switching selector turns on, as the applied voltage rises to the Vth voltage, the voltage across the MRAM device becomes zero. Once the threshold switching selector turns on, current begins to flow through the MRAM device, and the voltage across the MRAM device spikes to a level that subtracts the voltage Vhold that drops across the threshold switching selector from Vth. As a result, V MRAM jumps from 0 V to ΔV = (V th - Vhold), and then decays in response to the applied Iread, V MRAM (LRS) to the voltage drop across the MRAM device in the low resistance state.

[0079] The rate at which the VMRAM voltage decays towards the asymptote V MRAM (LRS) level depends on the magnitude of the spike from the "snapback voltage" ΔV, which is the difference between (Vth - Vhold) and V MRAM (LRS), and the rate at which charge can flow out of the device, which depends on the internal resistance of the MRAM and the selector when the selector is turned on, and the R-C characteristics of the memory cell and the lines to which it is connected (e.g., the word line from the word line driver to the memory cell, and the bit line from the bit line driver to the memory cell). The loss is faster for lower capacitance and lower resistance. This behavior leads to several practical consequences for the operation of the memory cell.

[0080] The first result is that, as shown in FIG. 14, both the low resistance state and the high resistance state decay, and FIG. 14 shows the low resistance state. The high resistance state exhibits similar behavior, but with a higher asymptotic state Vfinal determined by the path resistance × Iread. To distinguish between these two states, they need to be separated with sufficient margin, and thus, the sense operation cannot be performed until enough time has elapsed for the two states to have clearly distinguishable voltage levels.

[0081] As another result, spikes can disturb the data stored in the memory cell. As described with respect to FIGS. 10A and 10B, the state of the MRAM memory can be changed by passing a current through the memory cell, and as a result, if the voltage across the memory cell and / or the current through the memory cell is high enough for long enough, this can change the parallel state to the anti-parallel state (P2AP write) as shown in FIG. 10B or change the anti-parallel state to the parallel state (AP2P write) as shown in FIG. 10A, depending on the direction of the current. For example, the read processes of FIGS. 12 and 13 are described as being performed in the P2AP direction, whereby the disturbance by the waveform of FIG. 14 can switch the low-resistance state memory cell to the high-resistance state before the data state can be stored.

[0082] FIG. 15 shows an example of the current Icell flowing through the MRAM device when the threshold switching selector switches from the off state to the on state (a current plot corresponding to the voltage plot of FIG. 14). For FIG. 12, FIG. 14 shows the current flowing only through the MRAM device, and FIG. 12 represents the current required from the driver (e.g., the current flowing through a series combination of word lines, bit lines, threshold switching selector, and MRAM device). First, before the threshold switching selector turns on, when the applied voltage rises to V th voltage, the current flowing through the MRAM device becomes zero (or near zero). The word line and / or bit line to the memory cell can be charged during this time. When the threshold switching selector turns on, the parasitic capacitor formed between the word line and / or bit line discharges, so a relatively high current, sometimes called the "snapback current" or "Isb," flows through the MRAM device. The discharge rate can depend on several factors such as the resistance and capacitance of the word line and / or bit line connected to the memory cell.

[0083] FIG. 15 shows two curves corresponding to different snap-back currents experienced by different memory cells within the same memory array. The first curve 1562 shows a first snap-back current Isb1, and the second curve 1560 shows a second snap-back current Isb2 that is smaller than Isb1. Also, the first curve 1562 shows a decay time (t1) that is slower than the decay time (t2) of the second curve 1562. The snap-back current and the corresponding snap-back current decay time can vary between memory cells within the same array, which can result in specific outcomes. For example, a higher snap-back current and a longer current decay time (e.g., the first curve 1562) can cause more disturbance and more errors (e.g., a higher bit error rate, i.e., "BER") than memory cells having a lower snap-back current and a shorter decay time (e.g., the second curve 1560).

[0084] The snap-back current and the decay time can be affected by various factors such as the dimensions of the lines connecting the memory cells to their respective drivers. For example, the lines (e.g., word lines and / or bit lines) have a series resistance that depends on their dimensions (e.g., can increase proportionally to the length). The lines (e.g., word lines and / or bit lines) also have some capacitance (e.g., parasitic capacitors formed with adjacent lines) that can increase with the length. The word line drivers and the bit line drivers can be connected to different memory cells within the array by lines of different lengths (e.g., some memory cells (near cells) are closer to the word line driver and / or the bit line driver than other memory cells (far cells)). Such different geometries of the lines can affect the snap-back current and the snap-back current decay time of different memory cells within the array, thereby affecting the error rate.

[0085] FIG. 16 shows an example of a memory structure 602, as well as corresponding word line driver 660 and bit line driver 650 (the word line driver 660 and bit line driver 650 can be on the memory die having the memory structure 602 or on a separate die connected to the memory die including the memory structure 602). Two bit lines BL0 and BLn, as well as two word lines WL0 and WLn, are shown together with a first memory cell 1670 and a second memory cell 1672 (additional lines and memory cells are omitted for clarity). The first memory cell 1670 (near memory cell) is relatively close to both the word line driver 660 and the bit line driver 650. The first memory cell 1670 is connected to the bit line driver 650 by BLn (the effective bit line length is BLmin) and is connected to the word line driver 660 by WL0 (the effective word line length is WLmin). This gives an electrical total distance of BLmin + WLmin (the combined length of the effective word line and bit line). The second memory cell 1672 (far memory cell) is relatively far from both the word line driver 660 and the bit line driver 650. The second memory cell 1672 is connected to the bit line driver 650 by BL0 (having an effective bit line length BLmax) and is connected to the word line driver 660 by WLn (having an effective word line length WLmax). This gives an electrical total distance of BLmax + WLmax (the combined length of the effective word line and bit line). Due to the different electrical distances and their associated resistances and capacitances, the first memory cell 1670 and the second memory cell 1672 can have different snapback currents Isb and different snapback current decay times (for example, the first memory cell 1670 can have a higher snapback current and a longer snapback current decay time, like the first curve 1562, compared to the second memory cell 1672 which can have characteristics like the second curve 1560).As a result of these differences and / or for any other reason, the data read from the first memory cell 1670 and the second memory cell 1672 may have different error rates (e.g., the data from the first memory cell 1670 may have a higher BER than the data from the second memory cell 1672). Some examples may refer to mitigating snapback-related effects, but aspects of the present technique are not limited to such applications, and the present technique may be applied to mitigate other effects (e.g., effects that can generate non-uniform errors across the die).

[0086] The first memory cell 1670 and the second memory cell 1672 represent the case where they are at opposite ends of the possible electrical distance range of the memory cells of the memory structure 602 with respect to the bit line driver and the word line driver. Other memory cells may have any electrical distance within this range, and the corresponding snapback current and snapback current decay time are between the snapback current and snapback current decay time of the first memory cell 1670 and the second memory cell 1672, which may result in an error rate between the error rates of the first memory cell 1670 and the second memory cell 1672. The effect of the snapback current on some or all of the memory cells may be at least partially predictable based on the electrical distance of the memory cells (e.g., based on their respective distances to the word line driver and the bit line driver).

[0087] In some memory systems, data from different arrays (e.g., on different memory dies) may be read out in parallel and combined for ECC decoding. Such parallel operation can provide high throughput and allow the ECC codewords to be distributed across multiple arrays.

[0088] FIG. 17A shows an example of a configuration including five media, media 1 to media 5, connected to a memory controller 1780 including an ECC engine 1782. For example, each of media 1 to 5 can be a memory package 104 (such as shown in FIG. 1), a memory die 292 (such as shown in FIG. 4), or an integrated memory assembly 600 (such as shown in FIGS. 6A to 6B) connected to the controller. In the example of FIG. 17A, media 1 to 5 are connected to the memory controller 1780 via communication channels such as an address communication channel 1784 and a data communication channel 1786 (for example, a channel of the memory bus 294). The address communication channel 1784 is shared by media 1 to 5 (common communication channel), and the data communication channel 1786 is a dedicated communication channel and has one data communication channel (for example, x-bit width, where x can be any suitable number such as 16, 32, 64, 128, or more) for each media.

[0089] In an example of a read operation, the memory controller 1780 transmits a read address to media 1 to 5 via the address communication channel 1784 to specify the address to be read (target address). Since the address communication channel 1784 is common to media 1 to 5, each of media 1 to 5 receives the same address. Media 1 to 5 can read data in response to a read command and transmit the data via the data communication channel 1786 to the ECC engine 1782 (for example, ECC engines 226 / 256) in the memory controller 1780. In this example, each media transmits x bits at a time. Media 1 to 5 can read and transmit data in parallel so that the ECC engine 1782 receives 5x bits of data (for example, 4x bits of user data and x bits of ECC data) in parallel. The ECC engine 1782 can perform ECC correction together on the received 5x bits (for example, the ECC engine 1782 can be configured to have a codeword size of 5x bits). In other examples, different amounts of data can be transmitted from different numbers of media (for example, more or less than 5), and the ECC engine 1782 can be configured to encode / decrypt using a codeword of an appropriate size.

[0090] In an example of the write operation, the memory controller 1780 transmits a write address to media 1 to 5 via the address communication channel 1784 to specify the address to be written (target address). The ECC engine 1782 can generate a 5x-bit ECC codeword (for example, receive 4x-bit user data and generate a 5x-bit codeword), and can transmit x bits to each of media 1 to 5 via the data communication channel 1786. In response, media 1 to 5 can each write their respective x bits.

[0091] Figures 17B to 17D show an exemplary structure of the medium 1788 (for example, any one of media 1 to 5). Figure 17B shows a medium 1788 including K banks (1 to K, where K can be any suitable number such as 8, 16, 32, 64 or more).

[0092] Figure 17C shows an exemplary structure of a bank 1790 (for example, any one of banks 1 to K in Figure 17B) including x active modules such as the exemplary module 1792 (shaded). The modules are configured to enable parallel readout and parallel transmission of x bits from the modules of the selected bank in order to be read out in parallel and transmit data in parallel.

[0093] FIG. 17D shows an exemplary structure of a module 1792 including, for example, n bit lines (two sets of n / 2 bit lines “n / 2 BL”) and n word lines (two sets of n / 2 bit lines each “n / 2 WL”) in a configuration as shown in FIGS. 7A-7D above. In FIG. 16 and this example, the number of word bit lines and word lines is equal (n bit lines and n word lines), but in other examples, these numbers may be different. The module 1792 also includes a driver circuit 1794 (e.g., word line driver circuit 660 and / or bit line driver circuit 650), and in this example, the driver circuit 1794 is located in the center of the module 1792 and the memory array portion is shown on both sides. In some cases, the driver circuit may be located below the memory array. In some cases, the driver circuits may be present at multiple locations (e.g., some driver circuits are located below the memory array, some are located between the memory array portions or in the peripheral area of the array). The metal connections between the driver circuit and the array components (e.g., word lines and bit lines) may extend in the horizontal and / or vertical directions. In some cases, the driver circuit is located on a die separate from the memory die (e.g., within an integrated memory assembly). The present technology is not limited to a driver circuit at any particular location. Some logic circuits associated with the driver circuit may be located together with the driver circuit (e.g., the module 1792 may include some logic circuits for controlling the driver circuit 1794).

[0094] FIG. 18A shows a first example of a read operation for N media (e.g., media 1 to 5 in FIG. 17A). The read command may specify a selected bank 1790 and a selected memory cell (e.g., the intersection of a selected word line and a selected bit line). In each medium, the specified memory cells of each module of the selected bank 1790 are read in parallel. In the example of FIG. 18A, the specified memory cells are shown at the lower right corners (shaded) of each module 0 to x in the respective selected banks 1790 of media 1 to N. This position may correspond to the position of the first memory cell 1670 (near memory cell) shown in FIG. 16 such that the data read from these memory cells may have a relatively high error rate. The data bits 1894 (x bits from each of media 1 to N) read in the example of FIG. 18A may be sent in parallel to an ECC circuit (e.g., ECC engine 1782), where they are decoded together as units (ECC codewords) that may have a relatively high error rate and thus a relatively high probability of UE.

[0095] FIG. 18B shows another example of a read operation for the N media of FIG. 18A. In this example, the read command specifies different memory cells (the intersections of different word lines and bit lines). In each medium, the specified memory cells of each module of the selected bank 1790 are read in parallel. In the example of FIG. 18B, the specified memory cells are shown at the upper left corners (shaded) of each module 0 to x in the respective selected banks 1790 of media 1 to N. This position may correspond to the position of the second memory cell 1672 (far memory cell) shown in FIG. 16 such that the data read from these memory cells may have a relatively low error rate. The data bits 1896 (x bits from each of media 1 to N) read in the example of FIG. 18B may be sent in parallel to an ECC circuit (e.g., ECC engine 1782), where they are decoded together as units (ECC codewords) that may have a relatively low error rate and thus a relatively low probability of UE.

[0096] Aspects of the present technology are directed to accessing data in an MRAM structure to mitigate the non-uniformity of ECC (e.g., the non-uniformity shown in the example of FIG. 18A) by the error rate (e.g., BER) in any portion of the data that is read together and undergoes ECC decoding together and the probability of the UE. For example, data to be ECC decoded as a unit is stored and then can be read from different respective positions within different media and / or from different positions within different modules of the media and / or from positions that would otherwise be non-uniform.

[0097] FIG. 19 shows an example of a read operation in which each control circuit (e.g., system control logic 560 / 659) of media 1 to N applies a different offset to a read address received via address communication channel 1784 to generate respective offset addresses (the number of media N can be any suitable number, e.g., 2, 4, 8, 16 or more). For example, media 1 may apply a first offset (offset 1) that causes a read of the memory cells in the lower right of memory modules 1 to x of selected bank 1790 (similar to FIG. 18A) to obtain data 1902 (all modules 1 to x are read in parallel at the same respective positions). Media N may apply an Nth offset (offset N) that causes a read of the memory cells in the upper left of memory modules 1 to x of selected bank 1790 (similar to FIG. 18B) to obtain data 1904. Media 2 to media N-1 may apply other offsets to cause reads of memory cells at intermediate positions to obtain additional data (e.g., media 2 applies offset 2 to obtain data 1906). The individual address offsets used for each media may include at least one of a word line offset and / or a bit line offset that causes reads of modules of different media at different positions (in this example, the modules of a bank selected for any given media are read at a common offset address). Data from all media 1 to N (such as data 1902, 1904, and 1906) may be read in parallel, transmitted in parallel to an ECC circuit, and decoded there. Since the data is obtained from different respective positions within different media, the combined data may have an intermediate error rate (e.g., intermediate between the error rates of the examples of FIGS. 18A and 18B) and may represent the average error rate at different positions across the array. The error rate may be relatively uniform across different codewords such that the probability of a UE is relatively low (e.g., compared to the case of reading all data of a codeword from the same position across all media as in FIGS. 18A to 18B).

[0098] FIG. 19 shows an example of a read operation, but for a write operation, the same offset may be used such that the codewords generated by ECC encoding are spread to different positions in different media. For example, data 1902, 1904, 1906, and any additional portions of data from media 3 to N - 1 may be part of the ECC codewords written at the positions shown in parallel.

[0099] The method of FIG. 19 can be implemented by having a control circuit in each medium that records the corresponding individual address offset in an offset register, where different media have different address offsets (e.g., each of media 1 to N has a different address offset value stored in the register of its respective control circuit). The offset address value can be selected based on the number of media and the number of memory cells in the module (e.g., the number of cells can be divided by the number of media so that the offset accesses memory cells of different media at positions equally spaced from each other). The memory controller (e.g., controller 102) can determine the number of media (e.g., memory dies) present in the system and configure the offset register of each die to evenly distribute the addresses (e.g., by increasing the number of dies and decreasing the offset in proportion to the reciprocal of the number of dies). For example, FIG. 19 shows media 1 having a control circuit 1910 that includes an offset register (e.g., register 561) storing offset 1, media 2 having a control circuit 1912 that includes an offset register storing offset 2, and media N having a control circuit 1914 that includes an offset register storing offset N. The address offset can be set in one operation during the configuration of the memory system or can be reconfigurable during the operating life of the memory system. The control circuits of media 1 to N (such as control circuits 1910, 1912, and 1914) receive a read address in parallel from the memory controller (e.g., via a common address communication channel 1784), apply their respective individual address offsets to the read address to generate their respective offset addresses, read a portion of the data (e.g., data 1902, 1906...1904) from their respective offset addresses, and transmit the data read from the offset address to the memory controller to perform error correction code (ECC) decoding of the portion of the data.

[0100] Figure 20 shows another read operation where data is stored, read from an offset address, and an ECC codeword containing data from a range of positions is provided. In the example of Figure 20, an offset is applied and each offset address is generated by memory controller 1780. In this example, media 1 through media N may not apply an offset and may not include an offset register as in the previous example. Each media receives a different offset address from memory controller 1780. For example, media 1 receives offset address 1, media 2 receives offset address 2, and media N receives offset address N. In this example, dedicated communication channel 2020 is used to provide different offset addresses to each media and to read data from each respective offset address (one address communication channel per media to allow different offset addresses to be transmitted in parallel). Then, data from each different position is sent to the ECC engine for decoding as a unit as before.

[0101] In another example, instead of dedicated communication channel 2020, a common address communication channel (e.g., address communication channel 1784) can be used to transmit different addresses to different media (e.g., sequentially) (e.g., the control circuitry within each media can analyze commands such as read or write commands to determine if they are the destination of the command).

[0102] FIG. 21 shows another read operation in which data is stored, read from an offset address, and an ECC codeword including data from a range of positions is provided. In the example of FIG. 21, the offset is applied per module within the selected bank of each medium. For example, in medium 1, modules 0 to x of the selected bank 1790 are accessed at different positions indicated by the offset stored in register 2130. The memory cell in the lower right of module 0 is read in parallel with the memory cell in the upper left of module x and the intermediate memory cells of modules 1 to N-1. The data 2132 read from these memory cells is from memory cells at different positions with respect to the word line driver and the bit line driver, and may have an error rate that is the average of the error rates at different positions within the module. Similarly, in each of media 2 to N, the data within the selected bank 1790 is read from different positions within different modules and may have an error rate that is the average of the error rates at different positions within the module. The data 2132 from medium 1, the data 2134 from medium 2 to the data 2136 from medium N can be read in parallel and sent in parallel to the ECC engine for joint decoding.

[0103] Since data is read from a range of positions within each medium, the data from each medium may have a similar error rate. Each medium may apply a similar set of offsets such that the read pattern is the same for all media. Each medium includes a set of registers 2130 that store the offsets applied during data write and read. In some cases, the register 2130 may be unnecessary if different bits are sampled in each module. In one example, different offsets are applied to each module. In another example, the modules are grouped with different offsets for each group (e.g., x modules are obtained by grouping into 4 groups of x / 4 modules each, and each group has its respective offset for a total of 4 offsets within register 2130). In some cases, the offsets of different media may be different (e.g., the offset pattern per module may be combined with the offset per medium).

[0104] FIG. 22 shows an example of a method according to an aspect of the present technology. The method includes transmitting a read address to a plurality of memory dies (2240), and applying a plurality of address offsets to the read address to generate respective offset addresses in a plurality of memory dies, such as a first offset address in at least a first memory die and a second offset address in a second memory die (2242). The method further includes reading a first portion of data from the first offset address, and reading a portion of data from respective offset addresses of the memory dies, such as reading a second portion of data from the second offset address (2244), and decoding a portion of data of all the memory dies of the plurality of memory dies, such as the first portion and the second portion (2246).

[0105] The method of FIG. 22 can be implemented in various ways according to aspects of the present technology. FIG. 23 shows transmitting a read address to a plurality of memory dies including N memory dies, each memory die including its own array, and the read address being received in parallel by the plurality of memory dies via a common communication channel between the memory controller and the plurality of memory dies (e.g., the N media of FIGS. 19 or 21 receive the same read address via address communication channel 1784) (2350), and applying N different address offsets to the read address such that a portion of the data is read from different respective positions within each memory die (as shown, for example, by data 1902, 1904, and 1906 of FIGS. 19 - 20 or data 2132, 2134, and 2136 of FIG. 21) (2352), showing an exemplary implementation including this. This method reads a first portion of the data (e.g., data 1902) from a first offset address, reads a second portion of the data (e.g., data 1904) from a second offset address, etc., reading a portion of the data from each offset address of the memory die (2354), transmitting a portion of the data in parallel from the plurality of memory dies via a plurality of communication channels between the plurality of memory dies and the memory controller (e.g., data communication channel 1786 between media 1 - 5 of FIG. 17A and memory controller 1780) (2356), and decoding together a portion of the data of all the memory dies of the plurality of memory dies, such as the first portion and the second portion (2358, e.g., ECC engine 1782 decodes a portion of the data, such as data 1902 and 1904, together as a codeword).

[0106] An offset (e.g., die - specific, module - specific, or other offset) can be used for all memory accesses such as read access and write access (e.g., as shown in FIG. 22 or FIG. 23). The above example is described with respect to the read operation and subsequent ECC decoding of the data read using the offset. However, for the write operation, the offset can be used such that the data to be written is ECC - encoded and then written at different positions according to the offset (e.g., the offset in the examples of FIGS. 19 - 21). FIG. 24 shows an example of how to use an offset address during a write (e.g., writing data that will be read later, as shown in FIG. 22 or FIG. 23). The method of FIG. 24 can be implemented in any suitable memory system, e.g., a memory system including multiple media as shown in the examples of FIGS. 17A - 17D.

[0107] FIG. 24 shows an example of a method that includes receiving (2460) a write address and write data by a plurality of memory dies (e.g., media 1 - N of FIGS. 19 - 21), applying (2462) respective individual address offsets (e.g., offsets 1 - N) to the write address by each memory die (e.g., each of media 1 - N) to generate respective offset addresses, and writing (2464) the write data at each offset address within the plurality of memory dies (e.g., writing the data at the same offset addresses that can be used later during data readout, as shown by data 1902, 1904, and 1906 of FIGS. 19 - 20, or data 2132, 2134, and 2136 of FIG. 21).

[0108] According to a first set of aspects, the apparatus includes a plurality of control circuits configured to be individually connected to an array each including a plurality of non-volatile memory cells. Each non-volatile memory cell includes a programmable resistive element. Each control circuit is configured with an individual address offset. The plurality of control circuits receive read addresses in parallel from a memory controller, apply their respective individual address offsets to the read addresses to generate respective offset addresses, read a portion of data from the respective offset addresses, and transmit the data read from the offset addresses to the memory controller to perform error correction code (ECC) decoding of the portion of data.

[0109] The plurality of control circuits may include at least a first control circuit configured to connect to a first array and a second control circuit configured to connect to a second array. The first control circuit is configured with a first address offset, and the second control circuit is configured with a second address offset such that a first offset address generated by applying the first address offset is closer to at least one of a word line driver or a bit line driver than a second offset address generated by applying the second address offset. The first control circuit and the first array may be located on a first die, and the second control circuit and the second array may be located on a second die. The first control circuit may be located on a first control die configured to be bonded to a first memory die including the first array, and the second control circuit may be located on a second control die configured to be bonded to a second memory die including the second array. The plurality of control circuits may include N control circuits respectively connected to respective arrays, and the N control circuits apply N different address offsets. The N different address offsets may be configured to cause each array to be read at respective different positions with respect to at least one of a word line driver or a bit line driver. The N different address offsets may be configured to cause each array to be read at respective different locations equally spaced from each other. Each array may include a plurality of banks, each bank may include a plurality of modules configured to be read in parallel, and an individual address offset may include at least one of a word line offset or a bit line offset that causes all modules of a bank indicated by a read command at a common offset address to be read. Each array may include a plurality of banks, each bank may include a plurality of modules configured to be read in parallel, and an individual address offset may cause different modules of a bank indicated by a read command at different offset addresses to be read. Each control circuit may include a register that stores a corresponding individual address offset.

[0110] In another set of embodiments, the method includes transmitting a read address to a plurality of memory dies, applying a plurality of address offsets to the read address to generate a respective plurality of offset addresses including a first offset address in at least a first memory die and a second offset address in a second memory die in the plurality of memory dies, reading a first portion of data from the first offset address, and reading a second portion of data from the second offset address, reading a portion of data from each respective offset address of the memory dies, and decoding a portion of the data of all of the memory dies of the plurality of memory dies that together include the first portion and the second portion.

[0111] The plurality of memory dies may include N memory dies, each memory die including a respective array, and the N memory dies apply N different address offsets such that a portion of data is read from different respective positions within each memory die. The read address may be received in parallel by the plurality of memory dies via a common communication channel between the memory controller and the plurality of memory dies. A portion of the data from the plurality of memory dies may be transmitted in parallel via a plurality of communication channels between the plurality of memory dies and the memory controller. The method may further include receiving a write address and write data by the plurality of memory dies, generating a respective offset address by each memory die applying a respective individual address offset to the write address, and writing the write data at each respective offset address within the plurality of memory dies. The method may further include selecting each respective individual address offset according to the number of memory dies and the positions of the word line drivers and bit line drivers relative to the addresses within the die. Applying each respective individual address offset to the read address to generate a respective plurality of offset addresses within the plurality of memory dies may include applying different address offsets within a first memory die to read different modules of the first memory die in parallel.

[0112] In another set of embodiments, the system includes an error correction code (ECC) circuit, a first array including a plurality of non-volatile memory cells, where each non-volatile memory cell includes a programmable resistive element, a first array, means for applying a first address offset to a read command and a write command from a memory controller for a target address to obtain a first offset address, reading data from the first offset address within the first array, and transmitting the data from the first offset address within the first array to the ECC circuit for ECC decoding, a second array including a plurality of non-volatile memory cells, where each non-volatile memory cell includes a programmable resistive element, a second array, means for applying a second address offset to a read command and a write command from a memory controller for a target address to obtain a second offset address, reading data from the second offset address within the second array, and transmitting the data from the second offset address within the second array to the ECC circuit for ECC decoding using the data from the first offset address within the first array.

[0113] The first offset address may be located at a first distance from a word line driver and / or a bit line driver of the first array, the second offset address may be located at a second distance from a word line driver and / or a bit line driver of the second array, and the first distance may be less than the second distance. The first array and the means for applying the first address offset may be located within a first medium, the second array and the means for applying the second address offset may be located within a second medium, and the ECC circuit may be located within a memory controller die connected to the first medium, the second medium, and an additional medium.

[0114] For the purposes of this specification, references to "embodiments", "one embodiment", "some embodiments", or "another embodiment" in the specification may be used to describe different embodiments or the same embodiment.

[0115] For the purposes of this specification, a connection can be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as being connected or coupled to another element, this element may be directly connected to the other element or indirectly connected to the other element via an intervening element. When an element is referred to as being directly connected to another element, there is no intervening element between this element and the other element. Two devices are in a "communication state" when they are directly or indirectly connected such that they can exchange electronic signals with each other.

[0116] For the purposes of this specification, the term "based on" can be read as "at least partially based on".

[0117] For the purposes of this specification, the use of numerical terms such as "first" object, "second" object, and "third" object, without additional context, does not imply an order of the objects, but instead may be used for identification purposes to distinguish different objects.

[0118] For the purposes of this specification, the term "set" of objects may refer to a "set" of one or more of the objects.

[0119] The foregoing detailed description is presented for purposes of illustration and description. The foregoing detailed description is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize the technology in various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.

Claims

1. An apparatus comprising: a plurality of control circuits configured to be individually connected to an array, each including a plurality of non-volatile memory cells, each non-volatile memory cell including a programmable resistive element, each control circuit being configured with an individual address offset, the plurality of control circuits being configured to: receive read addresses in parallel from a memory controller; apply the respective individual address offsets to the read addresses to generate respective offset addresses; read a portion of data from the respective offset addresses; and transmit the data read from the offset addresses to the memory controller to perform error correction code (ECC) decoding of the portion of the data; wherein the plurality of control circuits includes at least a first control circuit configured to be connected to a first array and a second control circuit configured to be connected to a second array, the first control circuit being configured with a first address offset and the second control circuit being configured with a second address offset, and the first address offset and the second address offset are defined such that a position within the first array of a first offset address generated by applying the first address offset is closer to at least one of a word line driver or a bit line driver than a position within the second array of a second offset address generated by applying the second address offset.

2. The apparatus of claim 1, wherein the first control circuit and the first array are located on a first die, and the second control circuit and the second array are located on a second die.

3. The apparatus of claim 1, wherein the first control circuit is located on a first control die configured to be bonded to a first memory die including the first array, and the second control circuit is located on a second control die configured to be bonded to a second memory die including the second array.

4. An apparatus comprising: Comprising a plurality of control circuits configured to be individually connected to an array each including a plurality of non-volatile memory cells, each non-volatile memory cell comprising a programmable resistive element, each control circuit being configured with an individual address offset, the plurality of control circuits Receiving read addresses in parallel from a memory controller, Applying the respective individual address offsets to the read addresses to generate respective offset addresses, Reading a portion of data from the respective offset addresses, and Transmitting the data read from the offset addresses to the memory controller to perform error correction code (ECC) decoding of the portion of the data, and is configured to perform, The plurality of control circuits includes N control circuits respectively connected to respective arrays, the N control circuits applying N different address offsets, The N different address offsets are configured to cause each array to be read at different respective positions with respect to at least one of a word line driver or a bit line driver.

5. The apparatus according to claim 4, wherein the N different address offsets are configured to cause each array to be read at different respective positions equally spaced from each other.

6. An apparatus comprising Comprising a plurality of control circuits configured to be individually connected to an array each including a plurality of non-volatile memory cells, each non-volatile memory cell comprising a programmable resistive element, each control circuit being configured with an individual address offset, the plurality of control circuits Receiving read addresses in parallel from a memory controller, Applying the respective individual address offsets to the read addresses to generate respective offset addresses, Reading a portion of data from the respective offset addresses, and Transmitting the data read from the offset addresses to the memory controller to perform error correction code (ECC) decoding of the portion of the data, and is configured to perform, Each array includes a plurality of banks, each bank includes a plurality of modules configured to be read out in parallel, and the individual address offsets include at least one of a word line offset or a bit line offset that causes all modules of the bank indicated by a read command at a common offset address to be read out. Device. **Claim 7** A device comprising: a plurality of control circuits configured to be individually connected to an array each including a plurality of nonvolatile memory cells, each nonvolatile memory cell including a programmable resistance element, each control circuit being configured with an individual address offset, the plurality of control circuits receiving read addresses in parallel from a memory controller; applying the respective individual address offsets to the read address to generate respective offset addresses; reading a part of data from the respective offset addresses; and transmitting the data read from the offset address to the memory controller to perform error correction code (ECC) decoding of the part of the data. Each array includes a plurality of banks, each bank includes a plurality of modules configured to be read out in parallel, and the individual address offsets cause different modules of the bank indicated by a read command at different offset addresses to be read out. Device. **Claim 8** The device according to any one of claims 1, 4, 6, and 7, wherein each control circuit includes a register storing a corresponding individual address offset. **Claim 9** A method comprising: transmitting a read address to a plurality of memory dies; applying a plurality of address offsets to the read address to generate a plurality of respective offset addresses including a first offset address in at least a first memory die and a second offset address in a second memory die in the plurality of memory dies; reading a first portion of data from the first offset address and reading a second portion of data from the second offset address, reading a portion of data from respective offset addresses of the memory die. decoding a part of the data of all of the plurality of memory dies including the first part and the second part together; the plurality of memory dies includes N memory dies, each memory die includes a respective array, and the N memory dies apply N different address offsets so that a part of the data is read from different respective positions within each memory die; the N different address offsets are configured to enable reading each array at different respective positions for at least one of a word line driver or a bit line driver, a method.

10. The method according to claim 9, wherein the read address is received in parallel by the plurality of memory dies via a common communication channel between a memory controller and the plurality of memory dies.

11. The method according to claim 10, wherein a part of the data from the plurality of memory dies is transmitted in parallel via a plurality of communication channels between the plurality of memory dies and the memory controller.

12. receiving a write address and write data by the plurality of memory dies; applying, by each memory die, the respective individual address offset to the write address to generate respective offset addresses; The method according to claim 9, further comprising writing the write data at the respective offset addresses within the plurality of memory dies.

13. A method comprising: transmitting a read address to a plurality of memory dies; applying a plurality of address offsets to the read address to generate a plurality of respective offset addresses including a first offset address in at least a first memory die and a second offset address in a second memory die in the plurality of memory dies; reading a first part of data from the first offset address, and reading a second part of data from the second offset address, reading a part of data from respective offset addresses of the memory dies, including; decoding a part of the data of all of the plurality of memory dies including the first part and the second part together; A method further comprising selecting each respective individual address offset according to the number of the memory dies and the positions of the word line driver and the bit line driver with respect to the addresses in the memory dies.

14. Applying each respective individual address offset to the read address to generate a plurality of respective offset addresses in the plurality of memory dies includes applying different address offsets in a first memory die to read different modules of the first memory die in parallel, according to the method of Claim 13.

15. A system, An error correction code (ECC) circuit, A first array including a plurality of non-volatile memory cells, each non-volatile memory cell comprising a programmable resistance element, Means for obtaining a first offset address by applying a first address offset to a read command and a write command from a memory controller for a target address, reading data from the first offset address in the first array, and transmitting the data from the first offset address in the first array to the ECC circuit for ECC decoding, A second array including a plurality of non-volatile memory cells, each non-volatile memory cell comprising a programmable resistance element, Means for obtaining a second offset address by applying a second address offset to a read command and a write command from the memory controller for the target address, reading data from the second offset address in the second array, and transmitting the data from the second offset address in the second array to the ECC circuit for ECC decoding using the data from the first offset address in the first array, The position of the first offset address in the first array is located at a first distance from the word line driver and / or the bit line driver of the first array, the position of the second offset address in the second array is located at a second distance from the word line driver and / or the bit line driver of the second array, and the first distance is smaller than the second distance.

16. The first array and the means for applying the first address offset are located in a first medium, the second array and the means for applying the second address offset are located in a second medium, and the ECC circuit is located in a memory controller die connected to the first medium, the second medium, and an additional medium, the system of claim 15.

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