Circuit activation device, circuit activation program, and circuit for specific users

Abstract

To allow for individually enabling multiple modules of a user-specific circuit comprising a user circuit with multiple modules and a general purpose circuit.SOLUTION: A circuit enabling device provided herein is configured to respond to a situation, where multiple setting values predefined for respective modules get written in a predefined order into registers for individually enabling the multiple modules of a user-specific circuit comprising a user circuit with multiple modules and a general purpose circuit, by enabling modules corresponding to the multiple predefined setting values and the predefined order.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a circuit activation device, a circuit activation program, and a circuit for a specific user.

Background Art

[0002] Patent Document 1 discloses a circuit configuration identification prevention method characterized by providing a gate circuit in a field programmable gate array to control access from an external circuit to internal logic, comparing a permission key set in a pre-set internal permission key setting register with the permission key input from the external circuit, and when they match, releasing the lock of the gate circuit to permit access from the external circuit to the internal logic.

[0003] Patent Document 2 discloses a semiconductor integrated circuit comprising: a functional module that executes various data processes; a plurality of registers in which register values referred to by the functional module are set, and an external access prohibited register group that cannot be accessed from the outside; an external access possible register group that has registers corresponding to each register of the external access prohibited register group and in which register values are set from the outside; copy control means that copies the register values set in the external access possible register group to the external access prohibited register group in response to a copy instruction from the outside, and prohibits the copy if the copy instruction is in a period other than a predetermined copyable period.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] The present invention aims to provide a circuit activation device, a circuit activation program, and a specific user-oriented circuit that can individually activate a plurality of modules of a user circuit including a plurality of modules and a specific user-oriented circuit including a general-purpose circuit.

Means for Solving the Problems

[0006] The circuit activation device according to the first aspect includes a processor. When a plurality of preset values for each module are written in a preset order to a register for individually activating a plurality of modules of a user circuit including a plurality of modules and a specific user-oriented circuit including a general-purpose circuit, the processor activates the module corresponding to the plurality of preset values and the preset order.

[0007] The circuit activation device according to the second aspect is the circuit activation device according to the first aspect. For the activated module, the start address is made public. When the processor continuously writes data to the activated module, the processor increments the address from the start address and writes the data.

[0008] The circuit activation device according to the third aspect is the circuit activation device according to the first or second aspect. When the plurality of preset values are written in a preset order to a plurality of registers, the processor activates the module corresponding to the plurality of preset values and the preset order.

[0009] The circuit activation device according to the fourth aspect is the circuit activation device according to any one of the first to third aspects. When continuously activating the modules, the processor starts activating the next module after the setting for the activated module is completed.

[0010] The circuit activation program according to the fifth aspect causes a computer to execute a process of activating a module corresponding to a plurality of preset values and a preset order when the plurality of preset values for each module are written in a preset order in a register for individually activating a plurality of modules of a user circuit including a plurality of modules and a specific user-oriented circuit including a general-purpose circuit.

[0011] The specific user-oriented circuit according to the sixth aspect includes a user circuit including a general-purpose circuit, a plurality of modules, a register for individually activating the plurality of modules, and an activation determination unit that activates a module corresponding to the plurality of preset values and a preset order when the plurality of preset values for each module are written in a preset order in the register.

Advantages of the Invention

[0012] According to the first, fifth, and sixth aspects, a plurality of modules of a user circuit including a plurality of modules and a specific user-oriented circuit including a general-purpose circuit can be individually activated.

[0013] According to the second aspect, an address other than the start address of the module can be made non-public.

[0014] According to the third aspect, unauthorized access can be further restricted as compared with the case where there is one register.

[0015] According to the fourth aspect, it is possible to prevent the activation of a subsequent module from being started before the setting regarding a previously activated module is completed.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0017] Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[0018] FIG. 1 shows the configuration of the circuit 10 for a specific user. The circuit 10 for a specific user includes a general-purpose circuit 12, a user circuit 14, a general-purpose register unit 16, and a control unit 18.

[0019] The general-purpose circuit 12 is a generally publicly disclosed circuit and is a general-purpose circuit that can be used by various users without restriction.

[0020] The user circuit 14 is a generally non-public circuit and is a circuit that can be activated and used by a specific user.

[0021] The general-purpose register unit 16 includes a user circuit activation register 20.

[0022] When there is an instruction from an external device to activate the user circuit 14, the control unit 18 writes a predetermined release key to the user circuit activation register 20. The user circuit 14 is activated when the release key is written to the user circuit activation register 20. That is, the control unit 18 can control the user circuit 14. Note that activating the user circuit means permitting access to the user circuit.

[0023] The user circuit 14 includes a plurality of modules A, B, C, a user register section 22, and an activation determination section 24. In the example of FIG. 1, the number of modules is three, but the number of modules is not limited to this, and it may be two or four or more. Note that the activation determination section 24 is an example of a circuit activation device.

[0024] Modules A to C are circuits for each partial function obtained by subdividing the functions provided by the user circuit 14. For example, when the function provided by the user circuit 14 is an OCR (Optical Character Reader) function, for example, module A is a circuit that realizes a noise removal function for removing noise from an image. Also, module B is a circuit that realizes a tilt correction function for correcting the tilt of the image from which noise has been removed by module A. Also, module C is a circuit that realizes a character extraction function for extracting characters from the image whose tilt has been corrected by module B. Note that the function provided by the user circuit 14 is not limited to the OCR function.

[0025] The user register section 22 includes an access restriction release register 26 that is a register for individually activating a plurality of modules A, B, C, a register group 27A for module A, a register group 27B for module B, and a register group 27C for module C.

[0026] The activation determination section 24 stores a set value table 28. As shown in FIG. 2, in the set value table 28, a correspondence relationship is set between the writing order of the set values for the access restriction release register 26 and N (N≧2) set values determined in advance for each of the modules A, B, C. Note that the N set values are preferably different values, but the same value may be included.

[0027] The activation determination unit 24 activates the module corresponding to a plurality of preset values, that is, N preset values for each of modules A, B, and C, and the preset order, when they are written in the preset order in the access restriction release register 26. That is, when there is a continuous write of set values to the access restriction release register 26, the activation determination unit 24 refers to the set value table 28, and if there is a module whose write order and set value match, it activates that module, and if there is no module whose write order and set value match, it does not activate the module. For example, when N = 3, three set values for each module are set in the set value table 28 together with the write order. In this case, for example, when it is desired to activate module A, it is necessary to write the set value 1 for A, the set value 2 for A, and the set value 3 for A in this order to the access restriction release register 26.

[0028] Here, activating a module means permitting access to the module and the register group of the module. Note that for a module that has not been activated, since access to the register group for that module cannot be performed, the module cannot be used. For example, when module A is not activated, access to the register group 27A cannot be performed. For example, even if an attempt is made to write data to the register group 27A, access is made impossible by ignoring the write. Also, when an attempt is made to read data from the register group 27A, access is made impossible by returning a meaningless value such as a random number.

[0029] Next, the hardware configuration of the activation determination unit 24 will be described. As shown in FIG. 3, the activation determination unit 24 includes a controller 30. The controller 30 includes a CPU (Central Processing Unit) 30A, a ROM (Read Only Memory) 30B, a RAM (Random Access Memory) 30C, and an input / output interface (I / O) 30D. Then, the CPU 30A, the ROM 30B, the RAM 30C, and the I / O 30D are respectively connected via a system bus 30E. The system bus 30E includes a control bus, an address bus, and a data bus. Note that the CPU 30A is an example of a processor.

[0030] Also, a communication unit 32 and a storage unit 34 are connected to the I / O 30D.

[0031] The communication unit 32 is an interface for performing data communication with the user register unit 22 and modules A, B, and C.

[0032] The storage unit 34 is composed of, for example, a non-volatile memory and stores a circuit activation program 34A and the like, which will be described later. The CPU 30A reads the circuit activation program 34A stored in the storage unit 34 into the RAM 30C and executes it.

[0033] Next, the module activation process executed when the control unit 18 activates a module will be described with reference to the flowchart shown in FIG. 4. The process in FIG. 4 is executed when N setting values for activating a module are received from an external device (not shown).

[0034] In step S100, the control unit 18 writes a release key for activating the user circuit into the user circuit activation register 20. As a result, access to the user circuit 14 becomes possible, and writing of the setting value to the access restriction release register 26 becomes possible.

[0035] In step S102, the control unit 18 initializes a counter CT1 for counting the number of times a set value is written to the access restriction release register 26. That is, the control unit 18 substitutes "0" into the counter CT1.

[0036] In step S104, the control unit 18 increments the counter CT1 by one.

[0037] In step S106, the control unit 18 writes the setting value [CT1] received from the external device to the access restriction release register 26. Here, [CT1] represents the value of the counter CT1. For example, if the external device wishes to enable module A, it must write A setting value 1, A setting value 2, and A setting value 3 in this order to the access restriction release register 26.

[0038] In step S108, the control unit 18 judges whether the counter CT1 is equal to N. In this embodiment, for example, when N is equal to 3, the control unit 18 judges whether the counter CT1 is equal to 3. That is, the control unit 18 judges whether the set value has been written to the access restriction release register 26 for the third time since the counter CT1 was initialized.

[0039] If the determination in step S108 is positive, the process proceeds to step S110. On the other hand, if the determination in step S108 is negative, the process proceeds to step S104. In this manner, the processes in steps S104 to S108 are repeated until the process of writing the setting value of the access restriction release register 26 has been performed N times.

[0040] In step S110, the control unit 18 judges whether or not an external device has instructed the control unit 18 to activate other modules. If the judgment in step S110 is affirmative, the control unit 18 proceeds to step S102 and repeats the same processing as described above. On the other hand, if the judgment in step S110 is negative, the control unit 18 ends this routine.

[0041] Next, the circuit activation process executed by the CPU 30A of the activation determination unit 24 will be described with reference to the flowchart shown in FIG. 5. The circuit activation process shown in FIG. 5 is executed by the CPU 30A reading the circuit activation program 34A stored in the storage unit 34. Note that the process shown in FIG. 5 is repeatedly executed.

[0042] In step S200, the CPU 30A initializes a counter CT2 for counting the number of times a set value is written to the access restriction release register 26. That is, "0" is assigned to the counter CT2.

[0043] In step S202, the CPU 30A determines whether there has been a write to the access restriction release register 26. If the determination in step S202 is affirmative, the process proceeds to step S204. On the other hand, if the determination in step S202 is negative, it waits until there is a write to the access restriction release register 26.

[0044] In step S204, the CPU 30A increments the value of the counter CT2 by one.

[0045] In step S206, the CPU 30A determines whether the counter CT2 is "1". That is, it determines whether it is the first time a value has been written to the access restriction release register 26 since the counter CT2 was initialized. If the determination in step S206 is affirmative, the process proceeds to step S208.

[0046] In step S208, the CPU 30A determines whether the value written to the access restriction release register 26 matches any of the set values 1 for each module set in the set value table 28. If the determination in step S208 is affirmative, the process proceeds to step S210. On the other hand, if the determination in step S208 is negative, the process returns to step S200 and this routine is executed from the beginning.

[0047] In step S210, CPU 30A identifies a module that is a candidate for activation. For example, if the value written to access restriction release register 26 matches setting value 1 for A in setting value table 28, module A is identified as a candidate for activation.

[0048] On the other hand, if the determination in step S206 is negative, that is, if the counter CT2 is equal to or greater than 2, the process proceeds to step S212.

[0049] In step S212, CPU 30A determines whether or not the setting value [CT2] of the activation candidate module identified in step S210 matches, where [CT2] represents the value of counter CT2.

[0050] Specifically, for example, if the module to be enabled is identified as module A in step S210 and CT2=2, it is determined whether the value written to the access restriction release register 26 matches the setting value 2 for A in the setting value table 28.

[0051] If the determination in step S212 is positive, the process proceeds to step S214. On the other hand, if the determination in step S212 is negative, the process proceeds to step S200, and this routine is executed from the beginning.

[0052] In step S214, CPU 30A judges whether CT2=N. That is, CPU 30A judges whether the number of times a value has been written to access restriction release register 26 has reached N. If the judgment in step 214 is affirmative, CPU 30A proceeds to step S216. On the other hand, if the judgment in step 214 is negative, CPU 30A proceeds to step S202 and waits until a value is written to access restriction release register 26.

[0053] In step S216, CPU 30A enables the module that is a candidate for activation identified in step S210, thereby enabling access to the enabled module and its register group.

[0054] Thus, in this embodiment, since the setting values necessary for enabling the modules are set for each module, it is possible to enable some of the plurality of modules.

[0055] Also, when enabling a module, it is necessary to write the N setting values set for the module to be enabled to the access restriction release register 26 in a predetermined order. That is, if even one of the N setting values is incorrect or the writing order is incorrect, the module cannot be enabled. This restricts unauthorized access to the module.

[0056] Note that after enabling a module, until the enabling is released, the external device can access the register group for the enabled module and the module.

[0057] By the way, when the external device accesses the module, there may be a case where the external device does not want to disclose the addresses of all areas of the module.

[0058] Therefore, the external device may be provided with the start address of the module, and when continuously writing data to the enabled module, the address may be incremented from the start address of the module to write the data.

[0059] For example, in normal writing, assume that data1 is written to address 0x1000 of module A, data2 is written to address 0x1004, and data3 is written to address 0x1008. In this case, the start address 0x1000 of module A is disclosed, and after writing data1 to address 0x1000 of module A, the address is incremented from 0x1000 to write data2 to address 0x1004, and the address 0x1004 is incremented to write data3 to address 0x1008. Thus, since only the start address of the module needs to be disclosed, unauthorized access to the module is suppressed.

[0060] Also, when continuously activating modules, the activation of the next module may be started after the settings for the activated module are completed. Specifically, when continuously activating modules A and B, after module A is activated in the process of FIG. 5, the activation process of module B cannot be executed unless the settings for module A are performed on the register group 27A.

[0061] In addition, in this embodiment, the case where there is one access restriction release register 26 has been described. However, a plurality of access restriction release registers may be provided, and when a plurality of set values are written in the plurality of access restriction release registers in a predetermined order, the modules corresponding to the plurality of set values and the predetermined order may be activated. Specifically, for example, when N = 3, access restriction release registers 26-1, 26-2, and 26-3 are provided. When it is desired to activate module A, module A is activated when the set value 1 for A is written in the access restriction release register 26-1, the set value 2 for A is written in the access restriction release register 26-2, and the set value 3 for A is written in the access restriction release register 26-3. Thereby, unauthorized access to the module is further restricted.

[0062] Note that the flow of the processing of the circuit activation program 34A described in each of the above embodiments (see FIG. 5) is an example, and it goes without saying that unnecessary steps may be deleted, new steps may be added, or the processing order may be changed within the scope not departing from the gist of the present invention.

[0063] Also, the configuration of the circuit 10 for a specific user (see FIG. 1) is also an example, and it goes without saying that unnecessary parts may be deleted or new parts may be added within the scope not departing from the gist of the present invention.

[0064] In addition, in this embodiment, the form in which the circuit activation program 34A is installed in the storage unit 34 has been described, but the present invention is not limited to this. The information processing program according to this embodiment may be provided in a form recorded on a computer-readable storage medium. For example, the information processing program according to this embodiment may be provided in a form recorded on an optical disc such as a CD (Compact Disc)-ROM and a DVD (Digital Versatile Disc)-ROM, or in a form recorded on a semiconductor memory such as a USB (Universal Serial Bus) memory and a memory card. Further, the circuit activation program 34A according to this embodiment may be acquired from an external device via a communication line connected to the communication unit 32.

[0065] In the above embodiment, the processor refers to a processor in a broad sense, including a general-purpose processor (for example, a CPU: Central Processing Unit, etc.) and a dedicated processor (for example, a GPU: Graphics Processing Unit, an ASIC: Application Specific Integrated Circuit, an FPGA: Field Programmable Gate Array, a programmable logic device, etc.).

[0066] Also, the operation of the processor in the above embodiment may be achieved not only by one processor but also by a plurality of physically separated processors cooperating with each other. Further, the order of each operation of the processor is not limited to the order described in the above embodiments and may be changed as appropriate.

Explanation of Signs

[0067] 10 Circuit for Specific User 12 General-Purpose Circuit 14 User Circuit 16 Control Unit 16 User Circuit 16 General-Purpose Register Unit 18 Control Unit 20 User Circuit Enable Register 22 User register section 24 Validation Judgment Unit 26 Access Restriction Release Register 27A, 27B, 27C Register Group 28 Setting value table 30 Controller 32 Communications Department 34 Storage section 34A Circuit Enabler A, B, C Modules

Claims

1. A circuit activation device comprising a processor, wherein the processor enables modules corresponding to a plurality of preset values and a preset order when the plurality of preset values for each module are written in a preset order to a register for individually enabling modules of a user circuit having a plurality of modules and a specific user-oriented circuit having a general-purpose circuit .

2. For an enabled module, a start address is made public, wherein the processor when continuously writing data to the enabled module, increments the address from the start address and writes the data , the circuit activation device according to Claim 1

3. The processor enables modules corresponding to the plurality of preset values and the preset order when the plurality of preset values are written in the preset order to a plurality of registers , the circuit activation device according to Claim 1 or Claim 2

4. The processor when continuously enabling the modules, starts enabling the next module after the setting for the enabled module is completed , the circuit activation device according to any one of Claims 1 to 3

5. A circuit activation program that causes a computer to execute a process of enabling modules corresponding to a plurality of preset values and a preset order when the plurality of preset values for each module are written in a preset order to a register for individually enabling modules of a user circuit having a plurality of modules and a specific user-oriented circuit having a general-purpose circuit .

6. A general-purpose circuit, a user circuit comprising a plurality of modules, a register for individually enabling the plurality of modules, and an enabling determination unit that enables modules corresponding to the plurality of preset values and the preset order when the plurality of preset values for each module are written in the preset order to the register , a specific user-oriented circuit comprising the same

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