Method for manufacturing a photonic device

Abstract

Electro-optical devices, such as switches or phase shifters, and methods for constructing electro-optical devices include depositing an electrode layer on a substrate layer, depositing a waveguide structure on the electrode layer, depositing a first cladding layer on the waveguide structure, and planarizing and bonding the first cladding layer to a wafer. The substrate layer is removed, and the electrode layer is etched to divide the electrode layer into a first electrode separated from a second electrode. A second cladding layer is deposited on the etched electrode layer. The first and second electrodes may be composed of a material having a high dielectric constant, or they may be composed of a material having high electron mobility. The device may exhibit a sandwiched waveguide architecture, with an electro-optic layer disposed between two strip-like waveguides.

Description

Technical Field

[0001] Claim of Priority This application claims priority to U.S. Provisional Patent Application No. 62 / 984,759, filed on March 3, 2020, with the title "Fabrication Method for Photonic Device", and the entire disclosure of the provisional patent application is hereby incorporated by reference in its entirety as if fully set forth herein.

[0002] Embodiments herein generally relate to the fabrication of electro-optic devices such as phase shifters and switches.

Background Art

[0003] Electro-optic (EO) modulators and switches have been used in the optical field. Some EO modulators utilize free carrier electrorefraction, free carrier electric field absorption, the Pockels effect, or the DC Kerr effect to modulate the properties of light during operation, for example, changing the phase of light propagating through an EO modulator or switch. As an example, an optical phase modulator can be used in integrated optics, waveguide structures, and integrated optoelectronics.

[0004] Despite the progress made in the field of EO modulators and switches, there remains a need in the art for improved methods and systems related to the fabrication and architecture of EO modulators and switches.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Some embodiments described herein relate to photonic devices and methods for fabricating photonic devices such as electro-optic switches and phase shifters.

Means for Solving the Problems

[0006] In some embodiments, the device includes a first cladding layer, a first electrode, a second electrode, a waveguide structure made of a first material, and a second cladding layer. The waveguide structure is coupled to the first electrode and the second electrode. In some embodiments, the first electrode and the second electrode are made of a second material having an electron mobility higher than that of silicon.

[0007] In some embodiments, the device includes a first cladding layer, a first electrode, a second electrode, a second cladding layer, and a waveguide structure. The waveguide structure may include an electro-optic layer made of a first material, a first strip-shaped waveguide portion made of a second material, and a second strip-shaped waveguide portion made of a third material. The electro-optic layer may be disposed between the first strip-shaped waveguide portion and the second strip-shaped waveguide portion. The electro-optic layer may be coupled to the first electrode and the second electrode.

[0008] In some embodiments, a method of fabricating the device is described.

[0009] For example, in some embodiments, a seed layer is deposited on a substrate layer, an electro-optic layer is deposited on the seed layer, and a first cladding layer is deposited on the electro-optic layer. In some embodiments, a prefabricated first wafer composed of the stacked substrate layer, seed layer, electro-optic layer, and / or first cladding layer can be accepted as a starting point for further fabrication steps.

[0010] In some embodiments, the first cladding layer is planarized and bonded to a second wafer. The substrate layer is removed, and the seed layer is etched to split the seed layer into a first electrode separated from a second electrode. A second cladding layer is deposited on the etched seed layer. In some embodiments, the second cladding layer is etched to expose a first portion of the first electrode and a second portion of the second electrode. A first lead is deposited on the first electrode so as to pass through the exposed first portion, and a second lead is deposited on the second electrode so as to pass through the exposed second portion.

[0011] In some embodiments, a seed layer is deposited on a substrate layer, an electro-optic layer is deposited on the seed layer, and an electrode layer is deposited on the electro-optic layer. In some embodiments, a prefabricated first wafer comprising the stacked substrate layer, seed layer, electro-optic layer, and / or electrode layer can be received as a starting point for further fabrication steps.

[0012] In some embodiments, the electrode layer is etched to expose a portion of the electro-optic layer, and the electrode layer is split into a first electrode separated from a second electrode. A first cladding layer is deposited on the exposed portion of the electro-optic layer and on the first and second electrodes. The first cladding layer is planarized and bonded to a second wafer. The substrate layer and the seed layer are removed, and after removal of the substrate layer and the seed layer, the electro-optic layer is etched to fabricate a ridge waveguide having a first thickness disposed between a first slab layer and a second slab layer, where the first slab layer and the second slab layer have a second thickness smaller than the first thickness. A second cladding layer is deposited on the first and second slab layers and on the ridge waveguide structure.

[0013] In some embodiments, a seed layer is deposited on a substrate layer, an electro-optic layer is deposited on the seed layer, and a first cladding layer is deposited on the electro-optic layer. In some embodiments, a prefabricated first wafer comprising the stacked substrate layer, seed layer, electro-optic layer, and / or first cladding layer can be received as a starting point for further fabrication steps.

[0014] In some embodiments, the first cladding layer is planarized and adhered to the wafer. The substrate layer and the seed layer are removed, and after removal of the substrate layer and the seed layer, the electro-optic layer is etched to fabricate a ridge waveguide having a first thickness disposed between a first slab layer and a second slab layer, where the first and second slab layers have a second thickness smaller than the first thickness. First and second electrodes are deposited on the left and right sides of the ridge waveguide structure, respectively. And a second cladding layer is deposited on the first and second electrodes and the ridge waveguide structure.

[0015] The above "Summary of the Invention" is intended to provide an overview of some of the subject matter described in this document. Accordingly, it will be understood that the above features are merely examples and should in no way be construed as narrowing the scope or spirit of the subject matter described herein. Other features, aspects, and advantages of the subject matter described herein will become apparent from the following "Detailed Description of the Invention", drawings, and claims.

[0016] To better understand the various embodiments described, reference should be made to the following "Detailed Description of the Invention" in conjunction with the following drawings. In the following drawings, like reference numerals refer to corresponding parts throughout the several views.

Brief Description of the Drawings

[0017]

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Best Mode for Carrying Out the Invention

[0018] The features described in this specification can accept various modifications and alternative forms. However, specific embodiments are shown in the drawings as examples and are described in detail in this specification. However, the drawings and their detailed descriptions are not intended to limit to the specific forms disclosed, but rather are intended to cover all modifications, equivalents, and alternatives within the spirit and scope of the subject matter defined by the appended claims.

[0019] Hereinafter, a plurality of embodiments will be referred to in detail. Examples of these embodiments are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments described herein. However, it will be apparent to those skilled in the art that the various embodiments described herein may be practiced without these specific details. In other instances, well - known methods, procedures, components, circuits, and networks are not described in detail so as not to unnecessarily obscure aspects of the embodiments.

[0020] Also, in some examples, although terms such as "first", "second", etc. are used in this specification for the description of various elements, it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various embodiments described herein, the first electrode layer can also be called the second electrode layer, and similarly, the second electrode layer can also be called the first electrode layer. The first electrode layer and the second electrode layer are both electrode layers, but not the same electrode layer.

[0021] The above description has been presented for purposes of illustration and is described with reference to specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or to limit the claims to the precise forms disclosed herein. Numerous modifications and variations are possible in light of the above teachings. These embodiments have been selected in order to best explain the principles underlying the claims and their practical application, so as to enable those skilled in the art to make the best use of these embodiments with various modifications suitable for the particular purposes contemplated.

[0022] Embodiments of the present invention relate to optical systems. More particularly, embodiments of the present invention utilize high dielectric constant materials (i.e., high-κ materials) in optical modulators and switches to reduce power consumption during operation. As used herein, "high dielectric constant material" is intended to refer to a material having a higher dielectric constant compared to other materials within the components in which the optical modulator or switch operates, and particularly compared to the materials used in the construction of waveguides. As a mere example, embodiments of the present invention are provided in the context of integrated optical systems including active optical devices, but the present invention is not limited to this example and is widely applicable to various optical systems and optoelectronic systems.

[0023] According to some embodiments, the active photonic devices described herein utilize electro-optic effects such as refractive index variations induced by free carriers in a semiconductor and / or the DC Kerr effect to implement modulation and / or switching of optical signals. Thus, embodiments of the present invention are applicable to both modulators in which transmitted light is modulated to ON or OFF or light is modulated by a partial change in transmittance, and optical switches in which transmitted light is output at a first output (e.g., a waveguide) or a second output (e.g., a waveguide), or an optical switch having three or more outputs and two or more inputs. Thus, embodiments of the present invention are applicable to various designs including M (input) × N (output) systems that utilize the methods, devices, and techniques described herein. Some embodiments also relate to electro-optic phase shifter devices that can be used within a switch or modulator, which is also referred to herein as a phase adjustment section.

[0024] FIG. 1 is a simplified schematic diagram showing an optical switch according to an embodiment of the present invention. Referring to FIG. 1, switch 100 includes two inputs: input 1 and input 2, and two outputs: output 1 and output 2. As an example, the inputs and outputs of switch 100 can be implemented as optical waveguides operable to support single-mode or multi-mode optical beams. As an example, switch 100 can be implemented as a Mach-Zehnder interferometer integrated with a pair of 50 / 50 beam splitters 105, 107. As shown in FIG. 1, input 1 and input 2 are optically coupled to a first 50 / 50 beam splitter 105, also referred to as a directional coupler, which receives light from input 1 or input 2 and directs 50% of the input light from input 1 to waveguide 110 and 50% of the input light from input 1 to waveguide 112 by evanescent coupling at the 50 / 50 beam splitter. At the same time, the first 50 / 50 beam splitter 105 directs 50% of the input light from input 2 to waveguide 110 and 50% of the input light from input 2 to waveguide 112. Considering only the input light from input 1, the input light is evenly split between waveguide 110 and waveguide 112.

[0025] The Mach-Zehnder interferometer 120 includes a phase adjustment section 122. A voltage V0 can be applied to the waveguide of the phase adjustment section 122 so that the refractive index of the phase adjustment section 122 can be controllably changed. Since the light in waveguides 110 and 112 still has a well-defined phase relationship (for example, they may be in-phase, 180° out of phase, etc.) after propagating through the first 50 / 50 beam splitter 105, the phase adjustment in the phase adjustment section 122 can introduce a predetermined phase difference between the light propagating in waveguide 130 and the light propagating in waveguide 132. As will be apparent to those skilled in the art, the phase relationship between the light propagating in waveguide 130 and the light propagating in waveguide 132 can result in output light existing at output 1 (for example, the light beams are in-phase), or output light existing at output 2 (for example, the phases of the light beams are shifted), whereby the light is directed to output 1 or output 2 as a function of the voltage V0 applied to the phase adjustment section 122, thus providing a switching function. Although a single active arm is illustrated in FIG. 1, it will be understood that both arms of the Mach-Zehnder interferometer can include a phase adjustment section.

[0026] As shown in FIG. 1, electro-optic switch technology utilizes the application of an electrical bias (e.g., V0 in FIG. 1) across the active region of the switch to generate an optical change as compared to all-optical switch technology. The electric field and / or current generated by the application of this voltage bias results in a change in one or more optical properties of the active region, such as the refractive index or absorbance.

[0027] Although FIG. 1 illustrates an implementation of a Mach-Zehnder interferometer, embodiments of the present invention are not limited to this particular switch architecture, and other phase adjustment devices including ring resonator designs, Mach-Zehnder modulators, generalized Mach-Zehnder modulators, etc. are included within the scope of the present invention. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0028] In some embodiments, the optical phase shifter devices described herein can be utilized within a quantum computing system such as the hybrid quantum computing system shown in FIG. 10. Alternatively, these optical phase shifter devices may be used in other types of optical systems. For example, in various embodiments, other computing, communication, and / or technology systems may utilize a photonic phase shifter to direct optical signals (e.g., single photons or continuous wave (CW) optical signals) within a system or network, and the phase shifter architectures described herein may be used within these systems.

[0029] FIGS. 2 - 8 Cross-sectional views of photonic phase shifters FIGS. 2 - 8 are simplified cross-sectional views showing various architectures of photonic phase shifters according to various embodiments. Note that the architectures shown in FIGS. 2 - 8 are schematic diagrams and the scales are not necessarily accurate. Although the architectures shown in FIGS. 2 - 8 differ with respect to several important design features, they also share some features. For example, as will be described in more detail below, FIGS. 2 - 8 each exhibit two electrical contacts, and each electrical contact includes leads (230, 330, 430, 530, 630, 730, 830, and 232, 332, 432, 532, 632, 732, 832) connected to electrodes (240, 340, 440, 540, 640, 740, 840, and 242, 342, 442, 542, 642, 742, 842). As used herein, the term "electrode" refers to a device component that is directly coupled to a waveguide structure (e.g., to vary the voltage drop across the waveguide structure to operate a photonic switch). Further, the term "lead" refers to a backend structure that couples an electrode to other components of the device (e.g., a lead may couple an electrode to a controllable voltage source), but the lead is separated from the waveguide structure and is not directly coupled to the waveguide structure. In some embodiments, the lead may be composed of a metal (e.g., copper, gold, etc.) or a semiconductor material.

[0030] The electrodes are configured to extend in proximity to the position of the optical mode of the waveguide, and the photonic phase shifter is configured to change the cumulative phase of the photonic mode passing through the waveguide by introducing a controllable voltage difference across two electrodes (e.g., dielectric electrodes in some embodiments). For example, the electrodes may be coupled via leads to a voltage source that provides the controllable voltage difference.

[0031] In some embodiments, the electrodes may be composed of a High-κ dielectric material having a high relative permittivity, whereby the electrodes have a higher relative permittivity than the material of the waveguide and / or the slab layer. As used herein, κ is used to represent the relative permittivity, which is the real part of the complex relative permittivity:

[0032] [Number]

[0033] which refers to, where ε r is the complex relative permittivity, ε is the absolute permittivity of the material, and ε0 is the permittivity of vacuum. Note that for clarity, the imaginary part of ε r is related to the conductivity of the material, while the real part κ is related to the dielectric polarization rate of the material.

[0034] The relative permittivity of a material may have different values for an alternating current (AC) voltage in the presence of a direct current (DC) voltage, and the relative permittivity of the material at an AC voltage can be a function of frequency κ(ω). Thus, in some embodiments, when selecting the material of the electrodes, the slab layer, and / or the raised waveguide, the relative permittivity of the material at the operating frequency of the photonic phase shifter may be considered.

[0035] The electrodes may be composed of a material having a higher relative permittivity than the first material of the slab layer along the direction separating the first electrode and the second electrode (e.g., the x direction in FIGS. 2-5, 7-8, or the y direction in FIG. 6). For example, in an anisotropic medium, the permittivity tensor ε can be represented by the following matrix that relates the electric field E to the electric displacement D.

[0036]

Number

[0037] Here, component ε xx 、 ε xy etc. indicate the individual components of the permittivity tensor. In some embodiments, the materials of the first and second electrodes can be selected such that the diagonal components of the permittivity tensor along the direction separating these electrodes are greater than the corresponding diagonal components of the permittivity tensor of the material of the slab layer and / or the raised portion.

[0038]

Table 1

[0039] Table 1 shows the values of χ (3) 、 refractive index, and relative permittivity for various materials. As shown in Table 1, since STO has a very high relative permittivity for temperatures below 10K, STO can be a desirable material for use in electrodes. However, in some embodiments, BTO may be used for the slab layer and / or the raised portion of the waveguide.

[0040] As shown, the architectures shown in FIGS. 2 - 8 each show a photonic device having first and second cladding layers. For example, the regions indicated by 210, 310, 410, 510, 610, 710, 810 represent the first cladding layer on one side of the waveguide, and the regions indicated by 212, 312, 412, 512, 612, 712, 812 represent the second cladding layer on the other side of the waveguide. Note that the terms "first" and "second" are intended merely to distinguish between the two cladding layers. For example, the term "first cladding layer" can refer to the cladding layer on either side of the waveguide. In some embodiments, the refractive indices of the first and second cladding layers may be lower than the refractive index of the waveguide structure.

[0041] Figures 2 to 8 further show a first electrical contact including a first lead (230, 330, 430, 530, 630, 730, 830) coupled to a first electrode (240, 340, 440, 540, 640, 740, 840), and a second electrical contact including a second lead (232, 332, 432, 532, 632, 732, 842) coupled to a second electrode (242, 342, 442, 542, 642, 742, 842). The first and second leads may be made of a conductive material such as metal, or alternatively, they may be made of a semiconductor material. In various embodiments, the first electrode and the second electrode are made of gallium arsenide (GaAs), aluminum gallium arsenide (Al x G 1-x As) / GaAs heterostructure, indium gallium arsenide (InGaAs) / GaAs heterostructure, zinc oxide (ZnO), zinc sulfide (ZnS), indium oxide (InO), doped silicon, strontium titanate (STO), doped STO, barium titanate (BTO), barium strontium titanate (BST), hafnium oxide, lithium niobate, zirconium oxide, titanium oxide, graphene oxide, tantalum oxide, lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), strontium barium niobate (SBN), aluminum oxide, aluminum oxide, one or more of their doped and deformed forms or solid solutions, or two-dimensional electron gas. For embodiments in which the first and second electrodes are made of doped STO, STO may be doped with niobium, doped with lanthanum, or doped with vacancies, depending on the various embodiments.

[0042] Figures 2 to 8 show waveguide structures including slab layers (220, 320, 420, 520, 651, 754, 851) made of a first material, and the slab layers are coupled to a first electrode of a first electrical contact and a second electrode of a second electrical contact. In some embodiments, the waveguide structure further includes raised portions (251, 351, 451, 551) made of a first material (or a different material) and coupled to the slab layer, and the raised portions are disposed between the first electrical contact and the second electrical contact. In various embodiments, the first material is one of strontium titanate (STO), barium titanate (BTO), barium strontium titanate (BST), hafnium oxide, lithium niobate, zirconium oxide, titanium oxide, graphene oxide, tantalum oxide, lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), strontium barium niobate (SBN), aluminum oxide, aluminum oxide, or a doped, deformed form or solid solution thereof. In some embodiments, the first material may be a transparent material having a refractive index higher than the refractive indices of the first and second cladding layers.

[0043] In some embodiments, the second material that constitutes the first and second electrodes can be selected based on the first material that constitutes the slab layer and / or the waveguide structure. For example, the second material can be selected such that the second material has a relative permittivity higher than that of the first material. As an example, when the first material is BTO, the second material can be selected to be STO, which has a relative permittivity higher than that of BTO at cryogenic temperatures (e.g., 4K) at which the photonic device is designed to operate. Advantageously, due to the high relative permittivity of the electrode, for a given acceptable level of loss from the waveguide to the electrode, this electrode can be placed closer to the waveguide compared to a metal electrode. For example, due to the high conductivity of a metal electrode, the degree of photon absorption (i.e., loss) from the waveguide is greater compared to the absorption of an electrode spaced equally from the waveguide. Thus, for a given loss tolerance, the electrode can be placed closer to the waveguide compared to a metal electrode. The high relative permittivity of the electrode corresponds to a high polarization rate of the dielectric material, which provides an energy-efficient control mechanism for adjusting the electric field of the waveguide structure.

[0044] In some embodiments, the materials used for the electrodes and the waveguide structure can be selected based on their effective relative permittivities. For example, while the relative permittivity of a material (or the dielectric tensor for an anisotropic material) is an inherent property of the material, the effective relative permittivity of a structure depends not only on being proportional to its relative permittivity but also on the shape and dimensions of the structure. In these embodiments, the materials used for the first and second electrodes can be selected such that the effective relative permittivities of the first and second electrodes are higher than the effective relative permittivity of the waveguide structure.

[0045] In some embodiments, cryogenic devices such as the cryostat 1113 shown in FIG. 10 can be configured to maintain the first electrical contact, the second electrical contact, and the waveguide structure at cryogenic temperatures, e.g., 77 Kelvin or less.

[0046] In some embodiments, the first electrical contact and the second electrical contact are configured to generate an electric field within the waveguide structure along one or more directions, e.g., along the x-direction, and the waveguide structure has an electro-optic coefficient (e.g., Pockels coefficient χ (2) , or Kerr coefficient χ (3) ) that may be characterized as having a non-zero value aligned along the direction of the electric field. As shown, for example, in FIG. 10, an electric field may be generated within the waveguide structure by coupling a lead to a voltage source that applies a controllable (e.g., programmable) voltage difference. Further, or alternatively, the guided mode supported by the waveguide structure may have a polarization direction aligned in the x-direction.

[0047] In some embodiments, the first electrode and the second electrode are configured as a second layer disposed in the same plane as the slab layer and adjacent to a first side of the slab layer. For example, the first and second electrodes may be grown on the first side of the grown slab layer (e.g., using other methods such as epitaxy, or metal-organic chemical vapor deposition, electron beam epitaxy, physical vapor deposition, sol-gel) such that the first and second dielectric layers are directly bonded to the slab layer. Alternatively, in some embodiments, an intervening layer may be disposed between the slab layer and the first and second dielectric layers such that the slab layer and the first and second dielectric layers are indirectly bonded. In some embodiments, the intervening layer may be composed of an oxide material.

[0048] The first electrode and the second electrode may be separated by a gap region, e.g., gap region 243 or 343. In some embodiments, the gap region may be etched and filled with a cladding material. In some embodiments, both the first and second electrodes may be grown as a single second layer covering the slab layer, followed by etching a region to separate the first electrode from the second electrode. Subsequently, the etched region may be filled with a cladding material. Alternatively, the etched region may be left empty (i.e., filled with air or vacuum).

[0049] In some embodiments, the first electrode and the second electrode have a relative permittivity higher than that of the first material in a direction separating the first electrode and the second electrode. The relative permittivity of the first electrode and the second electrode may be higher than the relative permittivity of the waveguide structure at a first temperature higher than 1 mK, less than 77 K, less than 150 K, and / or within another temperature range. In some embodiments, the first material is a transparent material having a refractive index higher than the refractive indices of the first and second cladding layers. In some embodiments, the ratio between the relative permittivity of the first and second electrodes and the relative permittivity of the first material is 2 or more.

[0050] Transparent electrode The conductivity of a material is proportional to both its carrier mobility (e.g., electron mobility or hole mobility) and its carrier concentration (e.g., its free electron density or hole density). It may be desirable to increase the conductivity of the electrodes of a photonic phase shifter device. This is because it can improve the control of the device at higher frequencies and / or with reduced heating of the electrodes. However, a high free electron density in the electrodes may not be desirable. This is because an electrode with a high free electron density can provide a large absorptive reservoir for photons within the waveguide structure that will be absorbed by the free electrons of the electrode (e.g., escaping from the waveguide structure to the electrode). In other words, increasing the conductivity of the electrodes by increasing the free electron density of the material selected for the electrodes may not be desirable because it may increase the photonic loss rate of the device.

[0051] To address these concerns and others, in some embodiments, the electrodes may be composed of a second material selected to have a high conductivity by virtue of a high carrier mobility rather than a high carrier concentration. Advantageously, this high carrier mobility material can, in proportion, generate a high conductivity without introducing high photon absorption. The high carrier mobility material can exhibit desirable conductive properties while maintaining transparency to the optical mode in the waveguide due to its relatively low carrier concentration (e.g., low compared to a material having a similar conductivity and low carrier mobility). In classical Drude theory, free carrier absorption is predicted to be proportional to the doping level and inversely proportional to the optical mobility. Thus, materials with high mobility may exhibit a reduction in both resistance and free carrier absorption.

[0052] For example, in some embodiments, the first electrode and the second electrode are composed of a second material, and the second material has a high carrier mobility (e.g., high electron mobility or high hole mobility). As an example, the second material can be selected such that its electron mobility is higher than that of silicon. In some embodiments, the second material can be selected to have a bandgap larger than the operating frequency of the device.

[0053] In some embodiments, the second material consists of one of gallium arsenide (GaAs), aluminum gallium arsenide (Al x G 1-x As) / GaAs heterostructure, indium gallium arsenide (InGaAs) / GaAs heterostructure, zinc oxide (ZnO), zinc sulfide (ZnS), indium oxide (InO), doped silicon, two-dimensional electron gas, or doped strontium titanate (STO). For embodiments where the second material consists of doped STO, the doped STO may be doped with niobium, lanthanum, or vacancies, among other possible options. For example, the electron mobility of bulk GaAs is 8500 cm 2 / Vs, which is six times higher than the electron mobility of silicon. The InGaAs / GaAs heterostructure can reach a mobility of 41000 cm 2 / Vs at 4 Kelvin, and the Al x G 1-x As / GaAs heterostructure can reach a mobility of up to 180,000 cm 2 / Vs. For comparison, the mobility of Si is 1500 cm 2 / Vs. The doped STO can also exhibit a high electron mobility of 10,000 cm 2 / Vs to 53,000 cm 2 / Vs depending on the carrier concentration.

[0054] For embodiments where the second material is a doped material, the doping concentration can be selected based on the absorption characteristics of the resulting doped material. For example, the absorption of the doped material can be analyzed at one or more operating frequencies of the electro - photonic device for each of a plurality of doping concentrations, and a doping concentration that exhibits low absorption at the one or more operating frequencies can be selected.

[0055] The following several paragraphs describe various design features that differ among the architectures shown in FIGS. 2 - 8.

[0056] FIG. 2 shows an architecture in which the raised portion (251) of the waveguide structure is disposed at the bottom of the slab layer and extends into the first cladding layer (210). As shown in FIG. 2, the combination of the raised portion and the slab layer has a first thickness (262) greater than the second thickness (260) of the slab layer alone (220), and the portion of the first thickness that exceeds the second thickness extends into the cladding layer (210) below the slab layer. As shown in FIG. 2, the first electrode (240) and the second electrode (242) are coupled to the slab layer (220) on the upper side of the slab layer opposite the lower side. Further, the first electrical contact (230) and the second electrical contact (232) are disposed on the upper side of the slab layer (220). Note that the terms “top” and “bottom” are used with respect to the view shown in the drawing for clarity and do not necessarily refer to any specific direction with respect to the entire device.

[0057] FIG. 3 shows an architecture in which the raised portion (351) of the waveguide structure is disposed on the upper side of the slab layer and extends into the first cladding layer (312), and the first electrode and the second electrode are coupled to the slab layer on the lower side of the slab layer opposite the upper side. As shown, the combination of the raised portion and the slab layer has a first thickness (362) greater than the second thickness (360) of the slab layer (320) alone, and the portion of the first thickness that exceeds the second thickness extends into the first cladding layer (312) above the slab layer (320). As shown in FIG. 3, the first electrode (340) and the second electrode (342) are coupled to the slab layer (320) on the lower side of the slab layer opposite the upper side. Further, the first electrical contact (330) is coupled to the first electrode (340) by passing through the slab layer (320) from the upper side of the slab layer to the lower side, and the second electrical contact (332) is coupled to the second electrode (342) by passing through the slab layer (320) from the upper side of the slab layer to the lower side.

[0058] FIG. 4 shows an architecture in which the combination of the slab layer and the raised portion (451) of the waveguide structure has a first thickness (462) greater than the second thickness (460) of the slab layer (420), and the portion of the first thickness that exceeds the second thickness extends into the first cladding layer (412) above the slab layer. As shown in FIG. 4, the first electrode (440) and the second electrode (442) are coupled to the first material (420) above the slab layer. Further, the first electrode (440) and the second electrode (442) abut against the raised portion of the waveguide structure (451).

[0059] FIG. 5 shows an architecture in which the waveguide structure includes a first strip-shaped waveguide portion (554) and a second strip-shaped waveguide portion (556), the first and second waveguides are composed of a second material, and the slab layer (520) is disposed between the first waveguide portion (554) and the second waveguide portion (556). The first electrode (540) and the second electrode (542) are disposed on the electro-optic layer (520), the first lead (530) is coupled to the first electrode, and the second lead (532) is coupled to the second electrode. The device architecture shown in FIG. 5 can be fabricated by the method described with reference to FIG. 15 according to some embodiments.

[0060] In some embodiments, the first strip-shaped waveguide portion is composed of silicon nitride (Si3N4), and the second strip-shaped waveguide portion is composed of silicon. In other embodiments, both the first and second strip-shaped waveguide portions are composed of silicon nitride (Si3N4). Alternatively, the first and second waveguide portions may be composed of Si3N4, silicon dioxide (SiO2), aluminum oxide (Al2O3), or another material, respectively and separately.

[0061] As shown in FIG. 5, the first electrode and the second electrode abut against the first strip-shaped waveguide, and the first electrode and the second electrode have a first thickness (562). In some embodiments, the first electrode and the second electrode are in the same plane as the electro-optic layer and include a second layer disposed adjacent to the first side surface of the electro-optic layer.

[0062] In some embodiments, the first and second strip-shaped waveguide portions are configured to concentrate the maximum intensity portion of the optical mode within the electro-optic layer. In other words, having only the first strip-shaped waveguide portion (554) on one side of the slab layer (520) and a cladding layer on the other side (i.e., not having the second strip-shaped waveguide portion 556), or having only the second strip-shaped waveguide portion (556) on one side of the slab layer (520) and a cladding layer on the other side (i.e., not having the first strip-shaped waveguide portion 554), may result in a vertically offset and / or less concentrated optical mode. In some embodiments, the first strip-shaped waveguide portion abuts the slab layer, and the second strip-shaped waveguide portion is separated from the slab layer by a small distance (e.g., a distance such as a few nanometers). Alternatively (not shown in FIG. 5), both the first and second strip-shaped waveguide portions may abut the slab layer.

[0063] FIG. 6 shows a vertical waveguide architecture in which the first electrode (642) is coupled to the slab layer (651) above the slab layer, and the second electrode (640) is coupled to the slab layer (651) below the slab layer on the side opposite the above upper side. In other words, the first and second electrodes are coupled to the upper and lower sides of the waveguide structure such that the induced electric field within the waveguide structure is oriented along the y direction.

[0064] FIG. 7 shows a waveguide architecture in which the first electrode (740) and the second electrode (742) are arranged in a straight line within the waveguide structure (754). In other words, each of the first and second electrodes and the waveguide structure are arranged within a single layer having a single width.

[0065] FIG. 8 shows a waveguide architecture in which a first electrode (840) and a second electrode (842) share a raised profile, and the raised profile extends into a first cladding layer (812). For example, the first electrode (840) may include a raised portion (844) having a thickness (862) greater than the thickness (860) of the remainder of the first electrode, and the second electrode (842) may include a raised portion (846) having a thickness (862) greater than the thickness (860) of the remainder of the second electrode. Further, the raised portions of the first and second electrodes may exhibit the same thickness as the waveguide structure (851).

[0066] FIG. 9 Top view of a photonic phase shifter FIG. 9 is a top view of the architecture of a photonic phase shifter according to some embodiments. As shown, the phase shifter may include a first lead (930) and a second lead (932), a first electrode (940) and a second electrode (942), a slab (e.g., waveguide) layer (920), and a raised portion (951) of the waveguide structure.

[0067] FIG. 10 Hybrid quantum computing system Figure 10 is a simplified schematic diagram showing the incorporation of an electro-optical switch with a cryostat into a hybrid quantum computing system according to some embodiments. For operation at low temperatures, such as the temperature of liquid helium, embodiments of the present invention incorporate the electro-optical switch described herein into a device that includes a cooling system. In so doing, embodiments of the present invention provide an optical phase shifter that can be used within a hybrid computing system, such as that shown in FIG. 8. Hybrid computing system 1101 includes a user interface device 1103 communicatively coupled to a hybrid quantum computing (QC) subsystem 1105. The user interface device 1103 can be a terminal that includes any type of user interface device, such as a display, keyboard, mouse, touch screen, etc. Further, the user interface device itself can be a computer, such as a personal computer (PC), laptop, tablet computer, etc. In some embodiments, the user interface device 1103 provides an interface that allows a user to interact with the hybrid QC subsystem 1105. For example, the user interface device 1103 can execute software such as a text editor, an interactive development environment (IDE), a command prompt, a graphical user interface, etc., whereby the user can execute one or more quantum algorithms by programming the QC subsystem or interacting with the QC subsystem in other ways. In other embodiments, the QC subsystem 1105 may be pre-programmed, and the user interface device 1103 may be simply an interface through which a user can initiate quantum computing, monitor progress, and receive results from the hybrid QC subsystem 1105. The hybrid QC subsystem 1105 further includes a classical computing system 1107 coupled to one or more quantum computing chips 1109.In some examples, the classical computing system 1107 and the quantum computing chip 1109 can be coupled to other electronic components 1111, such as a pulsed pump laser, a microwave oscillator, a power supply, network configuration hardware, and the like.

[0068] In some embodiments that utilize cryogenic operation, the quantum computing system 1109 can be housed within a cryostat, such as cryostat 1113. In some embodiments, the quantum computing chip 1109 can include one or more constituent chips, such as a hybrid electronic chip 1115 and an integrated photonics chip 1117. Signals can be routed on-chip and off-chip via any number of paths, such as via optical interconnects 1119 and other electrical interconnects 1121.

[0069] FIG. 11 Induced Electric Field of a Photonic Phase Shifter FIG. 11 is a simplified schematic diagram showing a cross-section of the waveguide structure shown in FIG. 2, according to some embodiments, with the direction of the induced electric field indicated by arrows. As shown, the small arrows indicate the direction of the induced electric field that passes through the electrodes of the device and is generally in the positive x-direction. The electric field is curved convexly both above and below the electrodes as shown. Further, the large arrow (1150) in the positive x-direction indicates the direction of polarization of the optical mode that can pass through the slab layer and the waveguide.

[0070] FIGS. 12-15 Fabrication Method of an Electro-Optic Device Due to recent technological advancements, it has been demonstrated that high-quality ferroelectric thin films can be grown on planar Si substrates using complex molecular beam epitaxy (MBE) techniques, enabling the monolithic integration of various complex oxides into electro-optic devices using semiconductor processing technologies. BaTiO3, or BTO, is considered an optimal material for next-generation electro-optic switches due to its high Pockels coefficient, high bandwidth, and low dielectric loss. In some embodiments, SrTiO3 can be used as a buffer to epitaxially grow a blanket BTO thin film on a silicon substrate. Subsequently, a silicon dioxide (SiO2) adhesion layer can be deposited on the BTO thin film. On another silicon wafer, a silicon waveguide is formed and surrounded by a silicon dioxide cladding layer having a flat top surface, which can be obtained, for example, by chemical mechanical polishing after blanket depositing silicon dioxide on the silicon waveguide. The first wafer with the blanket BTO film formed thereon is adhered to the second wafer by wafer bonding, transferring the blanket BTO film to the flat top surface of the silicon dioxide cladding on the second wafer. Subsequently, the first wafer is removed (e.g., by grinding and / or chemical mechanical polishing), and electrodes or contacts are formed on the BTO film to enable the application of an electric field across multiple contacts. This process involves the transfer of the BTO film from one substrate to another, making it inefficient and costly and limiting the underlying device architecture. FIGS. 12-15 show an improved method for the fabrication process of the architectures of various electro-optic devices according to various embodiments.

[0071] FIGS. 12A-G are schematic diagrams showing a fabrication method for constructing an electro-optic device having a raised waveguide positioned on the side opposite to the electrode according to some embodiments.

[0072] FIG. 12A shows a first plurality of steps for constructing a device, which include depositing a seed layer (1204) on a substrate layer (1202) and depositing an electro-optical layer (1206) on the seed layer (1204). These successive layers may be deposited epitaxially or they may be deposited using another technique. In some embodiments, a first wafer including a first layer stack can be received, where the first layer stack includes the illustrated substrate layer (1202), seed layer (1204), and electro-optical layer (1206). In other words, a prefabricated wafer corresponding to what is shown in FIG. 12A can be received from a manufacturer. Alternatively, a partially completed wafer including one or more of the seed layer (1204), substrate layer (1202), and / or electro-optical layer (1206) can be received and the remaining layers can be deposited to complete the wafer.

[0073] In some embodiments, the substrate layer is a silicon-on-insulator (SOI) wafer and a first portion of the substrate layer is the uppermost silicon layer of the SOI wafer that contacts the seed layer. The SOI wafer may include a semiconductor (e.g., silicon or Si) base, an oxide layer (e.g., silicon dioxide or SiO2) on the semiconductor base substrate, and a semiconductor layer (e.g., silicon) on the oxide layer. A silicon-based SOI substrate having a silicon layer on a silicon dioxide layer on a silicon layer-based substrate is used herein as an example of an SOI substrate, but the SOI substrate can also be based on other types of semiconductors (e.g., germanium or gallium arsenide). The thicknesses of the silicon layer and the SiO2 layer on the SOI substrate can be varied according to various embodiments. In some embodiments, the thickness of the silicon layer on the SOI substrate is 150 nm or less, the thickness of the SiO2 layer can be 0.5 - 4 μm, and the silicon-based thickness can be 100 μm - 2 mm.

[0074] In some embodiments, the seed layer is composed of one of strontium titanate (STO), barium strontium titanate (BST), hafnium oxide, zirconium oxide, titanium oxide, graphene oxide, tantalum oxide, lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), strontium barium niobate (SBN), magnesium oxide (MgO), germanium (Ge), etc. In some embodiments, the seed layer may be thinner than 30 nm and can function as an interaction layer for attaching to the substrate layer. In these embodiments, the seed layer and the interaction layer can ultimately be removed in subsequent fabrication steps. Alternatively, in some embodiments, the seed layer may be thicker (e.g., having a thickness of 4 nm to 300 nm), and as will be described in more detail below, the seed layer can be split into a first electrode separated from the second electrode by later etching.

[0075] In some embodiments, the electro-optic layer is composed of one of barium titanate (BTO), barium strontium titanate (BST), lithium niobate, lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), aluminum oxide, aluminum nitrite, or strontium barium niobate (SBN). In some embodiments, the first cladding layer may be composed of silicon dioxide or another material.

[0076] In some embodiments, the step of depositing the seed layer on the substrate layer includes obtaining an SOI substrate having a clean silicon surface (e.g., Si(001) 2×1 reconstructed surface) and passivating the silicon surface using conventional techniques. After passivating the silicon surface, an SrTiO3 buffer layer can be epitaxially grown on the silicon layer. By first growing an epitaxially grown SrTiO3 layer of a thin film (about 3 nm to 30 nm) as a buffer layer, the epitaxial growth of the subsequently deposited BaTiO3 layer can be promoted. In some embodiments, the first few ML (1 to 3 ML) of SrTiO3 are, for example, 10 -8 ~1.5×10-6 Oxidation of the silicon surface can be avoided by growing at a relatively low temperature (e.g., 100 - 300 °C) under an oxygen pressure of Torr. Since most of this several ML of SrTiO3 is amorphous, an annealing process at a relatively high temperature (e.g., 500 - 750 °C) can be carried out under ultra-high vacuum conditions (e.g., a pressure of less than 5×10 -9 Torr) to crystallize the SrTiO3 grown on the silicon surface. Thereafter, further SrTiO3 can be grown at a relatively high temperature (e.g., 500 - 600 °C) or grown at a relatively low temperature (e.g., 300 - 500 °C) and then annealed at a relatively high temperature (e.g., 550 - 750 °C) until a SrTiO3 buffer layer of the desired thickness is obtained.

[0077] Figure 12b shows a method of etching an electro-optic layer to construct a raised waveguide structure (1224). Following the etching of the electro-optic layer, a first cladding layer (1208) is deposited on the electro-optic layer (1206). For example, before the deposition of the first cladding layer, the raised structure may be formed from a uniform electro-optic layer. In some embodiments, the raised waveguide structure can be formed by obtaining an electro-optic layer having a thickness of, for example, 200 - 350 nm, masking an area on the electro-optic layer where the raised waveguide structure will be located, and etching the electro-optic layer on the SOI substrate using an anisotropic etching (e.g., RIE) process to thin the unmasked portion of the electro-optic layer to less than, for example, 150 nm. Subsequently, the first cladding layer is deposited on the raised waveguide structure and on the unthinned portion of the electro-optic layer.

[0078] Figure 12C shows the step of planarizing the first cladding layer (1210). For example, the upper surface of the first cladding layer shown in Figure 12A may not be sufficiently flat, and planarizing the first cladding layer can reduce the variation in the thickness of the first cladding layer.

[0079] FIG. 12D shows the step of adhering a planarized first cladding layer (1210) to a wafer (1212). In some embodiments, the upper surface of the first cladding layer may be adhered to the wafer. In some embodiments, the wafer (1212) may include an optical interposer or the wafer may be another type of circuit component of the device. Generally, the wafer may include any of various types of components that will be configured in proximity to the raised waveguide.

[0080] FIG. 12E shows the step of removing the substrate layer (1202) from what is now shown as the upper surface of the device. Removal of the substrate layer can expose the seed layer.

[0081] FIG. 12F shows the step of dividing the seed layer into a first electrode (1214) separated from a second electrode (1216) by etching the seed layer. By performing the step of etching the seed layer, a portion of the electro-optic layer can be exposed. Continuing with the above method, a second cladding layer (1218) can be deposited on the etched seed layer and on the exposed portion of the electro-optic layer.

[0082] FIG. 12G shows the step of etching the second cladding layer to expose a first portion of the first electrode, the step of etching the second cladding layer to expose a second portion of the second electrode, the step of depositing a first lead (1220) on the first electrode (1214) so as to pass through the exposed first portion, and the step of depositing a second lead (1222) on the second electrode (1216) so as to pass through the exposed second portion. The first and second leads may be composed of a conductive material such as a metal (e.g., copper, gold, etc.) or alternatively, these may be composed of a semiconductor. The final device may be structurally similar to, for example, the device shown in FIG. 2.

[0083] Figures 13A - E are schematic diagrams showing a manufacturing method for constructing an electro - optical device having a raised waveguide positioned on the opposite side of an electrode with a lead penetrating through a slab layer of a waveguide, according to some embodiments. Using the steps of the method shown in Figures 13A - E, a device similar to the device shown in Figure 3, for example, can be constructed.

[0084] Figure 13A shows a first plurality of steps for manufacturing a device, which include depositing a seed layer (1304) on a substrate layer (1302), depositing an electro - optical layer (1306) on the seed layer (1304), and depositing an electrode layer (1308) on the electro - optical layer (1306). These successive layers may be deposited epitaxially or they may be deposited using another technique. Alternatively, a finished wafer such as that shown in Figure 13A can be received from a manufacturer. Alternatively, a partially completed wafer including one or more of the seed layer (1304), substrate layer (1302), and / or electro - optical layer (1306) can be received and the remaining layers can be deposited to complete the wafer.

[0085] In some embodiments, the seed layer is composed of one of strontium titanate (STO), barium strontium titanate (BST), hafnium oxide, zirconium oxide, titanium oxide, graphene oxide, tantalum oxide, lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), strontium barium niobate (SBN), magnesium oxide (MgO), germanium, etc.

[0086] In some embodiments, the electro - optical layer is composed of one of barium titanate (BTO), barium strontium titanate (BST), lithium niobate, lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), aluminum oxide, aluminum nitrite, or strontium barium niobate (SBN).

[0087] FIG. 13B shows the step of etching the electrode layer (1308) to expose a portion of the electro-optic layer and splitting the electrode layer into a first electrode (1310) separated from the second electrode (1312). After the etching is performed, a first cladding layer (1314) is deposited over the exposed portion of the electro-optic layer and over the first and second electrodes.

[0088] FIG. 13C shows the step of planarizing the first cladding layer and the step of adhering the planarized first cladding layer (1314) to a wafer (1316). For example, by planarizing the first cladding layer, the thickness uniformity thereof can be improved and the adhesion to the wafer can be enhanced. The device may be inverted before adhering to the wafer so that the planarized first cladding layer becomes the bottom of the device for wafer adhesion. In some embodiments, the wafer (1316) may include an optical interposer or the wafer may be another type of circuit component of the device. Generally, the wafer may include any of various types of components that will be configured in proximity to the electrodes.

[0089] FIG. 13D shows the step of removing the substrate layer (1302) and the seed layer (1304), and the step of etching the electro-optic layer (1306) after the removal of the substrate layer and the seed layer to create a ridge waveguide (1318) having a first thickness (1326) disposed between a first slab layer (1320) and a second slab layer (1322) having a second thickness (1328) smaller than the first thickness (1326). In some embodiments, in order to further improve the electro-optic coefficient of the region near the ridge waveguide, not only the substrate layer (1302) and the seed layer (1304) are removed, but also a portion of the electro-optic layer 1306 is removed to remove any c-axis electro-optic material grown in the region near the seed layer (e.g., in the case of STO-based and BTO electro-optic layers). After the etching of the ridge waveguide, a second cladding layer (1324) may be deposited over the first and second slab layers and over the ridge waveguide structure.

[0090] FIG. 13E shows the steps of exposing a first portion of the first electrode by etching through the second cladding layer (1324) and the first slab layer, exposing a second portion of the second electrode by etching through the second cladding layer and the second slab layer, depositing a first lead (1330) on the first electrode (1310) so as to pass through the exposed first portion, and depositing a second lead (1332) on the second electrode (1312) so as to pass through the exposed second portion. The first and second leads may be composed of a conductive material such as metal, or alternatively, they may be composed of a semiconductor.

[0091] FIGS. 14A - E are schematic diagrams showing a manufacturing method for constructing an electro - optical device having a raised waveguide positioned on the same side as the electrodes according to some embodiments. Using the steps of the method shown in FIGS. 14A - E, a device similar to the device shown in FIG. 4, for example, can be constructed.

[0092] FIG. 14A shows a first plurality of steps for manufacturing a device, which include depositing a seed layer (1404) on a substrate layer (1402), depositing an electro - optical layer (1406) on the seed layer (1404), and depositing a first cladding layer (1408) on the electro - optical layer (1406). These successive layers may be deposited epitaxially, or they may be deposited using another technique. Alternatively, a finished wafer such as that shown in FIG. 14A can be received from a manufacturer. Alternatively, a partially completed wafer including one or more of the seed layer (1404), substrate layer (1402), electro - optical layer (1406), and / or first cladding layer (1408) can be received, and the remaining layers can be deposited to complete the wafer.

[0093] In some embodiments, the electro-optic layer is composed of one of barium titanate (BTO), barium strontium titanate (BST), lithium niobate, lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), aluminum oxide, aluminum nitrite, or strontium barium niobate (SBN).

[0094] FIG. 14B shows the steps of planarizing the first cladding layer (1408) to improve the thickness uniformity of the first cladding layer, and bonding the planarized first cladding layer (1408) to the wafer (1410). The device may be inverted before bonding to the wafer so that the planarized first cladding layer becomes the bottom of the device for bonding to the wafer. In some embodiments, the wafer (1410) may include an optical interposer or the wafer may be another type of circuit component of the device. Generally, the wafer may include any of various types of components that will be configured in proximity to the seed layer.

[0095] FIG. 14C shows the steps of removing the substrate layer (1402) and the seed layer (1404), and etching the electro-optic layer after removing the substrate layer and the seed layer to create a ridge waveguide (1412) having a first thickness (1418) disposed between a first slab layer (1414) and a second slab layer (1416), where the first and second slab layers have a second thickness (1420) smaller than the first thickness (1418). In some embodiments, in order to further improve the electro-optic coefficient of the region near the ridge waveguide, not only the substrate layer (1402) and the seed layer (1404) are removed, but also a portion of the electro-optic layer 1406 is removed to remove any c-axis electro-optic material grown in the region near the seed layer (for example, in the case of STO species and BTO electro-optic layers).

[0096] FIG. 14D shows the steps of depositing a first electrode (1422) and a second electrode (1424) on the left and right side surfaces of a raised waveguide structure (1412), respectively, and depositing a second cladding layer (1426) on the first and second electrodes and on the raised waveguide structure. In some embodiments, the first and second electrodes are composed of one of strontium titanate (STO), barium strontium titanate (BST), hafnium oxide, zirconium oxide, titanium oxide, graphene oxide, tantalum oxide, lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), or strontium barium niobate (SBN).

[0097] FIG. 14E shows the steps of exposing a first portion of the first electrode by etching through the second cladding layer, exposing a second portion of the second electrode by etching through the second cladding layer, depositing a first lead (1428) on the first electrode (1422) through the exposed first portion, and depositing a second lead (1430) on the second electrode (1424) through the exposed second portion. The first and second leads may be composed of a conductive material such as metal, or alternatively, they may be composed of a semiconductor.

[0098] FIGS. 15A - E show a method of fabricating a photonic device having a sandwich - type architecture according to some embodiments. Using the steps of the method shown in FIGS. 15A - E, a device similar to the device shown in FIG. 5, for example, can be constructed.

[0099] FIG. 15A shows a cross-sectional view of a first wafer (1500) including an electrode layer (1504) disposed on a first substrate layer (1506) and an electro-optic layer (1502) disposed on the electrode layer (1504). Alternatively, in some embodiments, the electro-optic layer (1502) is disposed on a seed layer (not shown). In some embodiments, the first wafer may be pre-fabricated by a wafer manufacturer and received for further fabrication steps as described in FIGS. 15C-E. Alternatively, the first wafer may be fabricated in-house. For example, the electrode layer and the electro-optic layer can be sequentially deposited on the first substrate using epitaxial deposition or various other deposition techniques described throughout this disclosure.

[0100] FIG. 15B shows a cross-sectional view of a second wafer (1501) including a second substrate layer (1512) deposited under a second cladding layer (1510) and a second strip waveguide structure (1508) deposited within and near the upper surface of the second cladding layer. In some embodiments, the second wafer (1501) may be pre-fabricated by a wafer manufacturer and received for further fabrication steps as described in FIGS. 15C-E. Alternatively, the second wafer may be fabricated in-house as needed.

[0101] In some embodiments, the first wafer (1500) is turned over, and the exposed surface of the electro-optic layer (1502) of the first wafer is adhered to the exposed surface of the second cladding layer (1510) of the second wafer. Thus, the first and second wafers are adhesively bonded together.

[0102] FIG. 15C shows, in some embodiments, a method of separating an electrode layer into a first electrode (1514) separated from a second electrode (1516) by removing a first cladding layer (1506) and etching the electrode layer after bonding a first wafer to a second wafer. In other embodiments, the electrode layer (1504) functions as a relatively thin seed layer and is ultimately removed. To further improve the electro-optic coefficient in the region near the surface of the seed layer, a portion of the electro-optic layer (1502) may be removed in addition to the substrate layer (1506) and the electrode / seed layer (1504). In these embodiments, after removal of such a seed layer, or after some partial removal step, a new electrode layer may be deposited and etched as described above.

[0103] FIG. 15D shows a method of depositing a first strip waveguide structure (1520) between a first electrode (1514) and a second electrode (1516). In some embodiments, a planarization step is performed following the deposition process to remove excess material from the region above the electrodes, for example by lithographic patterning or chemical mechanical polishing (CMP). In some embodiments, the materials used for the strip waveguide structure (1520) and / or (1508) are as described above with reference to FIG. 5 and may be, for example, silicon nitride. Subsequently, a first cladding layer (1518) is deposited over the first and second electrodes and over the first strip waveguide structure.

[0104] Finally, FIG. 15E shows a method of etching the first cladding layer (1518) to expose a portion of the first electrode (1514) and a portion of the second electrode (1516). Subsequently, a first lead (1522) is deposited on the exposed portion of the first electrode, and a second lead (1524) is deposited on the exposed portion of the second electrode. FIG. 15E shows an embodiment in which the leads are deposited on the upper surfaces of the first and second electrodes. However, in other embodiments, the exposed portions of the first and second electrodes themselves may be etched, thereby depositing the first and second leads within a certain distance within the cross-sections of the first and second electrodes or potentially on the upper surface of the electro-optic layer (1502).

[0105] FIG. 16 shows a cross-sectional view of a first wafer including a layer stack that can be accepted as part of the fabrication process of various devices described herein according to various embodiments. As shown, the first insulating substrate layer (1502) may optionally be disposed under a seed layer (1504), the seed layer (1504) is disposed under the electro-optic layer (1506), the electro-optic layer (1506) is optionally disposed under the electrode layer (1508), and the electrode layer (1508) is optionally disposed under the second insulating substrate layer (1510). Note that since the seed layer, the electrode layer, and the second substrate layer may optionally be present or absent as needed, the first wafer can be of various types depending on the particular fabrication method employed.

[0106] In some embodiments, subsequently, the seed layer (1504) may be etched to form a first electrode separated from the second electrode. Alternatively, in some embodiments, the seed layer simply serves to provide an interaction layer between the electro-optic layer and the first substrate layer, and the seed layer is ultimately removed during the fabrication process. In these embodiments, the electrode layer (1508) may be etched to form the first and second electrodes.

[0107] The terminology used in the description of the various embodiments described herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Also, as used herein, the term "and / or" refers to and is understood to cover any and all possible combinations of one or more of the associated listed items. Further, as used herein, the terms "include," "including," "comprise," and / or "comprising" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0108] As used herein, the term "if" is optionally construed to mean "when," or "upon," or "in response to determining," or "in response to detecting," or "in accordance with a determination that," as appropriate to the context.

[0109] The above description, for the purpose of illustration, has been presented with reference to specific embodiments. However, the above exemplary description is not intended to be exhaustive or to limit the claims to the precise forms disclosed herein. Many modifications and variations are possible in light of the above teachings. These embodiments were chosen in order to best explain the principles underlying the claims and their practical application, to thereby enable one of ordinary skill in the art to best utilize these embodiments with various modifications as are suited to the particular use contemplated.

[0110] It is also understood that the examples and embodiments described herein are for illustrative purposes only, and in light thereof, various modifications or variations will suggest themselves to those of ordinary skill in the art and these are intended to be within the spirit and scope of this application and the appended claims.

Claims

1. A method of constructing a device, the method comprising: Receiving a first wafer comprising a first layer stack, the first layer stack comprising: A substrate layer; A seed layer disposed on the substrate layer; and An electro-optical layer disposed on the seed layer Comprising the step; Etching the electro-optical layer to create a ridge waveguide structure having the first thickness disposed between a first slab layer and a second slab layer having a second thickness less than the first thickness; Receiving a second wafer; After the step of etching the electro-optical layer: Adhering the first layer stack to the second wafer; Removing the substrate layer; Etching the seed layer to form a first electrode separated from a second electrode and the second electrode within the seed layer; and Depositing a second cladding layer over the first electrode and the second electrode Including the method.

2. The first layer stack further comprises a first cladding layer disposed on the electro-optical layer, The step of adhering the first layer stack to the second wafer includes the step of adhering the surface of the first cladding layer to the second wafer, the method according to claim 1.

3. The method according to claim 2, further comprising the step of planarizing the first cladding layer before the step of adhering the surface of the first cladding layer to the second wafer Including.

4. The method further comprises: Etching the second cladding layer to expose a first portion of the first electrode; Etching the second cladding layer to expose a second portion of the second electrode; Depositing a first lead over the first electrode through the exposed first portion; and Depositing a second lead over the second electrode through the exposed second portion Including the method according to claim 1.

5. The method according to claim 1, wherein the first thickness is 200 nanometers (nm) or more and 350 nm or less, and the second thickness is 150 nm or less.

6. The substrate layer consists of a silicon-on-insulator (SOI) wafer, The silicon layer of the SOI wafer contacts the seed layer, the method according to claim 5.

7. The method according to claim 1, wherein the second wafer comprises an optical interposer.

8. The seed layer is: strontium titanate; barium strontium titanate; hafnium oxide; zirconium oxide; titanium oxide; graphene oxide; tantalum oxide; lead zirconate titanate; lead lanthanum zirconate titanate; magnesium oxide; germanium; or barium strontium niobate and is composed of one of them, The electro-optic layer is: barium titanate; barium strontium titanate; lithium niobate; lead zirconate titanate; lead lanthanum zirconate titanate; aluminum oxide; aluminum nitrite; or barium strontium niobate and is composed of one of them, the method according to claim 1.

9. A method of constructing a device, the method comprising: receiving a first wafer comprising a first layer stack, the first layer stack comprising: a seed layer disposed on a substrate layer; an electro-optic layer disposed on the seed layer; and an electrode layer disposed on the electro-optic layer comprising a step; etching the electrode layer to expose a portion of the electro-optic layer and splitting the electrode layer into a first electrode separated from a second electrode; depositing a first cladding layer on the exposed portion of the electro-optic layer and on the first and second electrodes; adhering the surface of the first cladding layer to a second wafer; removing the substrate layer and the seed layer; after removing the substrate layer and the seed layer, etching the electro-optic layer to create a raised waveguide having the first thickness disposed between a first slab layer and a second slab layer having a second thickness smaller than the first thickness; and depositing a second cladding layer on the first and second slab layers and on the raised waveguide structure comprising a method.

10. The method further comprises: flattening the first cladding layer prior to the step of adhering the first cladding layer to the second wafer comprising the method according to claim 9.

11. The method further comprises: etching through the second cladding layer and the first slab layer to expose a first portion of the first electrode; Etching through the second cladding layer and the second slab layer to expose a second portion of the second electrode; Depositing a first lead onto the first electrode through the exposed first portion; and Depositing a second lead onto the second electrode through the exposed second portion The method according to claim 9, comprising:

12. The substrate layer is composed of a silicon-on-insulator (SOI) wafer, The method according to claim 9, wherein the silicon layer of the SOI wafer contacts the seed layer.

13. The method according to claim 9, wherein the second wafer comprises an optical interposer.

14. The seed layer is: Strontium titanate; Barium strontium titanate; Hafnium oxide; Zirconium oxide; Titanium oxide; Graphene oxide; Tantalum oxide; Lead zirconate titanate; Lead lanthanum zirconate titanate; Magnesium oxide; Germanium; Or Barium strontium niobate Composed of one of them, The electro-optic layer is: Barium titanate; Barium strontium titanate; Lithium niobate; Lead zirconate titanate; Lead lanthanum zirconate titanate; Aluminum oxide; Aluminum nitrite; Or Barium strontium niobate The method according to claim 9, composed of one of them.

15. A method of constructing a device, the method comprising: Receiving a first wafer comprising a first layer stack, the first layer stack comprising: A seed layer disposed on a substrate layer; An electro-optic layer disposed on the seed layer; and A first cladding layer disposed on the electro-optic layer Comprising; Adhering the first cladding layer to a second wafer; Removing the substrate layer and the seed layer; After removing the substrate layer and the seed layer, etching the electro-optic layer to create a ridge waveguide having a first thickness disposed between a first slab layer and a second slab layer, the first and second slab layers having a second thickness smaller than the first thickness; Depositing first and second electrodes on the left and right sides of the ridge waveguide structure, respectively; and Depositing a second cladding layer on the first and second electrodes and on the ridge waveguide structure Comprising.

16. The method further comprises: prior to the step of adhering the first cladding layer to the second wafer, a step of planarizing the first cladding layer The method according to claim 15, comprising the above. **Claim 17** The method further comprises: etching through the second cladding layer to expose a first portion of the first electrode; etching through the second cladding layer to expose a second portion of the second electrode; depositing a first lead onto the first electrode through the exposed first portion; and depositing a second lead onto the second electrode through the exposed second portion The method according to claim 15, comprising the above. **Claim 18** The substrate layer consists of a silicon-on-insulator (SOI) wafer, and the method further comprises: a step of oxidizing the uppermost silicon layer of the SOI wafer in contact with the seed layer The method according to claim 15, comprising the above. **Claim 19** The method according to claim 15, wherein the second wafer comprises an optical interposer. **Claim 20** The seed layer is: strontium titanate; strontium barium titanate; hafnium oxide; zirconium oxide; titanium oxide; graphene oxide; tantalum oxide; lead zirconate titanate; lead lanthanum zirconate titanate; magnesium oxide; germanium; or strontium barium niobate and is composed of one of them, The electro-optic layer is: barium titanate; barium strontium titanate; lithium niobate; lead zirconate titanate; lead lanthanum zirconate titanate; aluminum oxide; aluminum nitrite; or strontium barium niobate The method according to claim 16, and is composed of one of them.

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