Hardware-Added Software Modem

Abstract

To improve the processing speed when implementing a modem in software, thereby improving the communication speed as a modem's performance.SOLUTION: Hardware of a software modem includes a processor 29, four macro processing circuits 21, 22, 23, and 24 each of which executes a part of the modem signal processing, and a memory 20 in which a program (modem software program) is stored that causes the processor 29 to execute at least the remaining modem signal processing excluding the processing executed by the four macro processing circuits 21, 22, 23, and 24. An encoding processing circuit 21 performs processing of an encoding portion and a decoding portion. In addition, a scrambling portion and a descrambling processing executed by a bit processing circuit 22 write horizontally and read vertically the data on the memory, such that the memory access is complicated and time-consuming when it is processed by the processor 29 as software, and therefore the vertical / horizontal conversion is implemented as hardware to reduce the time.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a hardware-aided software modem that realizes a modem used in a mobile phone or the like by software.

Background Art

[0002] Historically, modems have evolved from the initial 300 bps for data communication in the late 1960s to 4800 bps digital modems for facsimiles in the 1970s, and in the current era of mobile phones, they have been accelerated to several hundred Mbps. And in 5G communication, giga bps is aimed for further acceleration. As a technology for constructing a modem, since the digital modem era, there have been many methods of constructing with dedicated LSIs along with the acceleration, but there are also software modems constructed with software. Software modems are inferior in processing speed, that is, communication speed as modem performance, compared to dedicated LSIs, but have features such as low cost and the ability to install application software that further uses the modem on the modem software.

[0003] As described in Patent Document 1, some software modems devise software processing methods such as interrupt processing on the premise that they are composed of only a CPU and a memory as hardware. However, for acceleration, a CPU with a large number of CPU cores is used, or a special CPU with a structure that can use many cores such as a GPU (Graphics Processing Unit) for parallel processing is used.

[0004] On the other hand, regardless of modems, pipeline processing that can execute a plurality of instructions in parallel has been used for a long time to accelerate computer processing. In the present invention, pipeline processing can be made efficient.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] Even for a software modem, it enables speed increase and realizes a communication speed of several hundred Mbps comparable to 4G.

EFFECTS OF THE INVENTION

[0007] It can exhibit a communication speed comparable to 4G, can also simultaneously install application software using the modem, can be customized according to the uses of various customers, and in particular, a system suitable for the use of local 5G can be constructed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

MODE FOR CARRYING OUT THE INVENTION

[0009] Figure 1 briefly shows the general configuration of a software modem. It has a CPU and MEMORY like a personal computer, and along with the OS (Operating System) which is the basic software to run the personal computer, the modem software is installed in the MEMORY as the application software of the personal computer. The DAC / ADC shown in Figure 1 has the function of converting the digital data which is the result of personal computer processing into analog data for transmission, that is, generating it as the output signal of the modem, and conversely, converting the input signal of the modem received as analog data into digital data for processing by the personal computer, which is the function of analog-digital conversion.

[0010] Hello, the performance of the CPU has been improved by installing multiple cores such as six cores, but the performance of the modem and The communication speed is limited to the order of several Mbps, which is the performance of 3G mobile phones. On the other hand, as seen in recent 4G (LTE) communications, it has become an era where a communication speed of several hundred Mbps is required as the performance of the modem for video viewing.

[0011] Figure illustrates the flow of signal processing (modem signal processing) in the modem of a mobile phone. The left side is the transmission side and the right side is the reception side. On the transmission side, user data is segmented into frames of a predetermined length. For each frame, a redundant code called CRC for error detection is added in the CRC addition section 1 to detect errors caused by communication, and the format as a frame signal is arranged. In the encoding section 2, the FEC (Forward Error Correction) function for countermeasures against transmission errors is executed and encoded using LDPC (Low Density Parity Check) codes or turbo codes.

[0012] In the scrambling unit 3, data is randomized so that the wireless energy becomes uniform, and the coding efficiency by the LDPC code is improved (such as not creating a special pattern such as consecutive 0s). Then, in the modulation unit 4, a plurality of bits of the output of the scrambling unit are grouped together to form one symbol, and the coordinate points in the two-dimensional coordinates for QAM (Quadrature Amplitude Modulation) are determined for each symbol. In the present invention, there are 64 coordinate points, and one symbol is 64QAM composed of 6-bit data. In the precoding unit 5, for MIMO (Multiple Input and Multiple Output) control, a spatial channel is formed so as to be orthogonal to a plurality of antennas to be used, and weighting is performed to appropriately control the transmission power distributed to each channel.

[0013] The resource element mapping unit 6 multi-carrierizes and frequency-division multiplexes the output data of the precoding unit. In the IFFT (Inverse Fast Fourier Transform) unit 7, the data sequence is converted from the frequency domain to the time domain, and in the DAC unit 8, the digital data is converted into analog and transmitted as a radio wave.

[0014] On the receiving side, first, the analog radio wave is converted into digital by the ADC unit 17, the data sequence is converted from the time domain to the frequency domain by the FFT (Fast Fourier Transform) unit 16, and the resource element demapping unit 15 extracts the data of the frequency component at a predetermined position from the frequency-division multiplexed signal.

[0015] In the equivalent processing unit 14, the time difference when the radio wave arrives (the time difference between the radio wave directly received between antennas and the radio wave received after being reflected by an obstacle such as a mountain, multipath fading) is corrected, and FFT processing and IFFT processing are also used here. Then, in the demodulation unit 13, the descrambling unit 12, the decoding unit 11, and the CRC check unit 10, signal processing opposite to that on the transmission side is performed.

[0016] Table 1 estimates the amount of computation for processing elements as software. To improve the speed (communication speed) as a software modem, it is important to circuitize (LSI-ize) elements with a large amount of computation. Therefore, it is effective to group such computations, that is, arithmetic operations such as addition, multiplication, and division, logical operations such as AND and OR, shift operations, bit operations, etc., and form a macro processing circuit together with a basic circuit and a sequence circuit that realizes a specific algorithm, and then LSI-ize it. The basic circuits described above include, in addition to logical operations such as AND and OR, shift operations, bit operations, etc., a temporary register for temporarily storing data during computation. The sequence circuit is a sequencer that executes an algorithm for efficiently performing computations and has an instruction function (computation program) for computations.

[0017] [Table 1]

[0018] From Table 1, as candidates for macro processing circuitization (LSI-ization), it is preferable to select at least one of the encoding process and the FFT / IFFT process, which have a relatively large amount of computation. Processes with a medium amount of computation, such as bit processing, scrambling processing, and modulation / demodulation processing, may be grouped together with processes with a small amount of computation for LSI-ization (for example, grouping bit processing and CRC processing, etc.). Processes with a small amount of computation may be processed by software without LSI-ization.

[0019] Figure 3 shows a configuration example of hardware (e.g., a hardware - added software modem (described later) or a system - on - chip) in the present invention. In the configuration of this figure, there are a processor 29, four macro - processing circuits 21, 22, 23, 24 each of which executes part of the modem signal processing, and a memory 20 in which a program (modem software program) is stored to cause the processor 29 to execute at least the remaining processing of the modem signal processing excluding the processing executed by the four macro - processing circuits 21, 22, 23, 24. The encoding processing circuit 21 performs the processing of the encoding unit 2 and the decoding unit 11 in FIG. 2. Also, the processing of the scrambling unit 3 and the descrambling unit 12 in FIG. 2 performed by the bit - processing circuit 22 is a software process by the processor 29 for data on the memory, which is written horizontally and read vertically, so the memory access is complicated and time - consuming. Therefore, the vertical - horizontal conversion is made hardware - based to shorten the time.

[0020] Also, the addition and check processing of the CRC in FIG. 2 are also performed by this bit - processing circuit. The modulation / demodulation processing circuit 23 performs the processing of the modulation unit and the demodulation unit in FIG. 2. The FFT / IFFT processing circuit (in the present invention, the term "fast Fourier transform" is used as a word combining FFT and IFFT) 24 performs fast Fourier transform processing that requires high computing power. Control arithmetic cores 25, 26, 27, 28 corresponding to each of the above - described four macro - processing circuits are built into the processor 29. The processor 29 is equivalent to the CPU in FIG. 1 and is what those skilled in the art commonly call a microprocessor or a CPU as a common noun.

[0021] Furthermore, the analog front - end 30 executes the functions of the DAC unit 8 and the ADC unit 17 in FIG. 2 and performs radio wave transmission (such as modulation) and reception (such as demodulation). This analog front end 30 corresponds to the DAC / ADC in FIG. 1. The processor 29, the memory 20, and the four macro - processing circuits 21, 22, 23, 24 shown in FIG. 3 are implemented on one chip as an LSI. The analog front - end 30 can also be housed on one chip.

[0022] The above four macro processing circuits 25, 26, 27, and 28 may perform pipeline processing as software in cooperation with the control arithmetic cores 25, 26, 27, and 28. For example, if a part of the operations performed by each macro processing circuit is performed by the corresponding control arithmetic core, the operation time can be shortened compared to when the macro processing circuit performs operations alone, and the pipeline processing time can be made uniform. Since the pipeline processing shown in FIG. 4 is uniform and there is no idle time (or waiting time), the processing is executed efficiently.

[0023] In addition, data accumulation and transfer can be performed for each processing unit in each macro processing circuit. Since the basic circuit of the macro processing circuit has a temporary register, it is not necessary to perform data accumulation and transfer for each operation, and the memory capacity for accumulating and transferring intermediate data can be reduced.

[0024] Note that FIG. 5 shows an example in which the times of each of the processes A, B, C, and D performing pipeline processing are not equal and uneven, and it is difficult to exhibit the characteristics of pipeline processing that can process a plurality of instructions in parallel, resulting in a decrease in processing efficiency. In the memory 20 of FIG. 3, in addition to the above three software programs, although not shown, in addition to the program memory including an operating system as basic software, a working memory for temporarily storing operation data, and a flash memory for storing data that needs to be permanently stored are included.

[0025] In addition to the above three software programs, the memory 20 includes, although not shown, a program memory including an operating system as basic software, a working memory for temporarily storing operation data, and a flash memory for storing data that needs to be permanently stored.

[0026] Speaking of the software implemented above, quoting the 7-layer protocol of OSI defined by ISO (International Organization for Standardization), there is modem software as Layer 1 (Physical Layer), MAC (Medium Access Control), RLC (Radio Link Control), PDCP (Packet Data Convergence Protocol) of Layer 2, and protocol software including Layer 4 that executes RPC (Radio Resource Control) of Layer 3 and Internet protocol. Furthermore, the customization software performs transmission of image data, sensor data, etc. at Layers 6 and 7 and executes various functions required by the customer system.

[0027] In an in-house wireless network system such as local 5G, it is common that a large number of sensor terminals, surveillance cameras, etc. are connected to the network, and a management center that executes analysis and management of data requested by the customer while accumulating the data received from the terminals is connected. The customization software executes the data transfer function and the analysis and management function for this purpose.

[0028] The analysis and management function includes, in addition to the analysis and management function that centrally manages all sensor terminal information managed by the management sensor, in each sensor terminal, functions such as determination of the normality and abnormality of sensor information, and inquiry about the sensor sensitivity setting to other sensor terminals while managing the sensor information in time series. This customization software enables flexible response to the customer system.

[0029] A major feature of 5G mobile phones is that they can transmit ultra-high-definition videos in a short time at a communication speed of several gigabits per second. However, in local 5G, as a customer requirement, a communication speed of several hundred megabits per second is considered sufficient, and many customers value customization functions more than speed. The present invention is highly practical.

[0030] Although many functions of the modem of the present invention are realized by software processing, since some functions are realized by a macro processing circuit, that is, hardware, it can be called a Hardware Aided Software Modem.

[0031] In the example of FIG. 3, four macro processing circuits (for example, LSIs) that execute some of the processing of the modem signal processing shown in FIG. 2 are provided. However, the number of macro processing circuits may be one or more. Also in FIG. 3, in order to equalize the processing time of the pipeline processing, a configuration is adopted in which the control arithmetic core corresponding to each macro processing circuit assists the processing executed by the macro processing circuit. However, each macro processing circuit may perform processing independently without assistance by the control arithmetic core. Further, in the memory 20 of FIG. 3, in addition to the modem software, protocol software and customization software are installed. However, software other than the protocol software and the customization software may be installed, and the installation of the protocol software and the customization software may be omitted.

Industrial Applicability

[0032] Since it can execute a modem function that can achieve a communication speed of several hundred Mbps by software, it can be used not only as a modem for 4G mobile phones but also in 5G mobile phone systems (especially local 5G), and its industrial applicability is extremely large.

Explanation of Signs

[0033] 1. CRC addition unit 2. Encoding unit 3. Scrambling unit 4. Modulation unit 5. Precoding unit 6. Resource element mapping unit 7. IFFT unit 8. DAC unit 10. CRC check unit 11. Decoding unit 12. Descrambling unit 13. Demodulation Unit 14. Equivalent Processing Unit 15. Resource Element Demapping Unit 16. FFT Unit 17. ADC Unit 20. Memory 21. Encoding Processing Circuit 22. Bit Processing Circuit 23. Modulation / Demodulation Processing Circuit 24. FFT / IFFT Processing Circuit 25. Control Arithmetic Core 1 26. Control Arithmetic Core 2 27. Control Arithmetic Core 3 28. Control Arithmetic Core 4 29. Processor 30. Analog Front End

Claims

1. A hardware-aided software modem, comprising a processor, a macro processing circuit that executes part of the modem signal processing, and a memory storing a modem software program that causes the processor to execute at least the remaining processing excluding the part of the processing from the modem signal processing, wherein a control arithmetic core corresponding to the macro processing circuit is provided inside the processor.

2. The hardware-aided software modem according to claim 1, wherein a customized software for managing sensor data is implemented in the memory as a program to be executed by the processor.

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