Transmitting device, communication system, and information transmitting method

Abstract

[Problem] To make it possible to reduce power consumption during the transmission of information. [Solution] This transmission device sends information generated by an information source and divided into blocks to a transmission path in frame units that contain a plurality of the blocks. The transmission device comprises a transmission unit which, if the amount of the information to be transmitted is less than the transmission capacity of the transmission path, either stops sending information to the information path, or sends toggle data which has information with a longer transition period than that of the information outside of the aforementioned one block in the aforementioned frame to the information path in one block among the plurality of blocks.

Description

Technical Field

[0001] The present disclosure relates to a transmission device, a communication system, and an information transmission method.

Background Art

[0002] In recent years, in the automotive field, various sensors are used for recognizing the external environment for driving assistance systems and autonomous driving technologies. As one of these sensors, it is common to use a camera incorporating an image sensor. The signal captured by the camera is transmitted to an ECU that performs recognition processing via the transmission path of a high-speed serial interface system. In the transmission path, information from various sensors other than the camera is also transmitted, but since the amount of information of the imaging signal from the camera is generally overwhelmingly larger than that of other sensors, most of the information transmitted via the transmission path is often the imaging signal from the camera.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] The transmission path has a determined transmission capacity for the information that can be transmitted, and it is not possible to transmit information exceeding the transmission capacity. When transmitting information with an amount less than the transmission capacity through the transmission path, the transmission capacity of the transmission path cannot be effectively utilized. Therefore, it is desirable to match the amount of information of the information source to be transmitted through the transmission path with the transmission capacity of the transmission path. However, in practice, it is difficult to achieve the match. Usually, the transmission capacity of the transmission path is made larger than the amount of information of the information source, and for the surplus in the transmission capacity, invalid data (also called null data) is sent to the transmission path. Although the invalid data is data that the receiving device does not originally need, it consumes transmission energy. Therefore, it is desirable to send as little invalid data to the transmission path as possible. In particular, a transmission device that transmits the imaging signal of an in-vehicle camera is often arranged on the vehicle body surface away from the power source, so it is difficult to supply power with a margin, and at the same time, the temperature conditions of the operating environment are also severe. For this reason, it is required to minimize the power consumption of the in-vehicle camera.

[0005] Therefore, the present disclosure provides a transmission device, a communication system, and an information transmission method capable of reducing the power consumption during information transmission.

Means for Solving the Problem

[0006] In order to solve the above problems, according to the present disclosure, there is provided a transmission device that sends information generated at an information source and divided into blocks to a transmission path in units of frames including a plurality of the blocks. When the amount of information to be transmitted is less than the transmission capacity of the transmission path, in one of several blocks in the frame, the transmission unit is provided that stops sending information to the transmission path or sends toggle data with a longer information transition period than the information other than the one block in the frame to the transmission path.

[0007] During the period when the transmission unit stops sending information to the transmission path, it may send data of a specific signal logic to the transmission path or set the transmission path to high impedance.

[0008] The transmitting unit may set a destination address of the one block for which transmission of information to the transmission path is to be stopped to an address different from an address of a receiving device that receives information via the transmission path.

[0009] The transmitting unit may include a scrambler that generates scrambled data by scrambling the information generated by the information source, regardless of whether or not the transmission of information to the transmission path is stopped.

[0010] the transmitting unit transmits a predetermined resynchronization pattern to the transmission path after a period during which transmission of information to the transmission path is stopped has elapsed and before transmission of information to the transmission path is resumed; The resynchronization pattern may be used by a receiving device to perform a synchronous reproduction process of information received via the transmission path.

[0011] The transmitting unit may have a selector that selects either the scrambled data or a predetermined resynchronization pattern used by the receiving device to perform synchronous reproduction processing of information received via the transmission path and sends it to the transmission path.

[0012] The transmission unit may include a scheduler that controls selection by the selector based on a control signal transmitted by the receiving device via the transmission path.

[0013] the transmitting unit has a scrambler that generates scrambled data by scrambling the information generated by the information source, The scrambler a shift register having a plurality of registers for sequentially shifting serial data corresponding to the information generated by the information source; a logic operation unit that generates the scrambled data by performing a predetermined logic operation on the data shifted by the shift register and the serial data input to the shift register, The transmitting unit may transition information to be sent to the transmission path in one block out of several blocks in the frame at a period corresponding to the number of stages of the plurality of registers in the shift register.

[0014] The transmitting unit may send information to the transmission path in which, in one of the blocks in the frame, a number of consecutive 1s equal to the number of the registers in the shift register and a number of consecutive 0s equal to the number of the registers in the shift register minus 1.

[0015] The transmitting unit may transmit to the transmission path information in which, in one block out of several blocks in the frame, a number of consecutive 1s equal to the number of bits selected by a predetermined method for either the number of the plurality of registers in the shift register or the number of the plurality of registers minus 1, and a number of consecutive 0s equal to the number of bits selected by a predetermined method for either the number of the plurality of registers in the shift register minus 1 or the number of the plurality of registers minus 2.

[0016] The transmitting unit may send header information to the transmission path, in one of the blocks in the frame, with the header information having a destination address that is different from the address of a receiving device connected to the transmission path, before sending information to the transmission path.

[0017] The header information may include identification information of the toggle data.

[0018] The transmission unit a pseudorandom number generator for generating a pseudorandom number signal; The frame may include a scrambler that generates the toggle data based on the pseudorandom signal in one of several blocks in the frame.

[0019] a permutation unit that selects information generated by the information source in blocks other than the one block in the frame, and selects the pseudorandom number signal in the one block; An error correction processing unit that adds an error correction code to the information selected by the replacement unit A delay unit that delays the pseudo-random number signal for a predetermined period, and For one block out of several blocks in the frame, the scrambler may generate the toggle data based on the output signal of the error correction processing unit and the output signal of the delay unit.

[0020] The predetermined period is the period from when the pseudo-random number generator generates the pseudo-random number signal until the output signal of the error correction processing unit is input to the scrambler. For one block out of several blocks in the frame, the scrambler may generate the toggle data by an exclusive logical sum of the output signal of the error correction processing unit and the output signal of the delay unit, or by an exclusive logical sum of the output signal of the error correction processing unit and the inverted signal of the output signal of the delay unit.

[0021] The pseudo-random number generator has a shift register having a plurality of registers. For one block out of several blocks in the frame, the scrambler may generate the toggle data in which the first signal logic continues continuously for the number of bits corresponding to the number of the plurality of registers in the shift register, and the second signal logic continues continuously for the number of bits corresponding to the number of the plurality of registers - 1 in the shift register.

[0022] The pseudo-random number generator has a shift register having a plurality of registers. For one block out of several blocks in the frame, the scrambler may generate the toggle data in which the first signal logic continues continuously for the number of bits corresponding to either one of the number of the plurality of registers in the shift register and the number of the plurality of registers - 1 selected by a predetermined method, and the second signal logic continues continuously for the number of bits corresponding to either one of the number of the plurality of registers - 1 and the number of the plurality of registers - 2 in the shift register selected by a predetermined method.

[0023] The scrambler may generate the toggle data with a period that is maximized or that can be arbitrarily selected for one block out of several blocks in the frame.

[0024] The transmitting unit may transmit information to the transmission path within a period allocated by TDD (Time Division Duplex).

[0025] According to another aspect of the present disclosure, a master device and a slave device that transmits information generated by an information source and divided into blocks to the master device via a transmission path in frame units each including a plurality of the blocks in accordance with an instruction from the master device, The slave device has a transmitting unit that, when the amount of information generated by the information source is less than the transmission capacity of the transmission path, stops sending information to the transmission path in one of several blocks in the frame, or sends toggle data to the transmission path, the cycle of which is longer than the information in the other blocks in the frame.

[0026] According to another aspect of the present disclosure, there is provided an information transmission method for transmitting information generated by an information source and divided into blocks to a transmission path in frame units each including a plurality of the blocks, the method comprising: When the amount of information generated by the information source is less than the transmission capacity of the transmission path, the information transmission to the transmission path is stopped in one of several blocks in the frame, or toggle data having a longer information transition period than the information in the blocks other than the one block is transmitted to the transmission path. [Brief explanation of the drawings]

[0027]

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Embodiments for Carrying Out the Invention

[0028] Hereinafter, embodiments of a transmission device, a communication system, and an information transmission method will be described with reference to the drawings. Hereinafter, the description will focus on the main components of the transmission device, the communication system, and the information transmission method, but there may be components and functions not shown or described in the transmission device, the communication system, and the information transmission method. The following description does not exclude components and functions not shown or described.

[0029] (Schematic Configuration of Communication System) FIG. 1 is a block diagram showing a schematic configuration of a communication system 1 according to the present disclosure. The communication system 1 in FIG. 1 includes a first information source (Source #1) 2, a first sink device (Sink #2) 3, a first SerDes unit (SerDes1) 4, a transmission path (cable) 5, a second SerDes unit (SerDes2) 6, a second sink device (Sink #3) 7, and a second information source (Source #4) 8. Each of the first SerDes unit 4 and the second SerDes unit 6 functions as a transmission device and a reception device. More specifically, when the first SerDes unit 4 functions as a transmission device, the second SerDes unit 6 functions as a reception device. Also, when the second SerDes unit 6 functions as a transmission device, the first SerDes unit 4 functions as a reception device. Hereinafter, the configuration and operation when the first SerDes unit 4 functions as a transmission device and the second SerDes unit 6 functions as a reception device will be mainly described. The second sink device 7 and the second information source 8 may be built in a host device, for example.

[0030] The first SerDes unit 4 and the second SerDes unit 6 are connected by a single cable (transmission path) 5, and signals are transmitted bidirectionally via this cable 5. More specifically, the first SerDes unit 4 and the second SerDes unit 6 transmit signals bidirectionally by, for example, a TDD (Time Division Duplexing) method. In FIG. 1, the signal path on the transmission path 5 for serially transmitting information from the first SerDes unit 4 to the second SerDes unit 6 is called a downlink or a forward channel, and the signal path on the transmission path 5 for serially transmitting information from the second SerDes unit 6 to the first SerDes unit 4 is called an uplink or a reverse channel. Also, in the present embodiment, it is assumed that the amount of information in the downlink is larger than that in the uplink.

[0031] The first SerDes unit 4 includes a downlink transmission unit (Dn Tx) 11 and an uplink reception unit (Up Rx) 12. The second SerDes unit 6 includes a downlink reception unit (Dn Rx) 13 and an uplink transmission unit (Up Tx) 14.

[0032] The first information source 2 has, for example, one or more sensors. Each sensor outputs sensing information. The sensors may include an image sensor. The image sensor outputs a captured imaging signal. The imaging signal may be a moving image signal or a still image signal. Hereinafter, various sensing information output from the first information source 2 is collectively referred to as "information".

[0033] The information output from the first information source 2 is input to the downlink transmission unit 11 in the first SerDes unit 4. The downlink transmission unit 11 performs packet processing on the information from the first information source 2, converts it into serial data, and sends it out to the transmission path 5. There may be another information source other than the first information source 2. The information output from each information source is transmitted to the downlink transmission unit 11 in the first SerDes unit 4.

[0034] The uplink reception unit 12 in the first SerDes unit 4 receives the serial data transmitted on the uplink on the transmission path 5 and converts it into parallel data. This parallel data is received by the first sink device 3. Among the parallel data received by the first sink device 3, a control signal from the second information source 8 is included. The control signal may include information for controlling the operating conditions and operating modes of various sensors such as an image sensor. The transmission and reception of the control signal between the first sink device 3 and the uplink reception unit 12 are performed, for example, by I2C (Inter-Integrated Circuit) communication or GPIO (General Purpose Input / Output).

[0035] The second information source 8 transmits the information to be transmitted to the first sink device 3 to the uplink transmission unit 14 in the second SerDes unit 6. Also, the downlink reception unit 13 in the second SerDes unit 6 converts the received serial data into parallel data and transmits it to the second sink device 7.

[0036] As described above, the first SerDes unit 4 and the second SerDes unit 6 can transmit and receive serial data, for example, in a TDD mode. FIG. 2 is a diagram for explaining the TDD mode. In the present embodiment, it is assumed that sensing data of various sensors including, for example, an image sensor is transmitted from the first information source 2 to the second sink device 7 via the transmission path 5. The sensing data such as an imaging signal is transmitted in the downlink. Further, the control signal transmitted from the second information source 8 to the first sink device 3 is transmitted in the uplink. In the communication system 1 according to the present disclosure, the amount of information in the downlink on the transmission path 5 is much larger than the amount of information in the uplink. Therefore, as shown in FIG. 2, the period for transmitting and receiving the downlink information is made longer than the period for transmitting and receiving the uplink information, so that the amount of information transmitted and received in the downlink and the uplink is made different. In the example of FIG. 2, the uplink information (such as a control signal from the second information source 8) is transmitted and received at times t1 to t2, and then the downlink information (such as sensing data from the first information source 2) is transmitted and received at times t3 to t4. Since the period from time t3 to t4 is longer than the period from time t1 to t2, the amount of downlink information can be increased compared to the amount of uplink information. The period from time t0 to t4 is one TDD cycle, and a plurality of TDD cycles are repeated.

[0037] FIG. 3 is a block diagram showing an example of the internal configuration of the downlink transmission unit 11 in FIG. 1. The downlink transmission unit 11 in FIG. 3 includes a buffer 21, a framer 22, a scheduler 23, a parallel-serial converter (P / S) 24, a scrambler 25, a mapper 26, and an output amplifier 27.

[0038] The buffer 21 temporarily holds the information output from the first information source 2. The buffer 21 is provided to adjust the transmission speed. Generally, the data rate of the sensing data output from the various sensors included in the first information source 2 differs from the transmission rate of the transmission path 5, so the buffer 21 adjusts the speed and transmits the information from the first information source 2 to the framer 22 at an appropriate timing. Note that the transmission rate of the transmission path 5 is usually set faster than the data rate of the first information source 2.

[0039] The framer 22 generates packet data in frame units based on information transmitted in block units from the first information source 2. The data structure of the packet data that constitutes a frame will be described later. The P / S 24 converts the packet data generated by the framer 22 into serial data.

[0040] The scrambler 25 generates scrambled data by performing a predetermined scrambling process on the serial data output from the P / S 24. For example, the scrambler 25 performs a process to randomize the timing at which the signal logic of the serial data changes. The scrambler 25 may generate scrambled data by scrambling the information generated by the first information source 2, regardless of whether or not the transmission of information to the transmission path 5 is stopped.

[0041] The mapper 26 converts the signal level according to the modulation method (NRZ, PAM4, etc.). The output signal of the mapper 26 is input to the output amplifier 27. The output amplifier 27 adjusts the gain of the output signal of the mapper 26 and sends it to the transmission path 5.

[0042] 4 is a diagram showing an example of the data structure of a frame. As shown in the figure, a frame has multiple containers. Each container is generated for each block in the frame. Each container has a header, a payload, and parity.

[0043] The header includes address information indicating the destination of the payload. The payload is the main body part of the data included in the transmitted and received signal. In addition to the video signal, the payload includes OAM (Operations, Administration, Maintenance) for controlling the first SerDes unit 4 and the second SerDes unit 6. Parity is a bit or bit sequence for error detection or error correction processing of the payload. The header has data identification information, a destination address, and other information. The data identification information is information for specifying the type of data in the payload. The destination address is the address of the receiving device that receives the frame.

[0044] FIG. 5 is a diagram showing the data configuration of the frame output from the framer 22. FIG. 5 shows an example in which there is another information source (hereinafter referred to as the nth information source 2a (Source #n)) in addition to the first information source 2 in the communication system 1. FIG. 5 shows an example in which the data rate ratio of the first information source 2, the nth information source 2a, and the first SerDes unit 4 is 3:1:4.

[0045] As shown in FIG. 5, based on the control from the scheduler 23, the framer 22 reads out the information output from the first information source 2 and the nth information source 2a and temporarily held in the buffer 21 in accordance with the timing of the payload in the container. First, the framer 22 stores the information from the first information source 2 in the payloads of the containers (Container #1 to #3), and adds data identification information (for example, a video signal), a destination address (here, the address of the second sink device 7 (Sink #3)), and parity to the header to complete the container. The framer 22 sequentially generates three containers (Container #1 to #3) based on the information output from the first information source 2.

[0046] Next, the frame 22 stores the information from the n-th information source 2a in the payload of the container (Container #4), and adds data identification information (e.g., audio signal), destination address (the second sink device 7 (Sink #3)), and parity to the header to complete the container. The frame 22 generates and outputs one container (Container #4) based on the information output from the n-th information source 2a.

[0047] After that, the frame 22 repeats the process of sequentially generating three containers (Container #1 to #3) based on the information from the first information source 2 and one container (Container #4) based on the information from the n-th information source 2a. Thereby, a frame including a plurality of containers is generated. The frame 22 outputs the generated containers in order.

[0048] P / S24 converts the containers sequentially output from the frame 22 into serial data. This serial data is input to the scrambler 25 in bit units.

[0049] FIG. 6 is a block diagram showing an example of the internal configuration of the scrambler 25. As shown in FIG. 6, the scrambler 25 includes a shift register 31 in which L (L is an integer of 2 or more) registers 30 are connected in series, a first XOR calculator 32, and a second XOR calculator 33.

[0050] The first XOR calculator 32 outputs the exclusive OR operation result of the output data of the register at the last stage of the shift register 31 and the output data of some registers other than the last stage. The output data of the first XOR calculator 32 is input to the register at the first stage and the second XOR calculator 33. By feeding back the output data of the first XOR calculator 32 to the input side of the register at the first stage of the shift register 31, the shift register 31 can randomly generate serial data of 1 to 2 L L -1 excluding zero. In this way, pseudo-random numbers can be generated by the shift register 31 and the first XOR calculator 32.

[0051] The second XOR operator 33 outputs the result of exclusive ORing the serial data output from the P / S 24 and the output data of the first XOR operator 32. Since the output data of the first XOR operator 32 is a pseudo-random number, the output data of the second XOR operator 33 is also pseudo-random number serial data. The scrambler 25 outputs the output data of the second XOR operator 33 as scrambled data.

[0052] If the information output from the first information source 2 is a video signal, it may become serial data in which bits of the same signal logic (0 or 1) continue for a long period of time. When such serial data is received by the downlink receiver (Dn Rx) 13, there is a risk that the received data may not be synchronously reproduced correctly because there is no change point in the signal logic. Therefore, the scrambler 25 intentionally generates pseudo-random numbers in the serial data based on the information from the first information source 2, thereby forcibly causing a change in the signal logic. This allows the receiving side to properly synchronously reproduce the received data.

[0053] The scrambled data generated by the scrambler 25 is input to the mapper 26. The mapper 26 adjusts the output level of the scrambled data depending on the modulation method. FIG. 7A shows an example of the output level when the modulation method is NRZ (non-return-to-zero), and FIG. 7B shows an example of the output level when the modulation method is PAM4 (4 Pulse Amplitude Modulation). In the case of NRZ, as shown in FIG. 7A, if the scrambled data is 1, the output level is set to a predetermined voltage level A, and if it is 0, the output level is set to 0. In the case of PAM4, as shown in FIG. 7B, if two consecutive bits of the scrambled data are (1,0), the output level is set to a predetermined voltage level B; if it is (1,1), the output level is set to 2 / 3 of B; if it is (0,1), the output level is set to 1 / 3 of B; and if it is (0,0), the output level is set to 0. The serial data whose output level has been adjusted by the mapper 26 is sent to the transmission path 5 via the output amplifier 27.

[0054] In FIG. 5 described above, an example is shown in which the transmission path 5 has a transmission capacity for sequentially transmitting four containers, which are three containers from the first information source 2 and one container from the n-th information source 2a. For example, when the n-th information source 2a does not output information, although the transmission path 5 has a transmission capacity for four containers, the framer 22 generates only three containers, resulting in poor transmission efficiency.

[0055] FIG. 8 is a diagram showing the data configuration of the frame output from the framer 22 when the n-th information source 2a does not output information. The buffer 21 outputs null data, which is invalid data, at the time when the n-th information source 2a should output information. For this reason, the payload of the container (Container #4) includes null data, and the data identification information in the header becomes null.

[0056] By providing a container including null data, it is possible to transmit an amount of information corresponding to the transmission capacity of the transmission path 5. However, the container including null data is meaningless information and only wastes power consumption. Therefore, it is desirable to partially change the internal configuration of the downlink transmitter 11 in FIG. 3 so that power consumption is not wasted when the amount of information to be transmitted is less than the transmission capacity of the transmission path 5. Hereinafter, the first improvement example to the third improvement example in which the internal configuration of the downlink transmitter 11 in FIG. 3 is changed will be described in order.

[0057] (First improvement example of the downlink transmitter 11) FIG. 9 is a block diagram of the first improvement example of the downlink transmitter 11 in FIG. 3. The downlink transmitter 11 in FIG. 9 has a resync pattern adder 28 in addition to the configuration in FIG. 3. When the amount of information of the information to be transmitted is less than the transmission capacity of the transmission path 5, the resync pattern adder 28 stops the transmission of information to the transmission path 5 for one block out of several blocks in the frame.

[0058] The resynchronization pattern adder 28 processes the scrambled data output from the scrambler 25 and transmits the processed serial data to the mapper 26. The resynchronization pattern adder 28 determines the timing to stop the transmission of information to the transmission path 5 based on the control from the scheduler 23.

[0059] FIG. 10 is a block diagram showing an example of the internal configuration of the resynchronization pattern adder 28. The resynchronization pattern adder 28 includes a resynchronization pattern generator 34 and a selector 35. The resynchronization pattern generator 34 generates a resynchronization pattern after stopping the transmission of information to the transmission path 5 and before resuming the transmission of information to the transmission path 5. The resynchronization pattern is received by a receiving device (downlink receiving unit (Dn Rx) 13) that receives information and is used to perform synchronous reproduction processing of the information.

[0060] The selector 35 selects either the scrambled data output from the scrambler 25 or the resynchronization pattern generated by the resynchronization pattern generator 34 based on the timing control by the scheduler 23. The data selected by the selector 35 is transmitted to the mapper 26.

[0061] In explaining the processing operation of the downlink transmission unit 11 in FIG. 9, the ratio of the transmission rate per unit time between the first information source 2 and the transmission device is set to 3:4. Therefore, by stopping the transmission of one container out of four containers, the transmission rate of the first information source 2 and the transmission rate of the transmission device can be made substantially the same.

[0062] 11A, 11B, 11C, and 11D are timing diagrams of the components in the downlink transmitter 11 according to the first improved example. As shown in FIG. 11A, information from the first information source 2 temporarily stored in the buffer 21 is sequentially input to the framer 22, and the input information is stored in the payload of the container. Furthermore, data identification information, a destination address, and parity are input to the header of the container. After information for three consecutive containers (Containers #1 to #3) is input from the buffer 21, invalid data is next stored in the payload of the container (Container #4), null is input as the data identification information in the header, and an invalid address (Address #X) that does not exist in the communication system 1 is input as the destination address. Because this container transmits null data to the invalid address, error correction processing is stopped in order to minimize power consumption. Therefore, parity is unnecessary and is left blank.

[0063] By setting the destination address of the container (Container #4) to an invalid address, the receiving side can ignore this container and omit the receiving process.

[0064] In the example of FIG. 11A, one container out of four consecutive containers is set to invalid data, but the ratio of containers to be set to invalid data depends on the relationship between the amount of information in the first information source 2 and the transmission capacity of the transmission path 5, and depending on this relationship, the ratio may be different from that shown in FIG. 11A. Which containers correspond to which information, among the information temporarily stored in the buffer 21, are set to null data is controlled by a timing control signal from the scheduler 23. The scheduler 23 can also generate a timing control signal based on setting information from the second information source 8.

[0065] The framer 22 sequentially outputs the individual containers that make up the frame. The P / S 24 sequentially converts the containers output from the framer 22 into serial data. The scrambler 25 scrambles the serial data to generate scrambled data. As shown in FIG. 11B, scrambled data is generated for each container output from the framer 22. For one of the four containers, the scrambler 25 generates scrambled data corresponding to null data.

[0066] 11C, the resynchronization pattern adder 28 removes the scrambled data corresponding to the null data based on the timing control signal from the scheduler 23. This stops the transmission of information from the first SerDes unit 4 to the second SerDes unit 6. While the transmission of information is stopped, the downlink signal logic on the transmission path 5 is fixed to 0 or 1, or is set to high impedance. This makes it possible to minimize energy consumption on the transmission path 5.

[0067] Furthermore, as shown in FIG. 11C, after temporarily stopping the transmission of information, the resynchronization pattern adder 28 sends a resynchronization pattern of a predetermined length onto the transmission path 5 before restarting the transmission of information.

[0068] The resynchronization pattern is preferably a randomized pattern such as a PRBS (Pseudorandom Binary Sequence). The resynchronization pattern includes a portion where the signal logic changes between 0 and 1, and the receiving side that receives the resynchronization pattern can use the resynchronization pattern to generate a clock signal for synchronously reproducing subsequently received information.

[0069] For containers corresponding to valid data, the resynchronization pattern adder 28 outputs the corresponding scrambled data as it is. The mapper 26 adjusts the output level of the output data of the resynchronization pattern adder 28 according to the modulation method. The output amplifier 27 adjusts the gain of the output data of the mapper 26 and then sends it to the transmission path 5. As shown in FIG. 11D, during the transmission period of the null data container, the output amplifier 27 temporarily stops the transmission of information, sets the signal level of the transmission path 5 to a fixed value or high impedance, and then sends a resynchronization pattern to the transmission path 5 before resuming the transmission of information.

[0070] In this way, when the amount of information of the first information source 2 is less than the transmission capacity of the transmission path 5, the downlink transmission unit 11 according to the first improvement example, when transmitting the container of invalid information in the frame, temporarily stops the transmission of information to the transmission path 5, and then, before resuming the transmission of information, sends a resynchronization pattern to the transmission path 5 and then resumes the transmission of information. According to the first improvement example, since it is not necessary to send invalid information to the transmission path 5, the energy consumption during transmission can be suppressed. In addition, since a resynchronization pattern is sent to the transmission path 5 before resuming the transmission of information to the transmission path 5, on the receiving side, a clock for synchronous reproduction of information can be generated based on the resynchronization pattern. Therefore, when the transmission of information to the transmission path 5 is temporarily stopped and then the transmission of information is resumed, the receiving side can surely perform the synchronous reproduction process of the information.

[0071] (Second improvement example of the downlink transmission unit 11) FIG. 12 is a block diagram of a second improvement example of the downlink transmission unit 11 in FIG. 3. The downlink transmission unit 11 in FIG. 12 has an LDTS replacement unit (Low Density Toggle Signal Replacer) 36 instead of the resynchronization pattern adder 28 in FIG. 9. When the amount of information of the information to be transmitted is less than the transmission capacity of the transmission path 5, the LDTS replacement unit 36 generates toggle data in which the period of information transition is longer than that of the information other than one block in the frame, for one block out of several blocks in the frame. That is, for one block out of several blocks in the frame, the period of information transition is made longer. In this specification, such toggle data with a long period is referred to as low density (or low period) toggle data. Here, the transition of information refers to the change of the signal logic on the transmission path 5 from 0 to 1 or from 1 to 0.

[0072] FIG. 13 is a block diagram showing an example of the internal configuration of the LDTS replacement unit 36. As shown in FIG. 13, the LDTS replacement unit 36 has an LDTS generator 37 that generates toggle data (hereinafter also referred to as LDTS) and a selector 38. The toggle data generated by the LDTS generator 37 is data in which the signal logic changes at a period corresponding to the number of serially connected registers of the shift register 31 shown in FIG. 6 in the scrambler 25.

[0073] As a more specific example, the LDTS generator 37 generates toggle data in which 1 continues continuously for the number of bits corresponding to the number of a plurality of registers in the shift register 31 and 0 continues continuously for the number of bits corresponding to the number of the plurality of registers in the shift register 31 - 1, for one block out of several blocks in the frame.

[0074] Alternatively, as described later, for one block out of several blocks in a frame, the LDTS generator 37 may generate toggle data in which 1s continue for a number of bits selected by a predetermined method from either the number of a plurality of registers in the shift register 31 or the number of the plurality of registers minus 1, and then 0s continue for a number of bits selected by a predetermined method from either the number of the plurality of registers minus 1 or the number of the plurality of registers minus 2 in the shift register 31. Further, as a method for performing the above selection, the LDTS generator 37 can use, for example, a method of randomly selecting using a random number generator or a method of selecting based on a preset value.

[0075] In explaining the processing operation of the downlink transmission unit 11 in FIG. 12, the ratio of the transmission rate per unit time between the first information source 2 and the transmission device is set to 3:4.

[0076] FIG. 14A is a diagram showing the data configuration of the scrambled data output from the scrambler 25. After the scrambled data corresponding to three containers (Container #1 to #3) each containing valid information, the scrambled data corresponding to one container (Container #4) containing invalid information is arranged. The scrambled data corresponding to these four containers is sequentially output from the scrambler 25. The payload of the container (Container #4) containing invalid information contains invalid data, the data identification information in the header is null, and the destination address may be set to an address that does not exist in the communication system 1.

[0077] FIG. 14B shows output data from the LDTS replacement unit 36. The LDTS replacement unit 36 leaves the header of the container (Container #4) containing null data intact in response to a timing control signal from the scheduler 23. This is different from the first improvement example, in which the header of the container containing null data is removed as shown in FIG. 11. The LDTS replacement unit 36 also inserts low-density toggle data (LDTS) whose signal logic changes into the container instead of the payload and parity of the container containing null data. More precisely, because the LDTS replacement unit 36 is provided downstream of the scrambler 25, it leaves the header portion of the scrambled data corresponding to the container containing null data intact and replaces the portions corresponding to the payload and parity of the container with low-density toggle data. The header is left intact so that the second sink device 7, which receives the low-cycle toggle data, can determine the type of the received toggle data.

[0078] The period during which 1s and 0s in the toggle data continue depends on the number L of connected stages of registers 30 in shift register 31 shown in FIG. 6 within scrambler 25. Shift register 31 shown in FIG. 6 shifts serial data between a plurality of registers for each cycle of the clock signal. Therefore, the maximum duration of output data "1" from shift register 31 is the number of bits equal to the number L of connected stages of registers 30, and the maximum duration of output data "0" is the number of bits equal to the number L-1 of connected stages of registers. Therefore, the toggle rate of 1s and 0s in the output data from shift register 31 is minimum when L consecutive 1s and L-1 consecutive 0s. Therefore, LDTS generator 37 generates toggle data in which L consecutive 1s and L-1 consecutive 0s are generated.

[0079] The LDTS replacement unit 36 outputs scrambled data corresponding to a container that does not contain null data as is, and outputs scrambled data corresponding to a container that contains null data after replacing the payload and parity parts of the container with toggle data generated by the LDTS generator 37 while leaving the header intact.

[0080] The output data of the LDTS replacement unit 36 is input to the mapper 26, converted to a signal level according to the modulation method, then input to the output amplifier 27 for gain adjustment, and finally sent to the transmission path 5. The output amplifier 27 sends the data of all the containers corresponding to all the information output by the first information source 2 to the transmission path 5.

[0081] Thus, in the second improvement example of the downlink transmission unit 11, for the container including null data, while leaving the header as it is, instead of the payload and parity of the container, the toggle data with the minimum toggle rate of 1 and 0 is sent to the transmission path 5. Therefore, in the second SerDes unit 6 that receives the toggle data and the corresponding header, the header recognizes that the toggle data is data for resynchronization, can generate a clock signal for synchronous reproduction using the toggle data, and when the transmission of information resumes later, can perform normal synchronous reproduction processing based on the toggle data.

[0082] The LDTS generator 37 in FIG. 13 always generates toggle data in which 1 continues for L bits and 0 continues for L - 1 bits. For this reason, the frequency of the toggle data becomes fixed, and there is a possibility that EMI (Electro Magnetic Interference) noise caused by this frequency is generated. Therefore, the frequency of the toggle data may be randomly changed while not increasing the energy consumption in the transmission path 5.

[0083] FIG. 15 is a block diagram showing the internal configuration of a modified example of the LDTS generator 37 in FIG. 13, and FIG. 16 is a diagram showing the output data of the LDTS replacement unit 36. The LDTS generator 37 in FIG. 15 has an LDTS generator 37a with a configuration different from that of the LDTS generator 37 in FIG. 13. The selector 38 in FIG. 15 is the same as the selector 38 in FIG. 13.

[0084] Each time the toggle data outputs "1", its duration is set to the number of bits for several minutes, which is either the number of connection stages L of the plurality of registers constituting the shift register 31 in the scrambler 25 or L - 1 which is 1 less than that, selected by a predetermined method. Also, each time the toggle data outputs "0", its duration is set to the number of bits for several minutes, which is L - 1 or L - 2 selected by a predetermined method.

[0085] As a result, as shown in FIG. 16, the toggle data included in the output data of the LDTS replacement unit 36 has no possibility of being biased to a specific frequency. The toggle data generated by the LDTS generator 37a in FIG. 15 has a slightly increased toggle rate compared to the toggle data generated by the LDTS generator 37 in FIG. 13, but the toggle rate of 1 and 0 can be made much smaller than that of the scrambled data containing valid information, and power consumption can be suppressed.

[0086] Thus, in the downlink transmission unit 11 according to the second improvement example, when transmitting the information of the container including null data to the transmission path 5, the toggle data with a sufficiently small toggle rate and the header for identifying the toggle data are transmitted to the transmission path 5, so that the power consumption on the transmission path 5 can be made sufficiently small.

[0087] (The third improvement example of the downlink transmission unit 11) FIG. 17 is a block diagram of the third improvement example of the downlink transmission unit 11 in FIG. 3. The downlink transmission unit 11 in FIG. 17 has a PRBS generator (pseudo-random number generator) 41, an LDTS replacement unit 42, an FEC (Forward Error Correction) unit 43, and a delay unit 44 instead of the resynchronization pattern adder 28 in FIG. 9.

[0088] The PRBS generator 41 generates a pseudo-random bit sequence. The internal configuration of the PRBS generator 41 has, for example, the same structure as that shown in FIG. 6, and includes a shift register having a plurality of registers, an XOR calculator that calculates the exclusive logical sum of the output of the register at the final stage in the shift register and the output of any register other than the final stage, and the output signal of the XOR calculator is input to the register at the first stage in the shift register. Note that since the specific internal configuration of the PRBS generator 41 is not limited, various modifications are conceivable.

[0089] The LDTS replacement unit 42 selects the pseudo-random bit sequence generated by the PRBS generator 41 for one block out of several blocks in the frame, and selects the container output from the framer 22 for the other blocks.

[0090] FIG. 18 is a block diagram showing an example of the internal configuration of the LDTS replacement unit 42. FIG. 19A is a diagram showing an example of the container output from the framer 22. An invalid address not used in the communication system 1 is stored in the destination address of the header of the container corresponding to one block out of several blocks in the frame, and null data is stored in the payload. By storing an invalid address in the destination address, the reception processing on the receiving side can be simplified and the power consumption can be reduced.

[0091] The LDTS replacement unit 42 in FIG. 18 includes an inverter 45, a first selector 46, a counter 47, and a second selector 48. The inverter 45 inverts the pseudo-random bit sequence generated by the PRBS generator 41. Hereinafter, the output of the inverter 45 is referred to as an inverted pseudo-random bit sequence. The counter 47 alternately performs counting for L bits and counting for L - 1 bits.

[0092] The first selector 46 selects the inverted pseudo-random bit sequence while the counter 47 is counting for L bits, and selects the pseudo-random bit sequence while the counter 47 is counting for L - 1 bits. The second selector 48 selects the container output from the framer 22 or the output signal of the first selector 46 based on the control signal from the scheduler 23. The signal selected by the second selector 48 is the output signal of the LDTS replacement unit 42.

[0093] Figure 19B is a diagram showing an example of the output data of the LDTS replacement unit 42. As shown in Figure 19B, in one block out of several blocks in the frame, the inverted pseudo-random bit sequence for L bits and the pseudo-random bit sequence for L - 1 bits are alternately output. In Figure 19B, the inverted pseudo-random bit sequence is denoted as!PRBS, and the pseudo-random bit sequence is denoted as PRBS.

[0094] The FEC unit 43 adds an error correction code to the output signal of the LDTS replacement unit 42. The P / S 24 converts the output signal of the FEC unit 43 into serial data.

[0095] Figure 19C is a diagram showing an example of the output signal of the FEC unit 43. The FEC unit 43 adds an error correction code (Parity) to each container corresponding to each block. For example, an error correction code is added at the end of the pseudo-random bit sequence replaced by the LDTS replacement unit 42.

[0096] The delay unit 44 delays the pseudo-random bit sequence output from the PRBS generator 41 by the time required for the pseudo-random bit sequence output from the PRBS generator 41 to pass through the LDTS replacement unit 42, the FEC unit 43, and the P / S 24.

[0097] The scrambler 25 calculates the exclusive OR of the serial data output from the P / S 24 and the pseudo-random bit sequence output from the delay device 44. More specifically, in one block within the frame, for L bits, the scrambler 25 outputs a 1 which is the exclusive OR of the inverted pseudo-random bit sequence in the serial data and the pseudo-random bit sequence delayed by the delay device 44, and for the next L - 1 bits, it alternately repeats the operation of outputting a 0 which is the exclusive OR of the pseudo-random bit sequence in the serial data and the pseudo-random bit sequence delayed by the delay device 44. As a result, in one block out of several blocks within the frame, the scrambler 25 outputs low-density toggle data.

[0098] For blocks other than one block out of several blocks within the frame, the scrambler 25 calculates the exclusive OR of the container output from the framer 22 and the pseudo-random bit sequence delayed by the delay device 44. As a result, the scrambler 25 performs scrambling processing on the container output from the framer 22. The output data of the scrambler 25 is adjusted in output level according to the modulation method by the mapper 26, and then the gain is adjusted by the output amplifier 27 and sent to the transmission path 5.

[0099] FIG. 19D is a diagram showing an example of the scrambled data output from the scrambler 25. In one block out of several blocks within the frame, the scrambler 25 outputs low-density toggle data in which "1" continues for L bits which is the number of connected stages of the shift register 31 in the PRBS generator 41, and "0" continues for L - 1 bits.

[0100] Since the period of the toggle data generated by the scrambler 25 in FIG. 17 is always fixed, there is a possibility that EMI noise may occur. Therefore, instead of the LDTS replacement unit 42 in FIG. 18, the LDTS replacement unit 42 of the first modified example shown in FIG. 20 may be provided.

[0101] The LDTS replacement unit 42 in FIG. 20 includes an inverter 51, a first counter 52, a second counter 53, a first selector 54, and a second selector 55.

[0102] Similar to the inverter 51 in FIG. 18, the inverter 51 outputs an inverted pseudo-random bit sequence obtained by inverting the pseudo-random bit sequence generated by the PRBS generator 41. The first counter 52 counts for L bits or L - 1 bits in a predetermined manner. The second counter 53 counts for L - 1 bits or L - 2 bits in a predetermined manner.

[0103] While the first counter 52 is counting for L bits or L - 1 bits, the first selector 54 continues to select the inverted pseudo-random bit sequence output from the inverter 51. Next, while the second counter 53 is counting for L - 1 bits or L - 2 bits, the first selector 54 continues to select the pseudo-random bit sequence. The first selector 54 alternately selects the inverted pseudo-random bit sequence and the pseudo-random bit sequence.

[0104] Similar to the second selector 55 in FIG. 18, for one block out of several blocks in the frame, the second selector 55 selects the output data of the first selector 54, and for the remaining blocks, the second selector 55 selects the container output from the frame.

[0105] FIGS. 21A to 21D are timing diagrams of the downlink transmission unit 11 corresponding to the LDTS replacement unit 42 in FIG. 20. FIG. 21A shows the output data of the framer 22, which is the same as that in FIG. 19A. FIG. 21B shows the output data of the LDTS replacement unit 42, and different data from that in FIG. 19B is output for one block out of several blocks in the frame. This data alternately includes the inverted pseudo-random data continuously output from the inverter 51 in FIG. 20 for L bits or L - 1 bits selected by a predetermined method and the pseudo-random data continuously output from the PRBS generator 41 for L - 1 bits or L - 2 bits selected by a predetermined method.

[0106] FIG. 21C is the output data of the FEC unit 43. Similarly, it is data that alternately includes the inverted pseudo-random number data output from the inverter 51 of FIG. 20 continuously for L bits or L-1 bits selected by a predetermined method, and the pseudo-random number data output from the PRBS generator 41 continuously for L-1 bits or L-2 bits selected by a predetermined method.

[0107] FIG. 21D is the output data of the scrambler 25, and toggle data different from that of FIG. 19D is output. The toggle data of FIG. 21D is data that alternately includes "1" continuing continuously for L bits or L-1 bits selected by a predetermined method and "0" continuing continuously for L-1 or L-2 bits selected by a predetermined method.

[0108] The LDTS replacement unit 42 in FIG. 20 shows an example in which the number of bits for which the signal logic "1" continues is selected by a predetermined method from among L bits or L-1 bits, and the number of bits for which the signal logic "0" continues is selected by a predetermined method from among L-1 bits or L-2 bits. However, the number of bits of the signal logic "1" and "0" may be set arbitrarily.

[0109] FIG. 22 is a block diagram showing the internal configuration of the LDTS replacement unit 42 of the second modification. The LDTS replacement unit 42 in FIG. 22 includes an inverter 56, a first selector 57, a selection control unit 58, and a second selector 59. The inverter 56 generates an inverted pseudo-random bit sequence obtained by inverting the pseudo-random bit sequence generated by the PRBS generator 41. The first selector 57 selects either the pseudo-random bit sequence generated by the PRBS generator 41 or the inverted pseudo-random bit sequence output from the inverter 56 based on a control signal from the selection control unit 58. The selection control unit 58 outputs a control signal for switching the selection of the first selector 57 at an arbitrary timing. For example, the selection control unit 58 may randomly switch the selection of the first selector 57 based on a pseudo-random number or the like. In the example of FIG. 22, an example in which the first selector 57 selects the inverted pseudo-random bit sequence is shown, but the number of bits for which the first selector 57 continuously selects the inverted pseudo-random bit sequence is arbitrary, and there is no limitation such as L bits or L-1 bits as in FIG. 20. The second selector 59 selects either the container output from the framer or the output signal of the first selector 57 based on a control signal from the scheduler.

[0110] FIG. 23 is a diagram showing an example of scrambled data output from the scrambler 25 when the LDTS replacement unit 42 of FIG. 22 is used. The scrambled data includes three containers (Container #1 to #3) and one container (Container #4) including a header, toggle data of an arbitrary period, and parity. The data of these four containers is repeatedly output in sequence.

[0111] When the LDTS replacement unit 42 of FIG. 22 is used, in one block out of several blocks in a frame, since the period of the toggle data can be arbitrarily changed, for example, the toggle data can be made as long as possible, or in some cases, the signal logic can be changed at an arbitrary timing.

[0112] Thus, in the third improvement example of the downlink transmission unit 11, for one block out of several blocks in a frame, toggle data is generated by the exclusive logical sum of serial data obtained by adding an error correction code to a pseudo-random bit sequence and the pseudo-random bit sequence. In the second improvement example, since it is assumed that the container to be replaced with toggle data does not have an error correction code added by the FEC unit 43, it is necessary to perform different processing from other containers. Also, even if there is an error in the header information of the container to be replaced with toggle data, it cannot be recovered. In contrast, in the third improvement example, since the container to be replaced with toggle data and other containers are treated in the same manner and an error correction code is added by the FEC unit 43 and then converted into serial data, it is not necessary to distinguish between the processing of the container to be replaced with toggle data and the processing of other containers within the downlink transmission unit 11, and the processing operation can be simplified. Also, for the container to be replaced with toggle data, since it is converted into serial data after an error correction code is added by the FEC unit 43, even if there is an error in the header part, it can be recovered, and there is no risk of the receiving side misrecognizing the toggle data as other data.

[0113] Note that the present technology can adopt the following configuration. (1) A transmission device that sends information generated at an information source and divided into blocks to a transmission path in units of frames including a plurality of the blocks, wherein when the amount of information of the information to be transmitted is less than the transmission capacity of the transmission path, in one block out of several blocks in the frame, the transmission unit is provided that stops sending information to the transmission path or sends toggle data having a longer information transition period than the information other than the one block in the frame to the transmission path. (2) The transmission device according to (1), wherein the transmission unit sends data of a specific signal logic to the transmission path or sets the transmission path to high impedance during the period of stopping sending information to the transmission path. (3) The transmission unit of the transmission device according to (1) or (2) sets the destination address of the one block that stops sending information to the transmission path to an address different from the address of the receiving device that receives information via the transmission path. (4) The transmission unit of the transmission device according to any one of (1) to (3) has a scrambler that generates scrambled data obtained by performing a scrambling process on the information generated at the information source, regardless of whether or not to stop sending information to the transmission path. (5) After the period during which the transmission of information to the transmission path is stopped has elapsed, the transmission unit sends a predetermined resynchronization pattern to the transmission path until the transmission of information to the transmission path is resumed. The resynchronization pattern is used for the receiving device to perform synchronous reproduction processing on the information received via the transmission path. The transmission device according to any one of (1) to (4). (6) The transmission unit of the transmission device according to (4) has a selector that selects either the scrambled data or a predetermined resynchronization pattern used for the receiving device to perform synchronous reproduction processing on the information received via the transmission path, and sends it to the transmission path. (7) The transmission unit of the transmission device according to (6) has a scheduler that controls the selection of the selector based on the control signal transmitted by the receiving device via the transmission path. (8) The transmission unit has a scrambler that generates scrambled data obtained by performing a scrambling process on the information generated at the information source. The scrambler has a shift register having a plurality of registers that sequentially shift serial data corresponding to the information generated at the information source, and a logic operation unit that generates the scrambled data by performing a predetermined logical operation on the data shifted by the shift register and the serial data input to the shift register. The transmitting device described in (1), wherein the transmitting unit transitions the information sent to the transmission path in one of several blocks in the frame at a period corresponding to the number of stages of the plurality of registers in the shift register. (9) The transmitting device described in (8), wherein the transmitting unit sends information to the transmission path in which, in one of the blocks in the frame, a number of consecutive 1s equal to the number of the registers in the shift register, and a number of consecutive 0s equal to the number of the registers in the shift register minus 1. (10) The transmitting unit transmits to the transmission path information in which, in one of the blocks in the frame, a number of consecutive 1s equal to the number of bits selected by a predetermined method for either the number of the plurality of registers in the shift register or the number of the plurality of registers minus 1, and a number of consecutive 0s equal to the number of bits selected by a predetermined method for either the number of the plurality of registers in the shift register minus 1 or the number of the plurality of registers minus 2. (11) A transmitting device described in any one of (8) to (10), wherein the transmitting unit sends header information to the transmission path in one of several blocks in the frame before sending information to the transmission path, the header information having a destination address different from the address of a receiving device connected to the transmission path. (12) The transmitting device according to (11), wherein the header information includes identification information of the toggle data. (13) The transmitting unit a pseudorandom number generator for generating a pseudorandom number signal; The transmitting device according to (1), further comprising: a scrambler that generates the toggle data based on the pseudorandom signal in one of several blocks in the frame. (14) a permutation unit that selects information generated by the information source in blocks other than the one block in the frame and selects the pseudorandom number signal in the one block; an error correction processing unit that adds an error correction code to the information selected by the replacement unit; a delay device that delays the pseudorandom number signal for a predetermined period of time; The transmitting device described in (13), wherein the scrambler generates the toggle data for one of several blocks in the frame based on the output signal of the error correction processing unit and the output signal of the delay unit. (15) The predetermined period is a period from when the pseudorandom number generator generates the pseudorandom number signal to when the output signal of the error correction processing unit is input to the scrambler, The transmitting device described in (14), wherein the scrambler generates the toggle data in one of several blocks in the frame by taking an exclusive OR of the output signal of the error correction processing unit and the output signal of the delay unit, or an exclusive OR of the output signal of the error correction processing unit and an inverted signal of the output signal of the delay unit. (16) The pseudorandom number generator has a shift register having a plurality of registers; The transmitting device described in (15), wherein the scrambler generates the toggle data in one of several blocks in the frame, in which a first signal logic continues consecutively for a number of bits equal to the number of the plurality of registers in the shift register, and a second signal logic continues consecutively for a number of bits equal to the number of the plurality of registers in the shift register minus 1. (17) The transmitting device described in (15), wherein the pseudo-random number generator has a shift register having a plurality of registers, and the scrambler generates the toggle data in one of several blocks in the frame, in which a first signal logic continues for a number of consecutive bits equal to the number of the plurality of registers in the shift register or the number of the plurality of registers minus 1 selected by a predetermined method, and a second signal logic continues for a number of consecutive bits equal to the number of the plurality of registers in the shift register minus 1 or the number of the plurality of registers minus 2 selected by a predetermined method. (18) The transmitting device described in (15), wherein the scrambler maximizes the period for one of several blocks in the frame, or generates the toggle data with a period that can be arbitrarily selected. (19) The transmission unit in the transmission device according to any one of (1) to (18) transmits information to the transmission path within a period assigned by TDD (Time Division Duplex). (20) A master device, A slave device that transmits, according to an instruction from the master device, information generated at an information source and divided into blocks, to the master device via a transmission path in units of frames including a plurality of the blocks, and the slave device includes: When the amount of information generated at the information source is less than the transmission capacity of the transmission path, the slave device has a transmission unit that, for one block out of several blocks in the frame, stops transmitting information to the transmission path or transmits toggle data to the transmission path in which the period of information transition is longer than that of information other than the one block in the frame. A communication system. (21) An information transmission method for transmitting information generated at an information source and divided into blocks in units of frames including a plurality of the blocks to a transmission path, When the amount of information generated at the information source is less than the transmission capacity of the transmission path, for one block out of several blocks in the frame, the method stops transmitting information to the transmission path or transmits toggle data to the transmission path in which the period of information transition is longer than that of information in blocks other than the one block. An information transmission method.

[0114] Aspects of the present disclosure are not limited to the above-described individual embodiments, but also include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described content. That is, various additions, changes, and partial deletions are possible without departing from the conceptual ideas and spirit of the present disclosure derived from the content defined in the claims and their equivalents.

Description of Reference Numerals

[0115] 1 Communication system, 2 First information source, 3 First sink device, 4 First SerDes unit, 5 Transmission path, 6 Second SerDes unit, 7 Second sink device, 8 Second information source, 11 Downlink transmission unit, 12 Uplink reception unit, 13 Downlink reception unit, 14 Uplink transmission unit, 21 Buffer, 22 Framer, 23 Scheduler, 24 Parallel-serial converter, 25 Scrambler, 26 Mapper, 27 Output amplifier, 31 Shift register, 32 First XOR calculator, 33 Second XOR calculator, 34 Resynchronization pattern generator, 35 Selector, 36 LDTS conversion unit, 37 LDTS generator, 38 Selector, 41 PRBS generator, 42 LDTS replacement unit, 43 FEC unit, 44 Delay unit, 45 Inverter, 46 First selector, 47 Counter, 48 Second selector, 51 Inverter, 52 First counter, 53 Second counter, 54 First selector, 55 Second selector, 56 Inverter, 57 First selector, 58 Selection control unit, 59 Second selector

Claims

1. A transmitting device that sends information generated at an information source and segmented into blocks to a transmission path in frame units including a plurality of said blocks, when the amount of information to be transmitted is less than the transmission capacity of the transmission path, in one of several blocks within the frame, the transmitting unit stops sending information to the transmission path or sends toggle data to the transmission path whose information transition period is longer than that of the information other than the one block within the frame, the transmitting unit has a scrambler that generates scrambled data by performing a scrambling process on the information generated at the information source, the scrambler, has a shift register having a plurality of registers that sequentially shift serial data corresponding to the information generated at the information source, and a logic operation unit that generates the scrambled data by a predetermined logical operation between the data shifted by the shift register and the serial data input to the shift register, the transmitting unit, in one of several blocks within the frame, transitions the information transmitted to the transmission path at a period corresponding to the number of stages of the plurality of registers in the shift register, a transmitting device.

2. The transmitting device according to claim 1, wherein the transmitting unit, in one of several blocks within the frame, sends to the transmission path information in which 1 continues continuously for the number of bits corresponding to the number of the plurality of registers in the shift register and 0 continues continuously for the number of bits corresponding to the number - 1 of the plurality of registers in the shift register.

3. The transmitting device according to claim 1, wherein the transmitting unit, in one of several blocks within the frame, continuously sends 1 for the number of bits selected by a predetermined method from either the number of the plurality of registers in the shift register or the number of the plurality of registers minus 1, and continuously sends 0 for the number of bits selected by a predetermined method from either the number of the plurality of registers minus 1 or the number of the plurality of registers minus 2 in the shift register, and sends the information to the transmission path.

4. The transmitting device according to any one of claims 1 to 3, wherein the transmitting unit, in one of several blocks within the frame, before sending information to the transmission path, sends header information having a destination address different from the address of the receiving device connected to the transmission path to the transmission path.

5. The transmission device according to claim 4, wherein the header information includes identification information of the toggle data.

6. A transmission device that sends information generated at an information source and divided into blocks to a transmission path in units of frames including a plurality of the blocks, when the amount of information to be transmitted is less than the transmission capacity of the transmission path, in one block out of several blocks in the frame, the transmission of information to the transmission path is stopped, or toggle data in which the period of information transition is longer than the information in the blocks other than the one block in the frame is sent to the transmission path, comprising a transmission unit; The transmission unit includes a pseudo-random number generator that generates a pseudo-random number signal, and a scrambler that generates the toggle data based on the pseudo-random number signal in one block out of several blocks in the frame, the transmission device.

7. a replacement unit that selects information generated at the information source in blocks other than the one block in the frame and selects the pseudo-random number signal in the one block; an error correction processing unit that adds an error correction code to the information selected by the replacement unit; and a delay unit that delays the pseudo-random number signal for a predetermined period, wherein the scrambler generates the toggle data based on the output signal of the error correction processing unit and the output signal of the delay unit in one block out of several blocks in the frame, the transmission device according to claim 6.

8. The predetermined period is the period from when the pseudo-random number generator generates the pseudo-random number signal until the output signal of the error correction processing unit is input to the scrambler, wherein the scrambler generates the toggle data by exclusive OR of the output signal of the error correction processing unit and the output signal of the delay unit, or by exclusive OR of the output signal of the error correction processing unit and the inverted signal of the output signal of the delay unit, in one block out of several blocks in the frame, the transmission device according to claim 7.

9. The pseudo-random number generator has a shift register having a plurality of registers, wherein the scrambler generates the toggle data in which the first signal logic continues continuously for the number of bits corresponding to the number of the plurality of registers in the shift register and the second signal logic continues continuously for the number of bits corresponding to the number of the plurality of registers in the shift register minus one, in one block out of several blocks in the frame, the transmission device according to claim 8.

10. The pseudo-random number generator has a shift register having a plurality of registers. The scrambler, in one block out of several blocks in the frame, generates the toggle data in which the first signal logic continues for a number of bits selected by a predetermined method from either the number of the plurality of registers in the shift register or the number of the plurality of registers minus 1, and the second signal logic continues for a number of bits selected by a predetermined method from either the number of the plurality of registers minus 1 or the number of the plurality of registers minus 2 in the shift register. The transmitting apparatus according to claim 8.

11. The scrambler, in one block out of several blocks in the frame, generates the toggle data in which the period is maximized or the period can be arbitrarily selected. The transmitting apparatus according to claim 8.

12. The transmitting unit transmits information to the transmission path within a period assigned by TDD (Time Division Duplex). The transmitting apparatus according to any one of claims 1 to 11.

13. A master device, A slave device that transmits information generated at an information source and divided into blocks according to an instruction from the master device to the master device via a transmission path in units of frames including a plurality of the blocks. When the amount of information generated at the information source is less than the transmission capacity of the transmission path, the slave device has a transmitting unit that, in one block out of several blocks in the frame, stops transmitting information to the transmission path or transmits toggle data to the transmission path in which the period of information transition is longer than that of information other than the one block in the frame. The transmitting unit has a scrambler that generates scrambled data obtained by performing a scrambling process on the information generated at the information source. The scrambler has a shift register that sequentially shifts serial data corresponding to the information generated at the information source, and a logic operation unit that generates the scrambled data by a predetermined logical operation between the data shifted by the shift register and the serial data input to the shift register. The transmitting unit transitions the information transmitted to the transmission path at a period corresponding to the number of stages of the plurality of registers in the shift register in one block out of several blocks in the frame. A communication system.

14. A master device, a slave device that, in accordance with an instruction from the master device, transmits information generated at an information source and divided into blocks to the master device via a transmission path in units of frames including a plurality of the blocks, wherein when the amount of information generated at the information source is less than the transmission capacity of the transmission path, the slave device has a transmission unit that, for one block out of several blocks in the frame, stops sending information to the transmission path or sends toggle data having a longer information transition period than the information other than the one block in the frame to the transmission path, the transmission unit includes a pseudo-random number generator that generates a pseudo-random number signal, and a scrambler that generates the toggle data based on the pseudo-random number signal for one block out of several blocks in the frame, and a communication system.

15. An information transmission method for sending information generated at an information source and divided into blocks to a transmission path in units of frames including a plurality of the blocks, wherein when the amount of information generated at the information source is less than the transmission capacity of the transmission path, for one block out of several blocks in the frame, sending of information to the transmission path is stopped or toggle data having a longer information transition period than the information in blocks other than the one block is sent to the transmission path, a scrambler that generates scrambled data by subjecting the information generated at the information source to a scrambling process includes a shift register having a plurality of registers that sequentially shift serial data corresponding to the information generated at the information source, and generates the scrambled data by a predetermined logical operation between the data shifted by the shift register and the serial data input to the shift register, and for one block out of several blocks in the frame, the information sent to the transmission path is transitioned at a period corresponding to the number of stages of the plurality of registers in the shift register, An information transmission method.

16. An information transmission method for sending information generated at an information source and divided into blocks to a transmission path in units of frames including a plurality of the blocks, When the amount of information of the information generated at the information source is less than the transmission capacity of the transmission path, for one block out of several blocks in the frame, transmission of information to the transmission path is stopped, or toggle data with a longer information transition period than the information in the blocks other than the one block is transmitted to the transmission path. Generate a pseudo-random number signal. A communication method in which, for one block out of several blocks in the frame, the toggle data is generated based on the pseudo-random number signal.

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