Nanosecond Pulsar ADC System

Abstract

To solve the problems that various defections occurs in an end part of a wafer increases a waste disposal and reduces a yield of the wafer.SOLUTION: A plasma film formation system comprises: a wafer platform; a second electrode 420; a first electrode 415; a first high voltage pulsar 425; and a second high voltage pulsar 430. According to some embodiments, the second electrode may be arranged so as to be near from the wafer platform. According to some embodiments, the second electrode may contain: a disk shape having a center open part; a center shaft; an open diameter; and an outer diameter. According to some embodiments, the first electrode may be arranged in a center open part of the second electrode so as to be near from the wafer platform. According to some embodiments, the first electrode may contain: the disk shape; the center shaft; and the outer diameter. According to some embodiments, the first high voltage pulsar may be electrically coupled to the first electrode. According to some embodiments, the second high voltage pulsar may be electrically coupled to the second electrode.SELECTED DRAWING: Figure 4B

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 62 / 711,464, entitled "NANOSECOND PULSER SYSTEM," filed July 27, 2018, which is incorporated herein by reference in its entirety. This application claims priority to U.S. Provisional Patent Application No. 62 / 711,334, entitled "NANOSECOND PULSER THERMAL MANAGEMENT," filed July 27, 2018, which is incorporated herein by reference in its entirety. This application claims priority to U.S. Provisional Patent Application No. 62 / 711,457, filed July 27, 2018, and entitled "NANOSECOND PULSER PULSE GENERATION," which is incorporated herein by reference in its entirety. This application claims priority to U.S. Provisional Patent Application No. 62 / 711,347, entitled "NANOSECOND PULSER ADC SYSTEM," filed July 27, 2018, which is incorporated herein by reference in its entirety. This application claims priority to U.S. Provisional Patent Application No. 62 / 711,467, entitled "EDGE RING POWER SYSTEM," filed July 27, 2018, which is incorporated herein by reference in its entirety. This application claims priority to U.S. Provisional Patent Application No. 62 / 711,406, filed July 27, 2018, and entitled "NANOSECOND PULSER BIAS COMPENSATION," which is incorporated herein by reference in its entirety. This application claims the priority of U.S. Provisional Patent Application No. 62 / 711,468, entitled "NANOSECOND PULSER CONTROL MODULE", filed on July 27, 2018, the entire disclosure of which is incorporated herein by reference. This application claims the priority of U.S. Provisional Patent Application No. 62 / 711,523, entitled "PLASMA SHEATH CONTROL FOR RF PLASMA REACTORS", filed on August 10, 2018, the entire disclosure of which is incorporated herein by reference. This application claims the priority of U.S. Provisional Patent Application No. 62 / 789,523, entitled "EFFICIENT NANOSECOND PULSER WITH SOURCE AND SINK CAPABILITY FOR PLASMA CONTROL APPLICATIONS", filed on January 1, 2019, the entire disclosure of which is incorporated herein by reference. This application claims the priority of U.S. Provisional Patent Application No. 62 / 789,526, entitled "EFFICIENT ENERGY RECOVERY IN A NANOSECOND PULSER CIRCUIT", filed on January 1, 2019, the entire disclosure of which is incorporated herein by reference. This application claims the priority of U.S. Patent Application No. 16 / 523,840, entitled "NANOSECOND PULSER BIAS COMPENSATION", filed on July 26, 2019, and is a partial continuation application, the entire disclosure of which is incorporated herein by reference.

[0002] The present invention relates to a spatially-varying wafer bias power system. BACKGROUND OF THE INVENTION

[0003] Generating high voltage pulses with fast rise and / or fall times is challenging. For example, to achieve fast rise and / or fall times (e.g., less than about 50 ns) for high voltage pulses (e.g., greater than about 5 kV), the slope of the rise and / or fall of the pulse must be incredibly steep (e.g., greater than 10 ns). 11 V / s). Such steep rise and / or fall times are very difficult to generate, especially in circuits driving low capacitance loads. Such pulses can be particularly difficult to generate using standard electrical components in a compact format, and / or with pulses having variable pulse widths, voltages, and repetition rates, and / or in applications with capacitive loads, such as plasmas. Summary of the Invention [Problem to be solved by the invention]

[0004] Furthermore, wafer yield can determine whether a process is successful. Often, chips at the edge of a wafer may be unusable due to various defects that occur at the edge of the wafer. These defects increase waste and reduce wafer yield. [Means for solving the problem]

[0005] Some embodiments of the present invention include a spatially varying wafer bias system that may include a first high-voltage pulser, a second high-voltage pulser, a chamber, a first electrode, and a second electrode. In some embodiments, the first high-voltage pulser may output a first plurality of pulses having a first voltage greater than about 1 kV, a first pulse width less than about 1 μs, and a first pulse repetition frequency greater than about 20 kHz. In some embodiments, the second high-voltage pulser may output a second plurality of pulses having a second voltage greater than about 1 kV, a second pulse width less than about 1 μs, and a second pulse repetition frequency greater than about 20 kHz. In some embodiments, the first electrode may be disposed within the chamber and electrically coupled to the first high-voltage pulser, and the second electrode may be disposed within the chamber adjacent to the first electrode and electrically coupled to the second high-voltage pulser.

[0006] In some embodiments, the chamber may contain either or both of the wafers, and the plasma may be capacitively coupled to the first electrode and the second electrode with a capacitance between 10 pF and 1 μF.

[0007] In some embodiments, when using the first nanosecond pulser and the second nanosecond pulser, the electric field across the surface of the wafer may be less than 25%, less than 20%, less than 15%, less than 10%, less than 5%, or less than 2% uniform, or better.

[0008] In some embodiments, the capacitance between the first electrode and the corresponding portion of the wafer is greater than 100 pF, and the capacitance between the second electrode and the corresponding portion of the wafer is greater than 100 pF.

[0009] In some embodiments, the chamber may contain a plasma of ions that are accelerated onto the wafer.

[0010] In some embodiments, the first high-voltage pulsar generates an electrode voltage on a first electrode exceeding about 1 kV, and the second high-voltage pulsar generates an electrode voltage on a second electrode exceeding about 1 kV. In some embodiments, the ratio of the first voltage to the second voltage is less than 2 to 1, or the ratio of the second voltage to the first voltage is less than 2 to 1.

[0011] In some embodiments, one or both of the first electrode and the second electrode are axially symmetric.

[0012] In some embodiments, the first electrode has a first planar surface, the second electrode has a second planar surface, and the area of the second planar surface is about 25% of the sum of the first planar surface and the second planar surface.

[0013] In some embodiments, both the first high-voltage pulsar and the second high-voltage pulsar include a resistive output stage. In some embodiments, both the first high-voltage pulsar and the second high-voltage pulsar include an energy recovery circuit.

[0014] In some embodiments, the parameters of the first plurality of pulses are controlled independently of the parameters of the second plurality of pulses. In some embodiments, the first pulse repetition frequency and the second pulse repetition frequency are in phase with each other.

[0015] In some embodiments, the capacitance between the first electrode and the second electrode is less than about 10 nF.

[0016] In some embodiments, the first electrode comprises a disc shape, a central axis, and an outer diameter. In some embodiments, the second electrode comprises a disc shape having a central opening, the first electrode is disposed within the central opening thereof, and further comprises a central axis aligned with the central axis of the first electrode, an opening diameter, and an outer diameter.

[0017] Some embodiments of the present invention include a spatially varying wafer bias system that may include a wafer platform, a first electrode, a second electrode, a first high-voltage pulser, and a second high-voltage pulser. In some embodiments, the first electrode may include a disk shape, a central axis, and an outer diameter. In some embodiments, the second electrode may include a disk shape with a central opening, the first electrode disposed within the central opening, and may further include a central axis aligned with the central axis of the first electrode, an opening diameter, and an outer diameter. In some embodiments, the first high-voltage pulser may be electrically coupled to the first electrode, and the first high-voltage pulser may generate pulses greater than 5 kV at a pulse repetition rate greater than 10 kHz. In some embodiments, the second high-voltage pulser may be electrically coupled to the second electrode, and the second high-voltage pulser may generate pulses greater than 5 kV at a pulse repetition rate greater than 10 kHz.

[0018] In some embodiments, the second high-voltage pulser provides pulses having an amplitude that is a fraction of the amplitude of the pulses delivered by the first high-voltage pulser, hi some embodiments, the second high-voltage pulser provides pulses having a pulse repetition frequency that is a fraction of the pulse repetition frequency of the pulses delivered by the first high-voltage pulser.

[0019] In some embodiments, the spatially varying wafer bias system may also include a first resistive output stage coupled to the first high voltage pulser and the first electrode, and a second resistive output stage coupled to the second high voltage pulser and the second electrode. In some embodiments, the spatially varying wafer bias system may also include a bias compensation circuit coupled to the first high voltage pulser and the first electrode.

[0020] In some embodiments, the spatially varying wafer bias system may also include a ring of insulating material disposed between the first electrode and the second electrode. In some embodiments, the wafer bias system includes a dielectric material or a ceramic material. In some embodiments, the wafer platform has an outer diameter substantially similar to an outer diameter of the second electrode.

[0021] Some embodiments may include a method including pulsing a first high-voltage pulser coupled to a first electrode in a plasma chamber, the first high-voltage pulser pulsing at a first voltage greater than about 1 kV, a first pulse repetition frequency greater than about 20 kHz, and a first pulse width; and pulsing a second high-voltage pulser coupled to a second electrode in the plasma chamber, the second high-voltage pulser pulsing at a second voltage greater than about 1 kV, a second pulse repetition frequency greater than about 20 kHz, and a second pulse width. In some embodiments, the first electrode and the second electrode are positioned below the wafer. The method may further include measuring a parameter corresponding to a physical phenomenon occurring in the plasma chamber (e.g., chuck voltage, electrode voltage, field uniformity, ion current, etc.). Then, adjusting at least one of the second voltage, the second pulse repetition frequency, and the second pulser width based on the measured parameter.

[0022] In some embodiments, the voltage or current measured at various locations within the plasma chamber corresponds to the uniformity of the electric field across the surface of the wafer.

[0023] In some embodiments, the voltage or current measured at various locations within the plasma chamber corresponds to the uniformity of the ion current across the surface of the wafer.

[0024] In some embodiments, the parameter is the current through a resistor in either the resistive output stage or the energy recovery circuit.

[0025] Some embodiments of the present invention include a spatially-varying wafer bias system. For example, the wafer bias system can include a disc-shaped wafer platform, a first electrode having a disc shape and disposed proximate to the wafer platform, a second electrode having a disc shape and having a central opening disposed proximate to and aligned with the wafer platform such that the first electrode is disposed within its central opening, a first high voltage pulsar electrically coupled to the first electrode, and a second high voltage pulsar electrically coupled to the second electrode.

[0026] In some embodiments, the second high voltage pulsar supplies a pulse having an amplitude that is a fraction of the amplitude of the pulse supplied by the first high voltage pulsar. The fraction can include, for example, 50%, 75%, 100%, 125%, 150%, 200%, etc.

[0027] In some embodiments, the system further includes a first resistive output stage coupled between the first high voltage pulsar and the first electrode.

[0028] In some embodiments, the system further includes a second resistive output stage coupled between the second high voltage pulsar and the second electrode.

[0029] In some embodiments, the system further includes a bias capacitor coupled between the first high voltage pulsar and the first electrode.

[0030] In some embodiments, the system further includes a bias capacitor coupled between the first high voltage pulsar and the second electrode.

[0031] In some embodiments, the first high voltage pulsar includes one or more nanosecond pulsars. In some embodiments, the second high voltage pulsar includes one or more nanosecond pulsars.

[0032] Some embodiments include a plasma deposition system comprising a wafer platform, a first electrode, a second electrode, a first high voltage pulser, and a second high voltage pulser. In some embodiments, the second electrode may be disposed under the wafer platform. In some embodiments, the second electrode may include a disk shape with a central opening, a central axis, an opening diameter, and an outer diameter. In some embodiments, the first electrode may be disposed under the wafer platform and within the central opening of the second electrode. In some embodiments, the first electrode may include a disk shape, a central axis, and an outer diameter. In some embodiments, the first high voltage pulser may be electrically coupled to the first electrode. In some embodiments, the first high voltage pulser can generate pulses exceeding 5 kV at a pulse repetition rate exceeding 10 kHz. In some embodiments, the second high voltage pulser may be electrically coupled to the second electrode. In some embodiments, the second high voltage pulser can generate pulses exceeding 5 kV at a pulse repetition rate exceeding 10 kHz.

[0033] Some embodiments include a plasma deposition system, the plasma deposition system comprising a wafer platform having a first platform region and a second platform region, a first electrode disposed under the first platform region of the wafer platform, a second electrode disposed under the second platform region of the wafer platform, and a first high voltage pulser electrically coupled to the first electrode, the first high voltage pulser generating pulses exceeding 2 kV at a pulse repetition rate exceeding 10 kHz, and further comprising a second high voltage pulser electrically coupled to the second electrode, the second high voltage pulser generating pulses exceeding 2 kV at a pulse repetition rate exceeding 10 kHz.

[0034] In some embodiments, the second high voltage pulser supplies pulses having an amplitude that is a fraction of the amplitude of the pulses supplied by the first high voltage pulser.

[0035] In some embodiments, the second high-voltage pulsar supplies a pulse having a pulse repetition frequency that is a fraction of the pulse repetition frequency of the pulses supplied by the first high-voltage pulsar.

[0036] In some embodiments, the first high-voltage pulsar or the second high-voltage pulsar includes one or more nanosecond pulsars.

[0037] In some embodiments, the first high-voltage pulsar or the second high-voltage pulsar includes one or more high-voltage switches.

[0038] Some embodiments include a system, the system comprising a wafer platform, a plurality of electrodes disposed under the wafer platform, and a plurality of high-voltage pulsars each electrically coupled to one of the plurality of electrodes, each of the plurality of high-voltage pulsars generating a pulse with a pulse repetition rate greater than 10 kHz and a pulse greater than 5 kV. In some embodiments, each of the plurality of electrodes is separated from each other by an insulator. In some embodiments, each of the plurality of high-voltage pulsars generates a pulse having either or both a different voltage or a different pulse repetition rate.

[0039] These exemplary embodiments are not meant to limit or define the present disclosure, but are mentioned to provide examples to aid in its understanding. Additional embodiments are discussed in the detailed description, and further explanation is provided there. The advantages provided by one or more of the various embodiments can be further understood by reviewing this specification or by practicing one or more of the presented embodiments.

Brief Description of the Drawings

[0040] These and other features, aspects, and advantages of the present disclosure will be better understood when the following detailed description is read with reference to the accompanying drawings. [Figure 1] It is a circuit diagram of a nanosecond pulsar according to some embodiments. [Figure 2]FIG. 1 illustrates an exemplary waveform generated by a nanosecond pulser. [Figure 3] FIG. 10 is a diagram of another example of a nanosecond pulser according to some embodiments. [Figure 4A] ~ [Figure 4B] FIG. 1 is a block diagram of a spatially varying wafer bias power system according to some embodiments. [Figure 5] FIG. 1 is a block diagram of a spatially varying wafer bias power system according to some embodiments. [Figure 6] FIG. 1 is a block diagram of a spatially varying wafer bias system according to some embodiments. [Figure 7] FIG. 1 is a schematic diagram of a spatially varying wafer bias system according to some embodiments. [Figure 8] FIG. 1 is a schematic diagram of a spatially varying wafer bias system according to some embodiments. [Figure 9] FIG. 1 illustrates an exemplary computing system for performing functions to facilitate implementation of embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0041] Systems and methods are disclosed for generating different high-voltage pulses on different electrodes. For example, multiple pulse generators (e.g., nanosecond pulsers, RF generators, or HV switches) can each be electrically coupled to a respective one of the multiple electrodes. The multiple pulse generators can generate different voltages, ion energies, or electric fields on the electrodes. This can be done for a variety of reasons, such as to compensate for plasma chamber imperfections, wafer discontinuities, or to reduce defects at the edge of the wafer. In one embodiment, multiple pulse generation systems can be used to generate a different electric field profile at the edge of the wafer than at the center of the wafer.

[0042] FIG. 1 is a circuit diagram of a nanosecond pulsar system 100 according to some embodiments. The nanosecond pulsar system 100 can be implemented within a high voltage nanosecond pulsar system. The nanosecond pulsar system 100 can be generalized into five stages (these stages can be decomposed into other stages, generalized into fewer stages, and / or include or not include the illustrated components). The nanosecond pulsar system 100 includes a pulsar transformer stage 101, a resistive output stage 102, a lead stage 103, a DC bias compensation circuit 104, and a load stage 106.

[0043] In some embodiments, the nanosecond pulsar system 100 can generate pulses from a power source having a voltage exceeding 2 kV, a rise time of less than about 20 ns, and a frequency exceeding about 10 kHz.

[0044] In some embodiments, the pulsar transformer stage 101 can generate a plurality of high voltage pulses having a high frequency and fast rise and fall times. In all of the circuits illustrated, the high voltage pulsar may comprise a nanosecond pulsar.

[0045] In some embodiments, the pulsar transformer stage 101 can include one or more solid state switches S1 (e.g., solid state switches such as IGBTs, MOSFETs, SiC MOSFETs, SiC junction transistors, FETs, SiC switches, GaN switches, photoconductive switches, etc.), one or more snubber resistors R3, one or more snubber diodes D4, one or more snubber capacitors C5, and / or one or more freewheel diodes D2. One or more switches and / or circuits can be arranged in parallel or in series.

[0046] In some embodiments, load stage 106 may represent an effective circuit for a plasma deposition apparatus, a plasma etching apparatus, or a plasma sputtering apparatus. Capacitance C2 may represent the capacitance of the dielectric material on which the wafer sits, or capacitance C2 may represent the capacitance between an electrode and the wafer separated by a dielectric material. Capacitor C3 may represent the sheath capacitance of the plasma to the wafer. Capacitor C9 may represent the capacitance within the plasma between the chamber wall and the top surface of the wafer. Current source I2 and current source I1 may represent ion current through the sheath of the plasma.

[0047] In some embodiments, resistive output stage 102 may include one or more inductive elements represented by inductor L1 and / or inductor L5. Inductor L5 may represent, for example, stray inductance of leads within resistive output stage 102. Inductor L1 may be configured to minimize power flowing directly from pulser-transformer stage 101 to resistor R1.

[0048] In some embodiments, resistor R1 may dissipate charge from load stage 106, for example, on a fast time scale (e.g., 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1000 ns, etc.). f The resistance of resistor R1 may be low to ensure that

[0049] In some embodiments, resistor R1 may include multiple resistors arranged in series and / or parallel. Capacitor C11 may represent the stray capacitance of resistor R1, including the capacitance of resistors arranged in series and / or parallel. The capacitance of stray capacitance C11 may be, for example, less than 5 nF, less than 2 nF, less than 1 nF, less than 500 pF, less than 250 pF, less than 100 pF, less than 50 pF, less than 10 pF, less than 1 pF, etc. The capacitance of stray capacitance C11 may be less than the load capacitance, for example, less than the capacitance of C2, C3, and / or C9.

[0050] In some embodiments, multiple pulser-transformer stages 101 may be arranged in parallel and coupled across inductor L1 and / or resistor R1 to resistive output stage 102. Each of the multiple pulser-transformer stages 101 may also include diode D1 and / or diode D6.

[0051] In some embodiments, capacitor C8 may represent the stray capacitance of blocking diode D1, and in some embodiments, capacitor C4 may represent the stray capacitance of diode D6.

[0052] In some embodiments, the DC bias compensation circuit 104 may include a DC voltage source V1 that can be used to bias the output voltage either positively or negatively. In some embodiments, capacitor C12 isolates / isolates the DC bias voltage from the resistive output stage and other circuit elements. It allows for a potential shift from one portion of the circuit to another. In some applications, the potential shift established thereby is used to hold a wafer in place. Resistor R2 may protect / isolate the DC bias supply from the high voltage pulse output from the pulser-transformer stage 101.

[0053] In this example, the DC bias compensation circuit 104 is a passive bias compensation circuit and may include a bias compensation diode D1 and a bias compensation capacitor C15. The bias compensation diode C15 may be disposed in series with the offset power supply voltage V1. The bias compensation capacitor C15 may be disposed across either or both of the offset power supply voltage V1 and resistor R2. The bias compensation capacitor C15 may have a capacitance of less than 100 nH to 100 μF, such as, for example, about 100 μF, about 50 μF, about 25 μF, about 10 μF, about 2 μF, about 500 nH, about 200 nH, etc.

[0054] In some embodiments, bias capacitor C12 may allow for a voltage offset between the output of pulser-transformer stage 101 (e.g., location labeled 125) and the voltage on the electrode (e.g., location labeled 124). In operation, the electrode may be at, for example, a DC voltage of -2 kV during the burst, while the output of the nanosecond pulser alternates between +6 kV during the pulse and 0 kV between pulses.

[0055] The bias capacitor C12 may be, for example, 100 nF, 10 nF, 1 nF, 100 μF, 10 μF, 1 μF, etc. Resistor R2 may have a high resistance, for example, about 1 kOhm, 10 kOhm, 100 kOhm, 1 Mohm, 10 Mohm, 100 Mohm, etc.

[0056] In some embodiments, bias compensation capacitor C15 and bias compensation diode D1 may be used to set the voltage offset between the output of pulser-transformer stage 101 (e.g., labeled 125) and the voltage on the electrode (e.g., labeled 124) at the beginning of each burst to allow the required equilibrium to be reached. For example, charge may be transferred from bias capacitor C12 to bias compensation capacitor C15 at the beginning of each burst over multiple pulses (e.g., approximately 5-100 pulses) to establish the correct voltage in the circuit.

[0057] In some embodiments, the DC bias compensation circuit 104 may include one or more high voltage switches disposed across the bias compensation diode D1 and coupled to the power supply V1. In some embodiments, the high voltage switch may include multiple switches disposed in series to collectively switch the high voltage.

[0058] The high-voltage switch may be coupled in series with an inductor and / or a resistor. The inductor may limit the peak current through the high-voltage switch. The inductor may have an inductance of, for example, less than about 100 μH, such as about 250 μH, 100 μH, 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, etc. The resistor may, for example, shift power dissipation to the resistive output stage 102. The resistor may have a resistance of less than about 1000 ohms, less than 500 ohms, less than 250 ohms, less than 100 ohms, less than 50 ohms, less than 10 ohms, etc.

[0059] In some embodiments, the high voltage switch may include a snubber circuit.

[0060] In some embodiments, the high voltage switch may include multiple switches arranged in series to globally switch the high voltage. For example, the high voltage switch may include any of the switches described in U.S. Patent Application No. 16 / 178,565, entitled "High Voltage Switch with Isolated Power," filed November 1, 2018, which is incorporated herein in its entirety for all purposes.

[0061] In some embodiments, the high voltage switch may be open while the pulser-transformer stage 101 is pulsing and may be closed when the pulser-transformer stage 101 is not pulsing. When the high voltage switch is closed, for example, it may short out current across the bias compensation diode C15. Shorting this current may result in a bias between the wafer and the chuck of less than 2 kV, which may be within an acceptable range.

[0062] In some embodiments, the pulser-transformer stage 101 can generate pulses having high pulse voltages (e.g., greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), high pulse repetition frequencies (e.g., greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), fast rise times (e.g., rise times less than about 1 ns, less than 10 ns, less than 50 ns, less than 100 ns, less than 250 ns, less than 500 ns, less than 1,000 ns, etc.), fast fall times (fall times less than about 1 ns, less than 10 ns, less than 50 ns, less than 100 ns, less than 250 ns, less than 500 ns, less than 1,000 ns, etc.), and / or short pulse widths (pulse widths less than about 1,000 ns, less than 500 ns, less than 250 ns, less than 100 ns, less than 20 ns, etc.).

[0063] FIG. 2 illustrates exemplary waveforms generated by the nanosecond pulser system 100. In these exemplary waveforms, pulse waveform 205 may represent the voltage supplied by pulser-transformer stage 101. As shown, pulse waveform 205 produces pulses with qualities such as a high voltage (e.g., greater than approximately 4 kV as shown in the waveform), a fast rise time (e.g., less than approximately 200 ns as shown in the waveform), a fast fall time (e.g., less than approximately 200 ns as shown in the waveform), and a short pulse width (e.g., less than approximately 300 ns as shown in the waveform). Waveform 210 may represent the voltage at the wafer surface, represented in the circuit shown in FIG. 1 at a point between capacitors C2 and C3, or may represent the voltage across capacitor C3. Pulse waveform 215 represents the current flowing from pulser-transformer stage 101 to the plasma. The nanosecond pulser system 100 may or may not include diodes D1 and D2.

[0064] During the transient state (e.g., during the first few pulses not shown), the high voltage pulses from pulser-transformer stage 101 charge capacitor C2. Because the capacitance of capacitor C2 is large compared to the capacitances of capacitors C3 and / or C1, and / or because the pulse width is short, it may take several pulses from the high voltage pulser for capacitor C2 to become fully charged. Once capacitor C2 is charged, the circuit reaches a steady state, as shown by the waveforms in FIG. 2.

[0065] At steady state, when switch S1 is open, capacitor C2 charges and slowly dissipates through the resistive output stage 102, as indicated by the slightly elevated slope of waveform 210. While capacitor C2 is charged and switch S1 is open, the voltage at the wafer surface (the point between capacitors C2 and C3) becomes negative. This negative voltage may be the negative of the voltage of the pulses provided by pulser-transformer stage 101. For example, in the exemplary waveform shown in FIG. 2, the voltage of each pulse is approximately 4 kV, and the steady-state voltage at the wafer is approximately -4 kV. This creates a negative potential across the plasma (e.g., across capacitor C3), accelerating positive ions from the plasma to the wafer surface. While switch S1 is open, the charge on capacitor C2 slowly dissipates through the resistive output stage.

[0066] When switch S1 is closed, the voltage across capacitor C2 may reverse (the pulse from the pulser is high, as shown in pulse waveform 205) as capacitor C2 charges. Furthermore, the voltage at a point between capacitors C2 and C3 (e.g., the surface of the wafer) changes to approximately zero as capacitor C2 charges, as shown in waveform 210. Thus, the pulses from the high voltage pulser create a plasma potential (e.g., the potential in the plasma) that rises from a negative high voltage to zero and then back to a negative high voltage at a high frequency, with a fast rise time, a fast fall time, and / or a short pulse width.

[0067] In some embodiments, the action of the elements represented by the resistive output stage, resistive output stage 102, may rapidly discharge stray capacitance C1, allowing the voltage at the point between capacitors C2 and C3 to quickly return to a steady negative value of approximately −4 kV, as shown by waveform 210. The resistive output stage may allow the voltage at the point between capacitors C2 and C3 to exist for as little as % of the time, thus maximizing the time ions are accelerated into the wafer. In some embodiments, the components included within the resistive output stage may be specifically selected to optimize the time ions are accelerated into the wafer and to hold the voltage nearly constant during this time. Thus, for example, a short pulse with a fast rise time and a fast fall time may be useful, so that a long period of fairly uniform negative potential may exist.

[0068] A variety of other waveforms may be generated by the nanosecond pulser system 100.

[0069] FIG. 3 is a circuit diagram of a nanosecond pulser system 300 including a pulser-transformer stage 101 and an energy recovery circuit 305, according to some embodiments. The energy recovery circuit may, for example, replace the resistive output stage 102 shown in FIG. 1. In this example, the energy recovery circuit 305 may be disposed on or electrically coupled to the secondary side of the transformer T1. The energy recovery circuit 305 may, for example, include a diode 330 (e.g., a crowbar diode) across the secondary side of the transformer T1. The energy recovery circuit 305 may, for example, include a diode 310 and an inductor 315 (arranged in series) that can conduct current from the secondary side of the transformer T1 to charge a power source C7. The diode 310 and the inductor 315 may be electrically connected to the secondary side of the transformer T1 and the power source C7. In some embodiments, the energy recovery circuit 305 may include a diode 335 and / or an inductor 340 electrically coupled to the secondary side of the transformer T1. The inductor 340 may represent and / or include the stray inductance of the transformer T1.

[0070] When the nanosecond pulser is activated, current may charge load stage 106 (e.g., charging capacitor C3, capacitor C2, or capacitor C9). Some current may flow through inductor 155, for example, when the voltage on the secondary side of transformer T1 rises above the charging voltage of power supply C7. When the nanosecond pulser is turned off, current may flow from the capacitor in load stage 106 through inductor 315 to charge power supply C7 until the voltage across inductor 315 becomes zero. Diode 330 may prevent the capacitor in load stage 106 from ringing due to inductance within load stage 106 or inductance within DC bias compensation circuit 104.

[0071] Diode 310 may, for example, prevent charge from flowing from power supply C7 to a capacitor in load stage 106.

[0072] The value of inductor 315 may be selected to control the current fall time, and in some embodiments, inductor 315 may have an inductance value between 1 μH and 500 μH.

[0073] In some embodiments, the energy recovery circuit 305 may include an energy recovery switch that may be used to control the flow of current through the inductor 315. The energy recovery switch may be placed, for example, in series with the inductor 315. In some embodiments, the energy recovery switch may close when the switch S1 is open and / or is no longer pulsing to allow current flow from the load stage 106 back to the high voltage load C7.

[0074] In some embodiments, the energy regeneration switch may include a plurality of switches arranged in series to comprehensively open and close a high voltage. For example, the energy regeneration switch may include any switch described in U.S. Patent Application No. 16 / 178,565, entitled "High Voltage Switch with Isolated Power," filed on November 1, 2018, which is incorporated herein by reference in its entirety for all purposes.

[0075] In some embodiments, the nanosecond pulsar system 300 may generate waveforms similar to those shown in FIG. 2.

[0076] FIG. 4A is a side cutaway block diagram of a spatially-varying wafer bias power system 400 according to some embodiments, and FIG. 4B is a top block diagram. The side cutaway view shown in FIG. 4A is along line A shown in FIG. 4B. The spatially-varying wafer bias power system 400 includes two electrodes, a first electrode 415 and a second electrode 420. The wafer 405 may be disposed on a wafer platform 410 above both the first electrode 415 and the second electrode 420. The wafer platform 410 may include a dielectric material such as ceramic. The first electrode 415 may be disk-shaped with a diameter smaller than the diameter of either or both of the wafer platform 410 or the wafer 405. The second electrode 420 may have a donut shape with an aperture diameter slightly larger than the diameter of the first electrode 415 and an outer diameter substantially similar to the diameter of either or both of the wafer platform 410 or the wafer 405. The first electrode 415 may be disposed within the aperture of the second electrode 420.

[0077] In some embodiments, the gap between the first electrode 415 and the second electrode 420 may be less than about 0.1 mm, less than 1.0 mm, or less than 5.0 mm. In some embodiments, the space between the first electrode 415 and the second electrode 420 may be filled with air, vacuum, insulating gas, solid dielectric material, or other insulating material.

[0078] In some embodiments, the first electrode 415 and the second electrode 420 may have substantially the same thickness. In some embodiments, the first electrode 415 and the second electrode 420 may have different thicknesses.

[0079] In some embodiments, the second electrode 420 may have an area that is between 5% and 50% of the area of the wafer platform.

[0080] In some embodiments, the first electrode 415 and the second electrode 420 may comprise the same material or different materials.

[0081] In some embodiments, the first high-voltage pulser 425 may be coupled to the first electrode 415, and the second high-voltage pulser 430 may be coupled to the second electrode 420. For example, the first high-voltage pulser 425 and the second high-voltage pulser 430 may comprise the pulser-transformer stage 101 of the nanosecond pulser system 100.

[0082] In some embodiments, the first high-voltage pulser 425 and the second high-voltage pulser 430 may provide different pulses. For example, the peak voltage provided by the second high-voltage pulser 430 to the second electrode 420 may be different from the peak voltage provided by the first high-voltage pulser 425 to the first electrode 415. As another example, the pulse repetition frequency provided by the second high-voltage pulser 430 to the second electrode 420 may be different from the pulse repetition frequency provided by the first high-voltage pulser 425 to the first electrode 415. As another example, the ion current provided by the second high-voltage pulser 430 to the second electrode 420 may be different from the ion current provided by the first high-voltage pulser 425 to the first electrode 415.

[0083] In some embodiments, the first high-voltage pulsar 425 and the second high-voltage pulsar may supply substantially the same pulses. For example, the peak voltage supplied to the second electrode 420 by the second high-voltage pulsar 430 may be substantially the same as the peak voltage supplied to the first electrode 415 by the first high-voltage pulsar 425. As another example, the pulse repetition frequency supplied to the second electrode 420 by the second high-voltage pulsar 430 may be substantially the same as the pulse repetition frequency supplied to the first electrode 415 by the first high-voltage pulsar 425. As another example, the ion current supplied to the second electrode 420 by the second high-voltage pulsar 430 may be substantially the same as the ion current supplied to the first electrode 415 by the first high-voltage pulsar 425.

[0084] The first high-voltage pulsar 425 may include any or all of the components of the nanosecond pulsar system 100. The first high-voltage pulsar 425 may include any or all of the components of the nanosecond pulsar system 300. In some embodiments, the first high-voltage pulsar 425 may include any switch described in U.S. Patent Application No. 16 / 178,565, entitled "High Voltage Switch with Isolated Power," filed on November 1, 2018, which application is incorporated herein by reference in its entirety for all purposes. In some embodiments, the first high-voltage pulsar 425 may include an RF generator.

[0085] The second high-voltage pulsar 430 may include any or all of the components of the nanosecond pulsar system 100. The second high-voltage pulsar 430 may include any or all of the components of the nanosecond pulsar system 300. In some embodiments, the second high-voltage pulsar 430 may include any switch described in U.S. Patent Application No. 16 / 178,565, entitled "High Voltage Switch with Isolated Power," filed on November 1, 2018, which application is incorporated herein by reference in its entirety for all purposes. In some embodiments, the second high-voltage pulsar 430 may include an RF generator.

[0086] In some embodiments, the first high-voltage pulsar 425 and the second high-voltage pulsar 430 may supply separately controlled pulse bias voltages or separate pulse repetition frequencies, or pulses with a phase shift, such that the voltage pulse applied to the end of the wafer by the second electrode 420 is different from the voltage applied to the center of the wafer by the first electrode 415. The different voltages may generate different electric field profiles at the ends of the wafer compared to the center, for example, such that the electric field or bias voltage across the wafer 405 is uniform. This may, for example, optimize the yield of the wafer. In some embodiments, the second high-voltage pulsar 430 may operate at a lower voltage than the first high-voltage pulsar 425, for example, the second high-voltage pulsar 430 may operate at 5%, 10%, 15%, 20%, 25%, 30%, etc. of the voltage of the first high-voltage pulsar 425.

[0087] In some embodiments, the pulses supplied by the first high-voltage pulsar 425 may be controlled independently of the second high-voltage pulsar 430.

[0088] In some embodiments, the spatially varying wafer bias power system may generate a uniform electric field (e.g., a difference of less than about 5%, 10%, 15%, or 20%) or a uniform voltage across the upper surface of the wafer platform 410 or the wafer 405.

[0089] In some embodiments, the spatially varying wafer bias power system may generate a non-uniform electric field or non-uniform voltage across the upper surface of the wafer platform 410 or the wafer 405.

[0090] In some embodiments, the first high voltage pulsar 425 and the second high voltage pulsar 430 may be capacitively coupled with a capacitance between about 1 pF and about 100 nF.

[0091] In some embodiments, the first high voltage pulsar 425 and the second high voltage pulsar 430 may be connected. For example, the first high voltage pulsar 425 and the second high voltage pulsar 430 may include a single nanosecond pulsar having a voltage divider (e.g., resistive, inductive, or capacitive) that generates different voltages for the first electrode 415 and the second electrode 420. As another example, a single pulsar on the primary side of a transformer may be coupled to a plurality of loads (and energy recovery circuits, resistive output stages, or bias compensation circuits) coupled to different secondary windings on the secondary side of the transformer T2. The different secondary windings may have different numbers of turns to generate different voltages.

[0092] Although two electrodes are illustrated in FIG. 4A, any number of electrodes may be used with any number of nanosecond pulsars, depending on the embodiment. In some embodiments, the first electrode 415 or the second electrode 420 may include any geometric region under the wafer platform 410 having any geometric shape. Similarly, additional electrodes and nanosecond pulsars may be included, the additional electrodes may have any shape, and may be disposed at any position relative to the other electrodes and relative to the wafer platform.

[0093] In some embodiments, the leads from the first high-voltage pulser 425 to the first electrode 415 and the leads from the second high-voltage pulser 430 to the second electrode 420 may be grouped or bundled together. This bundling may, for example, allow the total stray capacitance to ground of the bundled leads to be smaller than if each lead were operated separately. This bundling may, for example, save power consumption. In some embodiments, the leads may be arranged in a coaxial configuration, a twin-lead configuration, or a twisted pair. In some embodiments, the stray capacitance from the output to ground may be less than about 100 pF, or less than about 1 nF, or less than about 10 nF, etc. In some embodiments, the stray inductance of the outputs may be less than about 100 nH, less than about 1 μH, less than about 10 μH, etc. In some embodiments, the capacitive coupling between each output may be less than about 100 pF, 1 nF, 10 nF, etc.

[0094] 5 is a block diagram of a spatially varying wafer bias power system 500 according to some embodiments. The spatially varying wafer bias power system 500 may include a first high voltage pulser 425 and a second high voltage pulser 430.

[0095] The wiring board 505 may be electrically coupled to the first high-voltage pulser 425 and the second high-voltage pulser 430 or additional high-voltage pulsers. In some embodiments, the wiring board 505 may provide a high DC voltage to the first high-voltage pulser 425 or the second high-voltage pulser 430, respectively. In some embodiments, the wiring board 505 may provide a trigger signal to the first high-voltage pulser 425 or the second high-voltage pulser 430. In some embodiments, the wiring board 505 may provide a low-voltage pulse to the first high-voltage pulser 425 or the second high-voltage pulser 430.

[0096] In some embodiments, the wiring substrate 505 may include a controller or a processor that includes one or more components of the computing system 900. In some embodiments, for example, an electric field on the surface of the wafer, the uniformity of the electric field, the voltage on the first electrode 415, the voltage on the second electrode 420, the voltage across one or more resistive output stages, or a resistor within one or more energy recovery circuits, one or more sensors for measuring the characteristics of the plasma chamber may be included. Based on the measurements from the sensors, the voltages, pulse widths, or pulse repetition frequencies of the first high voltage pulsar 425 and the second high voltage pulsar 430 can be adjusted.

[0097] For example, if the voltage on the second electrode 420 is measured and determined to be lower than the voltage on the first electrode 415, there may be an electrical non-uniformity on the surface of the wafer (e.g., a difference of less than about 5%, less than about 10%, less than about 15%, or less than about 20%). The controller may adjust the pulse width of the control pulse sent to the second high voltage pulsar 430, which may increase the voltage generated by the second high voltage pulsar 430 (e.g., by increasing the capacitive charging time), and thus may increase the electric field on the second electrode. The process may be repeated until the electric field across the surface of the wafer becomes uniform (e.g., within 10%, 15%, 20%, 25%, etc.).

[0098] As another example, the voltage across the first resistive output stage and the second resistive output stage may be measured. These voltages may correspond to the ion current flowing in the chamber. This current may be affected by the electrode voltage. If the ion current to the first electrode and the ion current to the second electrode are non-uniform or inconsistent (e.g., the difference exceeds 10%, 20%, or 30%), the controller may adjust the pulse width of the control pulse sent to either the first high voltage pulsar 425 or the second high voltage pulsar 430, which may increase the voltage generated by the nanosecond pulsar (e.g., by increasing the capacitive charging time), and thus may increase the electric field on the corresponding electrode.

[0099] In some embodiments, pulses from the first high-voltage pulser 425 and the second high-voltage pulser 430 may pass through the chamber interface substrate or bias compensation circuit 510 to the energy recovery circuit 525 and to the plasma chamber 535. The energy recovery circuit 525 may include, for example, the resistive output stage 102 of the nanosecond pulser system 100. As another example, the energy recovery circuit 525 may include the energy recovery circuit 305. As another example, the energy recovery circuit 525 may not be used. As another example, the energy recovery circuit 525 may be coupled to either or both of the first high-voltage pulser 425 or the second high-voltage pulser 430. In some embodiments, the plasma chamber 535 may include a plasma chamber, an etch chamber, a deposition chamber, etc. In some embodiments, the effective circuit of the plasma chamber 535 may include a load stage 106.

[0100] Although two high voltage pulsers are shown, any number may be used, for example, multiple ring electrodes may be coupled to multiple high voltage pulsers.

[0101] In some embodiments, the first high-voltage pulser 425 may generate pulses that are different from the pulses generated by the second high-voltage pulser 430. For example, the first high-voltage pulser 425 may provide a pulse output of at least 2 kV. In some embodiments, the second high-voltage pulser 430 may provide pulses of at least 2 kV pulse output that are the same as or different from the pulses provided by the first high-voltage pulser 425.

[0102] As another example, the first high-voltage pulser 425 may generate pulses having a first pulse repetition frequency, and the second high-voltage pulser 430 may generate pulses having a second pulse repetition frequency. The first pulse repetition frequency and the second pulse repetition frequency may be the same or different. The first pulse repetition frequency and the second pulse repetition frequency may be in phase or out of phase with each other.

[0103] As another example, the first high-voltage pulsar 425 may generate a first plurality of bursts having a first burst repetition frequency, and the second high-voltage pulsar 430 may generate a second plurality of bursts having a second burst repetition frequency. Each burst may include a plurality of pulses. The first burst repetition frequency and the second burst repetition frequency may be the same or different. The first burst repetition frequency and the second burst repetition frequency may have phases that match each other or may be out of phase.

[0104] In some embodiments, the first high-voltage pulsar 425 and the second high-voltage pulsar 430 may be water-cooled or dielectric-cooled.

[0105] FIG. 6 is a schematic diagram of a spatially-varying wafer bias system 600 according to some embodiments. The spatially-varying wafer bias system 600 may include a first high-voltage pulsar 425 coupled to a plasma chamber 535 and a second high-voltage pulsar 430.

[0106] In this example, the first high-voltage pulsar 425 includes a first resistive output stage 610 and a first bias capacitor 615. In some embodiments, the first resistive output stage 610 may not be used, and for example, an energy recovery circuit as shown in the nanosecond pulsar system 300 may be used.

[0107] In this example, the second high-voltage pulsar 430 includes a second resistive output stage 620 and a second bias capacitor 625. In some embodiments, the second resistive output stage 620 may not be used, and for example, an energy recovery circuit as shown in the nanosecond pulsar system 300 may be used.

[0108] A first electrode 415 and a second electrode 420 are disposed within the plasma chamber 535. In this example, the first electrode 415 is disk-shaped and is disposed within a central opening of the second electrode 420. A first high-voltage pulser 425 is electrically coupled to the first electrode 415, and a second high-voltage pulser 430 is electrically coupled to the second electrode 420. In some embodiments, a stray coupling capacitance 630 may exist between the first high-voltage pulser 425 and the second high-voltage pulser 430. The stray coupling capacitance 630 may be, for example, less than about 100 pF, less than about 1 nF, less than about 10 nF, etc.

[0109] FIG. 7 is a schematic diagram of a spatially varying wafer bias system 700 according to some embodiments. In this example, the spatially varying wafer bias system 700 utilizes multiple isolated secondary windings to provide different voltages on two different wafer spatial regions. The spatially varying wafer bias system 700 includes a single high-voltage pulser 705. The single high-voltage pulser 705 may include the pulser-transformer stage 101 shown in FIG. 1 or 3. In this example, two independent sets of secondary windings may be wound around a transformer T1. The first secondary winding 710 may be electrically coupled to the first resistive output stage 610 and the first bias capacitor 615 to form a first electrode channel. The second secondary winding 715 may be electrically coupled to the second resistive output stage 620 and the second bias capacitor 625 to form a second electrode channel. In some embodiments, a stray coupling capacitance 630 may exist between the first electrode channel and the second electrode channel. The stray coupling capacitance 630 may be, for example, less than about 100 pF, less than about 1 nF, less than about 10 nF, and so on.

[0110] In some embodiments, a first energy recovery circuit (e.g., energy recovery circuit 305) may be used in place of first resistive output stage 610, and a second energy recovery circuit (e.g., energy recovery circuit 305) may be used in place of second resistive output stage 620. The first energy recovery circuit and the second energy recovery circuit may be arranged in parallel.

[0111] The voltages on the first electrode 415 and the second electrode 420 may depend on the number of turns of the first secondary winding and the second secondary winding.

[0112] FIG. 8 is a schematic diagram of a spatially varying wafer bias system 800 according to some embodiments. In this example, the spatially varying wafer bias system 800 uses a voltage divider to supply different voltages on two different wafer spatial regions. The spatially varying wafer bias system 800 includes a single high voltage pulsar 805 and a voltage divider 810. The voltage divider 810 may include a plurality of resistors and capacitors. The values of the resistors and capacitors may be selected to provide a voltage ratio between the voltage of the pulse supplied to the first electrode channel that supplies the pulse to the first electrode 415 and the voltage of the pulse supplied to the second electrode channel that supplies the pulse to the second electrode 420.

[0113] The first electrode channel may include a first resistive output stage 610 and a first bias capacitor 615. The second electrode channel may include a second resistive output stage 620 and a second bias capacitor 625.

[0114] In some embodiments, there may be a stray coupling capacitance 630 between the first electrode channel and the second electrode channel. The stray coupling capacitance 630 may be, for example, less than about 100 pF, less than about 1 nF, less than about 10 nF, etc.

[0115] In some embodiments, a first energy recovery circuit (e.g., energy recovery circuit 305) may be used instead of the first resistive output stage 610, and a second energy recovery circuit (e.g., energy recovery circuit 305) may be used instead of the second resistive output stage 620. The first energy recovery circuit and the second energy recovery circuit may be arranged in parallel.

[0116] Unless otherwise specified, the term "substantially" means within 5% or 10% of the recited value, or within manufacturing tolerances. Unless otherwise specified, the term "about" means within 5% or 10% of the recited value, or within manufacturing tolerances.

[0117] The computing system 900 shown in FIG. 9 can be used to implement any embodiment of the present invention. As another example, the computing system 900 can be used to perform any of the computations, identifications, and / or determinations described herein. The computing system 900 includes hardware elements that can be electrically coupled via bus 905 (or communicate in other suitable ways when appropriate). The hardware elements can include, without limitation, one or more processors 910 including one or more general-purpose processors and / or one or more special-purpose processors (e.g., digital signal processing chips, graphics acceleration chips, and / or the like), one or more input devices 915 that can include, without limitation, a mouse, a keyboard, and / or the like, and one or more output devices 920 that can include, without limitation, a display device, a printer, and / or the like.

[0118] Computing system 900 may further include (and / or be able to communicate with) one or more storage devices 925, which may include, but are not limited to, local and / or network-accessible storage and / or solid-state storage devices such as, but not limited to, disk drives, drive arrays, optical storage devices, random access memory (“RAM”) and / or programmable, flash-updatable read-only memory (“ROM”), and / or the like. Computing system 900 may also include a communications subsystem 930, which may include, but is not limited to, a modem, a network card (wireless or wired), an infrared communications device, a wireless communications device and / or chipset (e.g., a Bluetooth device, an 802.6 device, a Wi-Fi device, a WiMax device, a cellular communications facility, etc.), and / or the like. Communications subsystem 930 may permit data to be exchanged with a network (such as the networks described below, to name one example) and / or any other device described herein. In many embodiments, the computing system 900 further includes a working memory 935, which may include a RAM or ROM device, as described above.

[0119] The computing system 900 may further include software elements shown presently located in working memory 935, including other code, such as an operating system 940 and / or one or more application programs 945, which may include computer programs of the present invention and / or may be designed to implement methods of the present invention as described herein and / or to constitute systems of the present invention. For example, one or more of the procedures described with respect to the method(s) above may be implemented as code and / or instructions executable by a computer (and / or a processor within a computer). Sets of these instructions and / or code may be stored on a computer-readable storage medium, such as the storage device(s) 925 described above.

[0120] In some cases, the storage medium may be incorporated within the computing system 900 or may communicate with the computing system 900. In other embodiments, the storage medium may be separate from the computing system 900 (e.g., a removable medium such as a compact disk), and / or may be provided as an installation package, such that the storage medium can be used to program a general-purpose computer using the instructions / code stored therein. These instructions may take the form of executable code that is executable by the computing system 900 and / or in the form of source and / or installable code, which, when compiled and / or installed on the computing system 900 (e.g., using any of a variety of generally available compilers, installation programs, compression / decompression utilities, etc.), takes the form of executable code.

[0121] Numerous specific details are set forth herein to provide a complete understanding of the claimed subject matter. However, one of ordinary skill in the art would understand that the claimed subject matter may be practiced without these specific details. In other instances, well-known methods, devices, or systems may not be described in detail so as not to obscure the claimed subject matter.

[0122] Some portions are presented as algorithms or symbolic representations of operations on data bits or binary digital signals stored in a computing system memory, such as a computer memory. Descriptions or representations of these algorithms are examples of techniques used by those skilled in the data processing arts to convey the essence of their work to other artisans. An algorithm is a self-consistent series of operations or similar processes that lead to a desired result. In this context, operations or processes include physical operations on physical quantities. Typically, although not necessarily, such quantities may take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, or otherwise operated on. It has proven convenient, mainly for reasons of common usage, to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals, etc. However, it should be understood that all of these terms and similar terms should be associated with appropriate physical quantities and are merely convenient labels. Unless otherwise specified, discussions using terms such as "processing", "computing", "calculating", "determining", and "identifying" throughout this specification refer to the operation or transformation of data represented as physical electronic or magnetic quantities within the memory, registers, or other information storage devices, transmission devices, or display devices of a computing platform, by one or more computers or similar electronic computing devices or apparatuses, such as the operation or process of a computing device.

[0123] The system(s) discussed herein are not limited to any particular hardware architecture or configuration. A computing device may include any suitable arrangement of components that provide results conditioned on one or more inputs. Suitable computing devices range from general-purpose computing devices to specialized computing devices that implement one or more embodiments of the present subject matter, including general-purpose microprocessor-based computer systems that access stored software that programs or configures the computing device. Any suitable programming, scripting, or other type or combination of languages may be used to implement the teachings contained herein in software used in programming or configuring a computing device.

[0124] Embodiments of the methods disclosed herein may be performed during operation of such a computing device. The order of the blocks presented in the above examples may be changed, e.g., the blocks may be reordered, combined, and / or divided into sub-blocks. Certain blocks or processes may be performed in parallel.

[0125] The use of "adapted" or "configured" herein is intended to be open and inclusive and does not exclude devices adapted or configured to perform additional tasks or steps. Furthermore, the use of "based on" is intended to be open and inclusive in the sense that a process, step, calculation, or other action "based on" one or more stated conditions or values may in fact be based on additional conditions or values beyond those conditions or values. The headings, lists, and numbers contained herein are for ease of description and are not intended to be limiting.

[0126] The subject matter of the present disclosure is described in detail with respect to specific embodiments thereof, but it will be understood by those skilled in the art that, having obtained the above understanding, such embodiments can be readily modified, deformed, and equivalents thereof can be readily created. Therefore, the present disclosure is presented for purposes of illustration rather than limitation, and does not exclude including such modifications, deformations, and / or additions, which will be apparent to those skilled in the art. [Appendix 1] 1. A power system having a plasma load, comprising: a first high voltage pulser that outputs a first plurality of pulses having a first voltage greater than about 1 kV, a first pulse width less than about 1 μs, and a first pulse repetition frequency greater than about 20 kHz; a second high voltage pulser that outputs a second plurality of pulses having a second voltage greater than about 1 kV, a second pulse width less than about 1 μs, and a second pulse repetition frequency greater than about 20 kHz; a chamber; a first electrode disposed within the chamber and electrically coupled to the first high voltage pulser; a second electrode disposed within the chamber adjacent the first electrode and electrically coupled to the second high voltage pulser; A power system with [Appendix 2] 2. The system of claim 1, wherein the chamber includes a wafer and / or a plasma capacitively coupled to the first electrode and the second electrode with a capacitance between 10 pF and 1 μF. [Appendix 3] 10. The system of claim 1, wherein the electric field across the surface of the wafer is uniform to within 25%. [Appendix 4] 2. The system of claim 1, wherein a coupling capacitance between the first electrode and the corresponding portion of the wafer exceeds 100 pF, and a capacitance between the second electrode and the corresponding portion of the wafer exceeds 100 pF. [Appendix 5] 10. The system of claim 1, wherein the chamber contains a plasma of ions that are accelerated onto the wafer. [Appendix 6] 10. The system of claim 1, wherein the first high-voltage pulser generates an electrode voltage on the first electrode greater than about 1 kV and the second high-voltage pulser generates an electrode voltage on the second electrode greater than about 1 kV. [Appendix 7] 2. The system of claim 1, wherein the ratio of the first voltage to the second voltage is less than 2:1, or the ratio of the second voltage to the first voltage is less than 2:1. [Appendix 8] 2. The system of claim 1, wherein one or both of the first electrode and the second electrode are axially symmetric. [Appendix 9] 2. The system of claim 1, wherein the first electrode has a first planar surface, the second electrode has a second planar surface, and the second planar surface is 25% of the sum of the first planar surface and the second planar surface. [Appendix 10] The system according to appended claim 1, wherein both the first high-voltage pulsar and the second high-voltage pulsar include a resistive output stage. [Appended claim 11] The system according to appended claim 1, wherein both the first high-voltage pulsar and the second high-voltage pulsar include an energy recovery circuit. [Appended claim 12] The system according to appended claim 1, wherein the parameters of the first plurality of pulses are controlled independently of the parameters of the second plurality of pulses. [Appended claim 13] The system according to appended claim 1, wherein the phases of the first pulse repetition frequency and the second pulse repetition frequency coincide with each other. [Appended claim 14] The system according to appended claim 1, wherein the coupling capacitance between the first electrode and the second electrode is less than about 10 nF. [Appended claim 15] The first electrode has a disc shape, a central axis, and an outer diameter, and the second electrode has a disc shape with a central opening, and the first electrode is disposed within the central opening, and further has a central axis aligned with the central axis of the first electrode, an opening diameter, and an outer diameter. The system according to appended claim 1. [Appended claim 16] A system comprising a wafer platform, and a first electrode, wherein the first electrode has a disc shape, a central axis, and an outer diameter, and further comprises a second electrode, wherein the second electrode has a disc shape with a central opening, and the first electrode is disposed within the central opening, and further has a central axis aligned with the central axis of the first electrode, an opening diameter, and an outer diameter, and further comprises a first high-voltage pulsar electrically coupled to the first electrode and generating pulses with a pulse repetition rate exceeding 10 kHz and a pulse voltage exceeding 5 kV, and a second high-voltage pulsar electrically coupled to the second electrode and generating pulses with a pulse repetition rate exceeding 10 kHz and a pulse voltage exceeding 5 kV. The system provided with these. [Appended claim 17] The system according to appended claim 16, wherein the wafer platform has an outer diameter substantially similar to the outer diameter of the second electrode. [Appended claim 18] The system according to appended claim 16, wherein the second high-voltage pulsar supplies pulses having an amplitude that is a fraction of the amplitude of the pulses supplied by the first high-voltage pulsar. [Appended claim 19] The system according to appended claim 16, wherein the second high-voltage pulsar supplies pulses having a pulse repetition frequency that is a fraction of the pulse repetition frequency of the pulses supplied by the first high-voltage pulsar. [Appended claim 20] 17. The system of claim 16, further comprising: a first resistive output stage coupled to the first high-voltage pulser and the first electrode; and a second resistive output stage coupled to the second high-voltage pulser and the second electrode. [Appendix 21] 17. The system of claim 16, further comprising a bias compensation circuit coupled to the first high voltage pulser and the first electrode. [Appendix 22] 17. The system of claim 16, further comprising a ring of insulating material disposed between the first electrode and the second electrode. [Appendix 23] 17. The system of claim 16, wherein the wafer platform comprises a dielectric material or a ceramic material. [Appendix 24] 1. A method comprising: pulsing a first high voltage pulser coupled to a first electrode in the plasma chamber, the first high voltage pulser pulsing at a first voltage greater than about 1 kV, a first pulse repetition frequency greater than about 20 kHz, and a first pulse width; pulsing a second high voltage pulser coupled to a second electrode in the plasma chamber, the second high voltage pulser pulsing at a second voltage greater than about 1 kV, a second pulse repetition frequency greater than about 20 kHz, and a second pulse width, the first electrode and the second electrode being positioned below the wafer; measuring a parameter corresponding to a physical phenomenon occurring within the plasma chamber; adjusting at least one of the second voltage, the second pulse repetition frequency, and the second pulser width based on the measured parameter; The method includes: [Appendix 25] 25. The method of claim 24, wherein the physical phenomenon occurring in the plasma chamber corresponds to a uniformity of an electric field across a surface of the wafer. [Appendix 26] 25. The method of claim 24, wherein the physical phenomenon occurring in the plasma chamber corresponds to a uniformity of ion current across a surface of the wafer. [Appendix 27] 25. The method of claim 24, wherein the parameter is a current through a resistor of the first high voltage pulser.

Explanation of Symbols

[0127] 100, 300 nanosecond pulsar system 101 pulsar - transformer stage 102 resistance output stage 103 lead stage 104 DC bias compensation circuit 106 load stage 305, 525 energy recovery circuit 310, 330 diode 315, 340 inductor 400, 500 wafer bias power system 405 wafer 410 wafer platform 415 first electrode 420 second electrode 425 first high - voltage pulsar 430 second high - voltage pulsar 505 wiring board 510 bias compensation circuit 525 energy recovery circuit 535 plasma chamber 600, 700, 800 Wafer Bias System 610 First Resistor Output Stage 615 First bias capacitor 620 Second Resistor Output Stage 625 Second bias capacitor 630 Stray Coupling Capacitance 705, 805 High Voltage Pulser 710 First secondary winding 715 Secondary Winding 810 Voltage Divider 900 Computing Systems 925 Storage Devices 930 Communication Subsystem 935 Working Memory C5 snubber capacitor D2 Freewheeling diode D4 snubber diode S1 Solid State Switch R3 snubber resistor

Claims

1. Comprising a nanosecond pulsar, wherein the nanosecond pulsar, a pulsar input, a high-voltage DC power supply, one or more solid-state switches coupled to the high-voltage DC power supply and the pulsar input, wherein the one or more solid-state switches switch the high-voltage DC power supply based on an input supplied by the pulsar input, the one or more solid-state switches; one or more transformers electrically coupled to the one or more solid-state switches; a pulsar output coupled to the one or more transformers, which outputs a high-voltage pulse waveform having an amplitude greater than about 2 kV, a duty cycle, and a pulse repetition frequency greater than about 1 kHz based on the pulsar input, wherein the high-voltage pulse waveform includes a plurality of high-voltage pulses having a pulse width of less than 1 μs, the pulsar output; a control system coupled to the nanosecond pulsar at a measurement point and coupled to the pulsar input, wherein the control system measures a voltage at the measurement point, and the control system is configured to adjust the input so as to cause a change in the amplitude of the pulsar output, the pulse repetition frequency, and the duty cycle based on the measured voltage, and the measurement point includes a point between the one or more transformers and the pulsar output, the control system; comprising; a nanosecond pulsar system.

2. The nanosecond pulsar system further comprises an electrode coupled to the pulsar output, wherein the measurement point is the electrode, The nanosecond pulsar system according to claim 1.

3. The nanosecond pulsar system according to claim 1, further comprising one or more transformers coupled to the one or more switches.

4. The control system measures the pulse repetition frequency at the measurement point and adjusts the pulse repetition frequency of the input pulse based on the measured pulse repetition frequency. The nanosecond pulsar system according to claim 1.

5. The input pulse includes a first burst including a first plurality of low-voltage pulses, each of the first plurality of low-voltage pulses having a first pulse width, the input pulse includes a second burst including a second plurality of low-voltage pulses, each of the second plurality of low-voltage pulses having a second pulse width, the second pulse width is greater than the first pulse width, The nanosecond pulsar system according to claim 1.

6. The control system receives input data specifying a voltage and a pulse repetition frequency corresponding to a desired high-voltage pulse waveform, compares the output pulsar waveform measured at the measurement point with the desired high-voltage pulse waveform, and determines an adjustment of the pulsar input for generating the desired high-voltage pulse waveform. The nanosecond pulsar system according to claim 1.

7. The nanosecond pulsar system according to claim 1, wherein the control system includes a voltage divider that reduces the high-voltage pulse waveform to 1 / 1000.

8. The nanosecond pulsar system according to claim 1, wherein the control system includes an analog-to-digital converter that converts the measured high-voltage pulse waveform into a digital signal.

9. The nanosecond pulsar system according to claim 1, further comprising a metal shield disposed between the nanosecond pulsar and the control system.

10. The nanosecond pulsar system according to claim 1, wherein the nanosecond pulsar includes a resistive output stage, and the measurement point is across a resistor of the resistive output stage.

11. A nanosecond pulsar having a pulsar output that outputs a high-voltage pulse waveform including a plurality of bursts, each burst including a plurality of pulses having an amplitude greater than 2 kV, a pulse width less than 1 μs, and a pulse repetition frequency greater than 1 kHz, the nanosecond pulsar, and a control system that controls a plurality of characteristics of the high-voltage pulse waveform, including the number of pulses, the pulse repetition frequency, the pulse width, and the pulse voltage within each burst. The control system controls the plurality of characteristics of the high-voltage pulse waveform in response to a plasma processing recipe. The plasma processing recipe includes a plurality of stages, each stage being associated with an ion current, a chamber pressure, and a gas mixture. The high-voltage pulse waveform includes a first burst including a first plurality of pulses, each of the first plurality of pulses having a first pulse width. The high-voltage pulse waveform includes a second burst including a second plurality of pulses, each of the second plurality of pulses having a second pulse width. The second pulse width is greater than the first pulse width. Nanosecond pulsar system. **Claim 12**: The nanosecond pulsar system according to claim 11, wherein the control system controls at least one characteristic of the high-voltage pulse waveform with a resolution of less than about 1 μs. **Claim 13**: The nanosecond pulsar system according to claim 11, wherein the control system controls the period between pulses with an accuracy of less than about 10 μs. **Claim 14**: The nanosecond pulsar system according to claim 11, wherein the control system controls the number of characteristics of the high-voltage pulse waveform in real time. **Claim 15**: The nanosecond pulsar includes a transformer and an output for outputting the high-voltage pulse waveform. The control system is coupled to the nanosecond pulsar at a point between the transformer and the pulsar output. The nanosecond pulsar system according to claim 11. **Claim 16**: A nanosecond pulsar having a pulsar output that outputs a high-voltage pulse waveform including a plurality of pulses having an amplitude greater than 2 kV, a pulse width of less than 1 μs, and a pulse repetition frequency greater than 1 kHz; an electrode in a plasma chamber; a measurement point located at or near the electrode; a sensor coupled to the measurement point and providing an electronic sensor signal representative of a voltage pulse waveform generated at the measurement point; a control system coupled to the sensor and the nanosecond pulsar, the control system controlling the characteristics of the high-voltage pulse waveform in response to the electronic sensor signal. The high-voltage pulse waveform includes a first burst having a first plurality of pulses, each of the first plurality of pulses having a first pulse width. The high-voltage pulse waveform includes a second burst having a second plurality of pulses, each of the second plurality of pulses having a second pulse width. The second pulse width is greater than the first pulse width. The control system controls the pulsar output in response to a plasma processing recipe, the plasma processing recipe including a plurality of stages, each stage being associated with an ion current, a chamber pressure, and a mixed gas. Nanosecond pulsar system.

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