Semiconductor device and power conversion device

Abstract

To provide a semiconductor device in which the tilt of an electrode plate on a semiconductor element is suppressed.SOLUTION: A semiconductor device comprises: an insulated substrate 2; a semiconductor element 1 joined onto the insulated substrate 2 via first joint material 9; a plurality of support wires which are in contact with the semiconductor element 1 and an electrode plate 7, between the semiconductor element 1 and the electrode plate 7 provided above the semiconductor element 1; and second joint material 12 which is provided on the semiconductor element 1 and joins the semiconductor element 1 and the electrode plate 7 together.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device Place and a power conversion device.

Background Art

[0002] In recent years, in the fields of vehicles, industrial machines, and consumer devices, semiconductor devices capable of high-voltage and high-current operation have been demanded. Further, in a semiconductor device that operates at high voltage and high current, since the semiconductor elements mounted thereon become hot due to their own heat generation, high heat dissipation is also required. Therefore, a semiconductor device in which an electrode plate is bonded onto a semiconductor element has been proposed. For example, the semiconductor device of Patent Document 1.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, the semiconductor device of Patent Document 1 does not have a configuration in consideration of suppressing the inclination of the electrode plate on the semiconductor element, and there is a problem that the electrode plate may be inclined.

[0005] The present disclosure has been made to solve the above problems, and an object thereof is to obtain a semiconductor device capable of suppressing the inclination of an electrode plate on a semiconductor element.

Means for Solving the Problems

[0006] The semiconductor device according to the present disclosure is A circuit pattern, an insulating member provided below the circuit pattern, a semiconductor element joined to the circuit pattern via a bonding material, an electrode plate provided above the circuit pattern and the semiconductor element, a plurality of support wires that contact the circuit pattern and the electrode plate between the circuit pattern and the electrode plate, and a second bonding material provided on the semiconductor element for joining the semiconductor element and the electrode plate. The circuit pattern or the electrode plate has an insulating material on its surface, and the support wires are via the insulating material. characterized by the following.

Effects of the Invention

[0007] According to the semiconductor device of the present disclosure, the inclination of the electrode plate on the semiconductor element can be suppressed by supporting the electrode plate with a plurality of support wires.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are schematically shown, the size and the mutual relationship of the positions can be changed. In the following description, the same or corresponding components may be given the same reference numerals, and repeated descriptions may be omitted.

[0010] In the following description, terms such as "up", "down", "front", "back", "left", "right", "side", etc., which mean specific positions and directions, may be used. However, these terms are used for convenience in order to facilitate understanding of the content of the embodiments, and do not limit the positions and directions during implementation.

[0011] <Embodiment 1> The semiconductor device 50 in Embodiment 1 will be described. FIG. 1 is a plan view showing the semiconductor device 50 of Embodiment 1.

[0012] As shown in FIG. 1, eight cylindrical metal bushings 10 are provided at the left and right ends of a rectangular case 3 in a plan view on the surface of the case 3. The metal bushing 10 is formed with a through hole so that a bolt or the like can be inserted. For example, the semiconductor device 50 is fixed to a heat sink or the like by bolts. When the semiconductor device 50 is fixed to a heat sink or the like, it may be fastened with screws via the metal bushing 10 and a washer. The material of the metal bushing 10 may be any metal such as copper or iron, but a metal with good workability and low material cost such as brass or aluminum is preferable. The case 3 is a case 3 in which the metal bushing 10 is embedded and insert-molded, but an outsert molding in which the metal bushing 10 is fixed by press-fitting into a through hole penetrating the case 3 may also be used.

[0013] The metal bushings 10 are provided in one row each on the left and right of the case 3, and the row of metal bushings 10 provided on the left side of the case 3 and the row of metal bushings 10 provided on the right side of the case 3 are arranged in two parallel rows. Also, the plurality of metal bushings 10 are arranged at equal intervals within the row. Note that the metal bushings 10 may not be provided, but if the metal bushings 10 are provided, two or more are sufficient, and of course, they are not limited to eight. It is also possible to provide only one metal bushing 10 at each of the four corners of the case 3. Also, the respective metal bushings 10 do not have to be arranged parallel to each other and at equal intervals.

[0014] The electrodes 5a, 5b, and 5c are electrodes 5 for electrically connecting the semiconductor device 50 and an external device, and are provided so as to be exposed from the surface of the case 3. The electrode 5a is the P terminal of the semiconductor device 50, the electrode 5b is the N terminal of the semiconductor device 50, and DC power is input from an external device such as a power supply device to the semiconductor device 50 via the P terminal and the N terminal. The electrode 5c is the output terminal of the semiconductor device 50, and the DC power input from the electrodes 5a and 5b is power-converted by the semiconductor device 50 and output to a load device, which is an external device, via the electrode 5c. The electrodes 5a and 5b are respectively provided on parallel sides facing the electrode 5c on the surface of the case 3, and it is desirable that they be provided on a side orthogonal to the side on which the rows of the metal bushes 10 are provided on the surface of the case 3. Note that the electrodes 5a and 5b do not necessarily have to be provided on parallel sides facing the electrode 5c on the surface of the case 3, nor do they have to be provided orthogonally to the side on which the rows of the metal bushes 10 are provided. Therefore, they may be provided on the side on which the rows of the metal bushes 10 are provided. Also, although the electrodes 5a, 5b, and 5c are described as being the P terminal, the N terminal, and the output terminal respectively, and the case where there are three electrodes 5 is described, when the N terminal also serves as the output terminal, the number of electrodes 5 may be two. Note that the number of electrodes 5 may be two or more.

[0015] The signal terminal 6 is a terminal used for inputting and outputting electrical signals between the semiconductor device 50 and an external device. The signal terminal 6 is provided so as to be exposed from the sealing material 4. Note that the signal terminal 6 may be provided on the surface of the case 3. Also, the number of signal terminals 6 may be one or more, and of course, it is not limited to six. As shown in FIG. 1, the signal terminals 6 are provided between the respective rows of the metal bushes 10 provided on the left and right of the case 3, and the signal terminals 6 are respectively arranged in parallel with the row of the metal bushes 10 provided on the left side of the case 3 and the row of the metal bushes 10 provided on the right side of the case 3. Note that the respective signal terminals 6 are arranged parallel to each other, but they do not necessarily have to be arranged parallel. Also, the signal terminals 6 are arranged at equal intervals from each other, but they do not necessarily have to be arranged at equal intervals.

[0016] FIG. 2 is a cross-sectional view showing a semiconductor device 50 according to Embodiment 1 of the present disclosure. FIG. 2 is a cross-sectional view taken along the dashed line A-A of the semiconductor device 50 shown in FIG. 1. FIGS. 3 and 4 show cross-sectional views of the semiconductor device 50 as modified examples. As shown in FIG. 2, the semiconductor device 50 includes a semiconductor element 1 (1a, 1b), an insulating substrate 2, a case 3, a sealing material 4, an electrode 5, a signal terminal 6, an electrode plate 7, a metal bush 10, and a support wire 11.

[0017] The semiconductor element 1 (1a, 1b) may be a switching element or a diode. For example, an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a reverse conducting IGBT (RC-IGBT), etc. may be used, and a diode or the like may be used for the reflux element. Note that the number of semiconductor elements 1 is not naturally limited to one, and two or more may be used.

[0018] The insulating substrate 2 is composed of a metal plate 2a, an insulating member 2b, and a circuit pattern 2c. The semiconductor element 1 is joined to the circuit pattern 2c via solder, which is the first joining material 9. The insulating member 2b is provided on the metal plate 2a, and the insulating member 2b and the metal plate 2a are joined by, for example, a brazing material or a sintered material. The circuit pattern 2c is provided on the insulating member 2b, and the insulating member 2b and the circuit pattern 2c are joined by, for example, a brazing material or a sintered material. The metal plate 2a and the circuit pattern 2c may be made of any metal, and for example, they are formed of copper. The metal plate 2a is a heat sink that dissipates the heat generated by the semiconductor element 1, and the circuit pattern 2c forms the electrical circuit of the semiconductor device 50. The insulating member 2b only needs to ensure electrical insulation from the semiconductor element 1, and for example, it may be formed of an inorganic ceramic material or a resin material. Although the insulating substrate 2 has been described as being integrated with the metal plate 2a, the insulating member 2b, and the circuit pattern 2c, the metal plate 2a and the insulating member 2b may be provided as separate components without being integrally included in the insulating substrate 2.

[0019] The electrode plate 7 is formed of copper (Cu). The electrode plate 7 is disposed on the semiconductor element 1 via the second joining material 12 and the support wire 11, and the second joining material 12 joins the surface electrode of the semiconductor element 1 (for example, the emitter electrode in the case of an IGBT, or the anode electrode in the case of a diode) and the lower surface of the electrode plate 7. Note that the second joining material 12 only needs to be conductive, and for example, a brazing material such as silver paste or solder may be used. Also, the lower surface of the electrode plate 7 is arranged not only to face the surface electrode of the semiconductor element 1 but also to face the surface of the insulating substrate 2. That is, the semiconductor element 1, the insulating substrate 2, and the electrode plate 7 are arranged so as to be parallel to each other.

[0020] As shown in FIG. 1, the electrode 5 includes an electrode 5a which is the P terminal of the semiconductor device 50, an electrode 5b which is the N terminal of the semiconductor device 50, and an electrode 5c which is the output terminal of the semiconductor device 50. One end of the electrode 5 is electrically connected to the semiconductor element 1 via an electrode plate 7, a circuit pattern 2c, or a conductive wire 13, etc., and the other end is used for electrical connection with an external device of the semiconductor device 50. Although not shown, the electrode 5 and the electrode plate 7 may be joined via a joining material such as solder, or may be joined by solid-phase joining such as ultrasonic vibration.

[0021] One end of the signal terminal 6 is electrically connected via a control electrode, a circuit pattern 2c, or a conductive wire 13, etc. on the surface of the semiconductor element 1, and the other end is used for input / output of an electrical signal with an external device of the semiconductor device 50. The circuit pattern 2c may or may not be passed through. Also, the electrode 5 and the signal terminal 6 only need to be conductive, for example, they may be made of copper. Note that the control electrode may be provided in addition to the gate electrode for on / off control of the semiconductor element 1. For example, a current sense electrode or a Kelvin emitter electrode may be provided. The current sense electrode is an electrode for detecting the current flowing in the cell region of the semiconductor device 50, and the Kelvin emitter electrode is an electrode for measuring the temperature of the semiconductor device 50. Therefore, a plurality of signal terminals 6 may be provided corresponding to the control electrodes.

[0022] In FIG. 2, the electrode 5 and the signal terminal 6 have been described respectively. As a modification, the electrode 5 may be provided integrally formed with the electrode plate 7, or the signal terminal 6 may have an insert case structure integrated with the case 3. For example, FIG. 3 shows a modification of the semiconductor device 50 in which the electrode 5 and the electrode plate 7 in FIG. 2 are integrally formed, and the signal terminal 6 and the case 3 are integrated. In FIG. 3, one end of the electrode plate 7 is electrically connected to the semiconductor element 1, and the other end is used for electrical connection with an external device of the semiconductor device 50. The signal terminal 6 has a part of the terminal embedded inside the case 3, one end is electrically connected to the semiconductor element 1, and the other end is used for input / output of an electrical signal with an external device of the semiconductor device 50.

[0023] The semiconductor element 1 and the insulating substrate 2 are surrounded by a case 3. The case 3 is fixed via an adhesive 8 to the end of the insulating member 2b. The adhesive 8 is provided on four sides of the insulating member 2b corresponding to the shape of the rectangular case 3 in order to fix the rectangular case 3 in plan view. Note that the adhesive 8 may be provided so that the sealing material 4 does not leak from between the insulating substrate 2 and the case 3 when the case 3 is filled with the sealing material 4 as a result of the connection between the insulating substrate 2 and the case 3. Also, although the insulating member 2b and the case 3 are fixed by the adhesive 8, the metal plate 2a or the circuit pattern 2c may be fixed to the case 3 with the adhesive 8. The case 3 is formed of an insulator such as PPS (Poly Phenylene Sulfide Resin).

[0024] The semiconductor element 1, the insulating substrate 2, the electrodes 5, the signal terminals 6, the conductive wires 13, etc. surrounded by the case 3 are covered with a sealing material 4. The end portions of the electrodes 5 and the signal terminals 6 are exposed from the sealing material 4 for connection to external devices of the semiconductor device 50. Note that in FIG. 2, the case 3, the electrodes 5, and the signal terminals 6 are described as an outset case structure in which the case 3 is fixed to the electrodes 5 and the signal terminals 6 by press-fitting or screwing. However, an insert case structure in which the electrodes 5 and the signal terminals 6 are embedded inside the case 3 and the electrodes 5, the signal terminals 6, and the case 3 are integrated may also be used. For example, in FIG. 3, as described above, it is an insert case structure in which the signal terminal 6 and the case 3 are integrated. Also, the back surface of the insulating substrate 2 is exposed from the sealing material 4 because it is cooled by a heat sink or the like. The sealing material 4 is not particularly limited as long as it is a material having insulating properties. For example, silicone gel or an epoxy-based resin may be used, or a direct potting resin for sealing with a liquid epoxy resin or the like may be used. Note that in the case of direct potting resin, transfer molding, or the like, a lid, a case 3, or the like may not be provided on the upper portion of the sealing material 4.

[0025] The support wire 11 is provided on the semiconductor element 1 after the semiconductor element 1 is joined to the insulating substrate 2 via the first bonding material 9. A plurality of support wires 11 are provided between the surface of the semiconductor element 1 and the lower surface of the electrode plate 7, and the plurality of support wires 11 contact the electrode plate 7 and the semiconductor element 1 so that the distance between the surface of the semiconductor element 1 and the lower surface of the electrode plate 7 becomes constant, whereby the inclination of the electrode plate 7 can be suppressed. That is, the support wire 11 is provided so that the surface of the semiconductor element 1 and the lower surface of the electrode plate 7 are parallel. After the distance between the electrode plate 7 and the semiconductor element 1 is held constant by the support wire 11, the semiconductor element 1 and the electrode plate 7 are joined via the second bonding material 12. Further, after the semiconductor element 1 and the electrode plate 7 are joined with the second bonding material 12, as described above, they are sealed with the sealing material 4. When the sealing material 4 is provided, there is a concern that the end portion of the electrode plate 7 may be exposed from the sealing material 4 if the electrode plate 7 is inclined, but by supporting the electrode plate 7 with the support wire 11, it is possible to prevent the end portion of the electrode plate 7 from being exposed from the sealing material 4.

[0026] The support wire 11 has tip portions 11b at both ends thereof, which are solid-phase joined by wire bonding. Further, the support wire 11 has a vertex portion 11a where the height of the wire is the highest among the support wires 11. The vertex portion 11a may be provided as a point as the vertex of the loop shape formed by the support wire 11, may be formed as a line or a surface having the same height, or may be formed at a position higher than the tip portion 11b even if the loop shape of the support wire 11 is collapsed.

[0027] The tip portions 11b serve as starting or ending points that are solid-phase bonded by wire bonding, and the tip portions 11b are provided at a distance of 0.5 mm or more from each other. The reason why the distance between the tip portions 11b is 0.5 mm or more apart is to prevent tool interference during wire bonding. Also, when wire bonding is performed, the tip portions 11b may be crushed, so this is also to prevent interference between the tip portions 11b due to the crushing width. As shown in FIG. 2, the tip portions 11b are joined to the semiconductor element 1, and the apex portions 11a support the electrode plate 7 in such a way as to suppress the inclination of the electrode plate 7 by contacting the electrode plate 7. Note that the tip portions 11b may be provided so as to be joined to the electrode plate 7 and the apex portions 11a contact the semiconductor element 1. For example, as a modified example of FIG. 2, FIG. 4 shows a modified example of the semiconductor device 50 provided such that the tip portions 11b are joined to the electrode plate 7 and the apex portions 11a contact the semiconductor element 1. As shown in FIG. 4, the tip portions 11b are joined to the electrode plate 7, and the apex portions 11a support the electrode plate 7 in such a way as to suppress the inclination of the electrode plate 7 by contacting the semiconductor element 1.

[0028] A stress buffer material may be provided between the surface of the semiconductor element 1 and the lower surface of the electrode plate 7 around the support wire 11. The stress buffer material may be any material that can buffer stress, for example, polyimide or the like. Note that the area around the support wire 11 is the entire support wire 11 or at least the region surrounding the tip portion 11b. If the region where the tip portion 11b of the support wire 11 is joined to the surface of the semiconductor element 1 is defined as the tip-joining region, the stress buffer material is provided on the surface of the semiconductor element 1 around the tip-joining region. That is, the stress buffer material is provided on the surface of the semiconductor element 1 excluding the tip-joining region. By providing the stress buffer material around the support wire 11, the stress applied to the support wire 11 can be suppressed, so the wire bonding life is improved. Also, when the support wire 11 is solid-phase bonded to the surface of the semiconductor element 1 by wire bonding, the stress from the wire bonding tool to the semiconductor element 1 can be relaxed.

[0029] The support wire 11 preferably has a diameter of 30 μm or more and 500 μm or less in consideration of the rigidity and cushioning property during support. However, since the smaller the diameter of the support wire 11, the larger the number of support wires 11 for support, it is more preferable that the diameter of the support wire 11 is 100 μm or more and 500 μm or less. Further, the semiconductor element 1 includes an active region through which a main current flows and a termination region for maintaining the breakdown voltage of the semiconductor element 1 around the active region. The support wire 11 is preferably provided on the active region on the surface of the semiconductor element 1. However, if the number of support wires 11 becomes too large, it will also be positively provided on the outer peripheral side of the semiconductor element 1, which is the termination region side outside the active region. If the support wire 11 is provided on the outer peripheral side of the semiconductor element 1, which is the termination region side of the semiconductor element 1, there is a concern that the creepage distance from the collector electrode becomes short and a collector-emitter short circuit may occur. It is preferable to appropriately suppress the number of support wires 11 by setting the diameter of the support wire 11 to 100 μm or more. Note that the stress buffer material provided on the surface of the semiconductor element 1 described above may be provided either on the active region or on the termination region, or may be provided across the active region and the termination region.

[0030] The material of the support wire 11 may be any conductive metal, such as aluminum, copper, silver, or gold. Since the main current of the semiconductor device 50 flows from the emitter electrode on the surface of the semiconductor element 1 to the electrode plate 7 side, if there is a conductive support wire 11, the heat generated by the semiconductor element 1 can be dissipated onto the semiconductor element 1, and the heat dissipation performance from the semiconductor element 1 can be improved. By using a support wire 11 with a higher thermal conductivity than the second bonding material 12, the heat dissipation performance on the semiconductor element 1 can be further improved. The support wire 11 may be partially or entirely embedded in the second bonding material 12, or may not be embedded. When the support wire 11 is embedded in the second bonding material 12, by using a member with a linear expansion coefficient close to that of the second bonding material 12 for the support wire 11, the thermal stress at the joint between the semiconductor element 1 and the support wire 11 can be suppressed, so that the heat dissipation performance from the semiconductor element 1 can be further improved. Also, when providing the encapsulant 4, since the support wire 11 is buried in the second bonding material 12, it is possible to prevent the support wire 11 from falling due to the pressure from the encapsulant 4.

[0031] Here, the manufacturing method of the semiconductor device 50 will be described using the flowchart in FIG. 21. The manufacturing method of the semiconductor device 50 includes a die bonding process, a case attachment process, a support wire installation process, an electrode plate attachment process, a wire bonding process, and an encapsulation process.

[0032] In the die bonding process, the first bonding material 9 is disposed on the insulating substrate 2 to bond the semiconductor element 1. Note that the first bonding material 9 may be a solder paste, and the solder paste may be melted by heat treatment by reflow to bond the semiconductor element 1 and the insulating substrate 2.

[0033] Next, in the case attachment process, the case 3 and the insulating substrate 2 are adhered via the adhesive 8. By filling the gap between the case 3 and the insulating substrate 2 with the adhesive 8, leakage of the encapsulant 4 to be injected in a later process can be prevented.

[0034] Next, in the support wire installation step, a plurality of support wires 11 are provided on the surface of the semiconductor element 1 or the electrode plate 7 so that the semiconductor element 1 and the electrode plate 7 are arranged in parallel. The support wire 11 is solid-phase bonded by wire bonding to the surface of the semiconductor element 1, or is solid-phase bonded by wire bonding the support wire 11 to the lower surface of the electrode plate 7. As a result, the apex portion 11a of the support wire 11 having a loop shape contacts the lower surface of the electrode plate 7 or the surface of the semiconductor element 1, and the distance between the semiconductor element 1 and the electrode plate 7 is kept constant and parallel. Note that the support wire installation step may be provided before the casing step.

[0035] Next, in the electrode plate mounting step, a second bonding material 12 is disposed on the semiconductor element 1, and further, the support wire 11 and the electrode plate 7 are brought into contact with each other, and the electrode plate 7 is placed on the support wire 11. At this time, since the plurality of support wires 11 support the electrode plate 7, the inclination of the electrode plate 7 can be suppressed. When the second bonding material 12 is a solder paste, the solder paste is provided on the semiconductor element 1 within the region surrounded by the support wires 11, and the support wires 11 keep the distance between the semiconductor element 1 and the electrode plate 7 constant, and the solder paste is melted by heat treatment by reflow to bond the semiconductor element 1 and the electrode plate 7. Note that a through hole may be provided in the electrode plate 7, and after the electrode plate 7 is disposed on the support wire 11, the second bonding material 12 may be poured onto the semiconductor element 1 from the through hole to bond the semiconductor element 1 and the electrode plate 7.

[0036] Next, in the wire bonding step, the control electrodes and the signal terminals 6 on the surface of the semiconductor element 1 are wire-bonded by a conductive wire 13 so as to form an arbitrary circuit. Note that the support wire 11 may be provided during the wire bonding step of the conductive wire 13, and the support wire installation step may be omitted. When the support wire 11 is provided during the wire bonding step, the electrode plate mounting step is performed after the wire bonding step.

[0037] Next, in the sealing process, after joining the semiconductor element 1 and the electrode plate 7 with the second bonding material 12, the semiconductor device 50 is completed by injecting and sealing the sealing material 4 into the region surrounded by the case 3 and the insulating substrate 2. When providing the sealing material 4, there is a concern that the end portion of the electrode plate 7 may be exposed from the sealing material 4 if the electrode plate 7 is tilted. However, since the tilt of the electrode plate 7 is suppressed by supporting the electrode plate 7 with the support wire 11, it is possible to prevent the end portion of the electrode plate 7 from being exposed from the sealing material 4.

[0038] FIG. 5 is an electric circuit diagram showing the configuration of the semiconductor device 50 according to Embodiment 1 of the present disclosure. As shown in FIG. 5, when the semiconductor element 1 is an IGBT in the semiconductor device 50, a diode is located on the circuit pattern 2c, and a half-bridge circuit of a 2in1 module is configured when two circuits in which the IGBT and the diode are connected in parallel are prepared and connected in series.

[0039] The electrode 5a is electrically connected to the collector electrode 31a, which is the back electrode of the semiconductor element 1a, via the circuit pattern 2c. Also, the collector electrode 31a of the semiconductor element 1a and the cathode electrode 31b of the diode 1b are electrically connected via the circuit pattern 2c, and the emitter electrode 32a, which is the front electrode of the semiconductor element 1a, and the anode electrode 32b, which is the front electrode of the diode 1b, are electrically connected via the electrode plate 7 to form a parallel circuit of the semiconductor element 1a and the diode 1b. The electrode 5b is electrically connected to the emitter electrode 34a, which is the front electrode of the semiconductor element 1c, via the circuit pattern 2c or the conductive wire 13. Also, the emitter electrode 34a of the semiconductor element 1c and the anode electrode 34b, which is the front electrode of the diode 1d, are electrically connected via the conductive wire 13 or the circuit pattern 2c, and the collector electrode 33a, which is the back electrode of the semiconductor element 1c, and the cathode electrode 33b, which is the back electrode of the diode 1d, are electrically connected via the conductive wire 13 or the circuit pattern 2c to form a parallel circuit of the semiconductor element 1c and the diode 1d. The electrode 5c is electrically connected to the emitter electrode 32a of the semiconductor element 1a and the collector electrode 33a of the semiconductor element 1c via the electrode plate 7, the circuit pattern 2c, or the conductive wire 13, etc. When making an electrical connection between members, it may be via the circuit pattern 2c, the electrode plate 7, the conductive wire 13, etc.

[0040] Two sets of parallel circuits are formed. Taking one parallel circuit as the upper arm and the other parallel circuit as the lower arm, a half-bridge circuit of the 2in1 module is formed by connecting the upper arm and the lower arm in series. Of course, a circuit different from the above-described circuit configuration may be configured. For example, a parallel circuit of a 1in1 module or a three-phase inverter circuit of a 6in1 module may be formed. Depending on the circuit configuration, the electrode 5c may not be necessary.

[0041] FIG. 6 is a cross-sectional view showing a configuration in which the semiconductor device 50 according to the present disclosure is attached to the heat sink 20. The configuration other than the heat sink 20 in FIG. 6 is as shown in FIG. 2, and FIG. 6 is a cross-sectional view showing a configuration in which the semiconductor device 50 and the heat sink 20 are fastened by screws 14.

[0042] The heat sink 20 is fixed to the semiconductor device 50 by a screw 14 via a metal bush 10. The metal bush 10 has a through-hole which is cylindrical and has a constant inner diameter in the direction from the front surface to the back surface of the insulating substrate 2 to allow the screw 14 to pass through. Since the semiconductor element 1 generates heat during use of the semiconductor device 50, heat is dissipated from the back surface of the metal plate 2a through the heat sink 20. Therefore, screw fastening between the semiconductor device 50 and the heat sink 20 is performed by the screw 14 via the metal bush 10 so as to maintain the state where the metal plate 2a and the heat sink 20 are in contact with each other. In the plan view of FIG. 1, the inner diameter and the outer diameter of the metal bush 10 are concentric circles within the range of manufacturing error.

[0043] FIG. 7 is a partially enlarged view of the region surrounded by the broken line 80 in the semiconductor device 50 shown in FIG. 1. FIGS. 8, 9, 10, and 11 are diagrams showing modified examples of FIG. 7. In the following description, for convenience of explanation, the sealing material 4, the conductive plate 7, etc. are shown excluded.

[0044] The support wire 11 has a vertex portion 11a and a tip portion 11b. The vertex portion 11a is the portion including the point with the highest loop height among the support wires 11, and the tip portion 11b is the portion including the joining point of the support wires 11. Four support wires 11 are arranged on the surface of one semiconductor element 1, and are arranged such that when the vertex portions 11a of the support wires 11 are connected by an imaginary line 85 in a plan view, they form a square shape. Note that two support wires 11 may be provided on the surface of one semiconductor element 1, but it is preferable that three or more are provided. When two support wires 11 are provided on the surface of one semiconductor element 1, when the vertex portions 11a are connected by an imaginary line 85, it becomes linear between two points. However, when supporting with three support wires 11, for example, as shown in FIG. 8, it is arranged such that when the vertex portions 11a of the support wires 11 are connected by an imaginary line 85 in a plan view, it forms a triangular shape, and since it becomes planar between three points, the electrode plate 7 can be supported more stably. Note that in FIG. 8, only the vertex portion 11a is shown for convenience of explanation. Also, as the number of support wires 11 increases, the electrode plate 7 can be supported more stably, so the inclination of the electrode plate 7 can be suppressed. Therefore, corresponding to the number of support wires 11, it may be arranged such that when the vertex portions 11a of the support wires 11 are connected by an imaginary line 85, it forms a polygonal shape. Also, since the polygon becomes more stable as it approaches a regular polygon, the support wires 11 may be arranged such that when the vertex portions 11a are connected by an imaginary line 85, it forms a regular polygon. Note that in order to further suppress the inclination of the electrode plate 7, for example, when arranging such that when the vertex portions 11a of the support wires 11 are connected by an imaginary line 85 in a plan view, it forms a square shape, as long as it is on the imaginary line 85 that forms a square shape, as shown in FIG. 9, four or more support wires 11 may be arranged, and the same applies to other polygonal shapes.

[0045] FIG. 10 shows a modified example of the support wire 11, and the modified examples are shown in FIGS. 10(a) to (d). As shown in FIG. 10(a), a plurality of joints 11c are also provided between the tip portions 11b at both ends of one support wire 11. That is, by continuously providing the support wires 11, a plurality of apex portions 11a may be provided on one support wire 11 instead of one apex portion 11a on one support wire 11, and the support wire 11 may have a plurality of loop shapes. Further, as shown in FIG. 10(b), the support wires 11 may be continuously provided at an angle θ that is an acute angle, a right angle, or an obtuse angle.

[0046] As shown in FIG. 10(c), a plurality of support wires 11 may be provided, and the tip portions 11b of the plurality of support wires 11 may be joined to each other discontinuously between the plurality of support wires 11. That is, a plurality of support wires 11 each having one apex portion 11a may be provided. The distance between the tip portions 11b of the plurality of support wires 11 is determined in consideration of preventing interference due to tool interference or collapse width during wire bonding. The plurality of support wires 11 may be provided parallel to each other or at an angle to each other. Further, the support wires 11 may be provided such that when the tip portions 11b are connected by a virtual line 85 while being joined discontinuously, a polygon is formed. For example, as shown in FIG. 10(d), a plurality of support wires 11 may be provided discontinuously such that when the tip portions 11b are connected by a virtual line, a square shape is formed. Furthermore, the support wires 11 may be provided such that when the apex portions 11a are connected by a virtual line, polygons are formed at the four corners of the semiconductor element 1, respectively. For example, as shown in FIG. 11, the support wires 11 are provided such that when the apex portions 11a are connected by a virtual line 85, a square shape is formed at the four corners of the semiconductor element. It is more preferable if it is at the four corners on the active region of the semiconductor element 1.

[0047] As described above, according to the semiconductor device 50 of this Embodiment 1, by supporting the electrode plate 7 on the semiconductor element 1 with the plurality of support wires 11, the inclination of the electrode plate 7 can be suppressed.

[0048] The effects of the semiconductor device 50 configured as described above will be described in comparison with a comparative example. First, as a comparative example, a schematic diagram when the electrode plate 7 is tilted is shown in FIG. 12. When the electrode plate 7 is tilted, there is concern about the influence on the surrounding members such as the second bonding material 12 or the sealing material 4. For example, the fillet shape of the second bonding material 12 may have cracks 30 when the electrode plate 7 is tilted because the distance between the semiconductor element 1 and the electrode plate 7 is not constant. The fillet-shaped cracks 30 on the semiconductor element 1 become factors for reducing heat dissipation and current density, and differences in heat dissipation and current density occur between the semiconductor elements 1 depending on the presence or absence of the fillet-shaped cracks 30. Although FIG. 12 shows the explanation between a plurality of semiconductor elements 1, the same applies to one semiconductor element 1. For example, when a plurality of the second bonding materials 12 are provided on one semiconductor element 1, differences in heat dissipation and current density occur at each part on the same semiconductor element 1 depending on the presence or absence of the fillet-shaped cracks 30 in the plurality of second bonding materials 12. Note that the larger the angle θ of the fillet shape of the second bonding material 12 with respect to the surface of the semiconductor element 1, the greater the stress applied to the semiconductor element 1. Therefore, for example, as shown in FIG. 12, when the electrode plate 7 is tilted, the angle θ between the fillet shape of the second bonding material 12 and the surface of the semiconductor element 1 is different for each fillet shape, and the stress applied to the semiconductor element 1 becomes non-uniform. In addition, when a sealing material 4 made of an epoxy-based resin is used, since stress is applied from the electrode plate 7, when the electrode plate 7 is tilted and when it is not tilted, the propagation direction of the resin crack 31 from the end of the electrode plate 7 toward the sealing material 4 changes in the direction toward the circuit pattern 2c on which the semiconductor element 1 is arranged, making it difficult to ensure the insulation performance as designed. In particular, in the semiconductor device 50 in which the electrode 5 and the electrode plate 7 are integrally formed as shown in FIG. 3, although one end of the electrode plate 7 is fixed to the case, the other end of the electrode plate 7 is not fixed to the case, so the electrode plate 7 is likely to tilt due to its own weight.

[0049] On the other hand, according to the semiconductor device 50 of Embodiment 1, in order to suppress the inclination of the electrode plate 7, the electrode plate 7 on the semiconductor element 1 is supported by a plurality of support wires 11, thereby suppressing the influence on the second bonding material 12 or the sealing material 4, etc., which are members around the electrode plate 7. For example, it is possible to suppress the fillet-shaped cracks 30 on the semiconductor element 1, and to suppress the occurrence of differences in heat dissipation and current density between semiconductor elements 1 and at each part on the same semiconductor element 1. Further, it is possible to suppress the angle θ between the fillet shape of the second bonding material 12 and the surface of the semiconductor element 1 from being different for each fillet shape, and to equalize the stress applied to the semiconductor element 1. Further, when the sealing material 4 made of an epoxy resin is used, it is possible to suppress the application of stress from the electrode plate 7 to the sealing material 4, and to suppress the change in the propagation direction of the resin crack 31 from the end of the electrode plate 7 to the sealing material 4 when the electrode plate 7 is inclined and when it is not inclined. Note that the present disclosure is particularly effective in a semiconductor device in which the electrode 5 and the electrode plate 7 are integrally formed as shown in FIG. 3, and it is possible to suppress the inclination due to the weight of the electrode plate 7 itself.

[0050] <Modification Example> The configuration of the semiconductor device 51 according to the modification example of Embodiment 1 will be described with reference to FIG. 13. FIG. 13 is a plan view showing the semiconductor device 51 according to the modification example of Embodiment 1, and FIG. 14 is a cross-sectional view taken along the broken line A-A' of the semiconductor device 51 shown in FIG. 13. Further, FIG. 15 is a cross-sectional view showing a configuration in which the semiconductor device 51 according to the modification example of Embodiment 1 is attached to the heat sink 20. Note that in the modification example of Embodiment 1, the same components as those described in Embodiment 1 are denoted by the same reference numerals and the description thereof is omitted.

[0051] As shown in Fig. 13, in the semiconductor device 51 of the modified example, the signal terminal 6 is insert-molded into the case 3. The electrodes 5a, 5b, and 5c are not provided on opposite parallel sides on the surface of the case 3, and the electrode 5 and the signal terminal 6 are provided side by side on one side of the case. Further, as shown in Fig. 14, a plurality of pin fins 2d are provided on the lower surface of the base plate 2c. The pin fins 2d have a pin shape that is a cylinder or a prism, and the heat dissipation performance is improved by providing the pin fins 2d. Note that the pins 2d may be integrally formed with the base plate 2c, or the pin fins 2d may be provided on the base plate 2c as separate bodies. The semiconductor device 51 provided with the pin fins 2d is fixed to the heat sink 20 and cooled as shown in Fig. 15. In order to fix the semiconductor device provided with the pin fins 2d to the heat sink 20, through holes may be formed in the case 3, the terminal 5, etc. so that bolts or the like tightened by screws can be inserted. In the semiconductor device of the modified example, the cooling method using the heat sink 20 may be not only air cooling but also water cooling using a water cooling jacket. That is, in the semiconductor device of the modified example, a water cooling jacket through which water or the like passes inside is used as the heat sink 20 to cool the semiconductor device. Even in such a configuration, the inclination of the electrode plate 7 can be suppressed by supporting the electrode plate 7 on the semiconductor element 1 by a plurality of support wires 11.

[0052] Hereinafter, other embodiments will be described. However, since the description of the same effects as those of the first embodiment is redundant, it is omitted.

[0053] <Embodiment 2> The semiconductor device 52 of the second embodiment will be described. Fig. 16 is a cross-sectional view showing the semiconductor device 52 of the second embodiment. In the following description, for convenience of explanation, the signal terminal 6, the conductive wire 13, etc. are shown excepted. The semiconductor device 52 of the second embodiment is different from the semiconductor device of the first embodiment in that the support wire 11 is provided between the surface of the circuit pattern 2c and the lower surface of the electrode plate 7. Further, regarding the manufacturing method of the semiconductor device 52, in the support wire installation step, the semiconductor device 52 is different from the manufacturing method of the semiconductor device of the first embodiment in that a plurality of support wires 11 are provided on the surface of the circuit pattern 2c.

[0054] According to the semiconductor device 52 of the second embodiment, since the support wire 11 is provided not on the surface of the semiconductor element 1 but between the surface of the circuit pattern 2c and the lower surface of the electrode plate 7, damage due to wire bonding can be suppressed when attaching the support wire 11 onto the semiconductor element 1. Further, the support wire 11 is provided between the surface of the circuit pattern 2c and the lower surface of the electrode plate 7 via an insulating material 15. The insulating material 15 is, for example, polyimide. When providing the support wire 11 on the circuit pattern 2c, unlike when providing it on the semiconductor element 1, power can be applied during wire bonding, so the region where the insulating material 15 covers the circuit pattern 2c can also be wire-bonded to the support wire 11. Note that the insulating material 15 may be provided on the support wire 11 itself and then the support wire 11 may be wire-bonded, or the insulating material 15 may be provided on the circuit pattern 2c or the electrode plate 7 at the position where it contacts the tip portion 11b or the apex portion 11a of the support wire 11 and then the support wire 11 may be wire-bonded. By providing the insulating material 15 at the tip portion 11b or the apex portion 11a of the support wire 11, the emitter electrode and the collector electrode of the semiconductor element 1 can be prevented from being electrically connected. As shown in FIG. 16, the tip portion 11b is joined to the circuit pattern 2c via the insulating material 15 and the apex portion 11a contacts the electrode plate 7, but it may be provided such that the tip portion 11b is joined to the electrode plate 7 via the insulating material 15 and the apex portion 11a contacts the circuit pattern 2c. For example, as a modification of FIG. 16, FIG. 17 shows a modified example of the semiconductor device 52 provided such that the tip portion 11b is joined to the electrode plate 7 and the apex portion 11a contacts the circuit pattern 2c. As shown in FIG. 17, by having the tip portion 11b joined to the electrode plate 7 and the apex portion 11a contact the circuit pattern 2c, it is possible to support the electrode plate 7 so as to suppress its inclination. Further, the semiconductor device 52 of the second embodiment is an effective embodiment when it is difficult to provide the support wire 11 due to a small chip size. For example, when the area on the chip is 10 mm 2 When the wire diameter of the support wire 11 is 100 μm or more hereinafter, by adopting the configuration of the semiconductor device 52 of the second embodiment, it is possible to suppress the inclination of the support wire 11 without providing the support wire 11 on the chip.

[0055] <Embodiment 3> The semiconductor device 53 according to Embodiment 3 will be described. FIG. 18 is a cross-sectional view showing the semiconductor device 53 according to Embodiment 3. In the following description, for convenience of explanation, the signal terminal 6, the conductive wire 13, etc. are not shown. The semiconductor device 53 according to Embodiment 3 is different from the semiconductor devices according to Embodiments 1 and 2 in that the support wire 11 is provided between the surface of the insulating member 2b and the lower surface of the electrode plate 7. Further, regarding the manufacturing method of the semiconductor device 53, in the support wire installation step, the manufacturing method of the semiconductor devices according to Embodiments 1 and 2 is different in that a plurality of support wires 11 are provided on the surface of the insulating member 2b.

[0056] According to the semiconductor device 53 of this Embodiment 3, since the support wire 11 is provided not on the surface of the semiconductor element 1 but between the surface of the insulating member 2b and the lower surface of the electrode plate 7, no stress from the wire bonding tool is applied onto the semiconductor element 1 when attaching the support wire 11. Also, in Embodiment 3, since the support wire 11 is provided between the surface of the insulating member 2b and the lower surface of the electrode plate 7, it is possible to prevent the emitter electrode and the collector electrode of the semiconductor element 1 from being electrically connected without providing the insulating material 15 as in Embodiment 2. As shown in FIG. 18, the tip portion 11b is joined to the insulating member 2b and the apex portion 11a contacts the electrode plate 7, but it may be provided such that the tip portion 11b is joined to the electrode plate 7 and the apex portion 11a contacts the insulating member 2b. For example, as a modified example of FIG. 18, a modified example of the semiconductor device 53 provided such that the tip portion 11b is joined to the electrode plate 7 and the apex portion 11a contacts the insulating member 2b is shown in FIG. 19. As shown in FIG. 19, by the tip portion 11b being joined to the electrode plate 7 and the apex portion 11a contacting the insulating member 2b, it is possible to support the electrode plate 7 so as to suppress its inclination. Also, the semiconductor device 53 according to Embodiment 3 is an effective embodiment when the chip size is small and it is difficult to provide the support wire 11. For example, when the area on the chip is 10 mm 2 When the wire diameter of the support wire 11 is 100 μm or more hereinafter, by adopting the configuration of the semiconductor device 53 according to Embodiment 3, it is possible to suppress the inclination of the support wire 11 without providing the support wire 11 on the chip.

[0057] <Embodiment 4> This embodiment applies the semiconductor device according to the above-described Embodiments 1 to 3 to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, hereinafter, as Embodiment 4, a case where the present disclosure is applied to a three-phase inverter will be described.

[0058] FIG. 20 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0059] The power conversion system shown in FIG. 20 is composed of a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source and supplies DC power to the power conversion device 200. The power source 100 can be composed of various things. For example, it can be composed of a DC system, a solar cell, a storage battery, or it may be composed of a rectifier circuit or an AC / DC converter connected to an AC system. Further, the power source 100 may be composed of a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

[0060] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, converts the DC power supplied from the power source 100 into AC power, and supplies the AC power to the load 300. As shown in FIG. 20, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs a drive signal for driving each switching element of the main conversion circuit 201, and a control circuit 203 that outputs a control signal for controlling the drive circuit 202 to the drive circuit 202.

[0061] The load 300 is a three-phase motor driven by the AC power supplied from the power conversion device 200. Note that the load 300 is not limited to a specific application and is a motor mounted on various electrical devices. For example, it is used as a motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.

[0062] Hereinafter, the details of the power conversion device 200 will be described. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). By switching the switching elements, the DC power supplied from the power source 100 is converted into AC power and supplied to the load 300. Although there are various specific circuit configurations of the main conversion circuit 201, the main conversion circuit 201 according to the present embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes connected in anti-parallel to each of the switching elements. The semiconductor device according to any one of the above-described Embodiments 1 to 3 is applied to each switching element of the main conversion circuit 201. The six switching elements are connected in series in pairs of two switching elements to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. Then, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0063] The drive circuit 202 generates a drive signal for driving the switching elements of the main conversion circuit 201 and supplies it to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with the control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of each switching element. When maintaining the switching element in the on state, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the off state, the drive signal is a voltage signal (off signal) equal to or lower than the threshold voltage of the switching element.

[0064] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that desired power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, the time (on-time) during which each switching element of the main conversion circuit 201 should be in the on-state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 202 so that an on-signal is output to the switching element that should be in the on-state at each time point, and an off-signal is output to the switching element that should be in the off-state. The drive circuit 202 outputs an on-signal or an off-signal as a drive signal to the control electrode of each switching element according to this control signal.

[0065] In the power conversion device according to the present embodiment, since the semiconductor devices according to Embodiments 1 to 3 are applied as the switching elements of the main conversion circuit 201, the inclination of the electrode plate 7 on the semiconductor element 1 is suppressed by supporting the electrode plate 7 with a plurality of support wires 11, and reliability improvement can be realized.

[0066] In the present embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described. However, the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may also be used. When supplying power to a single-phase load, the present disclosure may be applied to a single-phase inverter. Further, when supplying power to a DC load or the like, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0067] Further, the power conversion device to which the present disclosure is applied is not limited to the case where the above-described load is an electric motor. For example, it can also be used as a power supply device for a discharge processing machine, a laser processing machine, an induction heating cooker, or a contactless power feeding system. Furthermore, it can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

[0068] In the above embodiment, the switching element and the diode element are shown as being formed of silicon, but they may be formed of a wide bandgap semiconductor having a larger bandgap than silicon. Examples of the wide bandgap semiconductor include silicon carbide, gallium nitride-based materials, or diamond.

[0069] The switching element and the diode element formed of such a wide bandgap semiconductor have high breakdown voltage and high allowable current density, so that the switching element and the diode element can be miniaturized. By using these miniaturized switching elements and diode elements, the semiconductor module incorporating these elements can be miniaturized.

[0070] In addition, since the heat resistance is also high, the heat dissipation fins of the heat sink 20 can be miniaturized and the water cooling part can be air-cooled, so that the semiconductor device can be further miniaturized.

[0071] Furthermore, since the power loss is low, the switching element and the diode element can be made more efficient, and by extension, the semiconductor device can be made more efficient.

[0072] Although it is desirable that both the switching element and the diode element are formed of a wide bandgap semiconductor, either one of the elements may be formed of a wide bandgap semiconductor, and the effects described in this embodiment can be obtained.

[0073] Although some embodiments of the present disclosure have been described, these embodiments are presented by way of example. Various omissions, replacements, and changes can be made without departing from the gist thereof. Also, the embodiments can be combined.

Explanation of Reference Numerals

[0074] 1(1a, 1b, 1c, 1d) Semiconductor element, 2 Insulating substrate, 2a Metal plate, 2b Insulating member, 2c Circuit pattern, 2d Pin fin, 3 Case, 4 Sealing material, 5 Electrode, 6 Signal terminal, 7 Electrode plate, 8 Adhesive, 9 First bonding material, 10 Metal bush, 11 Support wire, 11a Vertex portion, 11b Tip portion, 11c Joint portion, 12 Second bonding material, 13 Conductive wire, 14 Screw, 15 Insulating material, 20 Heat sink, 30 Crack, 31 Resin crack, 50, 51, 52, 53 Semiconductor device, 100 Power supply, 200 Power conversion device, 201 Main conversion circuit, 202 Drive circuit, 203 Control circuit, 300 Load

Claims

1. A circuit pattern and an insulating member provided below the circuit pattern, a semiconductor element bonded onto the circuit pattern via a bonding material, an electrode plate provided above the circuit pattern and the semiconductor element, a plurality of support wires that contact the circuit pattern and the electrode plate between the circuit pattern and the electrode plate, a second bonding material provided on the semiconductor element for bonding the semiconductor element and the electrode plate, comprising a semiconductor device, wherein the circuit pattern or the electrode plate has an insulating material on its surface, and the support wire passes through the insulating material.

2. The support wire has tip portions at both ends, and a vertex portion including the vertex of the support wire is provided between the tip portions of the support wire, the tip portions contact the circuit pattern, and the vertex portion contacts the electrode plate. The semiconductor device according to claim 1, characterized in that.

3. The support wire has tip portions at both ends, and a vertex portion including the vertex of the support wire is provided between the tip portions of the support wire, the vertex portion contacts the circuit pattern, and the tip portions contact the electrode plate. The semiconductor device according to claim 1, characterized in that.

4. A circuit pattern and an insulating member provided below the circuit pattern, a semiconductor element bonded onto the circuit pattern via a bonding material, an electrode plate provided above the insulating member and the semiconductor element, a plurality of support wires that contact the insulating member and the electrode plate between the insulating member and the electrode plate, a second bonding material provided on the semiconductor element for bonding the semiconductor element and the electrode plate, characterized by comprising a semiconductor device.

5. The support wire has tip portions at both ends, and a vertex portion including the vertex of the support wire is provided between the tip portions of the support wire, the tip portions contact the insulating member, and the vertex portion contacts the electrode plate. The semiconductor device according to claim 4, characterized in that.

6. The support wire has tip portions at both ends, and a vertex portion including the vertex of the support wire is provided between the tip portions of the support wire, the vertex portion contacts the insulating member, and the tip portions contact the electrode plate. The semiconductor device according to claim 4, characterized in that.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that three or more support wires are provided.

8. The semiconductor device according to any one of claims 1 to 3, wherein in the circuit pattern, the support wires are provided at four corners in a plan view.

9. The semiconductor device according to any one of claims 4 to 6, wherein in the insulating member, the support wires are provided at four corners in a plan view.

10. The semiconductor device according to any one of claims 2, 3, 5, and 6, wherein in one of the support wires, the vertex portion is one.

11. The semiconductor device according to any one of claims 2, 3, 5, and 6, wherein in one of the support wires, there are a plurality of vertex portions.

12. The semiconductor device according to any one of claims 2, 3, 5, and 6, wherein the tip portions are adjacent to each other with an interval of 0.5 mm or more.

13. The semiconductor device according to any one of claims 1 to 12, wherein at least a part of the support wire is embedded in the second bonding material.

14. A power conversion device comprising: a main conversion circuit that has the semiconductor device according to claims 1 to 13 and converts and outputs input power; a drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device; a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit. ​

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