Control Circuit and Semiconductor Memory Device

Abstract

To provide a control circuit that can prevent the delay operation from becoming long and complete a sequence for adjusting the delay of an internal clock signal using a DLL circuit within a specified execution period.SOLUTION: A control circuit includes a delay control unit 10 that delays an input clock signal on the basis of the phase difference between an input clock signal and an output clock signal to generate an output clock signal, and further includes a clock control unit 17, and when the phase difference is equal to or greater than a first predetermined amount, the clock control unit inputs a clock signal, the phase of which is delayed by a second predetermined amount, to the delay control unit as an input clock.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a control circuit and a semiconductor memory device.

Background Art

[0002] DRAM (Dynamic Random Access Memory), which is a type of semiconductor memory device, is a volatile memory that stores information by storing electric charges in capacitors, and the stored information is lost when the power supply is cut off. A delay locked loop (DLL) circuit is provided in the DRAM as a phase synchronization circuit. The DRAM uses the DLL circuit to generate an internal clock signal for outputting a data signal in synchronization with an input clock signal input from the outside. As such a DLL circuit, for example, the one described in Patent Document 1 is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, when adjusting the delay of the internal clock signal using the DLL circuit, for example, a sequence including a reset operation of the DLL circuit, a delay (lock) operation of the DLL circuit (for example, an operation of synchronizing the external clock and the internal clock while activating one delay line at a time), and a detection operation of an N value indicating the number of delay clock cycles between the input clock signal and the internal clock signal is executed.

[0005] Here, the lock time Tdll due to the delay operation of the DLL circuit can be expressed by the following formula.

[0006] Tint + Tdll = N × tCK

[0007] In the above formula, Tint represents the intrinsic delay time in the DLL circuit, and tCK represents the clock cycle. For example, when the clock cycle (tCK) becomes longer than the intrinsic delay time (Tint) due to the temperature or the like inside the semiconductor memory device, the lock time (Tdll) due to the delay operation of the DLL circuit also becomes longer as shown in the above formula. When the lock time becomes longer in this way, the execution time of the entire above sequence becomes longer, and there is a possibility that the execution of the next sequence is delayed. In particular, when the delay becomes longer, there is a risk of exceeding the predetermined execution period (tDLLK) of the sequence. Also, in order to cope with the current high-speed operation of semiconductor integrated circuits, it is desirable to speed up the delay operation during the sequence as much as possible.

[0008] The synchronization circuit described in Patent Document 1 is also aimed at speeding up such a delay operation, but its configuration is complicated, and a simpler configuration is desirable.

[0009] The present invention has been made in view of the above problems, and an object thereof is to provide a control circuit and a semiconductor memory device that have a simple configuration and can suppress the prolongation of the delay operation.

Means for Solving the Problems

[0010] The control circuit of the present invention is a control circuit including a delay control unit that generates the output clock signal by delaying the input clock signal based on the phase difference between the input clock signal and the output clock signal, and further includes a clock control unit. When the phase difference is equal to or greater than a first predetermined amount, the clock control unit inputs, as the input clock signal, a clock signal obtained by delaying the phase of the input clock signal by a second predetermined amount to the delay circuit.

[0011] In the present invention, when the phase difference is equal to or greater than a first predetermined amount, the clock control unit inputs, as the input clock signal, a clock signal obtained by delaying the phase of the input clock signal by a second predetermined amount to the delay circuit as the input clock. Thus, a delay operation can be performed using the clock signal delayed by the second predetermined amount, so that the phase difference between the input clock signal and the output clock signal can be shortened. As a result, it is possible to suppress the extension of the delay operation period.

[0012] The clock control unit receives a first input clock signal and a second input clock signal obtained by delaying the phase of the first input clock signal by the second predetermined amount. When the phase difference is equal to or greater than the first predetermined amount, the clock control unit preferably selects the second input clock signal as the input clock. By configuring the circuit to be able to select either the first input clock signal or the second input clock signal based on whether the phase difference is equal to or greater than the first predetermined amount, it is not necessary to delay the input clock signal to generate a second clock signal obtained by delaying the first input clock by the second predetermined amount. That is, by generating these two input clocks in advance, it is not necessary to delay the input clock signal according to the control, so that the extension of the delay operation period can be further suppressed and the entire circuit can have a simple configuration.

[0013] The clock control unit preferably determines whether the phase difference is equal to or greater than the first predetermined amount at a predetermined timing after the start of the delay operation. The phase difference can be determined at a predetermined timing after the start of a stable delay operation of the entire circuit.

[0014] The delay control unit preferably includes a phase detection unit that detects the phase difference between the input clock signal and the output clock signal, and the phase difference detected by the phase detection unit is input to the clock control unit. By inputting the phase difference detected by the phase detection unit included in the delay control unit to the clock control unit, it is possible to simplify the configuration of the entire control circuit.

[0015] The clock control unit includes a select signal generation unit and an internal clock selection unit to which the select signal generated by the select signal generation unit is input. The select signal generation unit generates a select signal indicating whether the phase difference is equal to or greater than a predetermined value, and the internal clock selection unit is preferably configured to select either the first input clock signal or the second input clock signal based on the select signal. By configuring it in this way, it is possible to simplify the overall configuration of the circuit.

[0016] Preferably, the first predetermined amount is 180 degrees. By setting the first predetermined amount to 180 degrees, the entire control circuit can be easily controlled, and the overall configuration of the circuit can be simplified.

[0017] Preferably, the second predetermined amount is 180 degrees. By setting the second predetermined amount to 180 degrees, the entire control circuit can be easily controlled, and the overall configuration of the circuit can be simplified.

[0018] It is preferable to include an input buffer to which an external clock signal is input. In the input buffer, a first input clock signal is generated from the external clock signal, and at the same time, the external clock signal is inverted to generate a second input clock signal. Alternatively, it is preferable to include an input buffer to which an external clock signal is input. In the input buffer, a first input clock signal is generated from the external clock signal, and a second input clock signal is generated from the compensation clock signal of the external clock signal. By configuring the input buffer in this way, the first input clock signal and the second input clock signal can be stably supplied to the control circuit and can be easily generated.

[0019] Preferably, the delay operation is performed based on the phase difference between the rising edge of the second input clock signal and the rising edge of the output clock signal. By performing the delay operation at the rising edges of both signals in this way, the time required for the delay operation can be shortened, and its extension can be suppressed.

[0020] The semiconductor memory device of the present invention is characterized by including any one of the above-described control circuits. By including any one of the control circuits, the execution time of the sequence can be shortened, and since it includes a control circuit in which the execution time of the sequence does not exceed a predetermined period defined in advance for the sequence, the return operation from a predetermined sequence is fast, and the response time can be shortened.

[0021] As a preferred embodiment of the present invention, the semiconductor memory device may be a dynamic random access memory.

Effect of the Invention

[0022] According to the control circuit, semiconductor memory device, and control method of the semiconductor memory device of the present invention, it is possible to suppress the prolongation of the delay operation.

Brief Description of the Drawings

[0023]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Embodiments for Carrying Out the Invention

[0024] Hereinafter, a control circuit, a semiconductor memory device, and a control method of a semiconductor memory device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, this embodiment is an example, and the present invention is not limited thereto.

[0025] In addition, notations such as "first", "second", etc. in this specification and the like are used to distinguish one component from other components, and are not for limiting the number, order, priority, etc. of the components. For example, when there are descriptions of "first element" and "second element", it does not mean that only two elements, namely "first element" and "second element", are adopted, nor does it mean that the "first element" must precede the "second element".

[0026] FIG. 1 shows a DLL circuit 1 (control circuit) according to an embodiment of the present invention. In this embodiment, the control circuit is provided in a semiconductor memory device such as a DRAM, for example.

[0027] In this embodiment, for the sake of simplicity of explanation, well-known configurations provided in a semiconductor memory device such as a DRAM (for example, an N-value detection unit, a latency control unit, a command decoder, a memory cell array, an interface unit for input / output, etc.) are not shown.

[0028] The DLL circuit 1 includes an input buffer 11, a phase detection unit 12, a DLL control unit 13, a delay circuit 14, a replica unit 15, an output buffer 16, and a clock control unit 17. The delay control unit 10 of the present embodiment is composed of the phase detection unit 12, the DLL control unit 13, the delay circuit 14, and the replica unit 15. Note that the delay control unit 10 may be composed of at least the phase detection unit 12, the DLL control unit 13, and the delay circuit 14. When the sequence is started, the DLL circuit 1 first performs a reset operation to reset the delay circuit 14 of the DLL circuit 1 to the initial state, and then performs a delay operation to delay the input clock signal by the delay circuit 14 to generate a desired output clock signal. That is, in the present embodiment, the sequence control includes a reset operation and a delay operation in this order.

[0029] The input buffer 11 buffers the clock signal CLKT and the clock signal CLKC input to the input buffer 11 to generate a first clock signal clk000 having the same phase as the clock signal CLKT and a second clock signal clk180 having the same phase as the clock signal CLKC. Specifically, as shown in FIG. 2(1), the input buffer 11 includes an amplifier 111. Two complementary clock signals CLKT as external clock signals and the clock signal CLKC are input to the amplifier 111. The input clock signal CLKT and the clock signal CLKC are amplified in the amplifier 111 to generate a first clock signal clk000 and a second clock signal clk180. The second clock signal clk180 is generated as a clock signal obtained by inverting the first clock signal clk000.

[0030] Returning to FIG. 1, the generated first clock signal clk000 and second clock signal clk180 are input to the clock control unit 17, and the first clock signal clk000 is also input to the phase detection unit 12 as a reference clock signal ref_clk. That is, the reference clock signal ref_clk is the same as the first clock signal clk000.

[0031] The clock control unit 17 further receives the phase signal up / down output from the phase detection unit 12 and the reset signal dll_reset_n. The reset signal dll_reset_n indicates that the reset operation has ended when it is at a high level. Although details will be described later, the clock control unit 17 outputs either the first clock signal clk000 or the second clock signal clk180 as the input clock signal in_clk based on the phase signal up / down, and this input clock signal in_clk is input to the delay circuit 14.

[0032] Based on the delay amount set by the DLL control unit 13, the delay circuit 14 generates a delayed signal (output clock signal) dll_clk by delaying the input clock signal in_clk input from the clock control unit 17, and transmits it to the output buffer 16 and the replica unit 15. The delayed signal dll_clk input to the output buffer 16 is buffered in the output buffer 16 and output as the output signal DQS. The replica unit 15 outputs the delayed signal dll_clk generated by the delay circuit 14 as the feedback signal fb_clk. The feedback signal fb_clk is input to the phase detection unit 12.

[0033] The phase detection unit 12 receives the reference clock signal ref_clk and the feedback signal fb_clk. In the phase detection unit 12, a phase signal up / down indicating the advance (delay less than 180 degrees) or delay (delay of 180 degrees or more) of the phase of the feedback signal fb_clk with respect to the reference clock signal ref_clk is generated and input to the DLL control unit 13.

[0034] Specifically, as shown in FIG. 2(2), the phase detection unit 12 is composed of a D flip-flop circuit 121. A feedback signal fb_clk is input as an input signal to the D flip-flop circuit 121, a reference clock signal ref_clk is input as a clock signal, and a phase signal up / down is output as an output signal. When the feedback signal fb_clk has a delay of less than 180 degrees with respect to the reference clock signal ref_clk, the generated phase signal up / down becomes high level (up). When the feedback signal fb_clk has a delay of 180 degrees or more with respect to the reference clock signal ref_clk, the generated phase signal up / down becomes low level (down).

[0035] Returning to FIG. 1, the DLL control unit 13 determines the delay amount from the phase difference detected by the phase detection unit 12. Specifically, the DLL control unit 13 generates and outputs a control signal dll_code composed of a plurality of bits as a signal indicating the delay amount in the delay operation based on the phase signal up / down from the phase detection unit 12. This output control signal dll_code is input to the delay circuit 14.

[0036] The delay circuit 14 is a variable delay unit that performs a delay operation. Specifically, the delay circuit 14 generates a delayed signal dll_clk by delaying the input clock signal in_clk by activating a delay line according to the control signal dll_code.

[0037] Also, when the DLL control unit 13 determines that the feedback signal fb_clk corresponding to the input clock signal in_clk and the delayed signal dll_clk has converged within a predetermined range based on the phase signal up / down, it determines that the delay operation has ended. Thereby, the delay operation ends.

[0038] As described above, in the DLL circuit 1 of this embodiment, the delay control unit 10 generates a delay signal dll_clk by delaying the input clock signal in_clk based on the phase difference between the input clock signal in_clk and the feedback signal fb_clk which is the delay signal dll_clk. Hereinafter, the clock control unit 17 that controls the input clock signal in_clk input to the delay control unit 10 will be described.

[0039] The clock control unit 17 receives a phase signal up / down, a reset signal dll_reset_n, a first clock signal clk000, and a second clock signal clk180. The clock control unit 17 selects either the first clock signal clk000 or the second clock signal clk180 as the input clock signal in_clk and outputs the input clock signal in_clk to the delay circuit 14. Before the delay operation, the clock control unit 17 selects the first clock signal clk000 as the input clock signal in_clk. When the delay operation is started, according to the phase signal up / down, either the first clock signal clk000 or the second clock signal clk180 is selected as the input clock signal in_clk.

[0040] The details of the configuration of the clock control unit 17 will be described with reference to FIG. 3. The clock control unit 17 includes a timing signal generation unit 171, a select signal generation unit 172, and an internal clock selection unit 173.

[0041] The timing signal generation unit 171 generates a timing signal sel_clk indicating the timing of the elapse of a predetermined period when the predetermined period has elapsed after the start of the delay operation, and inputs it to the select signal generation unit 172. This predetermined period is for selecting a clock after the DLL circuit 1 has stabilized when selecting a clock after a reset operation.

[0042] When the timing signal sel_clk indicates the timing of the elapse of the predetermined period, the select signal generation unit 172 uses the input clock signal (reference clock signal ref_clk) and the output clock signal (feedback signal fb_clk) of the delay control unit 10in the same phase as ) Determine whether the phase difference from is 180 degrees or more, generate a select signal sel180 indicating the determination result, and input it to the internal clock selection unit 173. Here, for the determination of whether the phase difference between the input clock signal and the output clock signal of the delay control unit 10 is 180 degrees or more, the phase signal up / down is used. The phase signal up / down is at a high level (up) when the feedback signal fb_clk (in phase with the output clock signal of the delay control unit 10) is less than 180 degrees delayed with respect to the reference clock signal ref_clk (in phase with the input clock signal of the delay control unit 10) as described above, and is at a low level (down) when the delay is 180 degrees or more. Therefore, this phase signal up / down can be used for simple determination. That is, when the timing signal sel_clk indicates the timing at which a predetermined period has elapsed, the select signal generation unit 172 determines whether the phase signal up / down is 180 degrees or more, generates a select signal sel180 indicating the determination result, and inputs it to the internal clock selection unit 173.

[0043] Based on the determination result indicated by this select signal sel180, the internal clock selection unit 173 selects either the first clock signal clk000 or the second clock signal clk180 as the input clock signal in_clk, and outputs the input clock signal in_clk.

[0044] The clock control unit 17 will be further described with reference to FIGS. 4 to 6. In the conventional example shown in FIG. 4(1), the DLL circuit 1A is different from the present embodiment in that it does not have a clock control unit 17. In the DLL circuit 1A, the clock signal CK output from the input buffer 11A is input to the delay control unit 10A (phase detection unit 12A, DLL control unit 13A, and delay circuit 14A), and a delay signal dll_clk is output. In the conventional example with such a configuration, as shown in FIG. 4(2), when the clock signal CK changes from the low level to the high level at time t1, if the feedback signal fb_clk changes from the low level to the high level at time t2 with a delay of the inherent delay Tint, the period t1 to t2 is less than half of the clock signal CK's period. Therefore, the feedback signal fb_clk is delayed by 180 degrees or more with respect to the clock signal CK's period. Then, when the delay circuit 14A performs a delay operation so that the clock signal CK and the feedback signal fb_clk (i.e., the output signal DQS) are synchronized, the rising edge of the clock signal CK and the rising edge of the output signal DQS coincide at time t5. Thus, in the conventional example, when the feedback signal fb_clk before the delay operation is delayed by half of the clock period or more with respect to the clock signal CK, that is, when the phase difference is 180 degrees or more, the lock time Tdll, which is the delay to be eliminated by the delay operation, is the period t2 to t5. Therefore, there is a possibility that the delay operation may be prolonged.

[0045] In contrast, in the present embodiment, a clock control unit 17 is provided which inputs either the first clock signal clk000 or the second clock signal clk180 as the input clock signal in_clk to the delay circuit 14 (delay control unit 10) according to the phase signal up / down, thereby suppressing the extension of the delay operation. First, since the input clock signal in_clk input to the delay control unit 10 before the delay operation is the first clock signal clk000, the input clock signal in_clk and the first clock signal clk000 are in the same phase. When the phase difference between this first clock signal clk000 and the feedback signal fb_clk, which is in the same phase as the delay signal dll_clk output from the delay control unit 10, is 180 degrees or more, the clock control unit 17 outputs the second clock signal clk180 as the input clock signal in_clk to the delay circuit 14. As a result, the fb_clk, which is in the same phase as the output clock signal from the delay circuit 14, is also delayed by 180 degrees. As a result, in the delay control unit 10, the delay operation is performed according to the phase difference between the rising edge of the second clock signal clk180 and the rising edge of the feedback signal fb_clk delayed by 180 degrees, so that the synchronization between the input clock signal in_clk and the feedback signal fb_clk is terminated early, and the desired output signal DQS can be generated.

[0046] Specifically, the case where the phase difference between the feedback signal fb_clk and the input clock signal in_clk is 180 degrees or more after the delay operation will be described. As shown in Fig. 5(1), while the input clock signal in_clk and the first clock signal clk000 change from the low level to the high level at time t11, the feedback signal fb_clk changes from the low level to the high level at time t12, delayed by the inherent delay Tint. Since the period t11~t12 indicating this phase difference is less than half the period of the clock signal CK, the feedback signal fb_clk is delayed by 180 degrees or more with respect to the period of the input clock signal in_clk. In this case, the clock control unit 17 selects the second clock signal clk180 as the input clock signal in_clk. As a result, the delay control unit 10 performs a delay operation on the second input clock signal clk180 so that the rising edge of the second clock signal clk180 at time t13 and the rising edge of the feedback signal fb_clk delayed by 180 degrees at time t14 are at the same timing (the second clock signal clk180 and the feedback signal fb_clk are synchronized). As a result, the lock time Tdll, which is the delay that must be eliminated by the delay operation, becomes the period t14~t15.

[0047] To summarize, as shown in Fig. 6(1), in the conventional example, when the phase difference between the input clock signal and the output clock signal in the delay control unit 10 is 180 degrees or more, the lock time Tdll becomes longer, resulting in a longer overall sequence time. In contrast, in the present embodiment, when the phase difference between the input clock signal and the output clock signal in the delay control unit 10 is 180 degrees or more, the DLL circuit 1 is configured so that the second input clock signal clk180 can be used as the input clock signal in_clk. Therefore, the delay operation can be completed early, and the overall sequence time can be shortened.

[0048] Also, the case where the phase difference between the feedback signal fb_clk and the input clock signal in_clk after the delay operation is less than 180 degrees is shown in FIG. 5(2). In this case, since the phase difference is small, as the input clock signal in_clk, the clock signal clk000 is selected. As a result, similar to the conventional example, the delay circuit 14 performs a delay operation on clk000 so that the rising edge of the clock signal clk000 at time t21 coincides with the rising edge of the feedback signal fb_clk at time t22. Thus, the inherent delay Tint is the period t21 to t22, and the lock time Tdll is the period t22 to t23. When the delay operation is performed in this way, as shown in FIG. 6(2), similar to the case where the delay is less than 180 degrees in the conventional case, the delay operation can be performed earlier, and the time of the entire sequence can be kept shortened.

[0049] Returning to FIG. 3, the specific configuration of the clock control unit 17 that realizes such an operation will be described. Of course, the configuration of the clock control unit 17 is not limited to the example shown below.

[0050] The timing signal generation unit 171 includes a plurality of flip-flop circuits 71 to 74 and 、A an ND circuit 75. Although four flip-flop circuits 71 to 74 are illustrated in the figure, the number is not limited and can be appropriately changed according to the length of a predetermined period required for circuit stability.

[0051] A plurality of flip-flop circuits 71 to 74 are connected in series. A reset signal dll_reset_n input from the outside is input as an input signal to the flip-flop circuit 71 on the most upstream side. To the other flip-flop circuits 72 to 74, the output signals of the adjacent upstream flip-flop circuits 71 to 73 are input as input signals, respectively. To the plurality of flip-flop circuits 71 to 74, a first clock signal clk000 is input in an inverted manner as a clock signal, respectively. Further, the reset signal dll_reset_n is inverted and input to the plurality of flip-flop circuits 71 to 74, respectively. The output signal of the flip-flop circuit 74 on the most downstream side is A is inverted and input to the ND circuit 75. Also 、A to the ND circuit 75, the output of the flip-flop circuit 73 adjacent to the upstream side of the flip-flop circuit 74 is input, and at the same time, the first clock signal clk000 is input 。A In the ND circuit 75, these input signals is A are ND-operated to output a timing signal sel_clk.

[0052] The operation of the timing signal generation unit 171 will be described. When the input reset signal dll_reset_n changes from a low level to a high level, this change is held by the plurality of flip-flop circuits 71 to 74 for a predetermined period and input to the flip-flop circuit 74 or A's such as input to the ND circuit 75 。A Since the output signal of the flip-flop circuit 73, the output signal of the flip-flop circuit 74, and the first clock signal clk000 are input to the ND circuit 75, when the output from the flip-flop circuit 74 becomes high level 、A the timing signal sel_clk is low level generated and output in the ND circuit 75. In other cases (For example, when the output from the flip-flop circuit 73 is high level and the output from the flip-flop circuit 74 is low level), A the timing signal sel_clk in the ND circuit 75 is high levelIt is generated and output. As a result, the timing signal sel_clk is output at a high level only at a predetermined timing after the delay operation starts after the reset operation. That is, the timing signal sel_clk is generated as a one-shot signal.

[0053] The select signal generation unit 172 consists of a flip-flop circuit 76. The flip-flop circuit 76 receives the phase signal up / down inverted as an input signal and the timing signal sel_clk as a clock signal. Also, the reset signal dll_reset_n is inverted and input. Then, a select signal sel180 is output from the flip-flop circuit 76 as an output signal. As described above, since the timing signal sel_clk is a one-shot signal that changes from a low level to a high level only when a predetermined period has elapsed after the start of the delay operation, the select signal generation unit 172 can determine whether the delay is 180 degrees or more only at a predetermined timing after the start of the delay operation.

[0054] The operation of the select signal generation unit 172 will be described. In the select signal generation unit 172, when the reset signal dll_reset_n is at a high level and the phase signal up / down is at a high level (up) at the rising edge where the timing signal sel_clk is input from a low level to a high level, the select signal sel180 maintains a low level. In this case, since the phase difference of the input signal to the delay control unit 10 is less than 180 degrees, the select signal sel180 is output at a low level indicating that the second clock signal clk180 is not selected. On the other hand, when the reset signal dll_reset_n is at a high level and the phase signal up / down is at a low level (down) at the rising edge where the timing signal sel_clk is input from a low level to a high level, the select signal sel180 is output at a high level indicating that the second clock signal clk180 is selected.

[0055] The internal clock selection unit 173 consists of a multiplexer 77, and is configured to select either the input first clock signal clk000 or the second clock signal clk180 according to the select signal sel180, and output it as the input clock signal in_clk. That is, when the select signal sel180 is at a high level indicating selection of the second clock signal clk180, the multiplexer 77 outputs the second clock signal clk180, and in other cases, the multiplexer 77 outputs the first clock signal clk000.

[0056] In this way, the clock control unit 17 can set either the first clock signal clk000 or the second clock signal clk180 as the input clock signal in_clk according to the phase signal up / down with a simple configuration, and input it to the delay circuit 14. Thereby, the DLL circuit 1 of the present embodiment can suppress the prolongation of the delay operation.

[0057] Next, the operation of the DLL circuit 1 of the present embodiment having the clock control unit 17 will be described using the flowcharts shown in FIGS. 7 and 8.

[0058] FIG. 7 shows a case where the phase difference between the feedback signal fb_clk and the input clock signal in_clk is 180 degrees or more. First, this sequence starts and the DLL is first in a reset state. In this state, the input clock signal in_clk is the first clock signal clk000, and the phase difference between the feedback signal fb_clk and the input clock signal in_clk is 180 degrees or more. Then, the DLL reset state ends at time t31, and the reset signal dll_reset_n changes from a low level to a high level. As the state of the DLL circuit, the delay operation starts simultaneously with the end of the DLL reset state at time t31.

[0059] Then, at time t32 in the timing signal generation unit 171, a predetermined period elapses and the timing signal sel_clk changes from a low level to a high level. At this time t32, the reset signal dll_reset_n is at a high level, and the phase signal up / down is at a low level (down). At the rising edge of the timing signal sel_clk, since the high-level reset signal dll_reset_n and the low-level phase signal up / down are input to the select signal generation unit 172, the select signal sel180 is output from a low level to a high level. As a result, the input clock signal in_clk output from the clock control unit 17 becomes the second clock signal clk180, so the input clock signal in_clk maintains a low level from time t32 to time t33 in the same manner as the second clock signal clk180.

[0060] The input clock signal in_clk changes from a low level to a high level following the rising edge of the second clock signal clk180 at time t33. Also, since the second clock signal clk180 is selected as the input clock signal in_clk, the feedback signal fb_clk is also delayed by 180 degrees, maintains a low level from time t32 to time t34, and changes from a low level to a high level at time t34. Thus, when the feedback signal fb_clk changes from a low level to a high level, at time t35, the phase signal up / down changes from a low level to a high level. That is, the phase difference between the feedback signal fb_clk and the input clock signal in_clk becomes small (less than 180 degrees).

[0061] In the delay circuit 14, based on this phase signal up / down, the input clock signal in_clk, which is the second clock signal clk180, is delayed, and it is determined that a desired phase difference is achieved at time t36, and the delay operation ends.

[0062] Next, the operation of the DLL circuit 1 when the phase difference between the feedback signal fb_clk and the input clock signal in_clk is less than 180 degrees will be described using the flowchart shown in FIG. 8.

[0063] First, this sequence control starts. First, the state of the DLL circuit 1 becomes the DLL reset state. After that, the reset operation ends at time t41, and the reset signal dll_reset_n changes from the low level to the high level. At the same time that the reset operation ends at time t41, the delay operation starts in the DLL circuit 1.

[0064] Then, at time t42, in the timing signal generation unit 171, the timing signal sel_clk changes from the low level to the high level. At this time t42, the reset signal dll_reset_n is at the high level, and the phase signal up / down is up (high level). At the rising edge of the timing signal sel_clk, in the select signal generation unit 172, since the high-level reset signal dll_reset_n and the high-level phase signal up / down are input, the select signal sel180 is maintained at the low level. As a result, as the input clock signal in_clk, the first clock signal clk000 is selected, so the input clock signal in_clk is maintained at the high level from time t42 to time t43 in the same manner as the first clock signal clk000. Also, since the input clock signal in_clk becomes the clock signal clk000, the feedback signal fb_clk is not delayed by 180 degrees either.

[0065] In the delay circuit 14, based on this phase signal up / down, the input clock signal in_clk, which is the first clock signal clk000, is delayed, and it is determined that the desired phase difference is achieved at time t44, and the delay operation ends.

[0066] In this way, the clock control unit 17 can, with a simple configuration, set either the first clock signal clk000 or the second clock signal clk180 as the input clock signal in_clk according to the phase difference signal up / down and input it to the delay circuit 14 (delay control unit 10). As a result, in the DLL circuit 1, it is possible to suppress the extension of the delay operation time.

[0067] Hereinafter, a modified example of the present invention will be described.

[0068] The configuration of the DLL circuit 1 in the above-described embodiment is an example, and it may be changed as appropriate, or various other configurations may be adopted. For example, as shown in FIG. 9, an input buffer 11 may be configured. In this case, the input buffer 11 includes an amplifier 112 and an inverter 113. The amplifier 112 receives the clock signal CLKT and the clock signal CLKC that are complementary to each other as external clock signals. The input complementary clock signals CLKT and CLKC are amplified in the amplifier 112, and the amplifier 112 outputs only the first clock signal clk000 that is in phase with the clock signal CLKT. Further, this first clock signal clk000 is input to the inverter 113, and a second clock signal clk180 obtained by inverting the first clock signal clk000 is generated. In the above-described embodiment, since all signals are output from the amplifier 111, the first clock signal clk000 and the second clock signal clk180 have the same number of CMOS gate stages. However, in the embodiment shown in FIG. 9, the first clock signal clk000 and the second clock signal clk180 differ from each other by one stage of the inverter 113 in terms of the number of CMOS gate stages.

[0069] In the above-described embodiment, the control is changed depending on whether the phase difference between the input clock signal in_clk and the delay signal dll_clk (feedback signal fb_clk) is 180 degrees or more, but this phase difference can be set to a desired value. Also, the second clock signal clk180 is obtained by delaying the phase of the input clock signal by 180 degrees with respect to the first clock signal clk000, but this phase difference can also be set to a desired value. On the other hand, by setting the phase difference to 180 degrees as in the above-described embodiment, the control becomes simple, and the overall circuit configuration can also be made simple. Furthermore, although the first clock signal clk000 and the second clock signal clk180 are generated in advance and configured to be selectable, this is not limiting. For example, three or more clock signals with different phases may be generated in advance, or the circuit may be configured to generate clock signals with different phases during the delay operation.

[0070] Also, in the present embodiment, in order to simplify the configuration, the phase difference between the input clock signal in_clk and the delay signal dll_clk (feedback signal fb_clk) is detected using the phase detection unit 12 that the delay control unit 10 normally has, but this is not limiting, and a separate phase detection unit may be provided.

[0071] In the above-described embodiment, the case where the semiconductor recording device including the control circuit is a DRAM has been described as an example, but the present invention is not limited to this case. For example, the semiconductor memory device may be an SRAM (Static Random Access Memory), a flash memory, or other semiconductor memory devices.

[0072] The above-described embodiments and modified examples are described to facilitate the understanding of the present invention, and are not described to limit the present invention. Therefore, each element disclosed in the above-described embodiments and modified examples is intended to include all design changes and equivalents belonging to the technical scope of the present invention.

Description of Reference Numerals

[0073] 1…DLL circuit 10…Delay control unit 11…Input buffer 12…Phase detection unit 13…DLL control unit 14…Delay circuit 15…Replica unit 16…Output buffer 17…Clock control unit fb_clk…Feedback signal in_clk…Input clock signal clk000…First clock signal clk180…Second clock signal up / down…Phase signal

Claims

1. A control circuit comprising a delay control unit that delays an input clock signal based on a phase difference between the input clock signal and an output clock signal, the phase difference being between the output clock signal and an input clock signal that transitions at a time later than the output clock signal, to generate the output clock signal, further comprising a clock control unit and an input buffer to which an external clock signal is input, wherein when the phase difference is equal to or greater than a first predetermined amount, the clock control unit inputs, as the input clock signal to the delay control unit, a clock signal obtained by delaying the phase of the input clock signal by a second predetermined amount, a first input clock signal and a second input clock signal obtained by delaying the phase of the first input clock signal by the second predetermined amount are input to the clock control unit, wherein when the phase difference is equal to or greater than the first predetermined amount, the clock control unit selects the second input clock signal as the input clock signal, wherein the clock control unit includes a timing signal generation unit, a select signal generation unit, and an internal clock selection unit, wherein the timing signal generation unit generates, at the elapse of a predetermined period after the start of a delay operation, a timing signal indicating the timing of the elapse of the predetermined period, the timing signal being for starting, in the select signal generation unit and the internal clock selection unit, the selection of either the first input clock signal or the second input clock signal, and the timing signal is input to the select signal generation unit, wherein in the input buffer, the first input clock signal is generated from the external clock signal, and the second input clock signal is generated from a compensation clock signal of the external clock signal. A control circuit characterized by this.

2. The control circuit according to claim 1, wherein the clock control unit determines whether the phase difference is equal to or greater than the first predetermined amount at a predetermined timing after the start of the delay operation.

3. The delay control unit of the control circuit according to claim 1 has a phase detection unit that detects the phase difference between the input clock signal and the output clock signal, characterized in that the phase difference detected by the phase detection unit is input to the clock control unit.

4. The select signal generated by the select signal generation unit is input to the internal clock selection unit, The select signal generation unit generates a select signal indicating whether the phase difference is equal to or greater than a predetermined value, The internal clock selection unit is configured to select one of the first input clock signal and the second input clock signal based on the select signal. The control circuit according to claim 1, characterized in that.

5. The control circuit according to claim 1, characterized in that the first predetermined amount and / or the second predetermined amount is 180 degrees.

6. The control circuit according to claim 1, characterized in that a delay operation is performed based on the phase difference between the rising edge of the second input clock signal and the rising edge of the output clock signal.

7. The delay control unit includes a delay circuit and a DLL control unit, The control circuit according to claim 1, characterized in that the delay circuit generates the output clock signal based on the delay amount set by the DLL control unit.

8. The delay control unit includes a phase detection unit connected to the DLL control unit, The control circuit according to claim 7, characterized in that the phase detection unit receives a feedback signal and a reference clock signal and generates a phase signal indicating the advance or delay of the phase of the feedback signal with respect to the reference clock signal.

9. The delay control unit includes a replica unit connected to the delay circuit and the phase detection unit, The control circuit according to claim 8, characterized in that the replica unit receives the output clock signal generated by the delay circuit and outputs the feedback signal.

10. A semiconductor memory device comprising the control circuit according to any one of claims 1 to 9.

11. The semiconductor memory device according to claim 10, characterized in that the semiconductor memory device is a dynamic random access memory.

12. The timing signal generation unit includes a plurality of flip-flop circuits and a NAND circuit, The plurality of flip-flop circuits are connected in series, A reset signal input from the outside is input as an input signal to the flip-flop circuit on the most upstream side among the plurality of flip-flop circuits, The control circuit according to claim 1, characterized in that the output signal of the flip-flop circuit adjacent to the upstream side is input as an input signal to other flip-flop circuits.

13. The first clock signal is inverted and then input as a clock signal to the plurality of flip-flop circuits. The reset signal is inverted and then input to the plurality of flip-flop circuits. The output signal of the flip-flop circuit on the most downstream side among the plurality of flip-flop circuits is inverted and then input to the NAND circuit. The output of the flip-flop circuit adjacent to the flip-flop circuit on the most downstream side is input to the NAND circuit. The control circuit according to claim 12, wherein the first clock signal is input to the NAND circuit. **Claim 14** When the input reset signal changes from a low level to a high level, after this change is held by the plurality of flip-flop circuits for a predetermined period, it is input from the most downstream flip-flop circuit to the NAND circuit. The control circuit according to claim 12, characterized in that. **Claim 15** The output signal of the flip-flop circuit adjacent to the flip-flop circuit on the most upstream side, the output signal of the flip-flop circuit on the most upstream side, and the first clock signal are input to the NAND circuit. When the output of the flip-flop circuit on the most upstream side is at a high level, the NAND circuit generates and outputs a high-level timing signal such that the timing signal becomes high level only until a predetermined time after the start of the delay operation after the reset operation. The control circuit according to claim 13, characterized in that.

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