A / D converter

Abstract

To provide an A / D converter capable of converting an analog signal into a digital value at high speed and with high accuracy.SOLUTION: A counting unit 26 repeatedly counts the number of pulse signals having passed through a plurality of second delay units. A first calculation unit 28A obtains difference between a value obtained by adding a sign bit to the latest count value by the count unit 26 and a value obtained by adding the sign bit to a past count value. A second calculation unit 28B adds a sign bit of the calculation result obtained by the first calculation unit 28A to the most significant bit other than the sign bit, uses the addition result as the new most significant bit, and outputs a new calculation result other than the sign bit.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to an A / D converter configured to output a digital value corresponding to the potential of an analog signal. [Background technology]

[0002] For example, Patent Document 1 below discloses an A / D converter equipped with a pair of ring-shaped pulse delay circuits (hereinafter also referred to as ring delay lines: RDLs) made up of serially connected delay units. The delay units are made up of various gate circuits. Note that A / D converter is an abbreviation for analog / digital converter.

[0003] In this A / D converter, a pulse signal is circulated through a pulse delay circuit, while an analog signal is input to the power line of the pulse delay circuit. The number of pulses the pulse signal passes through the delay unit within a given sampling time varies depending on the potential of the analog signal. The analog signal is converted into a digital value by counting this number. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2018-182561 Summary of the Invention [Problem to be solved by the invention]

[0005] However, as a result of detailed investigation by the inventors, it was found that the above A / D converter has a problem in that it outputs values with large errors depending on the situation. Specifically, in the A / D converter, the pair of ring-shaped pulse delay circuits have different numbers of delay units, and the data output from the pulse delay circuit with the larger number of delay units is set to have one more bit. Then, the number of delay units the pulse signal has passed through is calculated by subtracting data corresponding to the pulse position before and after the sampling time in a subtraction circuit.

[0006] In this configuration, when the pulse delay circuit overflows, that is, when the pulse returns from the last delay unit to the first delay unit, the subtraction result in the subtraction circuit may have a large error, because the most significant bit may have an incorrect value, as will be described later.

[0007] One aspect of the present disclosure is to provide an A / D converter that can convert an analog signal into a digital value at high speed and with high accuracy. [Means for solving the problem]

[0008] One aspect of the present disclosure is an A / D converter (1) configured to output a digital value corresponding to the potential of an analog signal. The A / D converter includes a first digitizing unit (10), a second digitizing unit (20), and an adding output unit (40).

[0009] The first digitizing unit includes a plurality of first delay units (11, 12, 13) and a first output unit (15). The plurality of first delay units are configured by connecting 2 n -p first delay units in series. The first output unit is configured to output n-bit data corresponding to the number of first delay units through which the pulse signal has passed.

[0010] The second digitizing section includes a plurality of second delay units (21:12,13) and a second digitizing section (20). The plurality of second delay units are configured by connecting 2 n + p second delay units in series. The second output section is configured to output n+1-bit data according to the number of second delay units through which the pulse signal has passed.

[0011] The addition output unit is configured to output, as a digital value, a sum obtained by adding a numerical value based on the output from the first digitization unit and a numerical value based on the output from the second digitization unit. Each delay unit representing each of the plurality of first delay units and the plurality of second delay units is configured so that the delay time of the pulse signal passing through each delay unit is changed in accordance with the potential of the analog signal.

[0012] The second output unit includes a count unit (26), a first calculation unit (28A), and a second calculation unit (28B). The count unit is configured to repeatedly count the number of times the pulse signal has passed through the plurality of second delay units. The first calculation unit is configured to determine the difference between the most recent count value by the count unit plus a sign bit and a previous count value plus a sign bit by performing a calculation using the complement of binary numbers.

[0013] The second calculation unit is configured to add the sign bit of the calculation result by the first calculation unit to the most significant bit excluding the sign bit, set the addition result as a new most significant bit, and output the new calculation result excluding the sign bit, where n and p are natural numbers and 2(n-1)>p.

[0014] This configuration can prevent the most significant bit from becoming an incorrect value when the pulse delay circuit overflows, thereby providing an A / D converter that can convert an analog signal into a digital value quickly and accurately. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 2 is a block diagram showing the configuration of an A / D converter. [Figure 2] FIG. 1 is a circuit diagram showing an example of a ring-shaped pulse delay circuit (for example, a ring delay line: RDL). [Figure 3] 4 is an operation timing chart of the A / D converter. [Figure 4] FIG. 10 is a block diagram showing the configuration of an adder in the second digitizing unit. [Figure 5A] FIG. 10 is an explanatory diagram showing a first calculation example by a first digitizing unit. [Figure 5B] FIG. 10 is an explanatory diagram showing a second calculation example by the first digitizing unit. [Figure 6A] FIG. 10 is an explanatory diagram showing an example of an erroneous calculation by a conventional second digitizing unit. [Figure 6B] FIG. 10 is an explanatory diagram showing an example of normal calculation by the second digitizing unit. [Figure 7] FIG. 1 is an explanatory diagram showing code loss, i.e., a 1 LSB decrease and a 1 LSB increase. [Figure 8] FIG. 10 is an explanatory diagram showing a state in which a missing code, that is, a decrease of 1 LSB and an increase of 1 LSB, are offset. DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. [1-1.Configuration] The A / D converter 1 of this embodiment shown in FIG. 1 functions as an A / D (that is, analog / digital) converter that outputs a digital value according to the potential of an analog input signal.

[0017] The A / D converter 1 shown in FIG. 1 includes a first digitizing section 10, a second digitizing section 20, and an addition output section 40. A power supply voltage VBB, a ground voltage GND, a pulse signal PA, a clock CKs, and an analog signal VIN may be input to the first digitizing unit 10 and the second digitizing unit 20. The first digitizing unit 10 and the second digitizing unit 20 function as a well-known A / D converter that outputs an A / D converted value.

[0018] The A / D converted values herein represent digital values corresponding to the voltage of the input analog signal, and in this embodiment, represent the numerical data DTc1 and DTc2. These numerical data DTc1 and DTc2 are input to the addition output unit 40.

[0019] The addition output unit 40 calculates the sum of the numeric data DTc1 and the numeric data DTc2, i.e., (DTc1+DTc2), and outputs it as A / D converted data DT of the analog input signal Vin. Here, the first digitization unit 10 includes a ring-shaped pulse delay circuit 11 and a first output unit 15. The second digitization unit 20 includes a ring-shaped pulse delay circuit 21 and a second output unit 25. The first output unit 15 and the second output unit 25 will hereinafter also be referred to as the output units 15, 25, respectively.

[0020] 1 and 2, the ring-shaped pulse delay circuits 11 and 21 include a plurality of delay units 12 and 13, which constitute a pulse delay circuit that functions as a time A / D conversion circuit, i.e., a TAD. TAD is an abbreviation for Time A / D converter.

[0021] The ring-shaped pulse delay circuits 11, 21 each include a plurality of delay units 12, 13, each of which includes a NAND circuit NAND12 that receives a pulse signal PA at its input terminal and a number (for example, an even number) of inverters INV13 as inverting circuits. These delay units 12, 13 are connected in a ring shape to form a ring delay line.

[0022] In particular, in this embodiment, the ring-shaped pulse delay circuit 11 of the first digitizing unit 10 is configured to include 127 (i.e., 2 to the power of 7-1) serially connected delay units 12, 13. That is, it includes one NAND circuit NAND12 and 126 inverters INV13.

[0023] The ring-shaped pulse delay circuit 21 of the second digitizing unit 20 includes 129 (i.e., 2 to the power of 7+1) series-connected delay units 12, 13. That is, it includes one NAND circuit NAND12 and 128 inverters INV13.

[0024] Here, the ring-shaped pulse delay circuits 11, 21 of the digitizing units 10, 20 are configured to operate upon receiving a pulse signal PA from the outside. As shown in Figure 2, the NAND 12 constituting the ring-shaped pulse delay circuits 11, 21 is a CMOS NAND gate including a p-channel transistor and an n-channel transistor. Also, the INV 13 is a CMOS inverter.

[0025] A positive power supply line and a negative power supply line are connected to each of these delay units 12, 13. A positive power supply voltage is applied to the power supply terminal VIN, and the ground terminal GND is set to a lower potential than the power supply terminal VIN, so that each of the delay units 12, 13 delays and transmits the pulse signal PA by a delay time corresponding to the voltage between these terminals. In this embodiment, the first digitizing unit 10 and the second digitizing unit 20 input an analog signal to the pulse delay circuit as VIN, and the speed at which the pulse signal PA circulates while passing through the delay units 12, 13 is changed according to the potential of VIN.

[0026] Here, "passing" means that the pulse signal PA reaches the gate of the delay unit 12, 13, i.e., the potential level of the gate changes from low to high or from high to low, and the output of this delay unit 12, 13 is inverted. When the pulse signal PA passes through this delay unit 12, 13, the pulse signal PA is input to the gate of the next delay unit 12, 13, and this operation occurs in a chain and successive manner for the multiple delay units 12, 13.

[0027] Furthermore, "speed" refers to the number of delay units 12, 13 through which a pulse signal can pass per unit time. As the speed increases, the number of delay units 12, 13 through which a pulse signal can pass per unit time increases.

[0028] For example, as shown in [a] in Figure 3, when the potential of the analog signal P1 input as VIN is high, the time until the ring-shaped pulse delay circuits 11, 21 overflow (for example, Trdl in Figure 4) becomes shorter, and overflow occurs frequently. Note that overflow occurs when the pulse signal PA returns from the last delay unit 12, 13 to the first delay unit 12, 13. In other words, it is a phenomenon in which the output DTp from the counting units 16, 26 returns to 0 after reaching its maximum value.

[0029] Furthermore, as shown in [b] and [c] in FIG. 3, as the potential of the analog signal P1 decreases, the time until the ring-shaped pulse delay circuits 11 and 21 overflow increases.

[0030] 2, the power supply VBB is applied to the back gate bias of the P-channel transistors constituting the NAND12 and INV13 included in the delay units 12 and 13. The speed at which the pulse signal PA passes through the delay units 12 and 13 can also be changed by the potential of VBB.

[0031] Each output unit 15, 25 includes a count unit 16, 26, a latch 17, 27, and an adder 18, 28. The count units 16, 26 are configured as, for example, a latch and an encoder.

[0032] The counting units 16 and 26 repeatedly take in outputs P1 to P127 or P1 to P129 of the delay units 12 and 13 that make up the ring-shaped pulse delay circuits 11 and 21 at predetermined timings according to the clock CKs, and generate outputs DTp that correspond to the positions of the pulse signals passing through the delay units 12 and 13.

[0033] The output DTp from the counting section 16 in the first digitizing section 10 is output in 7 bits, and the output DTp from the counting section 26 in the second digitizing section 20 is output in 8 bits, which is one bit more than the output DTp from the counting section 16. The reason for this configuration is that the number of delay units 12, 13 in the second digitizing section 20 is more than 2 to the power of 7, and 8 bits are required to represent the output P129.

[0034] These outputs DTp are input to latches 17 and 27 and an adder 18, respectively. The latches 17 and 27 hold the latest output DTp received from the counting unit 26, and also send the output DTp held immediately before the latest output DTp to the adders 18 and 28 as a comparison value.

[0035] The adders 18 and 28 subtract the comparison value from the latest output DTp. That is, they calculate the difference between the positions of the pulse signals before and after the time corresponding to the preset number of clocks CKs has elapsed. Here, subtraction is performed using the complement of binary numbers so that the adders 18 and 28 can perform subtraction. The adders 18 and 28 output the calculation results as numeric data DTc1 and DTc2 to the addition output unit 40.

[0036] In particular, the adder 28 in the second digitizing section 20 includes a first calculation section 28A and a second calculation section 28B, as shown in Fig. 4. For ease of explanation, the outputs DTp and DTc2 in Fig. 3 and Figs. 4 to 6B will be described assuming that the ring-shaped pulse delay circuits 11, 21 include 2 to the power of 4 (i.e., 16) ±1 delay units 12, 13.

[0037] 4, the first calculation unit 28A is configured to calculate the difference between a value D1 obtained by adding a sign bit SGB to the latest count value by the count unit 26, and a value D2 obtained by adding a sign bit SGB to a past count value, by performing a calculation using the complement of binary numbers. Note that a sign bit SGB of 0 is added to each of D1 and D2.

[0038] The latest count value is a value obtained from the counting unit 26, and the past count value is a value obtained from the latch 27. These count values are the 5-bit output DTp in the example of FIG.

[0039] The first calculation unit 28A adds a sign bit SGB to each of these 5-bit data, and calculates the difference between the 6-bit data D1 and D2 including the sign bit SGB for each bit.

[0040] The second calculation unit 28B adds the sign bit SGB of the calculation result by the first calculation unit 28A to the most significant bit tMSB excluding the sign bit SGB, and then sets the result of this addition as the new most significant bit MSB, and outputs the new calculation result excluding the sign bit SGB as numeric data DTc2.

[0041] That is, the second output section 25 performs a 6-bit calculation when calculating the difference between the count value data D1 and D2, but outputs the output DTc2 as 5 bits, which is one bit less.

[0042] A specific example of calculation will be described below. When the first output unit 15 of the first digitization unit 10 performs a calculation to subtract 13 from 17, this is equivalent to subtracting 13 from 1, since 17 is the same value as 1. This calculation is performed using 4 bits, as shown in FIG. 5A. This calculation can also be performed using the complement of a binary number, as the sum of 1 and the complement of 13. More specifically, the complement of 13 is expressed as "0011", which is obtained by inverting each bit of 13, or the binary number "1101", and then adding 1. This calculation obtains 4 as the correct calculation result after the code deletion, which reduces by 1 bit. A missing code indicates that the original code (i.e., value) is missing, resulting in another incorrect code. In this embodiment, missing code includes a case where the LSB decreases by 1 and a case where the LSB increases by 1. Here, the LSB indicates the least significant bit.

[0043] Next, when the sign bit is not used as in the conventional configuration, the calculation by the second output unit 25 of the second digitizing unit 20 is performed using 5 bits, as shown in Fig. 6A. In this configuration, when subtracting 13 from 17, the sum of "00001", which is 1, and "10011", which is the complement of 13, is calculated, and an abnormal calculation result of "10100", which is 20, may be obtained. Such an abnormal calculation result is obtained because the most significant bit MSB of the complement of 13 is 1, and this bit value is added to the calculation result.

[0044] Therefore, the calculation by the second output unit 25 of the second digitizing unit 20 of this embodiment is performed as shown in Fig. 6B. That is, the first calculation unit 28A adds "000001", which is 1, to "110011", which is the complement of 13, in 6 bits with the sign bit SGB added. Then, the second calculation unit 28B further adds the sign bit SGB "1" and the most significant bit tMSB "1" other than the sign bit SGB to this addition result "110100". Of the addition result of the sign bit SGB and the most significant bit tMSB by the second calculation unit 28B, only the least significant bit "0" is adopted as the new most significant bit MSB.

[0045] When 1 and the complement of 13 are added, the new most significant bit MSB becomes 0, and the calculation by the first calculation unit 28A and the second calculation unit 28B results in 4 as the correct calculation result. 3 also illustrates examples of numerical values handled by the second digitizing unit 20. In FIG. 3, the output value from the counting unit 26 is represented by ED, and the final output from the second digitizing unit 20 is represented by DTc2.

[0046] When the output value ED from the counting unit 26 passes through 5 DUs, i.e., five delay units 12 and 13, during one cycle of the clock CKs, the output value ED increases by 5 in the order 3, 8, and 13, and after 13 it does not become 18 but becomes 17. This is because a missing code occurs, which reduces the value by one bit.

[0047] On the other hand, although not shown, the output value ED from the counting unit 16 of the first digitizing unit 10 will not be 17 or 18 after 13, but will be 19. This is because a missing code occurs, which increases by one bit. As shown in FIG. 5B, when the first digitizing unit 10 performs a calculation to subtract 13 from 19, this is equivalent to performing an operation to subtract 13 from 3, because 19 is the same value as 3. This calculation obtains 6 as the correct calculation result after the missing code, which increases by one bit.

[0048] That is, as shown in the upper diagram of Fig. 7, the output DTc1 from the first digitizing section 10 may be 1 greater than the correct value C because the number of delay units 12, 13 is 1 less than 2 to the power of n. On the other hand, as shown in the lower diagram of Fig. 7, the output DTc2 from the second digitizing section 20 may be 1 less than the correct value C because the number of delay units 12, 13 is 1 more than 2 to the power of n.

[0049] However, since the addition output unit 40 adds and outputs the outputs DTc1 and DTc2 from the respective digitization units 10 and 20, when an increase of 1 LSB and a decrease of 1 LSB occur simultaneously, as shown in FIG. 8, these are offset and the correct value 2C is output.

[0050] [1-2.Effects] According to the embodiment described above in detail, the following effects are achieved. (1a) One aspect of the present disclosure is an A / D converter 1 configured to output a digital value corresponding to the potential of an analog signal. The A / D converter 1 includes a first digitizing unit 10, a second digitizing unit 20, and an adding / outputting unit 40.

[0051] The first digitizing section 10 includes a ring-shaped pulse delay circuit 11 having a plurality of delay units 12 and 13, and a first output section 15. The plurality of delay units 12 and 13 are configured by connecting 2 to the power of n -1 in series in the ring-shaped pulse delay circuit 11. The first output section 15 is configured to output n-bit data according to the number of times the pulse signal has passed through the plurality of delay units 12 and 13.

[0052] The second digitizing section 20 includes a ring-shaped pulse delay circuit 21 having a plurality of delay units 12, 13, and the second digitizing section 20. The plurality of delay units 12, 13 are configured by connecting 2 to the power of n+1 units in series in the ring-shaped pulse delay circuit 21. The second output section 25 is configured to output (n+1) bits of data according to the number of times the pulse signal has passed through the plurality of delay units 12, 13.

[0053] The addition output unit 40 is configured to output, as a digital value, a sum obtained by adding together a numerical value based on the output from the first digitization unit 10 and a numerical value based on the output from the second digitization unit 20. The delay units 12 and 13 constituting the ring-shaped pulse delay circuits 11 and 21 are configured so that the delay time of the pulse signal passing through each delay unit 12 and 13 is changed in accordance with the potential of the analog signal.

[0054] The second output unit 25 includes a counting unit 26, a first calculation unit 28A, and a second calculation unit 28B. The counting unit 26 is configured to repeatedly count the number of times the pulse signal has passed through the plurality of delay units 12, 13. The first calculation unit 28A is configured to determine the difference between the latest count value by the counting unit 26 plus a sign bit and a previous count value plus a sign bit, by performing a calculation using the complement of a binary number.

[0055] The second calculation unit 28B is configured to add the sign bit of the calculation result by the first calculation unit 28A to the most significant bit excluding the sign bit, set the addition result as a new most significant bit, and output the new calculation result excluding the sign bit, where n is a natural number, i.e., an integer of 1 or greater.

[0056] This configuration can prevent the most significant bit from becoming an incorrect value when the ring-shaped pulse delay circuits 11, 21 overflow. Therefore, it is possible to provide an A / D converter 1 that can convert an analog signal into a digital value quickly and accurately. Furthermore, this configuration can be configured as a complementary A / D converter that can mutually complement the 1 LSB decrease and 1 LSB increase that occur in the multiple ring-shaped pulse delay circuits 11, 21.

[0057] (1b) In one aspect of the present disclosure, each of the delay units 12, 13 is configured to receive an analog signal as input to a power supply line of the delay unit 12, 13. The first output section 15 and the second output section 25 are configured to output, as numerical data DTc1, DTc2, the number of delay units 12, 13 through which a pulse signal has passed within a preset time.

[0058] With this configuration, digital values corresponding to the potential of the analog signal can be output as the numeric data DTc1 and DTc2.

[0059] 2. Other Embodiments Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be implemented in various modified forms.

[0060] (2a) In the above embodiment, the ring-shaped pulse delay circuits 11, 21 are configured to have only 2 to the power of n ±1 delay units 12, 13, but this is not limited to this. For example, the ring-shaped pulse delay circuits 11, 21 may have only 2 to the power of n ±(2m-1) delay units 12, 13. However, it is preferable that n and m are natural numbers and n≧m.

[0061] With this configuration, the number of delay units 12, 13 included in the ring-shaped pulse delay circuits 11, 21 can be an odd number. Furthermore, the delay units 12, 13 (e.g., multiple INVs 12) other than the delay unit 12, 13 (e.g., NAND 13) that receives the pulse signal can be configured with simple elements such as inverters. Therefore, the A / D converter 1 can be made smaller.

[0062] (2b) The number of delay units 12, 13 provided in the ring-shaped pulse delay circuits 11, 21 is not limited to an odd number, but may be an even number. In this case, the number of delay units 12, 13 provided in the ring-shaped pulse delay circuits 11, 21 may be 2 to the power of n ± p. Here, n and p are natural numbers, and it is preferable that 2 to the power of (n-1) > p. Even with this configuration, errors due to missing cords can be made relatively small.

[0063] (2c) In the above embodiment, the delay units 12 and 13 are connected in series in a ring shape, but this is not limiting. For example, the delay units 12 and 13 may be arranged in a straight line, and when a pulse passes through the last delay unit 12 and 13, another pulse may be input to the first delay unit 12 and 13.

[0064] (2d) In the above embodiment, the ring-shaped pulse delay circuits 11 and 21 are used in the A / D converter 1, but this is not limiting. For example, they may be configured as a digitizing device that outputs preset analog information such as time, temperature, stress, etc. as a digital value.

[0065] Regarding time, if VIN, VBB, and GND are kept constant and CKs is input as the measurement start time and measurement end time, a value representing the difference between these times can be obtained as a digital value. For temperature and stress, it is advisable to record in advance the digital values obtained when VIN, VBB, and GND are kept constant and CKs is input at a constant interval for each temperature or stress.Then, when actually measuring the temperature or stress, it is sufficient to find out which temperature or stress the obtained digital value corresponds to.

[0066] (2e) Multiple functions possessed by one component in the above embodiments may be realized by multiple components, or one function possessed by one component may be realized by multiple components. Also, multiple functions possessed by multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Also, part of the configuration of the above embodiments may be omitted. Also, at least part of the configuration of the above embodiments may be added to or substituted for the configuration of another of the above embodiments.

[0067] (2f) In addition to the A / D converter 1 described above, the present disclosure can also be realized in various forms, such as a system including the A / D converter 1 as a component, an A / D conversion method, and the like. [Explanation of symbols]

[0068] 1...A / D converter, 10...first digitizing section, 11, 21...ring-shaped pulse delay circuit, 12, 13...delay unit, 15...first output section, 16, 26...counting section, 17, 27...latch, 18, 28...adder, 20...second digitizing section, 25...second output section, 28A...first calculation section, 28B...second calculation section, 40...addition output section.

Claims

1. An A / D converter (1) configured to output a digital value corresponding to the potential of an analog signal, A plurality of first delay units (11:12, 13) connected in series, the number of which is 2 n -p; a first output section (15) configured to output data in n bits according to the number of times the pulse signal has passed through the plurality of first delay units; a first digitizing unit (10) comprising: A plurality of second delay units (21:12, 13) connected in series, the number of which is 2 n +p; a second output section (25) configured to output data in n+1 bits according to the number of times the pulse signal has passed through the plurality of second delay units; a second digitizing unit (20) comprising: an addition output unit (40) configured to output, as the digital value, an addition value obtained by adding a numerical value based on the output from the first digitization unit and a numerical value based on the output from the second digitization unit; Equipped with each delay unit representing each of the plurality of first delay units and the plurality of second delay units is configured such that a delay time of the pulse signal passing through each delay unit is changed in accordance with a potential of the analog signal; The second output unit a counting section (26) configured to repeatedly output, as a count value, a number corresponding to positions of the pulse signal passing through the plurality of second delay units; a first calculation unit (28A) configured to calculate a difference between a value obtained by adding a sign bit to the latest count value by the count unit and a value obtained by adding a sign bit to a past count value; a second calculation unit (28B) configured to add the sign bit of the calculation result by the first calculation unit to a most significant bit excluding the sign bit, set the addition result as a new most significant bit, and output a new calculation result excluding the sign bit; Equipped with the numerical value based on the output by the first digitizing unit is n-bit data output from the first output unit, the numerical value based on the output by the second digitizing unit is n+1-bit data output from the second output unit, The new calculation result output by the second calculation unit (28B) is n+1-bit data output from the second output unit (25). Here, n and p are natural numbers, and 2 to the (n-1) power>p.

2. 2. The A / D converter according to claim 1, the plurality of first delay units are provided in a number of 2 n -(2 m - 1); The number of the second delay units is 2 n +(2 m - 1). A / D converter. Here, n and m are natural numbers, and n≧m.

3. 3. The A / D converter according to claim 2, the number of the first delay units is 2 n -1; The number of the second delay units is 2 n +1. A / D converter.

4. 4. The A / D converter according to claim 1, wherein: each delay unit is configured such that the analog signal is input to a power supply line of the delay unit; The first output unit and the second output unit output the number of delay units through which the pulse signal has passed within a preset time as numerical data. An A / D converter configured as follows.

Images