High frequency devices and Doherty amplifiers

Abstract

To provide a high frequency device that can be miniaturized.SOLUTION: A high frequency device includes a metal base 10, a dielectric substrate 30 mounted on the metal base 10, an insulating layer provided on the metal base 10, covering the dielectric substrate 30, and having a dielectric constant smaller than that of the dielectric substrate 30, and a line 19a that overlaps the dielectric substrate 30 when viewed from the thickness direction of the insulator layer, is provided on the upper surface of the insulator layer, and forms a first microstrip line Z1.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a high-frequency device and a Doherty amplifier. [Background technology]

[0002] A high-frequency device is known in which a circuit element and a semiconductor chip are mounted face-up on the metal base of a package having an insulating frame on the metal base, and the pattern on the insulating frame and the semiconductor chip are electrically connected using bonding wires (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-176149 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, high-frequency signals are transmitted through bonding wires, which results in poor high-frequency characteristics. Although it is conceivable to use a microstrip line as the transmission line, this would increase the size of the line, resulting in an increase in the size of the high-frequency device.

[0005] The present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a high-frequency device and a Doherty amplifier that can be miniaturized. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a high-frequency device comprising: a metal base; a dielectric substrate mounted on the metal base; an insulator layer disposed on the metal base and covering the dielectric substrate, the insulator layer having a dielectric constant smaller than that of the dielectric substrate; and a line that overlaps the dielectric substrate when viewed in the thickness direction of the insulator layer, is disposed on the upper surface of the insulator layer, and forms a first microstrip line.

[0007] One embodiment of the present disclosure includes a divider that divides a high frequency signal, a main amplifier that amplifies one of the high frequency signals divided by the divider, a peak amplifier that amplifies the other of the high frequency signals divided by the divider, a combiner that combines the high frequency signal amplified by the main amplifier and the high frequency signal amplified by the peak amplifier, a metal base, a first semiconductor chip mounted on the metal base and having the main amplifier formed thereon, a second semiconductor chip mounted on the metal base and having the peak amplifier formed thereon, and a semiconductor chip mounted on the metal base and having a first conductor pattern formed on its upper surface and a second conductor pattern formed on its lower surface. a dielectric substrate formed on the metal base, the dielectric substrate being a microstrip line formed by the first conductor pattern and the second conductor pattern; an insulator layer provided on the metal base, covering the first semiconductor chip, the second semiconductor chip, and the dielectric substrate, the dielectric substrate having a dielectric constant smaller than that of the dielectric substrate; a first wiring provided on the upper surface of the insulator layer, electrically connecting an output electrode of the main amplifier in the first semiconductor chip to a first end of the microstrip line; and a second wiring provided on the upper surface of the insulator layer, electrically connecting a second end of the microstrip line to a combiner. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide a high-frequency device and a Doherty amplifier that can be miniaturized. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a circuit diagram of a high-frequency device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of the high-frequency device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along line AA in FIG. [Figure 4] FIG. 4 is a cross-sectional view taken along line BB in FIG. [Figure 5] FIG. 5 is a cross-sectional view of a high-frequency device according to a first comparative example. [Figure 6]FIG. 6 is a cross-sectional view of a high-frequency device according to a second comparative example. [Figure 7] FIG. 7 is a plan view of a high-frequency device according to a first modification of the first embodiment. [Figure 8] FIG. 8 is a plan view of a high-frequency device according to a second modification of the first embodiment. [Figure 9] FIG. 9 is a block diagram of an amplifier according to a second embodiment. [Figure 10] FIG. 10 is a circuit diagram of an amplifier device according to a second embodiment. [Figure 11] FIG. 11 is a circuit diagram of an amplifier device according to a second embodiment. [Figure 12] FIG. 12 is a side view of the amplifier according to the second embodiment. [Figure 13] FIG. 13 is a cross-sectional view taken along the line AA in FIG. [Figure 14] FIG. 14 is a plan view of the amplifier according to the second embodiment. [Figure 15] FIG. 15 is a cross-sectional view taken along line AA in FIG. [Figure 16] FIG. 16 is a plan view of the vicinity of the passive element 20c in the second embodiment. [Figure 17] FIG. 17 is a plan view of the passive element 20d and its vicinity in the second embodiment. [Figure 18] FIG. 18 is a plan view of the vicinity of the semiconductor chip 22a in the second embodiment. [Figure 19] FIG. 19 is a cross-sectional view taken along the line AA in FIG. [Figure 20] FIG. 20 is a plan view of the vicinity of the semiconductor chip 22b in the second embodiment. [Figure 21] FIG. 21 is a plan view of the vicinity of the semiconductor chip 22c in the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a high-frequency device including a metal base, a dielectric substrate mounted on the metal base, an insulator layer provided on the metal base and covering the dielectric substrate, the dielectric substrate having a dielectric constant smaller than that of the dielectric substrate, and a line that overlaps the dielectric substrate when viewed in a thickness direction of the insulator layer and is provided on an upper surface of the insulator layer, the line forming a first microstrip line. This makes it possible to provide a high-frequency device that can be miniaturized. (2) It is preferable that the dielectric substrate has a first conductor pattern provided on an upper surface thereof, and the line is electrically connected to the first conductor pattern. (3) It is preferable that the dielectric substrate has a second conductive pattern provided on the lower surface and bonded to the metal base, and the first conductive pattern and the second conductive pattern form a first capacitor. (4) It is preferable that the dielectric substrate has a third conductor pattern provided on its upper surface, separated from the first conductor pattern on the upper surface, and forming a second capacitor together with the second conductor pattern, and that the line electrically connects the first conductor pattern and the third conductor pattern. (5) It is preferable that the area of the line that does not overlap with the conductor pattern provided on the upper surface of the dielectric substrate when viewed in the thickness direction of the insulator layer is at least half of the line. (6) It is preferable to provide a second line that does not overlap the dielectric substrate when viewed in the thickness direction of the insulator layer, is provided on the upper surface of the insulator layer, and forms a second microstrip line together with the metal base. (7) It is preferable that a semiconductor chip is provided on the metal base, and the insulating layer covers the semiconductor chip. (8) It is preferable that the semiconductor device further comprises an electronic component mounted on the insulating layer, and wiring provided on the upper surface of the insulating layer for connecting the semiconductor chip and the electronic component. (9) It is preferable that the device comprises a semiconductor chip mounted on the metal base and equipped with an amplifier, the insulator layer covering the semiconductor chip, the dielectric substrate comprising a first conductor pattern provided on its upper surface and a second conductor pattern provided on its lower surface and joined to the metal base, and the first microstrip line and a capacitor formed by the first conductor pattern and the second conductor pattern form a matching circuit connected to the input terminal or output terminal of the amplifier. (10) One embodiment of the present disclosure includes a divider that divides a high-frequency signal, a main amplifier that amplifies one of the high-frequency signals divided by the divider, a peak amplifier that amplifies the other of the high-frequency signals divided by the divider, a combiner that combines the high-frequency signal amplified by the main amplifier and the high-frequency signal amplified by the peak amplifier, a metal base, a first semiconductor chip mounted on the metal base and having the main amplifier formed thereon, a second semiconductor chip mounted on the metal base and having the peak amplifier formed thereon, and a semiconductor chip mounted on the metal base and having a first conductor pattern formed on its upper surface and a second conductor pattern formed on its lower surface. a dielectric substrate on which the first and second conductor patterns are formed, and on which a microstrip line is formed by the first and second conductor patterns, an insulator layer provided on the metal base, covering the first semiconductor chip, the second semiconductor chip, and the dielectric substrate, and having a dielectric constant smaller than that of the dielectric substrate, a first wiring provided on the upper surface of the insulator layer, electrically connecting an output electrode of the main amplifier in the first semiconductor chip to a first end of the microstrip line, and a second wiring provided on the upper surface of the insulator layer, electrically connecting a second end of the microstrip line to a combiner. This makes it possible to provide a high-frequency device and a Doherty amplifier that can be miniaturized.

[0011] [Details of the embodiments of the present disclosure] Specific examples of high-frequency devices and Doherty amplifiers according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0012] [Example 1] 1 is a circuit diagram of a high-frequency device according to a first embodiment. As shown in FIG. 1, in a high-frequency device 100, a transmission line Z1 is connected between terminals T1 and T2. A capacitor C101 is shunt-connected to a node N1 on the terminal T1 side of the transmission line Z1. Z1 A capacitor C102 is shunt-connected to a node N2 on the terminal T2 side of the high-frequency device 100. The high-frequency device 100 functions as a CLC π-type circuit.

[0013] FIG. 2 is a plan view of the high-frequency device according to the first embodiment. FIG. 3 is a cross-sectional view taken along line AA in FIG. 2. FIG. 4 is a cross-sectional view taken along line BB in FIG. 2. In FIG. 2, the insulator layer 26 is not shown, and the metal layer 32 is indicated by cross-hatching. The thickness direction of the metal base 10 is defined as the Z direction, and the planar directions of the upper surface of the metal base 10 are defined as the X and Y directions. As shown in FIGS. 2 to 4, a passive element 20a is mounted on the metal base 10. The metal base 10 is mainly composed of, for example, copper. The passive element 20a includes a dielectric substrate 30, a metal layer 32, and a conductor pattern 34. The metal layer 32 is provided on the upper surface of the dielectric substrate 30. The metal layer 32 forms conductor patterns 33a and 33b. The conductor patterns 33a and 33b are separated on the upper surface of the dielectric substrate 30. The conductor pattern 34 is provided on the lower surface of the dielectric substrate 30. The metal layer 32 and the conductor pattern 34 are metal layers such as gold layers. The conductor pattern 34 is provided over almost the entire lower surface of the dielectric substrate 30. The dielectric constant of the dielectric substrate 30 is, for example, 3 to 200, which is higher than the dielectric constants of the insulator layers 12 and 26. The conductor pattern 34 and the metal base 10 are bonded together by a bonding material 35. The bonding material 35 is, for example, a material obtained by sintering a metal paste such as silver paste.

[0014] An insulator layer 12 is provided on the metal base 10 so as to cover the passive element 20a. The insulator layer 12 is a resin layer such as an epoxy resin. The dielectric substrate 30 has a thickness T30, and the insulator layer 12 on the dielectric substrate 30 that overlaps the dielectric substrate 30 when viewed in the Z direction has a thickness T12. Pillars (or through electrodes) 16a, 16b, and 16c are provided so as to penetrate the insulator layer 12. The pillar 16a is provided on the conductor pattern 33a, and the pillars 16b and 16c are provided on the conductor pattern 33b. The pillars 16a, 16b, and 16c are metal pillars such as copper pillars. A metal layer 18 is provided on the insulator layer 12. The metal layer 18 is a rewiring layer, and the wiring 18a, 18b, and the line 19a are formed by the metal layer 18. The metal layer 18 is, for example, a copper layer or a gold layer. Wiring 18a and line 19a are electrically connected to conductor pattern 33a via pillar 16a, and wiring 18b and line 19a are electrically connected to conductor pattern 33b via pillars 16b and 16c. An insulator layer 26 is provided on insulator layer 12 so as to cover metal layer 18. Insulator layer 26 is a resin layer made of, for example, epoxy resin.

[0015] The conductor patterns 33a and 34 sandwiching the dielectric substrate 30 form a capacitor C101, and the conductor patterns 33b and 34 sandwiching the dielectric substrate 30 form a capacitor C102. A reference potential such as a ground potential is supplied to the metal base 10. This sets the conductor pattern 34 at the ground potential. The line 19a and the conductor pattern 34 form a transmission line Z1 as a microstrip line. As a result, the capacitors C101 and C102 are shunt-connected to both ends of the transmission line Z1. By using the dielectric substrate 30 for the passive element 20a, the capacitors C101 and C102 are C102 can be made smaller.

[0016] [Comparative Example 1] FIG. 5 is a cross-sectional view of a high-frequency device according to Comparative Example 1. As shown in FIG. 5, in the high-frequency device 110 of Comparative Example 1, the line 19a formed by the metal layer 18 does not overlap the passive element 20a when viewed in the Z direction. The line 19a and the metal base 10 form a microstrip line (transmission line Z1). In a microstrip line, as the dielectric constant of the dielectric provided between the line 19a and the metal base 10 decreases, the line width for obtaining the same characteristic impedance increases. Furthermore, the physical line length for obtaining the same electrical length increases. In Comparative Example 1, the relative dielectric constant of the insulator layer 12 is low, for example, 3 to 5. This is because the insulator layer 12 is provided so as to cover the passive element 20a, and therefore a resin layer is used. Therefore, in Comparative Example 1, the transmission line Z1 becomes large, resulting in an increase in the size of the high-frequency device 110.

[0017] Comparative Example 2 FIG. 6 is a cross-sectional view of a high-frequency device according to Comparative Example 2. As shown in FIG. 6, in a high-frequency device 112 according to Comparative Example 2, the line 19a is formed by a metal layer 32 provided on the upper surface of a dielectric substrate 30. The line 19a and a conductor pattern 34 provided on the lower surface of the dielectric substrate 30 form a microstrip line (transmission line Z1). In Comparative Example 2, the high dielectric constant of the dielectric substrate 30 allows the microstrip line to be made smaller, thereby enabling the high-frequency device to be miniaturized. However, if the dielectric constant of the dielectric substrate 30 is very high, for example, 40 or higher, the dimensional accuracy of the line 19a must be high to control the characteristic impedance and electrical length of the microstrip line. Furthermore, if the dielectric loss is α, the proportional constant is K, the frequency is f, the relative dielectric constant is εr, and the dielectric loss tangent is tanδ, then the dielectric loss α is α = K × f × √εr × tanδ. Thus, materials with a high relative dielectric constant tend to have large dielectric loss. Therefore, a dielectric substrate 30 using a high dielectric material exhibits large dielectric loss, resulting in significant loss of electrical energy within the dielectric.

[0018] According to the first embodiment, the dielectric substrate 30 is mounted on the metal base 10. The insulator layer 12 covers the dielectric substrate 30 provided on the metal base 10 and has a lower dielectric constant than the dielectric substrate 30. The line 19a (first line) overlaps the dielectric substrate 30 when viewed in the thickness direction of the insulator layer 12 and is provided on the upper surface of the insulator layer 12 to form a transmission line Z1 (first microstrip line). As a result, the insulator layer 12 and the dielectric substrate 30 are provided between the line 19a and the conductor pattern 34. Therefore, the relative dielectric constant of the composite layer of the insulator layer 12 and the dielectric substrate 30 is high, so the microstrip line can be shorter than in the first comparative example, and the high-frequency device 100 can be made smaller. Furthermore, since the microstrip line can be larger than in the second comparative example, the dimensional accuracy of the line 19a can be lower. Furthermore, the loss of electrical energy due to the dielectric substrate 30 can be reduced.

[0019] From the viewpoint of miniaturization, the dielectric constant of the dielectric substrate 30 is preferably 1.5 times or more, more preferably 2 times or more, and even more preferably 5 times or more, that of the insulator layer 12. A dielectric substrate 30 with a high dielectric constant has large dielectric loss and is difficult to manufacture. From the viewpoint of loss, the dielectric constant of the dielectric substrate 30 is preferably 100 times or less, more preferably 10 times or less, and even more preferably 5 times or less that of the dielectric layer 12. For example, if miniaturization is prioritized, the dielectric constant of the dielectric substrate 30 is set to 10 to 100 times that of the insulator layer 12, and if loss is prioritized, the dielectric constant of the dielectric substrate 30 is set to 1.1 to 10 times that of the insulator layer 12.

[0020] Regarding the thickness of the dielectric substrate 30, if the thickness T30 of the dielectric substrate 30 is too thin compared to the thickness T12 of the insulator layer 12 on the dielectric substrate 30 that overlaps the dielectric substrate 30 when viewed from the Z direction, the dimensions of the transmission line Z1 will increase, resulting in a large size. From the perspective of miniaturization, the thickness T30 of the dielectric substrate 30 is preferably 1 / 300 times or more, more preferably 1 / 10 times or more, and even more preferably 1 time or more, of the thickness T12 of the insulator layer 12 on the dielectric substrate 30. If the thickness T30 of the dielectric substrate 30 is too thick compared to the thickness T12 of the insulator layer 12 on the dielectric substrate 30, the dielectric loss of the dielectric substrate 30 will increase, and dimensional precision will need to be increased. Loss of From this viewpoint, the thickness T30 of the dielectric substrate 30 is preferably equal to or less than 1 time, more preferably equal to or less than 1 / 2 time, and even more preferably equal to or less than 1 / 10 time of the thickness T12 of the insulator layer 12 on the dielectric substrate 30. For example, if miniaturization is prioritized, the thickness T30 of the dielectric substrate 30 is set to 1 / 10 to 10 times the thickness T12 of the insulator layer 12, and if loss is prioritized, the thickness T30 of the dielectric substrate 30 is set to 1 / 300 to 1 / 10 times the thickness T12 of the insulator layer 12.

[0021] In the first embodiment, the dielectric substrate 30 has a conductor pattern 33a ( No. 2 This allows the conductor patterns to be used to form transmission lines and capacitors.

[0022] The line 19a is electrically connected to the conductor pattern 33a, which allows the transmission line Z1 connected to the conductor pattern 33a to be miniaturized.

[0023] The dielectric substrate 30 is provided on the lower surface of the dielectric substrate 30 and has a conductor pattern 34 ( No. 1 Conductor patterns 33a and 34 form a capacitor C101 (first capacitor). This allows the capacitor C101 to be miniaturized, and the transmission line Z1 to be miniaturized as well.

[0024] The dielectric substrate 30 includes a conductor pattern 33b provided on the upper surface of the dielectric substrate 30. The conductor patterns 33a and 33b are separated on the upper surface of the dielectric substrate 30. The conductor pattern 33b (third conductor pattern) forms a capacitor C102 (second capacitor) together with the conductor pattern 34. The line 19a electrically connects the conductor patterns 33a and 33b. This allows for a CLC π-type high-frequency device. Because the capacitors C101 and C102 are formed by the dielectric substrate 30, they can be miniaturized. Furthermore, the transmission line Z1 can be miniaturized.

[0025] The area of line 19a where metal layer 32 and line 19a overlap as viewed in the Z direction is not affected by dielectric substrate 30 and does not contribute much to miniaturization. Therefore, the area of line 19a where line 19a does not overlap with the conductor pattern provided on the upper surface of dielectric substrate 30 as viewed in the Z direction is preferably at least 1 / 2, and more preferably at least 2 / 3 of the total area of line 19a.

[0026] [Modification 1 of Example 1] FIG. 7 is a plan view of a high-frequency device according to Modification 1 of Example 1. As shown in FIG. 7, in a high-frequency device 102 according to Modification 1 of Example 1, a conductor pattern 33h is provided on the upper surface of a dielectric substrate 30. In Modification 1 of Example 1, a line 19e is formed on the metal layer 18 similar to that of Example 1. The line 19e is not electrically connected to the conductor pattern 33h. The other configurations are the same as those of Example 1, and therefore description thereof will be omitted. As in Modification 1 of Example 1, the line 19e does not have to be connected to the conductor pattern 33h. In Modification 1 of Example 1, the line 19e can be implemented in a small size, similar to the line 19a in Example 1, and therefore the high-frequency device 102 can be miniaturized.

[0027] [Modification 2 of Example 1] Fig. 8 is a plan view of a high-frequency device according to a second modification of the first embodiment. As shown in Fig. 8, in a high-frequency device 104 according to the second modification of the first embodiment, a conductor pattern 33h on the upper surface of the dielectric substrate 30 and a line 19e are electrically connected by a pillar 16d. The other configurations are the same as those of the first embodiment, and therefore a description thereof will be omitted. As in the second modification of the first embodiment, a capacitor may be shunt-connected to the line 19e by the conductor pattern 33h.

[0028] [Example 2] Example 2 is an example of an amplifying device using the high-frequency device of Example 1. Fig. 9 is a block diagram of an amplifying device according to Example 2. As shown in Fig. 9, an amplifying device 106 includes transistors Q1 to Q3. The transistors Q1 to Q3 are, for example, FETs (Field Effect Transistors), such as GaN HEMTs (Gallium Nitride High Electron Mobility Transistors). The transistor Q1 is a driver amplifier, and the transistors Q2 and Q3 are, respectively, a main amplifier and a peak amplifier of a Doherty amplifier.

[0029] The input terminal Tin is connected to the gate G1 of the transistor Q1 via a matching circuit 60. The matching circuit 60 matches the impedance seen from the input terminal Tin to the impedance seen from the matching circuit 60 to the gate G1. A gate bias voltage is applied to the gate G1 from the bias terminal Tg1 via the matching circuit 60. The source S1 of the transistor Q1 is grounded. The drain D1 of the transistor Q1 is connected to a divider 66 via a matching circuit 61. The matching circuit 61 matches the impedance seen from the drain D1 to the matching circuit 61 and the impedance seen from the matching circuit 61 to the divider 66. A drain bias voltage is applied to the drain D1 from the bias terminal Td1. The divider 66 divides the high-frequency signal output from the matching circuit 61 into two.

[0030] The divider 66 is connected to the gate G2 of transistor Q2 via a phase shifter 68 and a matching circuit 62. The phase shifter 68 shifts the phase of the high-frequency signal output by the divider 66. The matching circuit 62 matches the impedance seen from the divider 66 at the matching circuit 62 with the impedance seen from the matching circuit 62 at the gate G2. A gate bias voltage is applied to the gate G2 from the bias terminal Tg2 via the matching circuit 62. The source S2 of transistor Q2 is grounded. The drain D2 of transistor Q2 is connected to the combiner 67 via a matching circuit 64. The matching circuit 64 matches the impedance seen from the drain D2 at the matching circuit 64 with the impedance seen from the matching circuit 64 at the combiner 67. A drain bias voltage is applied to the drain D2 from the bias terminal Td2.

[0031] The divider 66 is connected to the gate G3 of transistor Q3 via a phase shifter 69 and a matching circuit 63. The phase shifter 69 shifts the phase of the high-frequency signal output by the divider 66. The matching circuit 63 matches the impedance seen from the divider 66 at the matching circuit 63 with the impedance seen from the matching circuit 63 at the gate G3. A gate bias voltage is applied to the gate G3 from the bias terminal Tg3 via the matching circuit 63. The source S3 of transistor Q3 is grounded. The drain D3 of transistor Q3 is connected to the combiner 67 via a matching circuit 65. The matching circuit 65 matches the impedance seen from the drain D3 at the matching circuit 65 with the impedance seen from the matching circuit 65 at the combiner 67. A drain bias voltage is applied to the drain D3 from the bias terminal Td3.

[0032] The combiner 67 combines the high frequency signal output from the drain D2 and the high frequency signal output from the drain D3 and outputs the combined signal to the output terminal Tout. Bias circuits (not shown) are provided between the bias terminals Tg1 to Tg3 and Td1 to Td3 and the transistors Q1 to Q3.

[0033] The high frequency signal input from the input terminal Tin is amplified by the transistor Q1. The transistors Q2 and Q3, the divider 66, and the combiner 67 form a Doherty amplifier. The divider 66 divides the amplified high frequency signal and outputs it to the transistors Q2 and Q3. The transistor Q2 is a main amplifier and amplifies one of the high frequency signals divided by the divider 66. The transistor Q3 is a peak amplifier and amplifies the other of the high frequency signals divided by the divider 66. The combiner 67 combines the high frequency signal amplified by the transistor Q2 and the high frequency signal amplified by the transistor Q3, and outputs the combined high frequency signal to the output terminal Tout. The high frequency signal input to the input terminal Tin and output from the output terminal Tout is, for example, a signal of 0.5 GHz to 100 GHz, and is typically 0.5 GHz It is a signal of ~10GHz.

[0034] Transistor Q2 operates in class A or class B, while transistor Q3 operates in class C. When the input power is low, transistor Q2 primarily amplifies the input signal. When the input power is high, transistor Q3 amplifies the peaks of the input signal in addition to transistor Q2. This allows transistors Q2 and Q3 to amplify the input signal. When the input power is low and transistor Q3 is not operating, the impedance seen from transistor Q2 to combiner 67 is twice the load R at output terminal Tout (2R, e.g., 2 × 50 Ω). When the input power is high and transistor Q3 is operating, the impedance seen from transistor Q2 to combiner 67 and the impedance seen from transistor Q3 to combiner 67 are both load R (e.g., 50 Ω). Matching circuits 62 and 64 are adjusted so that transistor Q2 operates optimally at saturated output with a load 2R when transistor Q3 is not operating, as described above. Conversely, they are adjusted so that transistor Q2 operates optimally at saturated output with a load R when transistor Q3 is operating. Matching circuits 63 and 65 are adjusted so that when transistor Q3 is not operating, the impedance seen from combiner 67 toward transistor Q3 is open, and when transistor Q3 is operating, they are adjusted so that transistor Q3 operates optimally at saturated output at load R. To achieve this operation, matching circuit 64 uses, for example, an impedance converter formed by a transmission line.

[0035] 10 and 11 are circuit diagrams of an amplifier device according to a second embodiment. FIG. 10 mainly illustrates the circuit between the input terminal Tin and a node Nm, and FIG. 11 mainly illustrates the circuit between the node Nm and the output terminal Tout. The node Nm is included in the divider 66 of FIG. 9. As shown in FIG. 10, a transistor Q1 is formed on a semiconductor chip 22a. A capacitor C1 is shunt-connected between the input terminal Tin and a gate G1 of the transistor Q1, and a capacitor C2 and a passive element 20a are connected in series. The passive element 20a is a CLC π-type circuit including a transmission line Z1 and capacitors C101 and C102. The passive element 20a forms at least a part of a matching circuit 60 (see FIG. 9). An inductor L1 is connected between a node between the capacitor C2 and the passive element 20a and a bias terminal Tg1, and a capacitor C5 is shunt-connected to a node between the inductor L1 and the bias terminal Tg1. The inductor L1 and the capacitor C5 form at least a part of a bias circuit.

[0036] Capacitors C8 and C9 are connected in series between the drain D1 and a node Nm. An inductor L4 is shunt-connected to a node between the capacitors C8 and C9, and an inductor L5 and a capacitor C23 are shunt-connected to the node Nm. The inductors L4, L5, and capacitor C9 form at least a part of a matching circuit 61 (see FIG. 9). An inductor L3 is connected between the node between the drain D1 and the capacitor C8 and a bias terminal Td1, and a capacitor C6 is shunt-connected to a node between the inductor L3 and the bias terminal Td1. The inductor L3 and capacitor C6 form at least a part of a bias circuit.

[0037] As shown in FIG. 11, transistors Q2 and Q3 are formed on semiconductor chips 22b and 22c, respectively. Node Nm forms at least a part of a divider 66 (see FIG. 9), and node No forms at least a part of a combiner 67 (see FIG. 9). Inductors L11 and L13, a capacitor C3, and a passive element 20b are connected in series between node Nm and a gate G2 of transistor Q2. Capacitors C24 and C30 are shunt-connected to a node between inductors L11 and L13 and a node between inductor L13 and capacitor C3, respectively. Inductors L11 and L13, and capacitors C24 and C30 form at least a part of a phase shifter 68 (see FIG. 9). Passive element 20b is a CLC π-type circuit including a transmission line Z2 and capacitors C103 and C104. Passive element 20b forms at least a part of a matching circuit 62 (see FIG. 9). An inductor L6 is connected between a node between the capacitor C3 and the passive element 20b and the bias terminal Tg2. The inductor L6 forms at least a part of a bias circuit. The passive element 20c and a capacitor C10 are connected in series between the drain D2 and the node No. Capacitors C17 and C18 are shunt-connected to the node between the passive element 20c and the capacitor C10. The passive element 20c includes a transmission line Z5 and forms at least a part of a matching circuit 64 (see FIG. 9).

[0038] Inductor L12, capacitors C4 and C7, and passive element 20d are connected in series between node Nm and gate G3 of transistor Q3. Capacitor C29 and inductor L16 are shunt-connected to a node between inductor L12 and capacitor C4, and to a node between capacitors C4 and C7, respectively. Inductors L12, L16, capacitors C4, and C29 form at least a part of phase shifter 69 (see FIG. 9). Passive element 20d has a CLC π-type circuit including transmission line Z3 and capacitors C105 and C106, and a CLC π-type circuit including transmission line Z4 and capacitors C107 and C108, connected in parallel, and forms at least a part of matching circuit 63 (see FIG. 9). Inductor L2 is connected between a node between capacitor C7 and passive element 20d and bias terminal Tg3. Inductor L2 forms at least a part of the bias circuit. Capacitor C15 is connected in series between drain D3 and node No. Capacitors C11 to C14 are shunt-connected to a node between drain D3 and capacitor C15. Drain D3 and capacitors C11 to C14 form at least a part of matching circuit 65 (see FIG. 9).

[0039] FIG. 12 is a side view of an amplifier 106 according to a second embodiment. FIG. 13 is a cross-sectional view taken along line AA in FIG. 12. As shown in FIGS. 12 and 13, the amplifier 106 includes a lead frame 11 and insulator layers 12 and 26 provided on the lead frame 11. The lead frame 11 includes a metal base 10 and a terminal 10a. The metal base 10 is exposed from the lower surface of the insulator layer 12. The terminal 10a is exposed from the lower surface and side surface of the insulator layer 12. The metal base 10 and the terminal 10a are electrically isolated by the insulator layer 12. A ground potential is supplied to the metal base 10. The terminal 10a corresponds to the input terminal Tin, the output terminal Tout, and the bias terminals Tg1 to Tg3 and Td1 to Td3. The lead frame 11 is, for example, a copper plate plated with silver. The insulator layers 12 and 26 are, for example, resin layers made of epoxy resin or the like.

[0040] FIG. 14 is a plan view of an amplifier device 106 according to a second embodiment. FIG. 15 is a cross-sectional view taken along the line AA in FIG. 14. FIG. 14 mainly shows a metal layer 18, through electrodes 14a and 14b, pillars 16, passive elements 20a to 20d, and semiconductor chips 22a to 22c. The metal layer 18 is indicated by cross-hatching, and a large dotted circle within the metal layer 18 indicates the through electrode 14b, a small dotted circle indicates the pillar 16, and a dotted circle of a size between the through electrode 14b and the pillar 16 indicates the through electrode 14a. FIG. 15 is a schematic diagram, and the dimensions in the X direction do not correspond to those in FIG. 14. The thickness direction of the metal base 10 is the Z direction, the long side direction of the high-frequency device is the X direction, and the short side direction is the Y direction.

[0041] As shown in FIG. 15, passive elements 20a to 20d and semiconductor chips 22a to 22c are mounted on a metal base 10 (see FIG. 14). For example, sintered silver paste is used to bond the passive elements 20a to 20d and semiconductor chips 22a to 22c to the metal base 10. An insulator layer 12 is provided on a lead frame 11 so as to cover the passive elements 20a to 20d and semiconductor chips 22a to 22c. The upper surface of the insulator layer 12 is substantially flat. A metal layer 18 is provided on the insulator layer 12. The metal layer 18 forms a rewiring layer. The metal layer 18 is, for example, a gold layer or a copper layer.

[0042] Through electrodes 14a and 14b are provided that penetrate the insulator layer 12. The through electrode 14a electrically connects and shorts the metal layer 18 and the metal base 10. The through electrode 14b electrically connects and shorts the metal layer 18 and the terminal 10a. The through electrodes 14a and 14b are, for example, gold or copper layers. Pillars 16 are provided that penetrate the insulator layer 12 and connect the metal layer 18 to the passive elements 20a to 20d and the semiconductor chips 22a to 22c. The pillars 16 are, for example, gold or copper layers. An electronic component 24 is mounted on the insulator layer 12. An electrode 25 of the electronic component 24 is bonded to the metal layer 18. A solder such as SnAgCu is used to bond the electrode 25 to the metal layer 18. The electronic component 24 is, for example, a discrete component, such as a chip resistor, a chip capacitor, or a chip inductor. An insulator layer 26 is provided on the insulator layer 12 so as to cover the electronic component 24. The insulating layer 26 is, for example, a resin layer such as an epoxy resin, etc. The lead frame 11 has a thickness of, for example, 200 μm, the insulating layer 12 has a thickness of, for example, 200 μm, and the insulating layer 26 has a thickness of, for example, 400 μm.

[0043] As shown in FIG. 14, a rewiring layer made of a metal layer 18 is provided on the insulator layer 12. The through electrodes 14b electrically connect the metal layer 18 to the terminals 10a, which are the input terminal Tin, the output terminal Tout, and the bias terminals Tg1 to Tg3 and Td1 to Td3. The through electrodes 14a electrically connect the metal layer 18 to the metal base 10. The metal layer 18 electrically connected to the metal base 10 by the through electrodes 14a serves as a ground pattern Gnd. Electronic components 24, such as capacitors, inductors, and resistors, are mounted on the metal layer 18. The pillars 16 electrically connect the metal layer 18 to the passive elements 20a to 20d and conductor patterns provided on the upper surfaces of the semiconductor chips 22a to 22c.

[0044] The passive elements 20a and 20b are the passive element 20a described in FIGS. 1 to 4 of the first embodiment. In FIG. 14, Y In the direction of - Y The wiring 18a extending from the side is connected to the capacitor C2 and the inductor L1.Y + in direction Y 1 to 4, the passive element 20a functions as capacitors C101 and C102, and the line 19a above the passive element 20a functions as a transmission line Z1 (the conductor patterns 33a and 33b shown in FIGS. 1 to 4 are omitted and not shown in FIGS. 14 and 15). In the passive element 20b, the line 18a is connected to the capacitor C3 and the inductor L6, and the line 18b is connected to the semiconductor chip 22b (see FIG. 14). The passive element 20b functions as capacitors C103 and C104, similar to the capacitors C101 and C102 of the passive element 20a, and the line 19a above the passive element 20b functions as a transmission line Z1 (the conductor patterns 33a and 33b shown in FIGS. 1 to 4 are omitted and not shown in FIGS. 14 and 15). of The line (corresponding to the line 19a in FIG. 2) functions as the transmission line Z2. The passive element 20a and the transmission line Z1 function as a matching circuit 60, and the passive element 20b and the transmission line Z2 function as a matching circuit 62.

[0045] Fig. 16 is a plan view of the vicinity of passive element 20c in Example 2. Conductor pattern 33c is provided on dielectric substrate 30 (conductive pattern 33c is omitted and not shown in Figs. 14 and 15). Wiring 18d to 18f are formed by metal layer 18. Wiring 18d is connected to semiconductor chip 22b, wiring 18e is connected to capacitor C10, and wiring 18f is connected to capacitor C17 (see Fig. 14). Wiring 18d to 18f are electrically connected to conductive pattern 33c via pillars 16, respectively. Conductor pattern 33c and conductive pattern 34 (see Figs. 3 and 4) provided on the underside of dielectric substrate 30 form a transmission line. Z5 Form a transmission line. Z5 forms part of the matching circuit 64. The cross-sectional structure of the passive element 20c is the same as that shown in Figures 3 and 4, and therefore a description thereof will be omitted.

[0046] FIG. 17 is a plan view of the vicinity of passive element 20d in Example 2. Conductor patterns 33d-33g are provided on dielectric substrate 30 (the conductor patterns 33d-33g are omitted and not shown in FIGS. 14 and 15). Lines 19c and 19d are formed by metal layer 18. Wiring 18a is connected to capacitor C7 and inductor L2, and wiring 18b1 and 18b2 are connected to semiconductor chip 22c (see FIG. 14). Line 19c electrically connects conductor patterns 33d and 33e via pillar 16. Line 19d electrically connects conductor patterns 33f and 33g via pillar 16. Conductor patterns 33d-33g and conductor pattern 34 (see FIGS. 3 and 4) provided on the lower surface of dielectric substrate 30 form capacitors C105-C108, respectively. The lines 19c and 19d and the conductor pattern 34 are transmission lines. Z3 and Z4 The passive element 20d and the lines 19c and 19d function as a matching circuit 63. The cross-sectional structure of the passive element 20d is the same as that shown in FIGS. 3 and 4, and therefore a description thereof will be omitted.

[0047] 3 and 4, the total thickness T30+T12 of the thickness T30 of the dielectric substrate 30 and the thickness T12 of the insulating layer 12 on the dielectric substrate 30 is, for example, 200 μm to 250 μm. μm The dielectric constant of the insulator layer 12 is, for example, 3.0 to 3.5. When priority is given to miniaturization, the dielectric constant of the dielectric substrate 30 in the passive elements 20a, 20b, and 20d is, for example, 150, and the thickness T30 of the dielectric substrate 30 is, for example, 120 μm. The dielectric constant of the dielectric substrate 30 in the passive element 20c is, for example, 40, and the thickness T30 of the dielectric substrate 30 is, for example, 120 μm. When priority is given to loss, the dielectric constant of the dielectric substrate 30 in the passive elements 20a to 20d is, for example, 5 to 30, and the thickness T30 of the dielectric substrate 30 is, for example, 1 μm to 25 μm.

[0048] FIG. 18 is a plan view of the semiconductor chip 22a and its vicinity in Example 2. FIG. 19 is a cross-sectional view taken along the line AA in FIG. 18. As shown in FIGS. 18 and 19, in the semiconductor chip 22a, a semiconductor layer 37 is provided on a substrate 36. When the transistors Q1 to Q3 are GaN HEMTs, the substrate 36 is, for example, a SiC substrate or a sapphire substrate. The semiconductor layer 37 includes a GaN channel layer and an AlGaN barrier layer. A metal layer 38 is provided on the upper surface of the semiconductor layer 37, and a metal layer 39 is provided on the lower surface of the substrate 36. The metal layer 38 forms a gate electrode 38a and a drain electrode 38b (conductor patterns 38a and 38b are omitted and not shown in FIGS. 14 and 15). The metal layer 39 is electrically connected to, for example, a source electrode. The metal layer 39 is bonded to the metal base 10 via a bonding material 35. The bonding material 35 is, for example, a sintered metal paste. The wirings 18b and 18c are electrically connected to the gate electrode 38a and the drain electrode 38b, respectively, via the pillar 16. The wiring 18b is connected to the passive element 20a, and the wiring 18c is connected to the capacitor C8 and the inductor L3 (see FIG. 14).

[0049] Fig. 20 is a plan view of the vicinity of a semiconductor chip 22b in Example 2. As shown in Fig. 20, in the semiconductor chip 22b, the wirings 18b and 18c are electrically connected to the gate electrode 38a and the drain electrode 38b, respectively, via pillars 16 (in Figs. 14 and 15, 38a and 38b are omitted as conductor patterns and are not shown). The source electrode is electrically connected to the metal base 10. The wiring 18b is connected to the passive element 20b, and the wiring 18c is connected to the passive element 20c and the bias terminal Td2 (see Fig. 14). The cross-sectional structure of the semiconductor chip 22b is the same as that in Fig. 19, and therefore a description thereof will be omitted.

[0050] FIG. 21 is a plan view of the vicinity of a semiconductor chip 22c in Example 2. As shown in FIG. 21, in the semiconductor chip 22c, wirings 18b1 and 18b2 are electrically connected to the gate electrode 38a via the pillar 16, and wiring 18c is electrically connected to the drain electrode 38b via the pillar 16 (in FIGS. 14 and 15, 38a and 38b are omitted as conductor patterns and are not shown). The source electrode is electrically connected to the metal base 10. Wirings 18b1 and 18b2 are connected to the passive element 20d, and wiring 18c is connected to capacitors C11 to C15 and a bias terminal Td3 (see FIG. 14). The cross-sectional structure of the semiconductor chip 22c is the same as that in FIG. 19, and therefore a description thereof will be omitted.

[0051] In the second embodiment, a line (second line: for example, the line between the inductor L11 and the capacitor C3 in FIG. 14) provided on the upper surface of the insulator layer 12 and not overlapping with the dielectric substrate 30 as viewed in the Z direction forms a second microstrip line together with the metal base 10. This allows the first line overlapping with the dielectric substrate 30 as viewed in the Z direction and the second line not overlapping with the dielectric substrate 30 to be used depending on the purpose. For example, when size is important, the first line overlapping with the dielectric substrate 30 as viewed in the Z direction is used, and when loss is important, the second line not overlapping with the dielectric substrate 30 as viewed in the Z direction is used.

[0052] The semiconductor chips 22a to 22c are mounted on a metal base 10. The semiconductor chips 22a to 22c are covered with an insulating layer 12. This allows the passive elements 20a to 20d and the semiconductor chips 22a to 22c to be mounted on the same metal base 10.

[0053] The electronic components 24 are mounted on the insulating layer 12. Wiring formed by the metal layer 18 is provided on the upper surface of the insulating layer 12 and connects the semiconductor chips 22a to 22c and the electronic components 24. This allows the electronic components 24 to be mounted.

[0054] The semiconductor chips 22a to 22c include transistors Q1 to Q3 as amplifiers.Z3 and Z4 The microstrip lines and the capacitors C101 to C108 form matching circuits 60, 62, and 63 connected to the input terminals or output terminals of the transistors Q1 to Q3. This allows the matching circuits 60, 62, and 63 to be made smaller.

[0055] An impedance converter is used in the matching circuit 64 of the main amplifier (transistor Q2) in the Doherty amplifier. The impedance converter is formed by a transmission line (e.g., a microstrip line). The electrical length of the transmission line is, for example, 1 / 4 wavelength. When the impedance converter is formed using a microstrip line made of a metal layer 18 and a metal base 10, if the relative permittivity of the insulator layer 12 is 3.3 and the thickness is 200 μm, the width and length of the line for 3.6 GHz are 400 μm and 12.8 mm. If the characteristic impedance is 5.4 Ω and the electrical length is 28°, the line becomes shorter but wider, with a width and length of 7.2 mm and 3.6 mm. In this way, the impedance converter becomes larger.

[0056] In the second embodiment, as shown in FIGS. 14 to 16, a semiconductor chip 22b (first semiconductor chip) on which a transistor Q2 (main amplifier) is formed and a semiconductor chip 22c (second semiconductor chip) on which a transistor Q3 (peak amplifier) is formed are mounted on a metal base 10. Furthermore, a conductor pattern 33c ( No. 2 Conductor pattern) is formed on the bottom surface, and conductive pattern 34 ( No. 1A dielectric substrate 30 is mounted on the metal base 10. The dielectric substrate 30 has a conductor pattern 33c and a transmission line Z5 (microstrip line) formed thereon. The conductor patterns 33c and 34 form a transmission line Z5 (microstrip line). The insulator layer 12 is provided on the metal base 10 and covers the semiconductor chips 22b and 22c and the dielectric substrate 30. The wiring 18d (first wiring) is provided on the upper surface of the insulator layer 12 and electrically connects the drain electrode 38b (output electrode of the main amplifier) of the semiconductor chip 22b to the first end of the transmission line Z5. The wiring 18e (second wiring) is provided on the upper surface of the insulator layer 12 and electrically connects the second end of the transmission line Z5 to the combiner 67. Because the dielectric constant of the dielectric substrate 30 is higher than that of the insulator layer 12, the impedance converter formed by the transmission line Z5 can be made smaller. For example, if the dielectric constant of the dielectric substrate 30 is 40 and the thickness of the dielectric substrate 30 is 120 μm, a line with a characteristic impedance of 5.4 Ω and an electrical length of 28° can be realized in a size of 1.1 mm×1.1 mm.

[0057] If miniaturization is prioritized, the dielectric constant of the dielectric substrate 30 is preferably 10 to 100 times that of the insulator layer 12. If loss is prioritized, the dielectric constant of the dielectric substrate 30 is preferably 1.1 to 10 times that of the insulator layer 12.

[0058] In the second embodiment, an amplifier device has been described as an example of the high-frequency device, but the high-frequency device may be something other than an amplifier device. Although a Doherty amplifier has been described as an example of the amplifier device, an amplifier device other than a Doherty amplifier may also be used. Although an example has been described in which the high-frequency device includes four passive elements 20a to 20d and three semiconductor chips 22a to 22c, the high-frequency device may include one or more passive elements and one or more semiconductor chips.

[0059] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0060] 10 Metal Base 10a terminal 11 Lead frame 12, 26 Insulator layer 14a, 14b Through electrode 16 Pillar 18, 32, 38, 39 metal layer 18a~18c, 18f wiring 18d Wiring (1st wiring) 18e Wiring (second wiring) 19a, 19c~19e tracks 20a~22d Passive elements 22a~22c Semiconductor chips 24 Electronic Components 25 electrodes 30 Dielectric substrate 33a Conductive pattern (first conductive pattern) 33b Conductive pattern (third conductive pattern) 34 Conductive pattern (second conductive pattern) 33c~33g Conductor pattern 36 PCB 37 Semiconductor layer 38a Gate electrode 38b Drain electrode 60~65 matching circuit 66 Distributor 67 Synthesizer 68, 69 Phase shifter 100, 102, 104, 110, 112 High frequency devices 106 Amplification Device C101 Capacitor (first capacitor) C102 Capacitor (second capacitor) Z1, Z3 Transmission line (microstrip line) Q2 Transistor (main amplifier) Q3 Transistor (Peak Amplifier)

Claims

1. A metal base and a dielectric substrate mounted on the metal base; an insulator layer provided on the metal base and covering the dielectric substrate, the insulator layer having a dielectric constant smaller than that of the dielectric substrate; a line provided on an upper surface of the insulator layer, the line overlapping the dielectric substrate when viewed in a thickness direction of the insulator layer; Equipped with the dielectric substrate has a first conductor pattern provided on a lower surface of the dielectric substrate and bonded to the metal base; The line and the first conductor pattern form a first microstrip line.

2. the dielectric substrate includes a second conductor pattern provided on an upper surface thereof; The high frequency device according to claim 1 , wherein the line is electrically connected to the second conductive pattern.

3. A high-frequency device as described in Claim 2, wherein the first conductive pattern and the second conductive pattern form a first capacitor.

4. the dielectric substrate includes a third conductor pattern provided on an upper surface thereof, separated from the second conductor pattern on the upper surface, and forming a second capacitor together with the first conductor pattern; The high-frequency device according to claim 3 , wherein the line electrically connects the second conductive pattern and the third conductive pattern.

5. A high-frequency device according to any one of claims 1 to 4, wherein the area of the line that does not overlap with the conductor pattern provided on the upper surface of the dielectric substrate when viewed in the thickness direction of the insulator layer is at least half of the line.

6. 6. The high-frequency device according to claim 1, further comprising a second line that does not overlap the dielectric substrate when viewed in the thickness direction of the insulator layer, is provided on the upper surface of the insulator layer, and forms a second microstrip line together with the metal base.

7. a semiconductor chip provided on the metal base; The high frequency device according to claim 1 , wherein the insulating layer covers the semiconductor chip.

8. an electronic component mounted on the insulator layer; The high frequency device according to claim 7 , further comprising wiring provided on the upper surface of the insulating layer, the wiring connecting the semiconductor chip and the electronic component.

9. a semiconductor chip mounted on the metal base and including an amplifier; the insulator layer covers the semiconductor chip; the dielectric substrate includes a second conductor pattern provided on an upper surface thereof; 2. The high-frequency device according to claim 1, wherein the first microstrip line and a capacitor formed by the first conductor pattern and the second conductor pattern form a matching circuit connected to an input terminal or an output terminal of the amplifier.

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