Power semiconductor module and power conversion device

Abstract

To provide a power semiconductor module including an internal wire structure capable of reducing electric vibrations generated in an internal wire, and an electric power conversion device.SOLUTION: In a power semiconductor module comprising: an upper arm part 20 including a first substrate on which a first switching element is mounted and a second substrate on which a second switching element is mounted; and a lower arm part 10 including a third substrate on which a third switching element is mounted and a fourth substrate on which a fourth switching element is mounted, the upper arm part includes a first wire 21 connecting an emitter or a source of the first switching element with an emitter or a source of the second switching element in order to connect the first substrate and the second substrate. The first wire is disposed at a position farther from the lower arm part than an end of a power semiconductor chip which is located at a farthest position from the lower arm part, at a side away from the lower arm part in the power semiconductor chip of the upper arm part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power semiconductor module and a power conversion device. [Background technology]

[0002] In recent years, there has been a demand for higher output density in inverter devices as power conversion devices, and power conversion devices have become smaller and lighter, resulting in a strong demand for smaller power conversion devices. Power conversion devices have the function of converting DC power supplied from a DC power source into AC power to be supplied to an AC electrical load such as a rotating electric machine, or the function of converting AC power generated by a rotating electric machine into DC power to be supplied to a DC power source. To perform this conversion function, power conversion devices have an inverter circuit with a power semiconductor module, which converts DC power to AC power or AC power to DC power by repeatedly conducting and interrupting the power semiconductor module.

[0003] A power semiconductor module is constructed by connecting multiple power semiconductor elements mounted inside in parallel to obtain high output. For example, a power semiconductor module is known in which multiple insulating substrates, each mounting multiple power semiconductor elements, are connected in parallel by soldering them onto a heat dissipation base.

[0004] Patent Document 1, for example, is known as a conventional technology for a power semiconductor module equipped with multiple power semiconductor elements mounted and connected in parallel. Patent Document 1 proposes an inverter module including a first insulating substrate having a first switching element, a second insulating substrate having a second switching element connected in parallel to the first switching element, and a wiring board electrically connected to common wiring patterns of the first switching element on the first insulating substrate and the second switching element on the second insulating substrate. The common wiring patterns are connected by a board-to-board connecting wiring member having an inductance smaller than the inductance formed in the current path of the first switching element on the wiring board and the inductance formed in the current path of the second switching element on the wiring board. Patent Document 1 claims that internal board-to-board wiring, which has a smaller inductance than the external wiring, can reduce wiring inductance and improve current imbalance.

[0005] Furthermore, Patent Document 2 discloses a 2-in-1 module 144 that configures a half-bridge circuit. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-278772 [Patent Document 2] Japanese Patent Publication No. 2020-124030 Summary of the Invention [Problem to be solved by the invention]

[0007] To further reduce the size of power conversion circuits, a 2-in-1 module has been proposed in which the upper and lower arms are mounted on the same power semiconductor module, as in the above-mentioned Patent Document 2, and there is a growing demand for lower inductance in the internal wiring.

[0008] In modules with low inductance internal wiring, variations in internal wiring inductance can cause voltage imbalances between the insulating substrates connected in parallel during the switching operation of the power semiconductor elements, which can trigger LC resonance between the parasitic capacitance C of the power semiconductor elements and the parasitic inductance L present in the electrical circuit.When the LC resonance is amplified, the oscillating voltage gradually increases, eventually destroying the power semiconductor elements.

[0009] Here, Patent Document 2 describes that in order to suppress gate voltage oscillation during switching, the sixth main electrode 14 and the eighth main electrode 16 are connected by a twelfth conductor 54. However, Patent Document 2 only discloses that the twelfth conductor 54 is disposed in a position approximately on a straight line between the sixth main electrode 14 and the eighth main electrode 16.

[0010] As a result of investigations by the present inventors, it has been found that the effect of suppressing gate voltage oscillations is not necessarily sufficient with the configuration described in Patent Document 2.

[0011] The present invention has been made in view of the above-mentioned problems, and has an object to provide an internal wiring structure that can reduce electrical vibrations generated in the internal wiring of a power semiconductor module. [Means for solving the problem]

[0012] One aspect of the present invention for solving the above-mentioned problems is a power semiconductor module including: an upper arm having a first substrate on which at least one power semiconductor chip including a first switching element is mounted; and a second substrate on which at least one power semiconductor chip including a second switching element connected in parallel to the first switching element is mounted; and a lower arm having a third substrate on which at least one power semiconductor chip including a third switching element is mounted; and a fourth substrate on which at least one power semiconductor chip including a fourth switching element connected in parallel to the third switching element is mounted, wherein the upper arm is a wiring connecting the first substrate and the second substrate, and the wiring is a wiring that is connected to an emitter or a source of the first switching element. and A first wiring that connects the emitter or source of the second switching element a second wiring that connects the first substrate and the third substrate and connects the emitter or source of the first switching element and the collector or drain of the third switching element; a third wiring that connects the second substrate and the fourth substrate and connects the emitter or source of the second switching element and the collector or drain of the fourth switching element; and a fourth wiring that connects the third substrate and the fourth substrate and connects the emitter or source of the third switching element and the emitter or source of the fourth switching element. and the first wiring is arranged at a position farther from the lower arm than an end of a power semiconductor chip farthest from the lower arm among the power semiconductor chips of the upper arm. , the total impedance of the first wiring, the second wiring, and the third wiring is greater than the impedance of the fourth wiring. The power semiconductor module is characterized by the above. [Effects of the Invention]

[0013] According to the present invention, it is possible to provide an internal wiring structure that can reduce electrical vibrations generated in the internal wiring of a power semiconductor module.

[0014] The specific effects of the present invention are as follows.

[0015] A) It is possible to reduce the inductance of the emitter-to-source wiring (or source-to-source wiring, hereinafter the same) of the power semiconductor elements on the upper arm, while increasing the inductance of the collector-to-collector wiring (or drain-to-drain wiring, hereinafter the same) of the power semiconductor elements on the lower arm. B) Increasing the inductance between collectors and decreasing the inductance between emitters makes it possible to converge the voltage oscillation between boards caused by the impedance difference between the boards connected in parallel. [Brief explanation of the drawings]

[0016] [Figure 1] Diagram of the internal wiring structure of the power semiconductor module of the present invention [Figure 2] Equivalent circuit diagram of the internal wiring of the power semiconductor module of the present invention [Figure 3] A simplified equivalent circuit diagram of the internal wiring of the power semiconductor module of the present invention. [Figure 4] Image of the solution S in the complex plane [Figure 5] A diagram showing the combination of Lpos and Lneg for vibration convergence [Figure 6] Comparison diagram of conventional internal wiring structure and internal wiring structure of the present invention [Figure 7] Operating waveforms of a power semiconductor element when using a conventional internal wiring structure and an internal wiring structure of the present invention, respectively [Figure 8] Wiring structure of a power semiconductor module according to a third embodiment of the present invention [Figure 9] Wiring structure of a power semiconductor module according to a fourth embodiment of the present invention [Figure 10] Wiring structure of a power semiconductor module according to a fifth embodiment of the present invention DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, the wiring structure of the power conversion device according to the present invention will be described with reference to the drawings. Note that the same elements in each drawing are denoted by the same reference numerals, and duplicated explanations will be omitted. [Example]

[0018] Fig. 1 is a diagram showing the internal wiring structure of a power semiconductor module of the present invention. As shown in Fig. 1, the internal wiring structure of a power semiconductor module 1 of the present invention is configured to include an upper arm section 20 in which a plurality of switching elements are connected in parallel, and a lower arm section 10 in which a plurality of switching elements are also connected in parallel, and the upper arm section 20 and the lower arm section 10 are connected by wiring 30, 31, and further connected to an AC terminal 2.

[0019] A first insulating wiring board 5 of the upper arm portion, on which at least one power semiconductor chip including a switching element is mounted, and a second insulating wiring board 6 of the upper arm portion, on which at least one power semiconductor chip including a switching element is similarly mounted, are connected in parallel to the upper arm portion 20. Here, the switching element of the first insulating wiring board 5 of the upper arm portion and the switching element of the second insulating wiring board 6 of the upper arm portion are connected in parallel.

[0020] FIG. 1 shows an example in which an IGBT is used as the switching element, and two IGBT chips and two diode chips connected in parallel are mounted on a single insulating wiring board as power semiconductor chips. Therefore, four IGBT chips and four diode chips are mounted in the entire upper arm 20. The number of IGBT chips and diode chips may be other than four. One IGBT chip and one diode chip may be mounted on a single insulating wiring board. Furthermore, the switching elements are not limited to IGBTs. MOSFETs may be used as the switching elements, and only MOSFET chips or MOSFET chips and diode chips may be mounted as power semiconductor chips. In the following description, an example is described in which an IGBT is used as the switching element, and therefore the terms emitter and collector are used. However, when a MOSFET is used as the switching element, the emitter may be read as the source and the collector as the drain, respectively.

[0021] The first insulating wiring plate 5 of the upper arm portion has wiring portion 22 for connecting the emitters (or sources, hereinafter the same) of the switching elements, and wiring portion 23 for connecting the collectors (or drains, hereinafter the same) of the switching elements. The second insulating wiring plate 6 of the upper arm portion has wiring portion 24 for connecting the emitters of the switching elements, and wiring portion 25 for connecting the collectors of the switching elements. Collector wiring portion 23 of the first insulating wiring plate 5 of the upper arm portion and collector wiring portion 25 of the second insulating wiring plate 6 of the upper arm portion are connected to the positive terminal 3.

[0022] In addition, upper arm portion 20 is provided with an upper arm gate wiring portion 28 and an upper arm emitter sense wiring portion 29 as wiring for control signals of switching elements mounted on the insulating wiring plate of the upper arm.

[0023] Similar to the upper arm portion 20, the lower arm portion 10 is connected in parallel to a third insulating wiring board 7 of the lower arm portion, which is mounted with at least one power semiconductor chip including a switching element, and a fourth insulating wiring board 8 of the lower arm portion, which is also mounted with at least one power semiconductor chip including a switching element.

[0024] FIG. 1 shows an example in which, similar to the upper arm portion 20, the lower arm portion 10 as a whole is equipped with four IGBT chips and four diode chips, but as already mentioned in the explanation of the upper arm portion 20, this is not limited to this.

[0025] The third insulating wiring board 7 of the lower arm has wiring portion 12 for connecting the emitters of the switching elements and wiring portion 13 for connecting the collectors of the switching elements, while the fourth insulating wiring board 8 of the lower arm has wiring portion 14 for connecting the emitters of the switching elements and wiring portion 15 for connecting the collectors of the switching elements.

[0026] The emitter wiring portion 12 and the emitter wiring portion 14 of the third insulating wiring board 7 of the lower arm portion are connected to the negative electrode terminal 4 .

[0027] In addition, lower arm portion 10 is provided with a lower arm gate wiring portion 18 and a lower arm emitter sense wiring portion 19 as wiring for control signals of switching elements mounted on the insulating wiring plate of the lower arm.

[0028] Furthermore, the upper arm portion 20 has an upper arm inter-substrate wiring portion 21 between the first insulating wiring plate 5 of the upper arm portion and the second insulating wiring plate 6 of the upper arm portion for connecting the upper arm emitter wiring portion 22 and the upper arm emitter wiring portion 24 between insulating substrates.

[0029] The lower arm portion 10 also has a lower arm emitter wiring portion 12 and a lower arm inter-substrate wiring portion 11 for connecting the lower arm emitter wiring portion 14 between insulating substrates between the third insulating wiring plate 7 of the lower arm portion and the fourth insulating wiring plate 8 of the lower arm portion.

[0030] Multiple power semiconductor chips are mounted on the first insulating wiring board 5 and the second insulating wiring board 6 of the upper arm portion 20, and the end of the chip closest to the lower arm portion 10 among the multiple chips is designated as chip end 201, and the end of the chip farthest from the lower arm portion 10 is designated as chip end 202.

[0031] In addition, multiple power semiconductor chips are mounted on the third insulating wiring board 7 and the fourth insulating wiring board 8 of the lower arm portion 10, and the end of the chip closest to the upper arm portion 20 among the multiple chips is referred to as chip end 101, and the end of the chip farthest from the upper arm portion 20 is referred to as chip end 102.

[0032] The present invention is characterized in that the inter-substrate wiring section (first wiring) 21 of the upper arm section 20 is arranged in a direction away from the lower arm (at a farther position) than the chip end 202 farther from the lower arm.

[0033] Next, an equivalent circuit diagram of the internal wiring structure of the power semiconductor module according to the present invention will be described with reference to Fig. 2. Fig. 2 is an equivalent circuit diagram of the internal wiring structure of the power semiconductor module according to the present invention. In Fig. 2, an upper arm portion 20 and a lower arm portion 10 are arranged in correspondence with Fig. 1.

[0034] The plurality of power semiconductor elements (here, IGBTs and diodes) mounted on first insulating wiring board 5 of upper arm portion 20 shown in FIG. 1 are collectively shown as power semiconductor elements 26 in FIG.

[0035] The plurality of power semiconductor elements mounted on the second insulating wiring board 6 of the upper arm portion 20 shown in FIG. 1 are collectively referred to as power semiconductor elements 27 in FIG.

[0036] The plurality of power semiconductor elements mounted on the third insulating wiring board 7 of the lower arm portion 10 shown in FIG. 1 are collectively referred to as power semiconductor elements 16 in FIG.

[0037] The plurality of power semiconductor elements mounted on third insulating wiring board 8 of lower arm portion 10 shown in FIG. 1 are collectively referred to as power semiconductor elements 17 in FIG.

[0038] A parasitic inductance component exists due to the wiring between the upper arm power semiconductor element 26, the upper arm power semiconductor element 27, and the positive electrode terminal 3.

[0039] The inductance components LP_L and LP_R in Figure 2 are formed by the collector wiring portion 23 and the collector wiring portion 25 of the upper arm between the first insulating wiring board 5 and the second insulating wiring board 6 shown in Figure 1, and Mp is formed as a mutual inductance.

[0040] The upper arm gate wiring 28 shown in FIG. 1 forms parasitic inductance components Lgup_L and Lgup_R of the upper arm gate wiring shown in FIG. 2, and MGup is formed as mutual inductance.

[0041] On the other hand, the upper arm emitter sense wiring 29 shown in FIG. 1 forms parasitic inductance components LESup_L and LESup_R of the upper arm emitter sense wiring shown in FIG. 2, and MEup is formed as mutual inductance.

[0042] A parasitic inductance component exists due to wiring between the power semiconductor element 16 of the lower arm, the power semiconductor element 17 of the lower arm, and the negative electrode terminal 4.

[0043] The emitter wiring portion 12 of the lower arm between the third insulating wiring board 7 and the fourth insulating wiring board 8 shown in Figure 1 and the emitter wiring portion 14 of the lower arm form inductance components LN_L and LN_R in Figure 2, forming a mutual inductance MN.

[0044] The lower arm gate wiring 18 shown in FIG. 1 forms parasitic inductance components Lglw_L and Lglw_R of the lower arm gate wiring shown in FIG. 2, and MGlw is formed as mutual inductance.

[0045] On the other hand, the parasitic inductance components LESlw_L and LESlw_R of the lower-arm emitter sense wire shown in FIG. 2 are formed by the lower-arm emitter sense wire 19 shown in FIG. 1, and MElw is formed as mutual inductance.

[0046] Next, we will explain the parasitic inductance between the emitters of the upper arm and the collectors of the lower arm. As explained in Figure 1, upper arm section 20 has upper arm emitter wiring section 22 and upper arm emitter wiring section 24, and lower arm section 10 has lower arm collector wiring section 13 and lower arm collector wiring section 15.

[0047] The emitter wiring portion 22 of the upper arm and the collector wiring portion 13 of the lower arm are connected by upper and lower arm wiring 30 shown in Fig. 1. The emitter wiring portion 24 of the upper arm and the collector wiring portion 15 of the lower arm are connected by upper and lower arm wiring 31 shown in Fig. 1.

[0048] As explained in FIG. 1, the upper arm emitter wiring portion 22 and the upper arm emitter wiring portion 24 are connected by the upper arm inter-substrate wiring 21.

[0049] Therefore, the emitter of the upper arm and the collector of the lower arm are connected by these wiring groups (upper arm emitter wiring parts 22, 24, lower arm collector wiring parts 13, 15, upper and lower arm inter-arm wiring parts 30, 31, upper arm inter-substrate wiring part 21).

[0050] These wiring groups form the parasitic inductance components Leup_L and Leup_R, Lac_L and Lac_R, and LClw_L and LClw_R shown in FIG. 2, respectively.

[0051] Lac_L and Lac_R are parasitic inductance components of the inter-substrate wiring 21 of the upper arm, Leup_L and Leup_R are parasitic inductance components of the emitter wiring portions 22 and 24 of the upper arm, and LClw_L and LClw_R are parasitic inductance components of the collector wiring portions 13 and 15 of the lower arm.

[0052] 1 of the present invention, by arranging the inter-substrate wiring 21 of the upper arm farther from the lower arm than the chip end 202 farthest from the lower arm, that is, by arranging it as far away from the lower arm as possible, it becomes possible to reduce the emitter wiring inductances Leup_L and Leup_R of the upper arm and increase the collector wiring inductances LClw_L and LClw_R of the lower arm, thereby making it possible to create a significant difference in magnitude relationship. Therefore, it becomes possible to obtain parasitic inductance components that satisfy the following equation.

[0053]

number

[0054]

number

[0055] Therefore, by using the internal wiring structure disclosed in Figure 1 of the present invention, it is possible to intentionally increase the collector-to-collector parasitic inductance of the lower arm belonging to the same wiring group while keeping the emitter-to-emitter parasitic inductance of the upper arm belonging to the same wiring group small.

[0056] 3 is a simplified equivalent circuit diagram of the present invention. When parallel-connected power semiconductor elements are operating, electrical vibrations may occur due to a difference in the operation timing of the power semiconductor elements or a difference in parasitic inductance in the parallel equivalent circuit.

[0057] For example, if a voltage imbalance occurs between the power semiconductor elements 26 and 27 of the upper arm in the equivalent circuit shown in FIG. 3, a high-frequency current is supplied to the parasitic inductances around the power semiconductor elements 26 and 27 to cancel out the potential difference caused by the voltage imbalance.

[0058] The high-frequency current exchanges energy with the parasitic capacitance of power semiconductor element 26 and power semiconductor element 27, resulting in LC resonance. This LC resonance is what is known as electrical oscillation. If this electrical oscillation is amplified, it may eventually exceed the withstand voltage of the power semiconductor element, leading to element destruction.

[0059] 3, the parasitic inductance on the collector side of the upper arm portion 20 is defined as Lpos_up, and the parasitic inductance on the emitter side of the upper arm portion 20 is defined as Lneg_up. Similarly, the parasitic inductance on the collector side of the lower arm portion 10 is defined as Lpos_lw, and the parasitic inductance on the emitter side of the lower arm portion 10 is defined as Lneg_lw.

[0060] For example, the transient state e(t) of the collector-emitter voltage of the power semiconductor element shown in FIG. 3 can be formulated as follows:

[0061]

number

[0062] The solution S for this transient state e(t) can be replaced by the following equation:

[0063]

number

[0064] Figure 4 is an image of the solution S on the complex plane. The solution S is a solution that can be expressed as a complex number, and when expressed on the polar coordinate plane it looks like Figure 4. The horizontal axis of Figure 4 represents the real part of the solution S, and the vertical axis represents the imaginary part of the solution S. If the solution S is not on the real axis, it will have two solutions that are multiple conjugates.

[0065] From Figure 4, when both the real and imaginary parts of the solution S are positive, the voltage e(t) in the transient state oscillates. On the other hand, when the real part of the solution S is negative and the imaginary part is positive, the voltage e(t) in the transient state is attenuation. Furthermore, when the real part of the solution S is positive and the imaginary part is negative, the voltage e(t) in the transient state monotonously increases. Furthermore, when both the real and imaginary parts of the solution S are negative, the voltage e(t) in the transient state monotonously decreases.

[0066] Therefore, to damp the transient voltage e(t), the real part of the solution S must be negative.

[0067] Figure 5 shows the combination of Lpos and Lneg required for vibration convergence. The horizontal axis of Figure 5 represents the collector-side parasitic inductance Lpos, and the vertical axis represents the emitter-to-emitter parasitic inductance Lneg. Figure 5 shows the combination of Lpos and Lneg required for vibration convergence.

[0068] If Lpos is increased and Lneg is decreased, with the combination condition 50 of Lpos and Lneg for oscillation convergence in Figure 5 as the boundary, the real part of the solution S becomes negative, and the transient state voltage e(t) can become a convergent oscillation.

[0069] Therefore, in the simplified equivalent circuit of Figure 3, in both the upper arm section 20 and the lower arm section 10, by increasing the collector-side parasitic inductance Lpos and decreasing the emitter-side parasitic inductance Lneg, even if electrical oscillation occurs, it can be made to converge.

[0070] 1 and 2, by adopting the internal wiring structure of the present invention, it is possible to allocate the wiring parasitic inductance between the upper and lower arms, which are the same wiring group, by reducing the emitter-to-emitter parasitic inductance of the upper arm and increasing the collector-to-collector parasitic inductance of the lower arm. Therefore, with the internal wiring structure disclosed in the present invention, it is possible to individually control the relationship between Lpos and Lneg for each of the upper and lower arms and to set them into the oscillation convergence region in Figure 5 (the combination of Lpos and Lneg where the real part of the solution is negative: Attenuation Region). [Example]

[0071] Figure 6 is a comparison diagram between the conventional internal wiring structure and the internal wiring structure of the present invention, and Figure 7 shows the operating waveforms of a power semiconductor element when using the conventional internal wiring structure and the internal wiring structure of the present invention, respectively. The effects of the present invention will be explained using Figures 6 and 7. Figure 6 shows configuration examples of the conventional wiring structure and the wiring structure of the present invention. However, Figure 6[a] shows the conventional internal wiring structure, and Figure 6[b] shows the internal wiring structure of the present invention. Also, Figure 7[a] shows the results of an electrical vibration analysis for the conventional internal wiring structure, and Figure 7[b] shows the results of an electrical vibration analysis for the internal wiring structure of the present invention.

[0072] The conventional internal wiring structure of Figure 6[a] is substantially the same as the mounting positions of the first insulating wiring board 5 to the fourth insulating wiring board 8, which are mounted on the upper arm portion 20 and the lower arm portion 10, respectively, of the internal wiring structure of Example 1 (Figure 6[b]) of the present invention.

[0073] The difference between the conventional internal wiring structure of FIG. 6[a] and the internal wiring structure of the first embodiment of the present invention is the position of the inter-board wiring 21 in the upper arm portion.

[0074] In the conventional internal wiring structure of Figure 6[a], the inter-board wiring 21 of the upper arm portion is arranged closer to the lower arm than the chip end 201 of the upper arm portion that is closer to the lower arm, whereas in Example 1 of the present invention, as described above, the inter-board wiring 21 of the upper arm portion is arranged farther from the lower arm than the chip end 202 of the upper arm portion that is farther from the lower arm.

[0075] 6[a], the length of the upper arm emitter-to-emitter wiring path is approximately equal to the length of the lower arm collector-to-collector wiring path, and therefore the parasitic inductance of the wiring path between the substrates, Lpos_lw, is approximately equal to Lneg_up, which is the parasitic inductance of the lower arm collector-to-collector wiring path.

[0076] On the other hand, according to the internal wiring structure of Example 1 of the present invention, since the inter-substrate wiring 21 of the upper arm portion is arranged in a direction farther from the lower arm, the inter-collector wiring path of the lower arm is longer than the inter-emitter wiring path of the upper arm. Therefore, as the parasitic inductance of the wiring path between the substrates, the inter-collector parasitic inductance Lpos_lw of the lower arm is larger than the inter-emitter inductance Lneg_up of the upper arm.

[0077] According to the first embodiment, by increasing the collector-to-collector parasitic inductance Lpos and decreasing the emitter-to-emitter parasitic inductance Lneg, even if electrical vibrations occur, they can be converged. Therefore, it can be said that the internal wiring structure of the first embodiment of the present invention is more effective in reducing vibrations than the conventional internal wiring structure of FIG. 6[a].

[0078] In Figure 5, "Before" shows the relationship between Lpos and Lneg of the upper and lower arms in Figure 6[a], and "After" shows the relationship between Lpos and Lneg of the upper and lower arms in Figure 6[b] after the countermeasures were implemented. As shown in Figure 5, it can be seen that the vibration convergence region can be achieved by using the configuration in Figure 6[b].

[0079] Figure 7[a] shows the results of a circuit analysis of the drive waveforms when power semiconductor elements connected in parallel are switched using the parasitic inductance of the internal wiring structure shown in Figure 6[a].These results show that the gate voltage waveform Vge, gate current waveform Ig, main voltage waveform Vce, and main current waveform Ic of the power semiconductor elements all oscillate greatly.

[0080] On the other hand, FIG. 7[b] shows the results of circuit analysis of the drive waveform when power semiconductor elements connected in parallel are subjected to switching operation using the parasitic inductance of the internal wiring structure of Example 1 of the present invention shown in FIG. 6[b].

[0081] From these results, it can be seen that when the internal wiring structure of Example 1 of the present invention is used, small oscillations are observed in the gate voltage Vge, but no large oscillation waveforms are observed in the main voltage Vce and main current Ic of the parallel-connected power semiconductor elements.

[0082] Therefore, it is clear that the internal wiring structure of Example 1 of the present invention can suppress electrical vibration during switching operations. [Example]

[0083] FIG. 8 shows a wiring structure of a power semiconductor module according to a third embodiment of the present invention.

[0084] The power semiconductor module of FIG. 8 uses the internal wiring structure 1 of the present invention according to the first embodiment, and the AC terminal 2, the positive electrode terminal 3, and the negative electrode terminal 4 are arranged as shown in FIG.

[0085] Furthermore, the first insulating wiring board 5 and the second insulating wiring board 6 of the upper arm portion, and the third insulating wiring board 7 and the fourth insulating wiring board 8 of the lower arm portion are disposed at the positions shown in Fig. 8. The inter-board wiring 21 of the upper arm portion is disposed at the position shown in Fig. 8, and is wired on the first insulating wiring board 5 and the second insulating wiring board 6 of the upper arm portion, and is disposed at the position farthest from the third insulating wiring board 7 and the fourth insulating wiring board 8 of the lower arm portion.

[0086] The inter-substrate wiring 21 of the upper arm portion can be configured by one or more wire bondings, and can also be wired by any metal conductor such as ribbon bonding wiring. [Example]

[0087] FIG. 9 shows a wiring structure of a power semiconductor module according to a fourth embodiment of the present invention.

[0088] The difference between the power semiconductor module shown in Fig. 8 and that shown in Fig. 9 of the present embodiment 4 is that the insulation distance 300 between the positive electrode terminal 3 and the negative electrode terminal 4 in the present embodiment 4 is larger than that in Fig. 8. By increasing the insulation distance, it is possible to improve the insulation resistance of the power semiconductor module of the present embodiment 4.

[0089] Furthermore, by arranging the inter-board wiring 21 of the upper arm portion in the same position as in the third embodiment, it is possible to expect an effect of suppressing electrical vibrations. [Example]

[0090] FIG. 10 shows a wiring structure of a power semiconductor module according to a fifth embodiment of the present invention.

[0091] 8 and 9 and the power semiconductor module shown in Fig. 10 of this embodiment 5 is that in this embodiment 5, two positive electrode terminals 3 and two negative electrode terminals 4 are mounted. By increasing the numbers of the positive electrode terminals 3 and the negative electrode terminals 4, the power semiconductor module described in this embodiment 5 is compatible with large output current specifications.

[0092] Furthermore, by arranging the inter-board wiring 21 of the upper arm portion in a position similar to that of the third and fourth embodiments, it is possible to expect an effect of suppressing electrical vibrations.

[0093] As described above, it has been shown that the present invention can provide an internal wiring structure that can reduce electrical vibrations generated in the internal wiring of a power semiconductor module.

[0094] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and are not necessarily limited to those including all of the configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0095] 1...internal wiring structure of power semiconductor module, 2...AC terminal, 3...positive terminal, 4...negative terminal, 5...first insulating wiring board of upper arm portion, 6...second insulating wiring board of upper arm portion, 7...third insulating wiring board of lower arm portion, 8...fourth insulating wiring board of lower arm portion, 10...lower arm portion, 11...inter-board wiring of lower arm portion, 12...lower arm emitter wiring portion on third insulating wiring board, 13...lower arm collector wiring portion on third insulating wiring board, 14...Lower arm emitter wiring portion on fourth insulating wiring plate, 15...Lower arm collector wiring portion on fourth insulating wiring plate, 16...Lower arm power semiconductor element on third insulating wiring plate, 17...Lower arm power semiconductor element on fourth insulating wiring plate, 18...Lower arm gate wiring, 19...Lower arm emitter sense wiring, 20...Upper arm portion, 21...Upper arm inter-substrate wiring, 22...Upper arm emitter wiring portion on first insulating wiring plate, 23 ...upper arm collector wiring portion on first insulating wiring plate, 24...upper arm emitter wiring portion on second insulating wiring plate, 25...upper arm collector wiring portion on second insulating wiring plate, 26...upper arm power semiconductor element on first insulating wiring plate, 27...upper arm power semiconductor element on second insulating wiring plate, 28...upper arm gate wiring, 29...upper arm emitter sense wiring, 30...wiring between first insulating wiring plate of upper arm and third insulating wiring plate of lower arm, 31...wiring between second insulating wiring plate of upper arm and fourth insulating wiring plate of lower arm, 50...combination conditions of Lpos and Lneg for vibration convergence, 101...chip end portion closer to the upper arm in the lower arm portion, 102...chip end portion farther from the upper arm in the lower arm portion, 201...chip end portion closer to the lower arm in the upper arm portion, 202...chip end portion farther from the lower arm in the upper arm portion.

Claims

1. an upper arm including a first substrate on which at least one power semiconductor chip including a first switching element is mounted, and a second substrate on which at least one power semiconductor chip including a second switching element connected in parallel to the first switching element is mounted; a lower arm having a third substrate on which at least one power semiconductor chip including a third switching element is mounted, and a fourth substrate on which at least one power semiconductor chip including a fourth switching element connected in parallel to the third switching element is mounted, the upper arm includes a first wiring that connects the first substrate and the second substrate and connects an emitter or a source of the first switching element and an emitter or a source of the second switching element; a second wiring that connects the first substrate and the third substrate and connects the emitter or source of the first switching element and the collector or drain of the third switching element; a third wiring that connects the second substrate and the fourth substrate and connects the emitter or source of the second switching element and the collector or drain of the fourth switching element; a fourth wiring that connects the third substrate and the fourth substrate and connects an emitter or a source of the third switching element and an emitter or a source of the fourth switching element; the first wiring is arranged at a position farther from the lower arm than an end portion of a power semiconductor chip farthest from the lower arm among the power semiconductor chips of the upper arm, the end portion being located on a side farther from the lower arm; A power semiconductor module, characterized in that a total impedance of the first wiring, the second wiring, and the third wiring is greater than an impedance of the fourth wiring.

2. 2. The power semiconductor module according to claim 1, A power semiconductor module, characterized in that a total path length of the first wiring, the second wiring, and the third wiring is longer than that of the fourth wiring.

3. 2. The power semiconductor module according to claim 1, 1. A power semiconductor module, wherein the first switching element is configured by a plurality of switching elements connected in parallel and mounted on the first substrate.

4. 2. The power semiconductor module according to claim 1, a positive electrode terminal connected to the first substrate and the second substrate; a negative terminal connected to the third substrate and the fourth substrate; A power semiconductor module comprising: an AC terminal electrically connected to wiring between the upper arm and the lower arm.

5. A power conversion device comprising the power semiconductor module according to any one of claims 1 to 4.

Images