Solid-state imaging device and electronic device

Abstract

The present invention suppresses color mixture between pixels of different colors. This solid-state imaging device is provided with: a semiconductor layer having a plurality of photoelectric conversion parts divided by a separation region; and a shared on-chip lens disposed on the light incident surface side of the semiconductor layer, shared between the photoelectric conversion parts adjacent to each other with the separation region therebetween, and having a light collection point located in the separation region, and is provided with a recessed part in an upper section of each of the photoelectric conversion parts sharing the common on-chip lens and on the light incidence surface of the semiconductor layer.

Description

[Technical Field]

[0001] The present technology (technology related to the present disclosure) relates to a solid-state imaging device and an electronic device, and in particular to a technology that is effective when applied to a solid-state imaging device and an electronic device that include a shared on-chip lens shared by a plurality of photoelectric conversion units. [Background technology]

[0002] The solid-state imaging device includes a semiconductor layer having a plurality of photoelectric conversion units partitioned by separation regions, and a color filter layer and an on-chip lens arranged on the light incident surface side of the semiconductor layer. Patent Document 1 discloses a pixel unit in which one shared on-chip lens is shared by two photoelectric conversion units arranged adjacent to each other in a 2 x 1 array in one direction. It also discloses a pixel unit in which one shared on-chip lens is shared by four photoelectric conversion units arranged in a 2 x 2 array in each of the X and Y directions that are orthogonal to each other in a plan view. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] WO2016 / 098640 publication Summary of the Invention [Problem to be solved by the invention]

[0004] In a pixel unit in which four photoelectric conversion units in a 2x2 array share one shared on-chip lens, the focal point of the shared on-chip lens is located at the intersection of an isolation region extending in the X direction and an isolation region extending in the Y direction. Therefore, incident light focused at the focal point of the shared on-chip lens is scattered due to the difference in refractive index between the silicon layer (n = 3.9) of the photoelectric conversion unit and the silicon oxide film (n = 1.4) of the isolation region. The scattered light then enters the isolation region on the opposite side of the focal point at an angle greater than the critical angle and may enter the photoelectric conversion unit of an adjacent pixel as unwanted light. When unwanted light enters an adjacent photoelectric conversion unit, it can cause color mixing between pixels of different colors, leaving room for improvement in terms of clarity and resolution.

[0005] An object of the present technology is to provide a solid-state imaging device and an electronic device that can suppress color mixing between pixels of different colors. [Means for solving the problem]

[0006] A solid-state imaging device according to one aspect of the present technology includes: a semiconductor layer having a plurality of photoelectric conversion units partitioned by isolation regions; a shared on-chip lens that is shared by the photoelectric conversion units adjacent to each other via the separation region and is provided on the light incident surface side of the semiconductor layer so that a light convergence point is located on the separation region; a light reflector that is provided in the photoelectric conversion unit that shares the shared on-chip lens and that reflects the light that has been focused at the light focusing point and scattered in the separation region toward an opposite side to the light incident surface of the semiconductor layer; It is equipped with:

[0007] An electronic device according to another aspect of the present technology includes: a solid-state imaging device; an optical lens that forms an image of image light from a subject on an imaging surface of the solid-state imaging device; a signal processing circuit that processes a signal output from the solid-state imaging device; It is equipped with: The solid-state imaging device a semiconductor layer having a plurality of photoelectric conversion units partitioned by isolation regions; a shared on-chip lens that is shared by the photoelectric conversion units adjacent to each other via the separation region and is provided on the light incident surface side of the semiconductor layer so that a light convergence point is located on the separation region; a light reflector that is provided in the photoelectric conversion unit that shares the shared on-chip lens and that reflects the light that has been focused at the light focusing point and scattered in the separation region toward an opposite side to the light incident surface of the semiconductor layer; It is equipped with: [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a chip layout diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. [Figure 2] 1 is a block diagram showing an example of the configuration of a solid-state imaging device according to a first embodiment of the present technology. [Figure 3A] 2 is a schematic plan view showing an enlarged view of a part of the pixel array section of FIG. 1. [Figure 3B] FIG. 3B is a schematic plan view showing an enlarged portion of FIG. 3A. [Figure 3C] FIG. 3C is a schematic plan view that simplifies FIG. 3B. [Figure 4A] FIG. 3C is a schematic cross-sectional view showing a cross-sectional structure taken along line II-II in FIG. 3B. [Figure 4B] FIG. 2 is a diagram illustrating a reflection state of incident light. [Figure 5A] 3A to 3C are cross-sectional views illustrating steps in a method for manufacturing a solid-state imaging device according to a first embodiment of the present technology. [Figure 5B] 5B is a cross-sectional view showing a process subsequent to FIG. 5A. [Figure 5C] 5B is a cross-sectional view showing a process subsequent to FIG. 5B. [Figure 5D] 5D is a cross-sectional view showing a process subsequent to FIG. 5C. [Figure 5E] FIG. 5D is a cross-sectional view showing a process subsequent to FIG. 5D. [Figure 5F] 5B is a cross-sectional view showing a process subsequent to FIG. 5E. [Figure 5G] FIG. 5C is a cross-sectional view showing a process subsequent to FIG. 5F. [Figure 5H] FIG. 5C is a cross-sectional view showing a process subsequent to FIG. 5G. [Figure 5I] 5H. FIG. [Figure 5J] 5I. FIG. [Figure 5K] 5J. FIG. [Figure 6] 10 is a schematic plan view showing a configuration example of a solid-state imaging device according to a second embodiment of the present technology. FIG. [Figure 7] FIG. 10 is a schematic plan view showing a configuration example of a solid-state imaging device according to a third embodiment of the present technology. [Figure 8A] FIG. 7C is a schematic cross-sectional view showing a cross-sectional structure taken along line III-III in FIG. 7B. [Figure 8B] FIG. 2 is a diagram illustrating a reflection state of incident light. [Figure 9] FIG. 10 is a schematic cross-sectional view showing a configuration example of a solid-state imaging device according to a fourth embodiment of the present technology. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a configuration example of a solid-state imaging device according to a fifth embodiment of the present technology. [Figure 11] FIG. 10 is a diagram showing a schematic configuration of an electronic device according to a sixth embodiment of the present technology. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings. In addition, in all the drawings for explaining the embodiments of the present technology, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[0010] Furthermore, the drawings are schematic and may differ from the actual product. The following embodiments exemplify devices and methods for embodying the technical ideas of the present technology, and do not limit the configuration to those described below. In other words, the technical ideas of the present technology can be modified in various ways within the technical scope described in the claims.

[0011] In the following embodiments, among the three mutually orthogonal directions in space, a first direction and a second direction that are mutually orthogonal in the same plane are defined as the X direction and the Y direction, respectively, and a third direction that is orthogonal to each of the first and second directions is defined as the Z direction. In the following embodiments, the thickness direction of a semiconductor layer 20, which will be described later, will be described as the Z direction.

[0012] [First embodiment] In this first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated CMOS (Complementary Metal Oxide Semiconductor) image sensor will be described.

[0013] <Overall configuration of solid-state imaging device> First, the planar layout of the solid-state imaging device 1 will be described.

[0014] 1, a solid-state imaging device 1A according to the first embodiment of the present technology is mainly configured with a semiconductor chip 2 having a rectangular two-dimensional planar shape when viewed in a plan view. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2. As shown in FIG. 11, the solid-state imaging device 1A takes in image light (incident light 106) from an object via an optical lens 102, converts the amount of incident light 106 formed on an imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the electrical signal.

[0015] As shown in Figure 1, the semiconductor chip 2 has a two-dimensional planar shape and includes a rectangular pixel array section 2A located in the center, a peripheral section 2B located outside the pixel array section 2A so as to surround the pixel array section 2A, and a pad arrangement section 2C located outside the peripheral section 2B so as to surround the peripheral section 2B.

[0016] The pixel array section 2A is a light receiving surface that receives light collected by an optical system (not shown). In the pixel array section 2A, a plurality of pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In the peripheral section 2B, the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, the output circuit 7, the control circuit 8, and the like shown in FIG. 2 are arranged.

[0017] Each of the plurality of pixels 3 includes a photoelectric conversion unit 23 shown in FIG. 4A and a plurality of pixel transistors (not shown). The plurality of pixel transistors may include, for example, four transistors: a transfer transistor, a reset transistor, a selection transistor, and an amplifier transistor. Alternatively, the plurality of pixel transistors may include, for example, three transistors excluding the selection transistor.

[0018] 2, the vertical drive circuit 4 is configured with, for example, a shift register. The vertical drive circuit 4 sequentially selects desired pixel drive wirings 10, supplies pulses to the selected pixel drive wirings 10 for driving the pixels 3, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel array section 2A row by row in the vertical direction, and supplies pixel signals from the pixels 3 based on signal charges generated in the photoelectric conversion section 23 of each pixel 3 according to the amount of received light to the column signal processing circuit 5 via the vertical signal line 11.

[0019] The column signal processing circuits 5 are arranged, for example, for each column of pixels 3, and perform signal processing such as noise removal for each pixel column on signals output from one row of pixels 3. For example, the column signal processing circuits 5 perform signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove fixed pattern noise specific to each pixel.

[0020] The horizontal drive circuit 6 is configured with, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn and causing each column signal processing circuit 5 to output a pixel signal that has undergone signal processing to a horizontal signal line 12.

[0021] The output circuit 7 performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12, and outputs the processed signals. Examples of signal processing that can be used include buffering, black level adjustment, column variation correction, and various types of digital signal processing.

[0022] Based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal, the control circuit 8 generates clock signals and control signals that serve as references for the operations of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

[0023] 1, in the pad arrangement section 2C, a plurality of electrode pads 13 are arranged along each of the four sides in a two-dimensional plane of the semiconductor chip 2. The electrode pads 13 are input / output terminals used to electrically connect the semiconductor chip 2 to an external device (not shown).

[0024] <Specific configuration of solid-state imaging device> Next, a specific configuration of the solid-state imaging device 1A will be described. 4A, the semiconductor chip 2 includes a semiconductor layer 20 having a plurality of photoelectric conversion units 23 partitioned by isolation regions 28, and a color filter layer 33 arranged on the light incident surface side, which is the second surface S2 side of a first surface S1 and a second surface S2 located opposite each other in the thickness direction (Z direction) of the semiconductor layer 20. The semiconductor chip 2 also includes an on-chip lens (microlens) 34 and a shared on-chip lens (shared microlens) 35 arranged on the second surface S2 side of the semiconductor layer 20 via the color filter layer 33. The semiconductor chip 2 further includes a multilayer wiring layer 40 arranged on the first surface S1 side of the semiconductor layer 20, and a support substrate 45 arranged on the side of the multilayer wiring layer 40 opposite the semiconductor layer 20 side.

[0025] 4A, the multilayer wiring layer 40 is disposed on the first surface S1 side opposite to the light incident surface (second surface S2) side of the semiconductor layer 20, and is configured to include an interlayer insulating film 41 and wiring 42 stacked in multiple layers with the interlayer insulating film 41 interposed therebetween. The pixel transistors that constitute each pixel 3 are driven via these multiple layers of wiring 42. Because the multilayer wiring layer 40 is disposed on the opposite side to the light incident surface side (second surface S2 side) of the semiconductor layer 20, the layout of the wiring 42 can be freely set.

[0026] 4A, the support substrate 45 is provided on the surface of the multilayer wiring layer 40 opposite to the surface facing the semiconductor layer 20. The support substrate 45 is a substrate for ensuring the strength of the semiconductor layer 20 during the manufacturing stage of the solid-state imaging device 1A. The support substrate 45 can be made of, for example, silicon (Si).

[0027] 4A, the semiconductor layer 20 has an isolation region 28 and a plurality of photoelectric conversion units 23 partitioned by the isolation region 28. Each of the plurality of photoelectric conversion units 23 is arranged in a matrix (X direction and Y direction) in the pixel array section 2A corresponding to each of the plurality of pixels 3. The semiconductor layer 20 is configured of a p-type semiconductor substrate made of, for example, single crystal silicon.

[0028] 3B, 3C, and 4A, each of the multiple photoelectric conversion units 23 has a rectangular planar pattern when viewed from above toward the second surface S2 of the semiconductor layer 20. The multiple photoelectric conversion units 23 have a dotted planar pattern in which the photoelectric conversion units 23 are repeatedly arranged in each of the X and Y directions with isolation regions 28 interposed therebetween in the planar view.

[0029] The isolation region 28 extends from the second surface S2 toward the first surface S1 of the semiconductor layer 20, and electrically and optically isolates adjacent photoelectric conversion units 23. The isolation region 28 corresponding to one pixel 3 has a rectangular annular planar pattern in plan view. The isolation region 28 corresponding to the entire pixel array unit 2A has a composite planar pattern having a lattice-like planar pattern within a rectangular annular planar pattern in plan view, although this is not shown in detail in FIGS. 3B and 3C .

[0030] Each of the photoelectric conversion units 23 includes an n-type well region 21 made of an n-type semiconductor region, for example. Although not shown in detail, each of the photoelectric conversion units 23 includes an avalanche photodiode (APD) element as a photoelectric conversion element, and further includes a pixel transistor. That is, in the pixel array unit 2A, a plurality of pixels 3, each including a photoelectric conversion unit 23 embedded in the semiconductor layer 20, are arranged in a matrix (two-dimensional matrix).

[0031] 4A, the separation region 28 has a buried structure in which an insulating film 27 is buried, via a functional layer 26, inside a separation groove 22 extending from the second surface S2 side toward the first surface S1 side of the semiconductor layer 20. The functional layer 26 is provided so as to cover the inner wall surfaces and bottom surfaces of the separation groove 22, as well as the inner wall surfaces and bottom surfaces of a reflecting groove 25 described below, and further cover the second surface S2 side of the semiconductor layer 20. The insulating film 27 is buried inside each of the separation groove 22 and the reflecting groove 25 via the functional layer 26, and is provided on the second surface S2 side of the semiconductor layer 20 via the functional layer 26. The functional layer 26 includes a fixed charge film and an anti-reflection film for suppressing dark current due to processing damage of the semiconductor layer 20. For example, aluminum oxide (AlO) or hafnium oxide (HfO) can be used as the fixed charge storage film. For example, tantalum oxide (TaO) or titanium oxide (TiO) can be used as the insulating film 27.

[0032] 4A, the color filter layer 33 includes, but is not limited to, a first red (R) color filter portion 33r, a second green (G) color filter portion 33g, and a third blue (B) color filter portion 33b. The first to third color filter portions 33r, 33g, and 33b are arranged in a matrix in the pixel array portion 2A corresponding to each of the pixels 3, i.e., each of the photoelectric conversion portions 23. The first to third color filter portions 33r, 33g, and 33b are arranged randomly and are not necessarily the same in number. In the first embodiment, for example, more green (G) second color filter portions 33g are provided than the red (R) first color filter portions 33r and the blue (B) third color filter portions 33b. 3A, in the first embodiment, a first red (R) color filter portion 33r, a second green (G) color filter portion 33g, and a third blue (B) color filter portion 33b are arranged in a Bayer array, with, for example, two pixels 3 as one unit. Each of the first to third color filter portions 33r, 33g, and 33b is configured to transmit a specific wavelength of incident light that is to be received by the photoelectric conversion portion 23, and to allow the transmitted incident light to enter the photoelectric conversion portion 23.

[0033] 3A, 3B, and 4A, an on-chip lens 34 is disposed for each pixel 3, that is, for each photoelectric conversion unit 23. The on-chip lens 34 condenses incident light (irradiation light) and allows the condensed light to efficiently enter the photoelectric conversion unit 23 of the semiconductor layer 20 via the color filter layer 33. The condensing point of the on-chip lens 34 is located at the center of the photoelectric conversion unit 23 in a plan view.

[0034] 3A, 3B, and 4A, the shared on-chip lens 35 is shared by a plurality of photoelectric conversion units 23 that are adjacent to each other with an isolation region 28 interposed therebetween. In this first embodiment, one shared on-chip lens 35 is shared by four photoelectric conversion units 23 that are arranged two by two in each of the X and Y directions that are orthogonal to each other in a plan view (a 2×2 arrangement). That is, the plurality of pixels 3 include a pixel 3a that corresponds to one on-chip lens and a pixel 3b that shares one shared on-chip lens 35 with the plurality of pixels. The four pixels 3b that share one shared on-chip lens 35 configure one pixel unit PU.

[0035] 4A, the shared on-chip lens 35 shared by the four photoelectric conversion units 23 condenses incident light (irradiation light) 36 and allows the condensed light to be efficiently incident on the photoelectric conversion units 23 in the semiconductor layer 20 via the color filter layer 33. As shown in FIGS. 3B and 4A, the light condensing point 37 of this shared on-chip lens 35 is located at an intersection 28a where an isolation region 28 extending in the X direction and an isolation region 28 extending in the Y direction intersect, in the center of the four photoelectric conversion units 23 (pixel units PU) that share the shared on-chip lens. This shared on-chip lens 35 and the above-mentioned on-chip lens 34 are formed in the same step in the manufacturing process of the solid-state imaging device 1A and are made of a material such as STSR or CSiL.

[0036] 3A and 3B, four pixels 3b of the pixel unit PU have a green (G) second color filter portion 33g. The pixels 3b of this pixel unit PU are adjacent to pixels 3a of the same color and pixels 3a of a different color that are arranged around this pixel unit PU. Of the pixels 3a adjacent to the pixel 3b of the pixel unit PU, the pixel 3a located on one of the two diagonals of the pixel unit PU, which has a square plane, has color filter portions 33r, 33b of a color different from the color filter portion 33g of the pixel 3b of the pixel unit PU.

[0037] This pixel unit PU is used, for example, as a phase difference detection pixel for pupil-dividing incident light in addition to being a normal pixel for obtaining pixel signals (color signals) that constitute an image.

[0038] 3B, 3C, and 4A, each of the four photoelectric conversion units 23 that share one shared on-chip lens 35 includes a light reflector 29 as a recess that reflects incident light 36 focused at a focusing point 37 of the shared on-chip lens 35 and scattered due to the difference in refractive index between the photoelectric conversion unit 23 and the separation region 28 at the focusing point 37, toward the first surface S1 of the semiconductor layer 20. The light reflector 29 is provided above the photoelectric conversion units 23 that share the shared on-chip lens 35, on the light incident surface (second surface S2) side of the semiconductor layer 20. The light reflector 29 has an embedded structure in which an insulating film 27 is embedded, via a functional layer 26, in a reflecting groove 25 extending from the second surface S2 side toward the first surface S1 side of the semiconductor layer 20. The light reflector 29 has a wedge shape whose width gradually narrows from the second surface S2 side toward the first surface S1 side of the semiconductor layer 20. The light reflector 29 extends along the diagonal line of the photoelectric conversion unit 23 in a plan view that does not include the light-focusing point 37 of the shared on-chip lens 35, and both ends of the light reflector 29 are connected to the separation region 28. That is, the light reflector 29 is away from the light-focusing point 37 and in contact with the separation region 28. The depth of the light reflector 29 from the second surface S2 side toward the first surface S1 side of the semiconductor layer 20 is shallower than the depth of the separation region 28. That is, the depth of the light reflector 29 from the second surface S2 side of the semiconductor layer 20 is shallower than the depth of the separation region 28.

[0039] The light reflector 29 is located on the side facing the light condensing point 37 in plan view, i.e., on the light condensing point 37 side, and is aligned along a virtual line V perpendicular to the thickness direction (Z direction) of the semiconductor layer 20. L The inclined surface 29a is inclined so that the inclination angle θ1 on the inner angle side formed by the inclined surface 29a and the inclined surface 29a is an acute angle. When the refractive index of the photoelectric conversion section 23 is n1 and the refractive index of the light reflector 29 is n2, the tilt angle θ1 satisfies the following formula (1). θ1≦θ=90-arcsin(n2 / n1) ……(1) In this first embodiment, the photoelectric conversion unit 23 is made of a silicon layer, and the separation region 28 is made of a silicon oxide film. The refractive index n1 of silicon is approximately 3.9, and the refractive index n2 of silicon oxide is approximately 1.4. Therefore, the light reflector 29 of this first embodiment has an inclined surface 29a inclined at an inclination angle θ1=67°. This inclined surface 29a extends in the direction of the inclination angle θ1=67° and extends along the diagonal line on the side where the light-focusing point 37 of the shared on-chip lens 35 is not located. The light reflector 29 has a slope 29b on the opposite side to the slope 29a, which is inclined under the same conditions as the slope 29a.

[0040] As shown in FIG. 4A, between the semiconductor layer 20 and the color filter layer 33, a light-shielding film 31 and an adhesive film 32 are laminated in this order from the semiconductor layer 20 side. The light-shielding film 31 has a grid-like planar pattern in plan view that opens the light-receiving surface side of each of the multiple photoelectric conversion units 23 so that light from a specific pixel 3 does not leak into an adjacent pixel 3. The light-shielding film 31 corresponding to the pixels 3a around the pixel unit PD has a square-shaped annular planar pattern in plan view. The light-shielding film 31 corresponding to one pixel unit PD (four pixels 4b), each of which has four pixels 3b as one unit, has a square-shaped annular planar pattern in plan view that extends along the periphery of the four pixels 3b, and is not provided between two adjacent pixels 4b. The light-shielding film 31 can be, for example, a tungsten (W) film. The adhesive film 32 is disposed between the insulating film 27 and the light-shielding film 31 and the color filter layer 33, and mainly serves to improve adhesion between the light-shielding film 31 and the color filter layer 33. The adhesive film 32 may be, for example, a silicon oxide film.

[0041] In the solid-state imaging device 1A having the above configuration, incident light is irradiated from the on-chip lens 34 and shared on-chip lens 35 side of the semiconductor chip 2, the irradiated incident light is transmitted individually through the on-chip lens 34, the shared on-chip lens 35 and the color filter units 33r, 33g, and 33b, and the transmitted light is photoelectrically converted in the photoelectric conversion unit 23 to generate signal charges. The generated signal charges are then output as pixel signals by the vertical signal lines 11 made up of the wiring 42 of the multilayer wiring layer 40 via pixel transistors formed on the first surface side of the semiconductor layer 20. Furthermore, the distance to the subject is calculated based on the difference between the signal charges generated in the photoelectric conversion unit 23.

[0042] <Method for manufacturing a solid-state imaging device> Next, a method for manufacturing the solid-state imaging device 1A according to the first embodiment will be described with reference to FIGS. 5A to 5K. First, the semiconductor layer 20 shown in Fig. 5A is prepared. As the semiconductor layer 20, for example, a single crystal silicon substrate is used. Next, as shown in FIG. 5A, a well region 21 made of an n-type semiconductor region is formed on the first face S1 side of the semiconductor layer 20.

[0043] Next, although not shown, transistors constituting a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, etc. are formed on the first surface S1 side of the semiconductor layer 20, and as shown in FIG. 5B, a multilayer wiring layer 40 including an interlayer insulating film 41 and wiring 42 stacked in multiple layers via this interlayer insulating film 41 is formed on the first surface S1 side of the semiconductor layer 20. 5C, a support substrate 45 is bonded to the side of the multilayer wiring layer 40 opposite to the semiconductor layer 20. Then, as shown in FIG. 5D, the second surface (light incident surface) S2 side of the semiconductor layer 20 is ground by a CMP method or the like to reduce the thickness of the semiconductor layer 20.

[0044] Next, as shown in FIG. 5D , a plurality of photoelectric conversion sections 23, each partitioned by an isolation trench 22, are formed on the second surface S2 side of the semiconductor layer 20. Each of the plurality of photoelectric conversion sections 23 is constructed by forming an isolation trench 22, an APD element, a pixel transistor, and the like on the second surface S2 side of the semiconductor layer 20. The isolation trench 22 is formed using well-known photolithography techniques and dry etching techniques such as RIE (Reactive Ion Etching). The isolation trench 22 defines the planar size and pixel size of the photoelectric conversion section 23. That is, the planar pattern of the isolation trench 22 in plan view is a composite planar pattern having a lattice-like planar pattern that defines the pixel size within a rectangular annular planar pattern that defines the pixel array section 2A.

[0045] 5E, an etching mask 24 is formed on the second surface S2 side of the semiconductor layer 20, covering the isolation groove 22 and the photoelectric conversion section 23 and having an opening 24a in the region where the reflection groove 25 is to be formed. This etching mask 24 is formed by forming a mask material with poor coverage, such as an oxide film, by a CVD method, and then patterning the mask material using photolithography technology.

[0046] Next, as shown in FIG. 5F , the photoelectric conversion unit 23 exposed from the opening 24a of the etching mask 24 is etched to form a reflecting groove 25. The reflecting groove 25 is formed in each of the four photoelectric conversion units 23 that share one shared on-chip lens 35, in other words, in each of the four photoelectric conversion units 23 that constitute one pixel unit PU. The reflecting groove 25 is formed in a wedge shape whose width gradually narrows in the thickness direction (Z direction) of the semiconductor layer 20 from the second surface S2 side to the first surface S1 side of the semiconductor layer 20. The reflecting groove 25 extends along one of two diagonals of the photoelectric conversion unit 23 in a plan view that does not include the light-focusing point 37 of the shared on-chip lens 35, and both ends of the reflecting groove 25 are connected to the separation groove 22. The reflecting groove 25 is formed by etching the photoelectric conversion unit 23 using a dry etching technique such as RIE.

[0047] Next, after removing the etching mask 24, as shown in Fig. 5G, a functional layer 26 is formed to cover the semiconductor layer 20 in the isolation grooves 22 and the reflecting grooves 25 and to cover the second surface S2 side of the semiconductor layer 20. The functional layer 26 is formed by depositing a fixed charge film such as aluminum oxide (AlO) or hafnium oxide (HfO), and then depositing an anti-reflection film such as tantalum oxide (TaO) or titanium oxide (TiO).

[0048] 5H, an insulating film 27 is formed on the second surface S2 of the semiconductor layer 20 via the functional layer 26, and the insulating film 27 is embedded in the isolation groove 22 and the reflecting groove 25 via the functional layer 26. This insulating film 27 can be formed by depositing, for example, a silicon oxide film by CVD on the entire surface of the second surface S2 of the semiconductor layer 20, including the insides of the isolation groove 22 and the reflecting groove 25, and then grinding the surface of the silicon oxide film on the second surface S2 of the semiconductor layer 20 by CMP, etch-back, or the like to reduce its thickness.

[0049] 5H, this step forms a separation region 28 having a buried structure in which the insulating film 27 is buried in the separation groove 22 via the functional layer 26. Also, a light reflector 29 having a buried structure in which the insulating film 27 is buried in the reflection groove 25 via the functional layer 26 is formed. Also, a photoelectric conversion section 23 that is partitioned by the separation region 28 and has the light reflector 29 is formed.

[0050] Next, as shown in FIG. 5I, a light-shielding film 31 is formed on the second surface S2 side of the semiconductor layer 20. The light-shielding film 31 is formed by depositing, for example, a tungsten (W) film as a high-melting-point metal film on the insulating film 27 by sputtering, and then turning the tungsten film into a predetermined pattern using well-known photolithography techniques. The light-shielding film 31 is formed in a grid-like planar pattern in plan view that opens on the light-receiving surface sides of each of the multiple photoelectric conversion units 23. The light-shielding film 31 corresponding to the four photoelectric conversion units 23 that share one shared on-chip lens 35 has a planar pattern in a rectangular annular shape in plan view that extends along the outer periphery of the four photoelectric conversion units 23, and is not provided between two adjacent photoelectric conversion units 23.

[0051] 5J, an adhesive film 32 is formed on the second surface S2 side of the semiconductor layer 20. The adhesive film 32 is formed by depositing, for example, a silicon oxide film by a CVD method on the entire surface of the insulating film 27, including on the light-shielding film 31. The adhesive film 32 is formed to a thickness thinner than the thickness of the light-shielding film 31, so that a recess is formed in the region surrounded by the light-shielding film 31.

[0052] 5K, a color filter layer 33 including a first red (R) color filter portion 33r, a second green (G) color filter portion 33g, and a blue (B) color filter portion 33b is formed on the second surface S2 side of the semiconductor layer 20. The first to third color filter portions 33r, 33g, and 33b are formed by depositing and patterning organic films having the spectral characteristics of the corresponding colors (red, green, and blue). The first to third color filter portions 33r, 33g, and 33b are formed in a matrix corresponding to each of the plurality of pixels 3, i.e., each of the plurality of photoelectric conversion portions 23. In addition, the four photoelectric conversion units 23 that share one shared on-chip lens 35 each have a second color filter unit 33g of the same color formed thereon.

[0053] 4A, on-chip lenses 34 and shared on-chip lenses 35 are formed on the second surface S2 side of the semiconductor layer 20, on the light incident surface side of the color filter layer 33. The on-chip lenses 34 and shared on-chip lenses 35 are formed by, for example, an etch-back method using a photosensitive resist film. The shared on-chip lenses 35 are formed corresponding to the four photoelectric conversion units 23 that constitute the pixel unit PU. The on-chip lenses 34 are formed corresponding to the photoelectric conversion units 23 arranged outside the four photoelectric conversion units 23 that constitute the pixel unit PU.

[0054] This process forms a semiconductor substrate including a semiconductor layer 20, a multilayer wiring layer 40, a light-shielding film 31, an adhesive film 32, a color filter layer 33, an on-chip lens 34, and a shared on-chip lens 35. Also, a solid-state imaging device 1A equipped with the shared on-chip lens 35 is almost completed. The solid-state imaging device 1A is formed in each of a plurality of chip formation regions defined by scribe lines (dicing lines) on the semiconductor substrate. Then, the plurality of chip formation regions are individually divided along the scribe lines to form a semiconductor chip 2 on which the solid-state imaging device 1A is mounted.

[0055] <<Major Effects of the First Embodiment>> Next, the main effects of the first embodiment will be described. Fig. 4B is a diagram showing the reflection state of incident light. Table 1 shows the critical angle at the Si-SiO2 interface for visible light calculated from Snell's law assuming the maximum wavelength of visible light is 700 nm.

[0056] [Table 1]

[0057] 4B , in a pixel unit PU in which one shared on-chip lens 35 is shared by four photoelectric conversion units 23 in a 2×2 arrangement, a light-converging point 37 of the shared on-chip lens 35 is located at an intersection 28a of the separation region 28. For this reason, incident light 36 converged at the light-converging point 37 of the shared on-chip lens 35 is scattered due to the difference in refractive index between the silicon (n=3.9) of the photoelectric conversion unit 23 and the silicon oxide (n=1.4) of the separation region 28 at the light-converging point 37. Then, the scattered light 36a strikes the inclined surface 29a of the light reflector 29. At this time, the inclined surface 29a is sandwiched between the silicon of the photoelectric conversion unit 23 on one side and the silicon oxide of the light reflector 29 on the other side. Furthermore, since the inclined surface 29a is inclined at an inclination angle θ1 = 67°, even if the scattered light 36a becomes parallel to a direction (virtual line VL) perpendicular to the thickness direction (Z direction) of the semiconductor layer 20, in other words, parallel to the light incident surface (second surface S2) of the semiconductor layer 20, the incident angle of the scattered light 36a on the inclined surface 29a of the light reflector 29 is 23° or more, which exceeds the critical angle of 23° (22.95°) for a wavelength of 700 nm shown in Table 1, and therefore the visible light is totally reflected. Therefore, when the inclination angle θ1 of the inclined surface 29a of the light reflector 29 satisfies the above-mentioned formula (1), the scattered light 36a scattered at the light focusing point 37 can be reflected by the inclined surface 29a of the light reflector 29 toward the first surface S1 of the semiconductor layer 20, thereby changing the optical path. This prevents the scattered light 36a scattered at the focal point 37 from entering the photoelectric conversion units 23 of the different color pixels 3a adjacent to the four photoelectric conversion units 23 that share one shared on-chip lens 35 as unnecessary light, thereby preventing color mixing between the different color pixels 3.

[0058] Both ends of the light reflecting portion 29 of the first embodiment are connected to the separation region 28. Therefore, even on the separation region side, the scattered light 36a scattered at the light condensing point 37 can be reflected by the inclined surface 29a of the light reflector 29 toward the first surface S1 of the semiconductor layer 20, thereby changing the light path. Therefore, color mixing between pixels 3 of different colors can be efficiently suppressed.

[0059] In the first embodiment, the critical angle of the Si--SiO2 interface has been described, but similar effects can be obtained with other combinations of materials at the interface of the inclined surface 29a by satisfying the above-mentioned formula (1).

[0060] Second Embodiment A solid-state imaging device 1B according to the second embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the configuration of the light reflector. That is, as shown in FIG. 3C, the light reflector 29 of the solid-state imaging device 1A according to the first embodiment is away from the light-converging point 37 and in contact with the separation region . In contrast, the light reflector 29 of the solid-state imaging device 1B according to the second embodiment is spaced apart from the light-condensing point 37 and the separation region 28, as shown in Fig. 6. The other configurations are the same as those of the second embodiment. According to the solid-state imaging device 1B of the second embodiment, the same effects as those of the solid-state imaging device 1A of the first embodiment described above can be obtained.

[0061] Furthermore, according to the solid-state imaging device 1B of this second embodiment, the light reflector 29 is configured to be separated from the focal point 37 and the separation region 28, which makes it easier to form the reflective groove portion 25 (see Figure 5F) in the manufacturing process, thereby making it possible to provide a solid-state imaging device 1B with a high yield.

[0062] Third Embodiment Fig. 7 is a schematic plan view showing a configuration example of a solid-state imaging device according to a third embodiment of the present technology. Fig. 8 is a schematic cross-sectional view showing a cross-sectional structure taken along line III-III in Fig. 7B. Fig. 8B is a diagram showing a reflection state of incident light. Note that in Fig. 7, for ease of viewing the drawing, on-chip lenses and shared on-chip lenses are omitted from illustration.

[0063] A solid-state imaging device 1C according to the third embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the configuration of the light reflector. 7 and 8A, a solid-state imaging device 1C according to the third embodiment includes a light reflector 51 instead of the light reflector 29 shown in Fig. 4A. The other configurations are the same as those of the first embodiment described above, and therefore, repeated explanations will be omitted.

[0064] As shown in FIGS. 7 and 8A, each of the four photoelectric conversion units 23 that share one shared on-chip lens 35 includes a light reflector 51 that reflects scattered light 36a (see FIG. 8B) that is generated when incident light 36 is focused at a focusing point 37 of the shared on-chip lens 35 and scattered due to the refractive index difference between the photoelectric conversion unit 23 and the separation region 28 at the focusing point 37, toward the first surface S1 of the semiconductor layer 20. The light reflector 51 has an embedded structure in which an insulating film 27 is embedded via a functional layer 26 in a reflecting groove 52 that extends from the second surface S2 side toward the first surface S1 side of the semiconductor layer 20. The light reflector 51 has a quadrangular pyramid shape whose width gradually narrows from the second surface S2 side toward the first surface S1 side of the semiconductor layer 20. That is, the light reflector 51 has four inclined surfaces 51a.

[0065] 7 and 8A, the light reflector 51 is disposed such that, in a plan view, four inclined surfaces 51a individually face four corners 23n of the photoelectric conversion unit 23. That is, of the four inclined surfaces 51a, one inclined surface 51a faces, in a plan view, an intersection 28a of the separation region 28 and a light-focusing point 37 of the shared on-chip lens 35. Furthermore, similar to the light reflector 51 of the first embodiment described above, the depth of the light reflector 51 from the second surface S2 side toward the first surface S1 side of the semiconductor layer 20 is shallower than the depth of the separation region 28, that is, the depth from the second surface S2 side of the semiconductor layer 20 is shallower than the separation region 28.

[0066] The four inclined surfaces 51a are inclined at the same angle. Of the four inclined surfaces 51a, the inclined surface 51a located on the light-condensing point 37 side will be described as a representative example. The inclined surface 51a is aligned with a virtual line V perpendicular to the thickness direction (Z direction) of the semiconductor layer 20. LThe inclination angle θ1 on the inner angle side formed by the photoelectric conversion body 23 and the light reflector 51 is an obtuse angle. The inclination angle θ1 satisfies the above-mentioned formula (1), where the refractive index of the photoelectric conversion body 23 is n1 and the refractive index of the light reflector 51 is n2. In this third embodiment, the inclined surface 51a has a (111) crystal plane of silicon. Therefore, the light reflector 51 of this third embodiment has the inclined surface 51a inclined at an inclination angle θ1=54.7°.

[0067] In the third embodiment, the inclined surface 51a of the light reflector 51 located on the light-converging point 37 side is inclined at an inclination angle θ1 of 54.7°. Therefore, even if the scattered light 36a becomes parallel to a direction (virtual line VL) perpendicular to the thickness direction (Z direction) of the semiconductor layer 20, in other words, parallel to the light incident surface (second surface S2) of the semiconductor layer 20, as shown in FIG. 8B , the incident angle of the scattered light 36a on the inclined surface 29a of the light reflector 29 is 35.3°, which is significantly greater than the critical angle of 23° (22.95°) for a wavelength of 700 nm shown in Table 1 above, and therefore the visible light is totally reflected. Therefore, when the inclination angle θ1 of the inclined surface 51a of the light reflector 51 satisfies the above-mentioned formula (1), the scattered light 36a scattered at the light-converging point 37 can be reflected by the inclined surface 51a of the light reflector 51 toward the first surface S1 of the semiconductor layer 20, thereby changing the optical path. As a result, similarly to the first embodiment described above, scattered light 36a scattered at the focal point 37 can be prevented from entering the photoelectric conversion units 23 of the different color pixels 3a adjacent to the four photoelectric conversion units 23 that share one shared on-chip lens 35 as unnecessary light, thereby preventing color mixing between the different color pixels 3.

[0068] The inclined surface 51a of the light reflector 51 can be easily formed in the manufacturing process of the solid-state imaging device 1C by, for example, wet etching the semiconductor layer 20 under etching conditions along the (111) crystal plane of silicon. In addition, the light reflector 51 of this third embodiment may also be configured to be away from the focusing point 37 and in contact with the separation region 28, similar to the light reflector 29 of the first embodiment shown in Figure 3C, or may be configured to be away from the focusing point 37 and the separation region 28, similar to the light reflector 29 of the second embodiment shown in Figure 6.

[0069] [Fourth embodiment] A solid-state imaging device 1D according to the fourth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1C according to the above-described third embodiment, but differs in the configuration of the light reflecting portion.

[0070] That is, as shown in Fig. 9, the photoelectric conversion section 23 of the fourth embodiment includes a light reflector 53 instead of the light reflector 51 shown in Fig. 8A. The other configurations are the same as those of the first embodiment described above.

[0071] The light reflector 53 has a configuration basically similar to that of the light reflector 51 of the third embodiment described above, but differs in the material filled in the reflecting grooves 52. The light reflector 51 of the third embodiment described above has an embedded structure in which an insulating film 27 is embedded, via a functional layer 26, in the reflecting grooves 52 extending from the second surface S2 side toward the first surface S1 side of the semiconductor layer 20. In contrast, the light reflector 53 of the fourth embodiment has an embedded structure in which a part of the second color filter portion 33g of the color filter layer 33 is embedded in the reflecting grooves 52 via the functional layer 26 and an adhesive film 32. The refractive index of this second color filter portion 33g is approximately 1.6 to 1.8 at a wavelength of 530 nm, for example.

[0072] Therefore, also in the light reflector 53 of the fourth embodiment, by making the inclination angle θ1 of the inclined surface 51a satisfy the above-mentioned formula (1), the scattered light 36a scattered at the light-converging point 37 can be reflected by the inclined surface 51a of the light reflector 51 toward the first surface S1 of the semiconductor layer 20, thereby changing the optical path. As a result, similar to the above-mentioned first embodiment, it is possible to prevent the scattered light 36a scattered at the light-converging point 37 from being incident as unwanted light on the photoelectric conversion units 23 of the different-color pixels 3a adjacent to the four photoelectric conversion units 23 that share one shared on-chip lens 35, and to prevent color mixing between the different-color pixels 3a. In addition, the light reflector 53 of this fourth embodiment may also be configured to be away from the focusing point 37 and in contact with the separation region 28, similar to the light reflector 29 of the first embodiment shown in Figure 3C, or may be configured to be away from the focusing point 37 and the separation region 28, similar to the light reflector 29 of the second embodiment shown in Figure 6.

[0073] Fifth Embodiment A solid-state imaging device 1E according to the fifth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the configuration of the light reflector.

[0074] That is, as shown in Fig. 10, a solid-state imaging device 1D according to the fifth embodiment includes a light reflector 55 instead of the light reflector 29 shown in Fig. 4A. The other configurations are the same as those of the first embodiment described above, and therefore repeated explanations will be omitted.

[0075] 10 , the light reflector 55 has a structure in which a cavity 56 is provided in a reflecting groove 25 extending from the second surface S2 side toward the first surface S1 side of the semiconductor layer 20. The light reflector 55 has a wedge shape whose width gradually narrows from the second surface S2 side toward the first surface S1 side of the semiconductor layer 20. The light reflector 55 extends along the diagonal line, of the two diagonals of the photoelectric conversion unit 23 in a plan view, that does not include the light-focusing point 37 of the shared on-chip lens 35, and both ends of the light reflector 55 are connected to the separation region 28. That is, the light reflector 55 is away from the light-focusing point 37 and in contact with the separation region 28. Furthermore, like the light reflector 51 of the first embodiment described above, the depth of the light reflector 55 from the second surface S2 side of the semiconductor layer 20 toward the first surface S1 side is shallower than the depth of the separation region 28, i.e., the depth from the second surface S2 side of the semiconductor layer 20 is shallower than the separation region 28.

[0076] The light reflector 55 is located on the side facing the light condensing point 37 in plan view, i.e., on the light condensing point 37 side, and is aligned along a virtual line V perpendicular to the thickness direction (Z direction) of the semiconductor layer 20. L The inclined surface 29a is inclined so that the inclination angle θ1 on the inner angle side formed by the inclined surface 29a and the inclined surface 29a is an acute angle. The tilt angle θ1 satisfies the above-mentioned formula (1) when the refractive index of the photoelectric conversion section 23 is n1 and the refractive index of the light reflector 55 is n2.

[0077] The hollow portion 56 of the light reflector 55 is filled with an inert gas or is in a vacuum state, and has a refractive index lower than that of silicon oxide. Therefore, the fifth embodiment also provides the same effects as the first embodiment.

[0078] Note that by forming the reflecting groove after filling the isolation groove with the insulating film, it is possible to fill the reflecting groove with a material having a lower refractive index than the silicon oxide film. In addition, the light reflector 55 of this fifth embodiment may also be configured to be away from the focusing point 37 and in contact with the separation region 28, similar to the light reflector 29 of the first embodiment shown in Figure 3C, or may be configured to be away from the focusing point 37 and the separation region 28, similar to the light reflector 29 of the second embodiment shown in Figure 6.

[0079] Sixth Embodiment <Application examples to electronic devices> The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0080] FIG. 11 is a diagram showing a schematic configuration of an electronic device (for example, a camera) according to a sixth embodiment of the present technology. 11, the electronic device 100 includes a solid-state imaging device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. In the electronic device 100, the solid-state imaging device 101 is any one of the solid-state imaging devices 1A, 1B, 1C, 1D, and 1E according to the first to fifth embodiments of the present technology.

[0081] The optical lens 102 focuses image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period for the solid-state imaging device 101. The drive circuit 104 supplies drive signals that control the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signals (timing signals) supplied from the drive circuit 104 cause signal transfer in the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on signals (pixel signals) output from the solid-state imaging device 101. The processed video signals are stored in a storage medium such as a memory or output to a monitor.

[0082] With this configuration, the electronic device 100 of the sixth embodiment can suppress color mixing between pixels of different colors in the solid-state imaging device 101, thereby improving image quality.

[0083] The electronic device 100 to which the above-described solid-state imaging devices 1A to 1E can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging devices 1A to 1E may be applied to imaging devices such as camera modules for mobile devices such as mobile phones and tablet terminals.

[0084] The present technology may be configured as follows. (1) a semiconductor layer having a plurality of photoelectric conversion units partitioned by isolation regions; a shared on-chip lens that is disposed on a light incident surface side of the semiconductor layer, is shared by the photoelectric conversion units adjacent to each other via the separation region, and has a light focusing point located in the separation region; a solid-state imaging device including a recessed portion on the light incident surface of the semiconductor layer above the photoelectric conversion unit that shares the shared on-chip lens; (2) The solid-state imaging device according to (1), wherein the recess is a light reflector that reflects light scattered at the focusing point of the shared on-chip lens toward an opposite side to the light incident surface of the semiconductor layer. (3) The solid-state imaging device described in (2) above, wherein the light reflector is located on the focal point side in a planar view and has an inclined surface that is inclined so that the inclination angle between the light reflector and a virtual line perpendicular to the thickness direction of the semiconductor layer is an acute angle. (4) When the inclination angle is θ1, the refractive index of the photoelectric conversion portion is n1, and the refractive index of the light reflector is n2, θ1≦θ=90-arcsin(n2 / n1) The solid-state imaging device according to (3) above, which satisfies the above. (5) The solid-state imaging device according to any one of (2) to (4) above, wherein the light reflector is away from the light-converging point and in contact with the separation region. (6) The solid-state imaging device according to any one of (2) to (4) above, wherein the light reflector is spaced apart from the light-converging point and the separation region. (7) The solid-state imaging device according to any one of (2) to (6) above, wherein the light reflector has a (111) surface. (8) The solid-state imaging device according to (7) above, wherein the light reflector is a quadrangular pyramid. (9) the shared on-chip lens is disposed on the semiconductor layer side via a color filter, A solid-state imaging device according to any one of (2) to (8) above, wherein the light reflector includes a groove provided in the photoelectric conversion section and a portion of the color filter embedded in the groove. (10) The solid-state imaging device according to any one of (2) to (8) above, wherein the light reflector includes a groove provided in the photoelectric conversion portion and a cavity provided within the groove. (11) The solid-state imaging device according to any one of (2) to (11) above, wherein the light reflector has a depth from the light incident surface side of the semiconductor layer that is shallower than the separation region. (12) a solid-state imaging device; an optical lens that forms an image of image light from a subject on an imaging surface of the solid-state imaging device; a signal processing circuit that processes a signal output from the solid-state imaging device; Equipped with the solid-state imaging device, a semiconductor layer having a plurality of photoelectric conversion units partitioned by isolation regions; a shared on-chip lens that is shared by the photoelectric conversion units adjacent to each other via the separation region and is provided on the light incident surface side of the semiconductor layer so that a light convergence point is located on the separation region; a light reflector that is provided in the photoelectric conversion unit that shares the shared on-chip lens and that reflects the light that has been focused at the light focusing point and scattered in the separation region toward an opposite side to the light incident surface of the semiconductor layer; An electronic device comprising:

[0085] The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve equivalent effects to those intended by the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective disclosed features. [Explanation of symbols]

[0086] 1A, 1B, 1C, 1D, 1E...Solid-state imaging device 2. Semiconductor chip 2A: Pixel array section 2B: Periphery 2C...Pad placement area 3...pixel 4...Vertical drive circuit 5...Column signal processing circuit 6...Horizontal drive circuit 7...Output circuit 8...Control circuit 10...Pixel drive wiring 11...Vertical signal line 12...Horizontal signal line 13...Electrode pad 20...Semiconductor layer 21...n-type well region 22...Separation groove 23...Photoelectric conversion unit 24...Etching mask 25...Reflection groove 26...Functional layer 27...insulating film 28...Separation area 28a...Intersection 29...Light reflector 29a…Slope surface 31...Light-shielding film 32…Adhesive film 33...Color filter layer 34...On-chip lens 35...Shared on-chip lens 36...Incoming light 37...Convergence point 40…Multilayer wiring layer 41...Interlayer insulating film 42...Wiring 45...Support substrate

Claims

1. a semiconductor layer having a plurality of photoelectric conversion units partitioned by isolation regions; a shared on-chip lens that is disposed on a light incident surface side of the semiconductor layer, is shared by the photoelectric conversion units adjacent to each other via the separation region, and has a light focusing point located in the separation region; a recessed portion provided on the light incident surface of the semiconductor layer above the photoelectric conversion unit that shares the shared on-chip lens; the recessed portion is a light reflector that reflects light scattered at the light focusing point of the shared on-chip lens toward an opposite side to the light incident surface of the semiconductor layer, the light being focused at the light focusing point of the shared on-chip lens; The solid-state imaging device, wherein the light reflector is in contact with the separation region away from the light-focusing point.

2. 2. The solid-state imaging device according to claim 1, wherein the light reflector has an inclined surface located on the light-focusing point side in a planar view and inclined so that an inclination angle formed by an imaginary line perpendicular to the thickness direction of the semiconductor layer is an acute angle.

3. The solid-state imaging device according to claim 1 , wherein the light reflector has a (111) surface.

4. The solid-state imaging device according to claim 1 , wherein the light reflector has a depth from the light incident surface side of the semiconductor layer that is shallower than the separation region.

5. A semiconductor layer having a plurality of photoelectric conversion units partitioned by isolation regions; a shared on-chip lens that is disposed on a light incident surface side of the semiconductor layer, is shared by the photoelectric conversion units adjacent to each other via the separation region, and has a light focusing point located in the separation region; a recessed portion provided on the light incident surface of the semiconductor layer above the photoelectric conversion unit that shares the shared on-chip lens; the recessed portion is a light reflector that reflects light scattered at the light focusing point of the shared on-chip lens toward an opposite side to the light incident surface of the semiconductor layer, the light being focused at the light focusing point of the shared on-chip lens; The solid-state imaging device, wherein the light reflector is spaced apart from the light-focusing point and the separation region.

6. 6. The solid-state imaging device according to claim 5, wherein the light reflector has an inclined surface that is located on the light-converging point side in a planar view and that is inclined so that an inclination angle formed by an imaginary line perpendicular to the thickness direction of the semiconductor layer is an acute angle.

7. The solid-state imaging device according to claim 5 , wherein the light reflector has a (111) surface.

8. The solid-state imaging device according to claim 5 , wherein the light reflector has a depth from the light incident surface side of the semiconductor layer that is shallower than the separation region.

9. A semiconductor layer having a plurality of photoelectric conversion units partitioned by isolation regions; a shared on-chip lens that is disposed on a light incident surface side of the semiconductor layer, is shared by the photoelectric conversion units adjacent to each other via the separation region, and has a light focusing point located in the separation region; a recessed portion provided on the light incident surface of the semiconductor layer above the photoelectric conversion unit that shares the shared on-chip lens; the recessed portion is a light reflector that reflects light scattered at the light focusing point of the shared on-chip lens toward an opposite side to the light incident surface of the semiconductor layer, the light being focused at the light focusing point of the shared on-chip lens; the shared on-chip lens is disposed on the semiconductor layer side via a color filter, The solid-state imaging device, wherein the light reflector includes a groove provided in the photoelectric conversion portion and a part of the color filter embedded in the groove.

10. 10. The solid-state imaging device according to claim 9, wherein the light reflector has an inclined surface located on the light-converging point side in a planar view and inclined so that an inclination angle formed by an imaginary line perpendicular to the thickness direction of the semiconductor layer is an acute angle.

11. The solid-state imaging device according to claim 9 , wherein the light reflector has a (111) surface.

12. A solid-state imaging device as described in Claim 9, wherein the optical reflector has a depth from the light incident surface side of the semiconductor layer that is shallower than the separation region.

13. A semiconductor layer having a plurality of photoelectric conversion units partitioned by isolation regions; a shared on-chip lens that is disposed on a light incident surface side of the semiconductor layer, is shared by the photoelectric conversion units adjacent to each other via the separation region, and has a light focusing point located in the separation region; a recessed portion provided on the light incident surface of the semiconductor layer above the photoelectric conversion unit that shares the shared on-chip lens; the recessed portion is a light reflector that reflects light scattered at the light focusing point of the shared on-chip lens toward an opposite side to the light incident surface of the semiconductor layer, the light being focused at the light focusing point of the shared on-chip lens; The light reflector includes a groove provided in the photoelectric conversion portion and a cavity provided within the groove.

14. A solid-state imaging device as described in Claim 13, wherein the light reflector is located on the side of the focusing point in a planar view and has an inclined surface that is inclined so that the inclination angle between the reflector and a virtual line perpendicular to the thickness direction of the semiconductor layer is an acute angle.

15. A solid-state imaging device as described in Claim 13, wherein the optical reflector has a (111) surface.

16. A solid-state imaging device as described in Claim 13, wherein the optical reflector has a depth from the light incident surface side of the semiconductor layer that is shallower than the separation region.

17. a solid-state imaging device; an optical lens that forms an image of image light from a subject on an imaging surface of the solid-state imaging device; a signal processing circuit that processes a signal output from the solid-state imaging device; Equipped with the solid-state imaging device, a semiconductor layer having a plurality of photoelectric conversion units partitioned by isolation regions; a shared on-chip lens that is shared by the photoelectric conversion units adjacent to each other via the separation region and is provided on the light incident surface side of the semiconductor layer so that a light convergence point is located on the separation region; a light reflector that is provided in the photoelectric conversion unit that shares the shared on-chip lens and that reflects the light that has been focused at the light focusing point and scattered in the separation region toward an opposite side to the light incident surface of the semiconductor layer; Equipped with The electronic device, wherein the light reflector is in contact with the separation region away from the light focusing point.

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