Semiconductor elements, devices, chips

Abstract

To increase the stability of a supply voltage supplied on a plurality of avalanche photodiodes even if the number of avalanche photodiodes increases while corresponding to the voltage supplied on the avalanche photodiodes.SOLUTION: A semiconductor element includes an array in which a plurality of avalanche photodiodes is arranged. The semiconductor element has a plurality of first electrodes to which a first voltage used for the plurality of avalanche photodiodes is supplied from an external source and second electrodes to which a second voltage different from the first voltage is supplied from an external source. The plurality of first and second electrodes is arranged on the exterior of the array. The second electrode is disposed on a portion between one of the plurality of first electrodes and the other one.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, devices and chips. [Background technology]

[0002] There is known a photoelectric conversion element that can detect weak light at the single photon level by using avalanche (electron avalanche) multiplication. Patent Document 1 describes a configuration that includes an avalanche photodiode and a pad electrode for supplying a voltage to the avalanche photodiode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-96158 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the placement of the pad electrodes is insufficient. Avalanche photodiodes require the supply of a large voltage necessary to cause avalanche multiplication. Furthermore, as the number of avalanche photodiodes increases, differences in the voltages supplied to the multiple avalanche photodiodes become more likely. Differences in the supplied voltages can cause differences in the signal linearity (output signal value relative to the amount of incident light) between the multiple avalanche photodiodes.

[0005] The present disclosure relates to a technology that corresponds to the voltage supplied to the avalanche photodiode and improves the stabilization of the power supply voltage supplied to a plurality of avalanche photodiodes even when the number of avalanche photodiodes increases. [Means for solving the problem]

[0006] One aspect of the present disclosure is a semiconductor device having an array in which a plurality of avalanche photodiodes are arranged, the semiconductor device having a plurality of first electrodes to which a first voltage used by the plurality of avalanche photodiodes is supplied from the outside, and a second electrode to which a second voltage different from the first voltage is supplied from the outside, the plurality of first electrodes and the second electrode being arranged outside the array, and the second electrode being arranged between one of the plurality of first electrodes and another of the plurality of first electrodes. [Effects of the Invention]

[0007] The present disclosure can accommodate the voltage supplied to the avalanche photodiode, and can contribute to stabilizing the power supply voltage supplied to a plurality of avalanche photodiodes even if the number of avalanche photodiodes increases. [Brief explanation of the drawings]

[0008] [Figure 1] Overall view of semiconductor element [Figure 2] Plan view of a semiconductor element [Figure 3] Overall view of semiconductor element [Figure 4] Pixel configuration diagram [Figure 5] Pixel configuration and operation diagram [Figure 6] Plan view of a semiconductor element [Figure 7] Cross-sectional view of a semiconductor element [Figure 8] Plan view of a semiconductor element [Figure 9] Plan view of a semiconductor element [Figure 10] Plan view of a semiconductor element [Figure 11] Plan view of a semiconductor element [Figure 12] Plan view of a semiconductor element [Figure 13] Plan view of a semiconductor element [Figure 14] Plan view of a semiconductor element [Figure 15] Plan view of a semiconductor element [Figure 16] Equipment configuration diagram DETAILED DESCRIPTION OF THE INVENTION

[0009] The embodiments shown below are intended to embody the technical concept of the present invention and are not intended to limit the present invention. The size and positional relationship of components shown in each drawing may be exaggerated for clarity. In the following description, the same components may be designated by the same reference numerals and their description may be omitted.

[0010] The following explanation will mainly focus on semiconductor elements. Semiconductor elements can be used as imaging elements (image sensors) for generating images. Other examples of semiconductor elements include distance measurement elements (sensors for distance measurement using focus detection or TOF (Time Of Flight)), photometry elements (sensors for measuring the amount of incident light), and LiDAR sensors. The forms described below can be applied to semiconductor elements in general.

[0011] 1 to 4, a configuration common to the semiconductor device in each embodiment will be described. The semiconductor device has a SPAD (Single Photon Avalanche Diode) pixel including an avalanche photodiode. The conductivity type corresponding to the polarity of the charge used as the signal charge among the charge pairs generated in the avalanche photodiode is called the first conductivity type. The first conductivity type refers to a conductivity type in which charges of the same polarity as the signal charge are the majority carriers. The conductivity type opposite to the first conductivity type is called the second conductivity type. In the following, an example will be described in which the signal charge is electrons, the first conductivity type is N-type, and the second conductivity type is P-type; however, the signal charge may be holes, the first conductivity type is P-type, and the second conductivity type is N-type.

[0012] In this specification, "plan view" refers to a view from a direction perpendicular to the light incident surface of a semiconductor substrate, which will be described later. Furthermore, a cross section refers to a surface in a direction perpendicular to the light incident surface of the semiconductor layer 302 of the sensor substrate 11. Note that if the light incident surface of the semiconductor layer is rough when viewed microscopically, the plan view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0013] In this specification, the depth direction is the direction from the light incident surface (first surface) of the semiconductor layer 302 toward the surface (second surface) on which the circuit board 21 is disposed.

[0014] First, the configuration common to each embodiment will be described.

[0015] FIG. 1 is a diagram showing the configuration of a stacked semiconductor device 100 according to this embodiment. In the semiconductor device 100, two substrates, a sensor substrate 11 and a circuit substrate 21, are stacked and electrically connected. The sensor substrate 11 has a first semiconductor layer having a photoelectric conversion element 102 (described later) and a first wiring structure. The circuit substrate 21 has a second semiconductor layer having circuits such as a signal processing unit 103 (described later) and a second wiring structure. The semiconductor device 100 is stacked in the following order: the second semiconductor layer, the second wiring structure, the first wiring structure, and the first semiconductor layer. The semiconductor devices described in each embodiment are so-called back-illuminated semiconductor devices in which light is incident from a first surface and a circuit substrate is disposed on a second surface.

[0016] In the following description, the sensor substrate 11 and the circuit substrate 21 are described as diced chips, but are not limited to chips. For example, each substrate may be a wafer. Furthermore, each substrate may be stacked in the wafer state and then diced, or may be chipped and then stacked and bonded.

[0017] The sensor substrate 11 has a pixel region 12 arranged thereon, and the circuit substrate 21 has a circuit region 22 arranged thereon for processing signals detected in the pixel region 12 .

[0018] 2 is a diagram showing an example of the arrangement of the sensor substrate 11. Pixels 101, each having a photoelectric conversion element 102 including an avalanche photodiode (hereinafter, referred to as APD), are arranged in a two-dimensional array in plan view to form a pixel region 12.

[0019] The pixel 101 is typically a pixel for forming an image, but when used for TOF (Time of Flight), it does not necessarily have to form an image. In other words, the pixel 101 may be a pixel for measuring the time and amount of light that arrives.

[0020] 3 is a configuration diagram of the circuit board 21. It has a signal processing unit 103 that processes the charges photoelectrically converted by the photoelectric conversion element 102 in FIG. 2, a readout circuit 112, a control pulse generation unit 115, a horizontal scanning circuit unit 111, a signal line 113, and a vertical scanning circuit unit 110.

[0021] The photoelectric conversion element 102 in FIG. 2 and the signal processing unit 103 in FIG. 3 are electrically connected via connection wiring provided for each pixel.

[0022] The vertical scanning circuit unit 110 receives a control pulse supplied from the control pulse generating unit 115 and supplies the control pulse to each pixel. The vertical scanning circuit unit 110 uses logic circuits such as a shift register and an address decoder.

[0023] The signal output from the photoelectric conversion element 102 of the pixel is processed by the signal processing unit 103. The signal processing unit 103 is provided with a counter, a memory, etc., and the memory holds digital values.

[0024] The horizontal scanning circuit unit 111 inputs a control pulse to the signal processing unit 103 to sequentially select each column in order to read out the signal from the memory of each pixel in which the digital signal is held.

[0025] A signal is output to the signal line 113 from the signal processing unit 103 of the pixel selected by the vertical scanning circuit unit 110 for the selected column.

[0026] The signal output to the signal line 113 is output via an output circuit 114 to a recording unit or a signal processing unit outside the semiconductor device 100 .

[0027] 2, the photoelectric conversion elements in the pixel region may be arranged one-dimensionally. The function of the signal processing unit does not necessarily need to be provided for each photoelectric conversion element, and for example, one signal processing unit may be shared by multiple photoelectric conversion elements, and signal processing may be performed sequentially.

[0028] 2 and 3, a plurality of signal processing units 103 are arranged in a region overlapping the pixel region 12 in a plan view. A vertical scanning circuit unit 110, a horizontal scanning circuit unit 111, column circuits 112, output circuits 114, and a control pulse generating unit 115 are arranged so as to overlap between an edge of the sensor substrate 11 and an edge of the pixel region 12 in a plan view. In other words, the sensor substrate 11 has the pixel region 12 and a non-pixel region arranged around the pixel region 12, and the vertical scanning circuit unit 110, the horizontal scanning circuit unit 111, the column circuits 112, the output circuits 114, and the control pulse generating unit 115 are arranged in a region overlapping the non-pixel region in a plan view.

[0029] FIG. 4 is an example of a block diagram including the equivalent circuits of FIGS.

[0030] In FIG. 2, the photoelectric conversion element 102 having the APD 201 is provided on a sensor substrate 11, and the other members are provided on a circuit board 21.

[0031] The APD 201 generates charge pairs in response to incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD 201. A voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the APD 201. A reverse bias voltage is supplied to the anode and cathode so that the APD 201 performs avalanche multiplication. With this voltage supplied, charges generated by the incident light undergo avalanche multiplication, generating an avalanche current.

[0032] When a reverse bias voltage is supplied, there are two modes: Geiger mode, in which the anode and cathode are operated at a potential difference greater than the breakdown voltage, and linear mode, in which the anode and cathode are operated at a potential difference close to or less than the breakdown voltage.

[0033] An APD operated in Geiger mode is called a SPAD. For example, the voltage VL (first voltage) is −30 V, and the voltage VH (second voltage) is 1 V. As such, an APD requires a larger voltage than a photodiode that does not perform avalanche multiplication. The APD 201 may be operated in either linear mode or Geiger mode. A SPAD is preferable because the potential difference is larger than that of a linear mode APD, resulting in a more pronounced effect in terms of withstand voltage.

[0034] The quench element 202 is connected to a power supply that supplies voltage VH and the APD 201. The quench element 202 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, suppressing the voltage supplied to the APD 201 and suppressing avalanche multiplication (quench operation). The quench element 202 also functions to return the voltage supplied to the APD 201 to voltage VH by passing a current equivalent to the voltage drop caused by the quench operation (recharge operation).

[0035] The signal processing unit 103 has a waveform shaping unit 210, a counter circuit 211, and a selection circuit 212. In this specification, the signal processing unit 103 may have any one of the waveform shaping unit 210, the counter circuit 211, and the selection circuit 212.

[0036] The waveform shaping unit 210 shapes the potential change at the cathode of the APD 201 obtained when photons are detected, and outputs a pulse signal. For example, an inverter circuit is used as the waveform shaping unit 210. While an example using one inverter as the waveform shaping unit 210 is shown in FIG. 4, a circuit in which multiple inverters are connected in series, or another circuit having a waveform shaping effect, may also be used.

[0037] The counter circuit 211 counts the pulse signals output from the waveform shaping unit 210 and holds the count value. When a control pulse pRES is supplied via a drive line 213, the signal held in the counter circuit 211 is reset.

[0038] A control pulse pSEL is supplied to the selection circuit 212 from the vertical scanning circuit unit 110 in Fig. 3 via a drive line 214 (not shown in Fig. 3) in Fig. 4, and switches between electrical connection and disconnection between the counter circuit 211 and the signal line 113. The selection circuit 212 includes, for example, a buffer circuit for outputting a signal.

[0039] The electrical connection may be switched by disposing a switch such as a transistor between the quench element 202 and the APD 201 or between the photoelectric conversion element 102 and the signal processing unit 103. Similarly, the supply of the voltage VH or the voltage VL to the photoelectric conversion element 102 may be electrically switched using a switch such as a transistor.

[0040] In this embodiment, a configuration using the counter circuit 211 has been described. However, instead of the counter circuit 211, the semiconductor device 100 may be configured to acquire pulse detection timing using a time-to-digital converter (hereinafter referred to as TDC) and a memory. In this case, the generation timing of the pulse signal output from the waveform shaping unit 210 is converted into a digital signal by the TDC. To measure the timing of the pulse signal, a control pulse pREF (reference signal) is supplied to the TDC from the vertical scanning circuit unit 110 in FIG. 1 via a drive line. The TDC acquires, as a digital signal, a signal obtained by converting the input timing of the signal output from each pixel via the waveform shaping unit 210 into a relative time based on the control pulse pREF.

[0041] FIG. 5 is a diagram showing a schematic diagram of the relationship between the operation of an APD and an output signal.

[0042] Fig. 5(a) is a diagram illustrating the APD 201, quench element 202, and waveform shaping unit 210 of Fig. 4. Here, the input side of the waveform shaping unit 210 is referred to as node A, and the output side is referred to as node B. Fig. 5(b) shows the waveform change at node A in Fig. 5(a), and Fig. 5(c) shows the waveform change at node B in Fig. 5(a).

[0043] Between time t0 and time t1, a potential difference of VH-VL is applied to the APD 201 in FIG. 5(a). When a photon is incident on the APD 201 at time t1, avalanche multiplication occurs in the APD 201, an avalanche multiplication current flows through the quench element 202, and the voltage at node A drops. As the voltage drop increases and the potential difference applied to the APD 201 decreases, avalanche multiplication in the APD 201 stops, as shown at time t2, and the voltage level at node A drops no more than a certain value. After that, between time t2 and time t3, a current flows through node A from voltage VL to compensate for the voltage drop, and at time t3, node A settles to its original potential level. At this time, the portion of the output waveform at node A that exceeds a certain threshold is shaped by the waveform shaping unit 210 and output as a signal at node B.

[0044] The arrangement of the output lines 113, the column circuits 112, and the output circuits 114 is not limited to that shown in Fig. 3. For example, the output lines 113 may be arranged to extend in the row direction, and the column circuits 112 may be arranged at the ends of the output lines 113.

[0045] The semiconductor device of each embodiment will be described below.

[0046] (First embodiment) The present embodiment will be described.

[0047] FIG. 6 is a diagram illustrating the configuration of a first chip 301 and a package 20 included in the semiconductor device of this embodiment. The first chip 301 has a shape with long and short sides. The first chip 301 includes a pixel array 110 in which a plurality of pixels 100 are arranged across a plurality of rows and a plurality of columns. The first chip is provided with power supply wiring 130 arranged to surround the periphery of the pixel array 110. The power supply wiring 130 is connected to a plurality of pad electrodes 352, which are an example of a first electrode, arranged outside the pixel array 110 and in a region closer to the edge of the first chip 301 than the pixel array 110. The plurality of pad electrodes 352 are arranged outside the pixel array 110 in regions 150 to 154 on the long sides of the first chip 301. More specifically, the plurality of pad electrodes 352 connected to the power supply wiring 130 are provided in regions on two long sides of the first chip 301 that face each other across the pixel array 100. The relationship in which the two long side regions face each other across the pixel array 100 refers to the relationship between region 150 and region 152 and the relationship between region 151 and region 153. The power supply wiring 130 is a wiring that supplies a power supply voltage VH to the pixel 100. Each of the multiple pad electrodes 352 is connected to a pin (package connection terminal) 102 provided on the package 20. The pin 102 receives a power supply voltage VH, which is a first voltage supplied from outside the semiconductor device. Furthermore, in addition to the multiple pad electrodes 352, a pad electrode 120 and a pad electrode 122 are provided on the long side region of the first chip 301. The pad electrode 120, which is an example of a second electrode, receives a power supply voltage VL, which is a second voltage different from the power supply voltage VH, supplied to the pixel 100. In this embodiment, the power supply voltage VH, which is the first voltage, is 1.1 V. In this embodiment, the power supply voltage VL, which is the second voltage, is −30 V. The pad electrode 122 is an example of a third electrode that receives a third voltage (for example, a ground voltage) different from the power supply voltage VH and the power supply voltage VL. Each of the regions 150 to 153 has a configuration in which the pad electrode 120 is arranged between a plurality of pad electrodes 352. From another perspective, the pad electrode 352 is arranged between a plurality of pad electrodes 120. From another perspective, the pad electrodes 352 and the pad electrodes 120 are arranged alternately.The pad electrode 122 is provided between the two regions 140 and 141 in which the pad electrodes 352 and 120 are alternately arranged. The pad electrode 122 is also provided between the pad electrodes 352 and 120.

[0048] Furthermore, pad electrodes 354, which are an example of fourth electrodes, are provided in regions 160 and 161 on the short sides of the first chip 301. The pad electrode 354 receives a fourth voltage, which is a power supply voltage used by circuit elements of the second chip, which will be described later. Pad electrodes 120, 122, and 354 are provided in regions 160 and 161. Each of the pad electrodes 352, 120, and 122 receives a power supply voltage supplied from outside the semiconductor element through a corresponding pin 102.

[0049] Fig. 7 is a cross-sectional view corresponding to the position of line AB shown in Fig. 6. In Fig. 7, the same members as those shown in Fig. 6 are denoted by the same reference numerals as those used in Fig. 6.

[0050] The first chip 301 has a first semiconductor layer 302 and a first wiring layer 303. The first semiconductor layer 302 is provided with a semiconductor region included in the pixel 100. As the semiconductor region included in the pixel 100, a first semiconductor region 311 of a first conductivity type, a second semiconductor region 312 of a second conductivity type, and a third semiconductor region 313 of the first conductivity type are provided at positions where light transmitted through the microlens 344 is incident. When the signal charge is an electron, the first conductivity type is p-type and the second conductivity type is n-type. When holes are used as the signal charge, the first conductivity type is n-type and the second conductivity type is p-type. In this embodiment, the signal charge is an electron. The first semiconductor region 311 and the second semiconductor region 312 form an avalanche photodiode 331 corresponding to the avalanche photodiode 201 shown in FIG. 5(a).

[0051] In a plan view of the first chip 301 viewed from above, at least a portion of each of the first semiconductor region 311 and the second semiconductor region 312 overlaps with the microlens 344.

[0052] The third semiconductor region 313 is provided at both ends of the first semiconductor region 312, and alleviates electric field concentration in the first semiconductor region 312. At this time, the impurity concentration of the third semiconductor region 313 is set lower than the impurity concentration of the first semiconductor region 312. For example, when the impurity concentration of the first semiconductor region 312 is 6.0×10 18 [atoms / cm 3 ] or more, the impurity concentration of the third semiconductor region 313 is 1.0×10 16 [atoms / cm 3 ] or more, 1.0 × 10 18 [atoms / cm 3 ] below.

[0053] A fourth semiconductor region 316 of the second conductivity type is arranged in a region closer to the surface 350 than the second semiconductor region 312 (on the incident surface side). Furthermore, a fifth semiconductor region 314 of the second conductivity type is arranged between adjacent pixels as an inter-pixel isolation region, and a sixth semiconductor region 315 of the second conductivity type is arranged in a region closer to the surface 350 than the fourth semiconductor region 316.

[0054] Here, the impurity concentrations of the fifth semiconductor region 314 and the sixth semiconductor region 315 are made higher than the impurity concentration of the fourth semiconductor region 316. This makes it easier for charges generated by photoelectric conversion in the fourth semiconductor region 316 to be collected in the avalanche photodiode 324 rather than leaking into adjacent pixels. Therefore, the charges generated in the fourth semiconductor region 316 are efficiently avalanche multiplied.

[0055] A pinning film 341 is provided on the upper surface of the sixth semiconductor region 315. This makes it possible to reduce dark current occurring near the surface of the semiconductor layer 302.

[0056] A planarization layer 342 is provided on the pinning film 341. A color filter layer 343 and a microlens 344 are provided on the planarization layer 342.

[0057] The first chip 301 has a wiring layer 303. The wiring layer 303 has a first wiring layer 321 and a second wiring layer 324. The first wiring layer 321 and the fifth semiconductor region 314 are connected by a contact plug 322. The first wiring layer 321 and the second wiring layer 324 are connected by a via 323.

[0058] The first chip 301 has an opening 351 for exposing the pad electrode 352. The pad electrode 352 is provided on the bottom surface of the opening 351. The opening 351 is provided between a surface 350 (first surface) and a surface 370 (second surface) of the first chip 301. The surface 370 will be described later, and is the bonding surface between the first chip 301 and the second chip 401. The pad electrode 352 is connected to the pin 102 shown in FIG. 6 by a wire provided in the opening 351. When the pad electrode 352 is provided on the top layer of the wiring layer 303, the top layer of the wiring layer 303 may be made of aluminum wiring, and the other wiring layers may be made of copper wiring.

[0059] The first chip 301 has an opening 353 for exposing the pad electrode 354. The pad electrode 354 is provided on the bottom surface of the opening 353. The opening 353 is provided between a surface 350 (first surface) and a surface 370 (second surface) of the first chip 301. The surface 370 will be described later, and is the bonding surface between the first chip 301 and the second chip 401. The pad electrode 354 is connected to the pin 102 shown in FIG. 6 by a wire provided in the opening 353. When the pad electrode 354 is provided on the top layer of the wiring layer 331, the top layer of the wiring layer 331 may be made of aluminum wiring, and the other wiring layers may be made of copper wiring.

[0060] The pad electrode 354 is connected to wiring 414 provided on the second chip 401 through multiple joints 380. The wiring 414 is connected to other wiring provided on the wiring layer 403 through vias. The second chip 401 includes a circuit for processing signals output from the first chip 301. The second chip 401 includes a semiconductor layer 402. The semiconductor layer 402 includes a sixth semiconductor region 411. The sixth semiconductor region 411 is connected to the first semiconductor region 311 of the first chip 301 through a contact plug 421, multilayer wiring provided on the wiring layer 403, joints 381, and multilayer wiring provided on the wiring layer 303. The second chip 401 further includes a gate electrode and source / drain regions (not shown) to form a MOS transistor. An example of a MOS transistor provided on the second chip 401 is a quench element. The quench element corresponds to the element 202 in Fig. 2 and functions as a load circuit when photoelectrically converted charges are avalanche multiplied. It functions as a quenching operation that suppresses avalanche multiplication by suppressing the voltage supplied to the avalanche photodiode 324.

[0061] Between adjacent MOS transistors, an element isolation region 412 is arranged. The element isolation region 412 may be, for example, LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation).

[0062] The junction 384 disposed on the wiring layer 403 of the second chip 401 serves to transmit the output of the avalanche photodiode 331 of the first chip 301 to the second chip 401. This junction is a metal wiring such as a copper wiring.

[0063] A multilayer wiring layer 431 (second multilayer wiring layer) is arranged on the wiring layer 403 of the second chip 401. This multilayer wiring layer 431 is, for example, wiring for transmitting signals sent from the first chip 301 to the processing circuit of the second chip 401, and power supply wiring and ground wiring for driving the signal processing unit 102 mounted on the second chip 401.

[0064] The semiconductor layer 411 of the second chip 401 includes a ground area (not shown). A voltage of ground potential (ground voltage; third voltage) is supplied to the ground area from the pad electrode 122 shown in FIG. 6. Note that it is not necessary to provide a ground area to which the voltage applied from the pad electrode 122 is supplied. In this case, the voltage applied from the pad electrode 122 is directly supplied to other circuit elements.

[0065] Furthermore, a power supply voltage VH is supplied to the semiconductor region 411 arranged on the second chip 401 through a pad electrode 354 arranged at the bottom of the opening 353 and a quench element (not shown).

[0066] The effects of this embodiment will be described. As shown in FIG. 6, the pad electrode 352 that receives the first voltage supplied to the pixel 100 is arranged in the long-side region of the first chip 301. As an example, FIG. 6 shows pixel 100-1. In pixel 100-1, distance B to the pad electrode in the long-side region is shorter than distance A to the pad electrode in the short-side region. Thus, pixels 100 in which the distance to the pad electrode in the long-side region is shorter than the distance to the pad electrode in the short-side region are within the region X enclosed by the dashed-dotted line. Therefore, placing the pad electrodes that supply power supply voltage to pixels 100 arranged across multiple rows and columns in the long-side region shortens the transmission distance of the power supply voltage. This shortening of the transmission distance of the power supply voltage has the advantageous effect of reducing the amount of power supply voltage drop and stabilizing the power supply voltage in semiconductor elements where the power supply voltage is prone to fluctuations due to avalanche multiplication.

[0067] In this embodiment, the number of pad electrodes 352 provided on the first chip 301 is greater than the number of pad electrodes 122 receiving the third voltage. By providing a large number of pad electrodes 352 in this manner, the number of pixels 100 covered by one pad electrode 352 can be reduced. This allows the current flowing through the pad electrodes 352 due to avalanche multiplication of the pixels 100 to be leveled among the multiple pad electrodes 352. This reduces fluctuations in the power supply voltage supplied to other pixels 100 due to avalanche multiplication in one pixel 100, thereby reducing crosstalk. Typically, 10 to 200 columns of pixels 100 should be associated with one pad electrode 352. More preferably, 50 to 100 columns of pixels 100 should be associated with one pad electrode 352. Similarly, the pad electrodes 120 receiving the second voltage are provided in the long side regions of the first chip 301. Furthermore, the number of pad electrodes 120 is greater than the number of pad electrodes 122. This, like the pad electrode 352, provides the advantageous effects of reducing (stabilizing) fluctuations in the power supply voltage and reducing crosstalk. Furthermore, by providing an area in which the pad electrode 120 is disposed between the multiple pad electrodes 352, the pad electrodes 352 and 120 can be disposed with less positional deviation. From another perspective, it can also be said that the pad electrode 352 is disposed between the multiple pad electrodes 120. If only the multiple pad electrodes 352 are disposed in the area 150 and only the multiple pad electrodes 120 are disposed in the area 151, the first voltage will be supplied from the area 140 and the second voltage will be supplied from the area 151. Therefore, with regard to the supply of the power supply voltage, deviations will occur depending on the position of the pixel 100 in the pixel array 110. In this embodiment, this deviation can be reduced. Furthermore, among the long side regions, there is a region 150 that is closer to one of the short sides than the center line along the short sides of the pixel array 110, and a region 151 that is closer to the other short side than the center line. It can be said that in each of the regions 150 and 151, a region is provided in which the pad electrode 120 is arranged between a plurality of pad electrodes 352. From another perspective, it can be said that the pad electrode 352 is arranged between a plurality of pad electrodes 120.This makes it possible to make it more difficult for the supply of the first voltage and the second voltage to be biased depending on the position of the pixel array 110.

[0068] As described above, the semiconductor device according to this embodiment has advantageous effects in stabilizing the power supply voltage and reducing crosstalk.

[0069] (Other Examples) In the first embodiment, an example in which the pad 120 is arranged between a plurality of pads 352 has been shown, but this is not limited to this example. For example, the pad 122 or the pad 354 may be arranged between a plurality of pads 352. In such a case, it can also be said that the second electrode is arranged between a plurality of first electrodes. Furthermore, the pad 122 or the pad 354 may be arranged between a plurality of pads 120.

[0070] Further, pads 352 may be arranged in the short side regions as well. In this case, the pads 352 in the short side regions are also connected to the power supply wiring 130.

[0071] In the first embodiment, an example has been described in which the pad electrode 354 is provided on the first chip 301, but as shown in Fig. 8, the pad electrode 354 may be provided on the second chip 401. Since the pad electrode 354 is an electrode that receives the power supply voltage used by the circuit provided on the second chip 401, providing the pad electrode 354 on the second chip 401 can shorten the supply path of the power supply voltage.

[0072] 9, buried electrodes 441 and 442 may be provided that penetrate the semiconductor layer 402 and the wiring layer 403 to receive the power supply voltage from outside the semiconductor element. In this case, there is no need to provide a pad opening, and the area of the electrode portion that receives the power supply voltage can be reduced. This is therefore advantageous for miniaturizing the semiconductor element.

[0073] Furthermore, in the first embodiment, the pad 122 that receives the third voltage is provided between the pad electrode 120 and the pad electrode 352, but as shown in FIG. 10, a configuration in which the pad 122 is not provided may also be used.

[0074] Furthermore, in the first embodiment, the pad electrodes 352 and the pad electrodes 120 are arranged alternately. However, as shown in FIG. 11, a set in which a plurality of pad electrodes 352 are arranged adjacently and a set in which a plurality of pad electrodes 120 are arranged adjacently may be arranged alternately. In the example of FIG. 11, a double bonding configuration is used in which a plurality of pad electrodes are connected to one pin. Furthermore, as shown in FIG. 12, each of the sets may include three or more pad electrodes. In the configuration of FIG. 12, a triple bonding configuration is used in which three or more pad electrodes are connected to one pin. Furthermore, single bonding, double bonding, and triple bonding may be combined as appropriate.

[0075] In the first embodiment, the pad electrodes 352 and the pad electrodes 120 are alternately arranged, but as shown in Fig. 13, a set of adjacently arranged pad electrodes 352 and a set of adjacently arranged pad electrodes 120 may alternate in set units. In Fig. 13, a pad 122 to which a third voltage is supplied is arranged between the sets.

[0076] 14, in a configuration in which a plurality of pad electrodes 352 are connected to one pin, the pad electrodes 352 connected to different pins may be adjacent to each other. Even in this configuration, there is an area in which the pad 352 and the pad 120 are adjacent to each other.

[0077] 15, a dummy pad electrode 500 may be arranged in the long side region. A pin may or may not be connected to the dummy pad electrode 500. The potential of the pad electrode 500 may be floating, or a predetermined voltage may be supplied to it.

[0078] In addition to the circuit for processing the signals output from the pixel array 110, the second chip 401 may further include a computing element for performing image processing, signal arithmetic processing, and calculations using a neural network that is updated as appropriate.

[0079] Furthermore, in this embodiment, a semiconductor element in which the first chip 301 and the second chip 401 are stacked has been described, but the semiconductor element may also be a non-stacked chip in which the pixel array 110 and a circuit for processing signals output by the pixel array 110 are provided on a single chip.

[0080] In addition, although the present embodiment has described a semiconductor device in which first chip 301 and second chip 401 are stacked, another chip may be stacked on top of it. This chip may be provided with a storage component such as a memory element, or with a computing element that performs image processing, signal processing, and calculations using a neural network that is updated as needed.

[0081] As described above, the semiconductor elements described in this embodiment and other examples have the advantageous effects of stabilizing the power supply voltage and reducing crosstalk.

[0082] (Second embodiment) This embodiment is applicable to any of the semiconductor elements described in the first embodiment and other examples. FIG. 16( a) is a schematic diagram illustrating a device 9191 including a semiconductor device 930 according to this embodiment. The device 9191 including the semiconductor device 930 will be described in detail. As described above, the semiconductor device 930 includes a package 920 that houses the semiconductor device 910 in addition to the semiconductor device 910. The package 920 can include a base to which the semiconductor device 910 is fixed and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910. The semiconductor device 910 and the package 920 can be applied as the semiconductor elements described in the first embodiment and other examples.

[0083] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a memory device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0084] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0085] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0086] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0087] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0088] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0089] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0090] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration. [Explanation of symbols]

[0091] 100 pixels 102 pins (package connection terminal) 110 pixel array 120, 122, 352, 354 Pad electrode (electrode) 301 First Chip 401 Second Chip

Claims

1. A semiconductor device including an array in which a plurality of avalanche photodiodes are arranged, the semiconductor element includes a plurality of first electrodes to which a first voltage used for the plurality of avalanche photodiodes is externally supplied, and a second electrode used for the plurality of avalanche photodiodes to which a second voltage different from the first voltage is externally supplied, the plurality of first electrodes and the second electrode are disposed outside the array; the second electrode is disposed between one of the plurality of first electrodes and another of the plurality of first electrodes; the semiconductor element has a shape with two long sides and two short sides on its periphery, The semiconductor element, wherein the plurality of first electrodes and the second electrodes are arranged outside the array in regions on each of the two long sides.

2. wiring arranged along the periphery of the array; 2. The semiconductor element according to claim 1, wherein the plurality of first electrodes in a region of one of the two long sides and the plurality of first electrodes in a region of another long side are connected to the wiring.

3. a plurality of the second electrodes; 3. The semiconductor element according to claim 2, wherein a plurality of pairs each including the plurality of first electrodes and the plurality of second electrodes are provided in the region of the long side.

4. 4. The semiconductor element according to claim 3, wherein a third electrode is disposed between one of the plurality of pairs and another of the plurality of pairs, to which a third voltage different from the first voltage and the second voltage is supplied from outside.

5. 5. The semiconductor element according to claim 3, wherein each of the plurality of sets has a plurality of adjacent first electrodes and a plurality of adjacent second electrodes, and one of the adjacent first electrodes and one of the adjacent second electrodes are adjacent to each other.

6. The semiconductor element according to any one of claims 2 to 5, further comprising a fourth electrode to which a fourth voltage different from the first voltage and the second voltage is supplied, the fourth electrode being arranged in the region of the short side.

7. The semiconductor element according to any one of claims 1 to 5, characterized in that the semiconductor element has a stacked structure of a first chip having the array and a second chip having a circuit for processing signals output from the first chip.

8. 8. The semiconductor device according to claim 7, wherein the plurality of first electrodes and the second electrode are disposed on the first chip.

9. the first chip includes a semiconductor layer including the array and a wiring layer; 9. The semiconductor element according to claim 8, wherein the plurality of first electrodes and the second electrode are disposed on the wiring layer.

10. a plurality of joints at which the first chip and the second chip are electrically connected; the second chip includes a semiconductor region in which a quenching element is disposed, the semiconductor region being connected to the avalanche photodiode by one of the plurality of junctions; a difference between the second voltage and a ground voltage is smaller than a difference between the first voltage and the ground voltage, and the first voltage is supplied to the semiconductor region via the first electrode and one junction among the plurality of junctions; 10. The semiconductor device according to claim 8, wherein the first voltage is supplied to the avalanche photodiode from the semiconductor region via the junction.

11. 11. The semiconductor device according to claim 10, further comprising a fourth electrode to which a fourth voltage different from the first voltage and the second voltage is supplied, the fourth electrode being connected to the circuit of the second chip via one of the plurality of junctions.

12. A semiconductor element according to any one of claims 8 to 10, characterized in that the second chip is provided with a fourth electrode to which a fourth voltage different from the first voltage and the second voltage is supplied, and the fourth electrode is connected to the circuit of the second chip.

13. 13. The semiconductor device according to claim 1, wherein the first electrode is connected to a pin via a wire, and the first voltage is supplied to the pin from outside.

14. 14. The semiconductor element according to claim 13, wherein each of the plurality of first electrodes is connected to a corresponding one of a plurality of wires, and the plurality of wires are connected to one of the pins.

15. 14. The semiconductor element according to claim 13, further comprising a plurality of pins, each of the plurality of first electrodes being connected to a corresponding one of a plurality of wires, and the plurality of wires being connected to different pins.

16. 16. The semiconductor device according to claim 1, wherein the second voltage is a voltage supplied to the plurality of avalanche photodiodes.

17. An apparatus comprising the semiconductor device according to any one of claims 1 to 16, an optical device corresponding to the semiconductor element; a control device for controlling the semiconductor device; a processing device that processes signals output from the semiconductor device; a display device that displays information obtained by the semiconductor device; a storage device that stores information obtained by the semiconductor device; and and a mechanical device that operates based on information obtained by the semiconductor element.

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