Circuit board, semiconductor device, device, circuit board driving method, and semiconductor device manufacturing method

Abstract

To improve the yield of a semiconductor device.SOLUTION: A circuit board for lamination to another board includes a plurality of signal lines, a plurality of input units connected to the plurality of signal lines and receiving signals from the outside of the circuit board, a plurality of signal processing circuits connected to the plurality of input units via the plurality of signal lines, and a plurality of transistors that supply predetermined voltages to the plurality of signal lines in a state in which no signal is input from the outside to the plurality of input units.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a circuit board, a semiconductor device, an apparatus, a method for driving a circuit board, and a method for manufacturing a semiconductor device. [Background technology]

[0002] 2. Description of the Related Art In the field of semiconductors such as memories and image sensors, semiconductor devices in which a plurality of substrates are stacked are known.

[0003] One example of such a stacked photoelectric conversion device is a stacked photoelectric conversion device. A known example of such a photoelectric conversion device is the configuration disclosed in Patent Document 1. In this configuration, a signal processing circuit for processing signals output by the pixels is provided on a circuit board that is to be stacked on a pixel board on which pixels having photoelectric conversion units are provided.

[0004] Furthermore, Patent Document 2 describes a configuration in which a predetermined voltage is supplied to a plurality of signal lines to which a plurality of signal processing circuits are connected. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-68271 [Patent Document 2] International Publication No. 2015 / 151793 Brochure Summary of the Invention [Problem to be solved by the invention]

[0006] When multiple substrates are stacked and then inspected, even if some of the substrates have defects (failures, poor characteristics, etc.), the defects cannot be detected and other normal substrates are stacked. As a result, not only the defective substrate but also the normal substrates stacked on the defective substrate cannot be shipped, or a process for separating the substrates is required. This reduces the yield of semiconductor devices.

[0007] Patent Documents 1 and 2 do not consider such issues at all. [Means for solving the problem]

[0008] One aspect of the present disclosure is a circuit board to be stacked on another board, the circuit board comprising: a plurality of signal lines; a plurality of input units connected to the plurality of signal lines and receiving signals from outside the circuit board; a plurality of signal processing circuits connected to the plurality of input units via the plurality of signal lines; and a plurality of transistors that supply a predetermined voltage to the plurality of signal lines when no signals are being input to the plurality of input units from outside. a plurality of current sources connected to the plurality of signal lines; and a plurality of second transistors connected to each of the plurality of signal lines, for switching between conduction and non-conduction of an electrical path between a corresponding input section of the plurality of input sections and a corresponding signal processing circuit of the plurality of signal processing circuits, wherein one node of each of the plurality of second transistors is connected to a corresponding transistor of the plurality of transistors and a corresponding current source of the plurality of current sources, and the other node of each of the plurality of second transistors is connected to a corresponding signal processing circuit of the plurality of signal processing circuits. The circuit board is characterized by the above. [Effects of the Invention]

[0009] The present disclosure can improve the yield of semiconductor devices. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a diagram showing the configuration of a photoelectric conversion device; [Figure 2] 1 is a diagram showing the configuration of a photoelectric conversion device; [Figure 3] Diagram showing the pixel configuration [Figure 4] A diagram showing the operation of the second substrate [Figure 5] 1 is a diagram showing the configuration of a photoelectric conversion device; [Figure 6] 1 is a diagram showing the configuration of a photoelectric conversion device; [Figure 7] A diagram showing the operation of the second substrate [Figure 8] FIG. 1 shows the configuration of a second substrate [Figure 9] A diagram showing the operation of the second substrate [Figure 10] A diagram showing the operation of the second substrate [Figure 11] FIG. 1 shows the configuration of a second substrate [Figure 12] A diagram showing the operation of the second substrate [Figure 13] FIG. 1 shows the configuration of a second substrate [Figure 14] Equipment configuration diagram DETAILED DESCRIPTION OF THE INVENTION

[0011] In the following embodiments, a photoelectric conversion device will be described as an example of an application of a circuit board. The photoelectric conversion device will be described, focusing on an imaging device. However, the embodiments are not limited to imaging devices and can be applied to other examples of photoelectric conversion devices. For example, a distance measuring device (a device that measures distance using focus detection or TOF (Time Of Flight)) or a photometric device (a device that measures the amount of incident light) can be used. Furthermore, application examples of the circuit board of the present disclosure are not limited to photoelectric conversion devices, but can also be applied to various semiconductor devices such as memories (DRAMs, etc.) and light-emitting devices.

[0012] In the following description, the substrate will be described as including not only the semiconductor layer but also the interlayer insulating film and wiring layer provided on the semiconductor layer.

[0013] The conductivity types of the transistors described in the following embodiments are merely examples and are not limited to those described in the embodiments. The conductivity types described in the embodiments can be changed as appropriate, and the potentials of the gate, source, and drain of the transistors can be changed as appropriate.

[0014] For example, in the case of a transistor operated as a switch, the low and high levels of the potential supplied to the gate may be reversed in accordance with the change in the conductivity type. The conductivity types of the semiconductor regions described in the following examples are merely examples and are not limited to the conductivity types described in the examples. The conductivity types described in the examples can be changed as appropriate, and the potential of the semiconductor regions is accordingly changed accordingly.

[0015] Furthermore, the transistors described in the following embodiments are typically MOS transistors, but other types of transistors may also be used, such as thin film transistors.

[0016] In the following examples, connections between circuit elements may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest will be treated as being connected unless otherwise specified. For example, assume that element A is connected to one node of a capacitance element C having multiple nodes, and element B is connected to the other node. Even in such a case, elements A and B will be treated as being connected unless otherwise specified.

[0017] Example 1 The present embodiment will be described below with reference to the drawings.

[0018] FIG. 1 is a diagram showing a first substrate 1 and a second substrate 5 included in the photoelectric conversion device of this embodiment. The first substrate 1 is a pixel substrate (pixel chip) on which a plurality of pixels 10 are arranged across a plurality of rows and a plurality of columns. The second substrate 2 is a circuit substrate (circuit chip) on which a plurality of signal processing circuits are arranged. Note that although the pixels 10 are illustrated here, the first substrate 1 also has control lines for controlling the pixels 10 and signal lines for transmitting signals output by the pixels 10. Drive circuits such as a vertical scanning circuit and a timing generator are also arranged on the first substrate 1 or the second substrate 5 as appropriate. The second substrate 5 also has a plurality of signal processing circuits arranged thereon.

[0019] FIG. 2 is a diagram showing the configuration of the photoelectric conversion device shown in FIG.

[0020] The first substrate 1 includes a pixel array 3 arranged across multiple rows and multiple columns, and pixel signal lines L1 to L4. The pixel signal line L1 is connected to a junction 110a provided on the first substrate 1. Similarly, the pixel signal lines L2 to L4 are connected to corresponding junctions 111a, 112a, and 113a. The pixel array 3 typically has several thousand rows and several thousand columns of pixels 10, but FIG. 2 shows only a portion of those pixels 10.

[0021] The configuration of pixel 10 will be described with reference to FIG. 3. FIG. 3 shows an example circuit of pixel 10. In FIG. 3, 460 denotes a power supply terminal, 450 denotes a GND terminal, and 455 denotes a reset transistor. Photocharges generated in a photodiode 400, which is a photoelectric conversion unit, are transferred to a floating diffusion 420 by turning on a transfer transistor 410, and are converted into a signal voltage by a parasitic capacitance associated with the floating diffusion 420. The signal voltage is then output to a corresponding signal line (denoted as signal line L1 in FIG. 3) among signal lines L1 to L4 via an amplification transistor (source follower transistor) 430 and a selection transistor 440. The amplification transistor 430, together with the current source 40 of FIG. 2, forms a source follower, and the signal voltage on the floating diffusion 420 is buffered by the source follower and output to signal line L1.

[0022] Referring again to FIG.

[0023] The bonding portion 110a is bonded to the bonding portion 110b provided on the second substrate 2. The first substrate 1 and the second substrate 2 are bonded together so that the first substrate 1 is on top and the second substrate 2 is on the bottom when viewed from the light incident surface. The first substrate 1 and the second substrate 2 are electrically connected by the bonding of the bonding portions 110a and 110b. This electrical connection can be achieved using a TSV (Through Silicon Via) structure. Another connection method is hybrid bonding, in which insulating films and conductive members provided in grooves in the insulating films are provided on the bonding surfaces of the first substrate 1 and the second substrate 2, respectively, and the insulating films and conductive members are bonded to each other. Typically, the conductive members are primarily composed of copper. The insulating film can be a single-layer film made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon oxycarbide, or the like, or a multilayer film combining multiple layers. Note that the electrical connection between the multiple substrates is not limited to these forms; various connection methods, such as microbumps, can also be used.

[0024] Similarly, bonding portions 111a, 112a, and 113a are respectively bonded to bonding portions 111b, 112b, and 113b provided on the second substrate 2. When the bonded bonding portions of the first substrate 1 and the second substrate 2 are to be collectively represented, the "a" and "b" at the end of the reference numerals are deleted. For example, as shown in FIG. 2, when bonded bonding portions 110a and 110b are collectively represented, they are represented as bonding portion 110. The same applies to the other bonding portions.

[0025] The second substrate 2 has signal lines 30 to 33 connected to the joints 110b, 111b, 111c, and 111d. The joints 110b, 111b, 111c, and 111d are a plurality of input units to which signals are input from outside the second substrate 2, which is a circuit board. In the example of Fig. 2, the signals input from outside are pixel signals output by the pixels 10.

[0026] Current sources 40 to 43 are connected to the signal lines 30 to 33. The current sources 40 to 43 supply current to the signal lines 30 to 33. The current sources 40 to 43 also supply current to the pixels 10 via the junctions 110 to 113 and the pixel signal lines L1 to L4 of the first substrate 1. The current sources 40 to 43 supply current to the amplification transistors provided in the pixels 10. As a result, as described above, the current sources 40 to 43, together with the amplification transistors provided in the pixels 10, form a source follower circuit.

[0027] N-type transistors 20 to 23 are connected to the signal lines 30 to 33. The transistors 20 to 23 can be operated as switches. Furthermore, like the amplifying transistors of the pixel 10 described above, the transistors 20 to 23 can also function as source-follower transistors by operating together with current sources 40 to 43.

[0028] A control line C1 that transmits a signal VC1 is connected to the gates of the transistors 21 and 23. A control line C2 that transmits a signal VC2 is connected to the gates of the transistors 20 and 22. Although two control lines C1 and C2 are provided in FIG. 2, they may be connected to a single common control line. Even in this configuration, it is possible to inspect whether the signal processing circuits P1 to P4 are normal. One main node of the source or drain of the transistors 20 to 24 is connected to a power supply voltage supply node, and the other main node of the source or drain is connected to signal lines 30 to 33. The transistors 20 to 23 are a plurality of transistors that supply a predetermined voltage (test voltage) to the signal lines 30 to 33. When the transistors 20 to 23 act as switches, they can also be said to be a plurality of transistors that switch between supplying and not supplying a predetermined voltage. The predetermined voltage supplied by the transistors 20 to 23 is typically a voltage that is lower by the threshold voltage of the transistors 20 to 23 than the power supply voltage supplied to one of the main nodes of the transistors 20 to 23. In addition, due to various resistance components and capacitance components such as the on-resistance of the transistors 20 to 23, a voltage different from the power supply voltage supplied to one of the main nodes of the transistors 20 to 23 may be supplied to the signal lines 30 to 33.

[0029] When the transistors 20- operate as switches, the reference voltage that is the basis for the predetermined voltages supplied to the signal lines 30-33 is the power supply voltage applied to the main nodes of the transistors 20- .

[0030] When the transistors 20 to 23 are operated as source follower transistors, a predetermined voltage based on the potentials of the signal lines VC1 and VC2 is output as a source follower to the signal lines 30 to 33. In this case, the potentials of the signal lines VC1 and VC2 become reference voltages that determine the value of the predetermined voltage.

[0031] Transistors S1 to S4 are connected to the signal lines 30 to 33. One main node of the transistor S1 is connected to the current source 40, the transistor 20, and the junction 110, and the other main node is connected to the comparator 60. Similarly, one main node of each of the transistors S2 to S4 is connected to the corresponding current sources 41 to 43, the transistors 21 to 23, and the junctions 111 to 113. The other main nodes of each of the transistors S2 to S4 are connected to the corresponding comparators 61 to 63. The transistors S1 to S4 operate as switches that switch the electrical paths between the multiple input sections 110 to 114 and the signal processing circuits P1 to P4 between conductive and non-conductive states. After being stacked on the first substrate 1, these switches are turned on and off according to the timing of reading out signals from the pixels 10. Typically, the transistors S1 to S4 are controlled to be off during the period in which the transfer transistor 410 of the pixel 10 is turned on and charge is transferred from the photodiode 400 to the floating diffusion 420. After the transfer transistor 410 changes from on to off, the transistors S1 to S4 are turned on, and the output of the pixel 10 is input to the signal processing circuits P1 to P4.

[0032] The second substrate 2 has a plurality of signal processing circuits P1 to P4. The signal processing circuit P1 has a comparator 60, a first memory 70, and a second memory 80. Similarly, the signal processing circuits P2 to P4 also have comparators 61 to 63, first memories 71 to 73, and second memories 81 to 83.

[0033] The second substrate 2 has a ramp signal supply circuit 50. The ramp signal supply circuit 50 supplies ramp signals to the comparators 60 to 63. A ramp signal is a signal whose voltage increases or decreases over time. This voltage change does not need to be constant, and the amount of change may vary along the way. Furthermore, the voltage change is not limited to a slope-like waveform, and may take the form of a step-like change.

[0034] The second substrate 2 has a counter 90. The counter 90 generates a count signal by counting the clock signal supplied thereto. This count signal is supplied to the first memories 70 to 73. The first memories 70 to 73 hold count signals corresponding to the timing at which the output signals of the corresponding comparators 60 to 63 change. This count signal is a digital signal corresponding to the input signal (analog signal). In this way, each of the signal processing circuits P1 to P4 can perform AD conversion, converting the input signal into a digital signal. In other words, each of the signal processing circuits P1 to P4 is an AD conversion unit that converts the input signal (including the predetermined voltage supplied from the transistors 20 to 23) into a digital signal.

[0035] The digital signal of the first memory 70 is transferred to the second memory 80 and then output outside the chip via the output circuit 100. Although this embodiment shows an example in which a common counter 90 is used for a plurality of circuits, a configuration in which a common count clock is supplied and a counter is provided for each circuit corresponding to each signal line can also be applied.

[0036] In this embodiment, transistors 20 to 23 are provided on the second substrate 2. These transistors 20 to 23 can be controlled by signals VC1 and VC2 even before the second substrate 2 and the first substrate 1 are stacked together. That is, the transistors 20 to 23 can supply a predetermined voltage to the signal lines 30 to 33 when no signals are input to the input sections 110 to 114. The signals VC1 and VC2 can be supplied from a control circuit provided inside the substrate. As another example, input pads to which the signals VC1 and VC2 are input may be provided on the second substrate 2 or the first substrate 1, and the signals VC1 and VC2 may be supplied from an external source.

[0037] When signals VC1 and VC2 go high, transistors 20-23 are turned on, and a predetermined voltage is supplied to signal lines 30-33. This predetermined voltage is input to signal processing circuits P1-P4 via signal lines 30-33. Each of signal processing circuits P1-P4 converts the input predetermined voltage into a digital signal, similar to AD conversion of pixel signals. At this time, if there is a break in signal lines 30-33 or if there is a malfunction or characteristic defect in signal processing circuits P1-P4, a digital signal will not be generated, or a digital signal of an expected value will not be generated. Therefore, second substrate 2 can be inspected based on whether digital signals are output from signal processing circuits P1-P4 and whether the difference between the output digital signal and the expected value is smaller than a predetermined amount. Therefore, second substrate 2 can be inspected individually before first substrate 1 and second substrate 2 are stacked. If the second substrate 2 is not inspected separately but is inspected after the first and second substrates 1 and 2 are stacked, the following problems arise if the second substrate 2 is defective. First, the process of stacking the defective second substrate 2 on the first substrate 1 results in lost man-hours, reducing the yield of photoelectric conversion devices. This process also incurs cost losses. Furthermore, if the first substrate 1 is normal, the normal first substrate 1 is lost. This reduces the yield of photoelectric conversion devices. Separating the first and second substrates 1 and 2 after stacking them is difficult because it can damage the joints. Even if the substrates are separated, additional processing steps are required, resulting in losses and a reduction in the yield of photoelectric conversion devices. Furthermore, when inspecting the first and second substrates 1 and 2 after stacking them, it can be difficult to determine whether the defect is in the first or second substrate 1 or 2. As a result, it is difficult to properly feed back inspection results to the manufacturing equipment used to manufacture the photoelectric conversion devices, making it difficult to improve the yield of photoelectric conversion devices.

[0038] In this embodiment, inspection of the second substrate 2 alone is achieved. This allows defects in the second substrate 2 to be detected before the first substrate 1 and the second substrate 2 are stacked. This reduces the man-hours and costs associated with the process of stacking the first substrate 1 and the defective second substrate 2. It also reduces the loss of normal first substrates 1, improving the yield of photoelectric conversion devices. Furthermore, when inspecting the first substrate 1 and the second substrate 2 after stacking them, it can be difficult to determine whether the defect is in the first substrate 1 or the second substrate 2. By inspecting the second substrate 2 alone, it becomes possible to clearly determine whether the defect is in the first substrate 1 or the second substrate 2. If a defect is detected in the second substrate 2 during inspection of the second substrate 2 alone, the inspection results can be fed back to the manufacturing equipment that produces the second substrate 2. Furthermore, when a defect is detected in a photoelectric conversion device using a second substrate 2 that passed inspection of the second substrate 2 alone, it becomes easier to narrow down the possible defect location to either the first substrate 1 or the junction between the first substrate 1 and the second substrate 2. This allows the inspection results to be quickly fed back to the manufacturing equipment that manufactures the first substrate 1 and the manufacturing equipment that bonds the first substrate 1 and the second substrate 2. This has the effect of improving the yield of photoelectric conversion devices.

[0039] In this way, the technology of the present disclosure is particularly effective when the manufacturing equipment used to manufacture the first substrate 1 is different from the manufacturing equipment used to manufacture the second substrate 2. Furthermore, the manufacturing equipment used to manufacture the first substrate 1 and the manufacturing equipment used to manufacture the second substrate 2 often have different process rules. In particular, the manufacturing equipment used to manufacture the second substrate 2 uses a finer process rule than the manufacturing equipment used to manufacture the first substrate 1. In this case, since defects are more likely to occur in the second substrate 2 than in the first substrate 1, a configuration that allows inspection of the second substrate 2 alone is effective.

[0040] Although the effects have been described here mainly with respect to photoelectric conversion devices, the effects of this embodiment can also be obtained in semiconductor devices involving stacking of multiple substrates, such as memory elements and light-emitting devices.

[0041] Furthermore, in this embodiment, two control lines, C1 and C2, are provided to control the transistors 20 to 23. Even if a single common control line is used, it is effective in that it is possible to check whether the signal processing circuits P1 to P4 are operating normally, as described above. Below, we will explain the operation using the two control lines shown in the figure and the additional advantages that can be obtained.

[0042] 4, the inspection for short circuits between the signal lines 30 to 33 will be described. Here, the transistors 20 to 23 will be described as configuring source followers together with the current sources 40 to 43.

[0043] At time t0, the signals VC1 and VC2 are at the same potential. Voltages corresponding to the signals VC1 and VC2 appear on the signal lines 30 to 33.

[0044] At time t1, the ramp signal starts to operate. At time t2, the ramp signal input to the comparators 60-63 becomes equal to the signal on the signal line, causing the outputs of the comparators 60-63 to change. Based on this change in the outputs of the comparators 60-63, the first memories 70-73 hold count signals at this timing. These count signals have values corresponding to the length of time from when the ramp signal starts to operate until the outputs of the comparators 60-63 change. This allows AD conversion of the reference levels of the signals VC1 and VC2. Thereafter, at time t3, the ramp signal is reset.

[0045] At time t4, of signals VC1 and VC2, the voltage of signal VC2 is reduced. Now consider a case where a short circuit fault has occurred between signal lines 32 and 33. The potential of signal VC1 is not changed. Therefore, the potential of signal line 30 remains unchanged, and signal line 31 changes in accordance with the amount of change in VC2, whereas signal lines 32 and 33 are at an intermediate level between signal lines 30 and 31 due to the occurrence of a short circuit fault.

[0046] From time t5, the slope operation of the ramp signal starts again.

[0047] The output of comparator 60 changes at time t6, the output of comparators 62 and 63 changes at time t7, and the output of comparator 61 changes at time t8. Each of first memories 70 to 73 holds a count signal corresponding to the timing at which the output of the corresponding comparator 60 to 63 changes.

[0048] Then, a signal representing the difference between this and the AD conversion result of the reference level obtained at time t2 is generated. This difference may be generated by the output circuit 100 or may be generated inside the signal processing circuits P1 to P4. This difference signal is referred to as the generated signal. This generated signal is a signal obtained as a result of processing a predetermined voltage by the multiple signal processing circuits P1 to P4. The output circuit 100 is a circuit that compares the generated signal with an expected value. Furthermore, if the difference between the generated signal and the expected value is greater than a predetermined amount, the output circuit 100 outputs the detection result to the outside of the second substrate 2. This makes it possible to detect a defect in the second substrate 2.

[0049] The signals generated by the signal processing circuits P3 and P4 connected to the signal lines 32 and 33 differ from the expected values. As a result, it is possible to detect that a short circuit has occurred in the signal lines 32 and 33.

[0050] The comparison of the generated signal with the expected value may be performed outside the second substrate 2.

[0051] The above-described operation makes it possible to detect short circuits between multiple signal lines. While this operation has been described with a focus on short circuits between multiple signal lines, it is also possible to detect short circuits between the first memories 70-73 and between the second memories 80-83. It is also possible to detect whether the signal processing circuits P1-P4 are operating normally. It is also possible to check whether the output change timing of the comparators 60-63 deviates from a predetermined range, whether the first memories 70-73 and the second memories 80-83 are writing faults, and whether transmission faults occur between the memories. Although not shown in FIG. 2 , a horizontal scanning circuit may be provided that sequentially reads out digital signals from the second memories 80-83 for each column. In this case, it is also possible to check whether the horizontal scanning circuit is operating normally and whether the transmission path from the second memories 80-83 to the output circuit 100 is normal.

[0052] As described above, according to this embodiment, it is possible to inspect (evaluate) the second substrate 2 alone. This improves the yield of semiconductor devices. Also, by separating the control lines for some of the multiple transistors from the other transistors, it is possible to inspect for short-circuit defects.

[0053] 2, a capacitance element or a resistance element may be provided as appropriate. For example, a clamp capacitance element may be provided between the transistor S1 and the comparator 60. Even in this configuration, the transistor S1 and the comparator 60 can be said to be connected.

[0054] Furthermore, in this embodiment, the configuration in which two substrates are stacked has been described, but other substrates may also be stacked.

[0055] In addition, although the evaluation was made based on whether the difference between the generated signal and the expected value was smaller than a predetermined amount, this evaluation also includes a form in which it is determined whether the difference is larger than a predetermined amount. Furthermore, the evaluation may also be made based on whether the generated signal matches the expected value.

[0056] Example 2 Fig. 5 shows a schematic diagram of a photoelectric conversion device according to Example 2. The following description will focus on the differences from Example 1. Fig. 5 shows a switch group OFFS provided with a plurality of switches having the same functions as the transistors S1 to S4 shown in Fig. 2.

[0057] 5, one pixel column has 12 signal lines 30 to 35, 330 to 335. The signals supplied to the gates of the transistors 20 to 25 connected to the signal lines 30 to 35 are divided into signals VC1 to VC6.

[0058] This makes it possible to detect short circuits between different signal lines in the same pixel column.

[0059] Generally, when there are multiple signal lines per pixel column, the space between the lines becomes narrower, making short circuits more likely to occur, compared to when there is one signal line per pixel column as shown in Figure 2. The technology disclosed herein makes it possible to detect short circuits on the second substrate 2, thereby improving yield.

[0060] Example 3 6 and 7 show a schematic diagram and a timing chart of a photoelectric conversion device according to Example 3. The following description will focus on the differences from Example 1.

[0061] In this embodiment, the control lines (gate wiring) connected to the gates of the N-type transistors 20 to 27 are divided into multiple pixel column units (region units), which makes it possible to detect defects between columns over a wide range, not just adjacent columns.

[0062] In FIG. 6, the second substrate 2 has two circuit groups 190 and 191. The left half (circuit group 190) and the right half (circuit group 191) of the second substrate 2 are fabricated by two separate exposures using a common mask set. Therefore, the circuit groups 190 and 191 have substantially the same configuration. However, by subjecting the upper metal wiring layer to one-shot exposure, it is possible to mutually change the wiring states within the circuit groups 190 and 191. For example, the ramp signal supply circuit within the circuit group 191 can be made unused and inoperative. On the other hand, it is possible to supply the ramp signal generated by the ramp signal supply circuit 50 within the circuit group 190 to the circuit group 191. It is also possible to share the gate wiring 160 of the current source transistors 150 to 157 within the current sources 40 to 47 between the circuit groups 190 and 191. This reduces the difference in characteristics between the circuit groups 190 and 191.

[0063] In this example, the gate wiring of the N-type transistors 20 to 27 is divided into multiple pixel column units (region units). This makes it possible to inspect for interference defects between columns over a wide range (not limited to adjacent columns) caused by shorts or coupling from the signal lines 30 to 37 to the wiring 160. The operation will be explained using the timing chart in Figure 7.

[0064] At time t0, the potentials of signals VC1 to VC4 are equal. N-type transistors 20 to 27 form source followers with current sources 40 to 47, and voltages corresponding to the potentials of signals VC1 to VC4 appear on signal lines 30 to 37. At time t1, the ramp signal starts to operate. At time t2, the ramp signal input to the comparator and the signal on the signal line become equal, causing the output of the comparator to change. The time required for this change is measured by counters 90 and 91, and stored in first memories 70 to 77, thereby performing AD conversion of the reference levels of VC1 to VC4. At time t3, the ramp signal is reset.

[0065] At time t4, the voltages of signals VC2 and VC4 among signals VC1 to VC4 are reduced. This reduces the potentials of signal lines 32, 33, 36, and 37. Consider a case where a large capacitive coupling or short circuit occurs between one of signal lines 32, 33, 36, and 37 and wiring 160. When a large capacitive coupling or short circuit occurs, the potential of wiring 160 temporarily drops at time t4 in FIG. 7. This reduces the current of current source transistors 150 to 157, causing the potentials of signal lines 30, 31, 34, and 35 to fluctuate. At time t6, when the potentials become equal to the ramp signal, an error occurs compared to when there is no defect. This operation makes it possible to detect abnormalities in the output results of the signal lines. This allows for stacking of the first substrate 1 after excluding defective second substrates 2, thereby improving the yield of stacked chips. Therefore, the gate wiring of N-type transistors 20 to 27 is separated. This enables detection of interference defects between columns over a wide area (not limited to adjacent columns) and improves the yield of photoelectric conversion devices.

[0066] 6, the transistors S1 to S4 shown in Fig. 2 are omitted, but they can be provided in the same manner as in Fig. 2. In this case, both the circuit groups 190 and 191 are provided with the transistors S1 to S4.

[0067] Example 4 8, 9 and 10 show a schematic diagram and a timing chart of a photoelectric conversion device according to Example 4. The following description will focus on the differences from Example 3.

[0068] In FIG. 8, signal lines 30 to 35 are provided, with six signal lines per column. Also, switches 200 to 205 are provided. Furthermore, N-type transistors 26, 27, and 28 and switches 206, 207, and 208 are provided in columns in another region. In this embodiment, like FIG. 6, it is possible to inspect for interference defects between columns over a wide range, while also being able to inspect for short-circuit defects between signal lines within the same column as in FIG. 4. Furthermore, it is possible to suppress an increase in the number of control lines required.

[0069] First, detection of a short circuit between signal lines will be described with reference to FIG. 9. At time t0, signals VC1 to VC6 are equal. Furthermore, signals SW1 to SW4 are at a high level, and switches 200 to 205 are turned on, supplying signals VC1 to VC6 to the gates of N-type transistors 20 to 25, respectively. N-type transistors 20 to 25 form source followers with current sources 40 to 45, and voltages corresponding to signals VC1 to VC6 appear on signal lines 30 to 35. At time t1, the ramp signal begins to operate. At time t2, the ramp signal input to the comparator and the signal on the signal line become equal, causing the output of the comparator to change. The time required for this change is measured, and AD conversion of the reference levels of signals VC1 to VC6 is performed. At time t3, the ramp signal is reset.

[0070] At time t4, among the signals VC1 to VC6, the voltages of signals VC2, VC4, and VC6 are reduced. This causes the potentials of the signal lines 30, 32, and 34 to differ from the potentials of the signal lines 31, 33, and 35. This makes it possible to detect short-circuit defects and improve yield, similar to the first and second embodiments.

[0071] Next, a wide-area inspection of column-to-column interference defects will be described with reference to FIG.

[0072] At time t0, signal VC1 is set to a high voltage. Signals SW1 to SW4 are also at a high level, and switches 200, 206 to 208 are turned on, supplying signal VC1 to the gates of N-type transistors 20, 26 to 28, respectively. N-type transistors 20, 26 to 28 form source followers with current sources 40, 46 to 48, and a voltage corresponding to signal VC1 appears on signal lines 30, 36 to 38. At time t1, the ramp signal begins to ramp. At time t2, the ramp signal input to the comparator and the signal on the signal line become equal, causing the output of the comparator to change. The time required for this change is measured, and A / D conversion of the reference level of signal VC1 is performed. At time t3, the ramp signal is reset. At time t3, signals SW1 and SW4 are set to a low level, turning off switches 200 and 208. As a result, the gate potential of N-type transistors 20 and 28 is maintained at the potential of signal VC1 at time t3, so when signal VC1 is lowered at time t4, the potentials of signal lines 36 and 37 only drop, without changing the potentials of signal lines 30 and 38. In this way, it is possible to apply different signals to signal lines in separate regions, just as in Figure 7. This makes it possible to inspect for interference defects between columns over a wide area, improving yield.

[0073] In this embodiment, the above two operations are realized with a total of 10 wires for signals VC1 to VC6 and signals SW1 to VC4, which is less than the 24 wires required when simply dividing the gates of all N-type transistors.

[0074] Example 5 11 and 12 show a schematic diagram and a timing chart of a photoelectric conversion device according to Example 5. The following mainly describes the differences from the second substrate 2 of Example 1. In FIG. 11, the N-type transistors 20 to 23 share a gate line, but have P-type transistors 210 to 213. That is, the transistors 210 to 213 are provided as transistors of a second conductivity type different from the first conductivity type which is the conductivity type of the transistors 20 to 23. These gate lines are divided into two systems for signals RES1 and RES2. This makes it possible to reduce power consumption during testing.

[0075] The operation will be described using FIG. 12. At time t0, signal RES1 is at a high level and signal RES2 is at a low level. As a result, P-type transistors 211 and 213 are off, and P-type transistors 210 and 212 are on. N-type transistors 21 and 23 form source followers with current sources 41 and 43, and a voltage corresponding to signal VC appears on signal lines 31 and 33. Normally, signal lines 30 and 32 are fixed to the power supply voltage. Consider a case where a short circuit occurs between signal lines 32 and 33. In this case, as shown in FIG. 12, signal line 33 is also fixed to the power supply voltage. This operation allows for detection of an abnormality in the output result of signal line 33, and for detection of a short circuit occurring between signal lines 32 and 33. This allows for stacking of the first substrate 1 after removing the defective second substrate 2, thereby improving the yield of stacked chips. Therefore, by separating the gate wiring of P-type transistors 210 to 213, short circuits can be detected, improving the yield.

[0076] Example 6 13 is a schematic diagram of a photoelectric conversion device according to Example 6. The following description will focus on the differences from the second substrate 2 of Examples 4 and 5.

[0077] In FIG. 13, signal lines 30-35 are provided, with six signal lines per column. Accordingly, N-type transistors 20-25 and P-type transistors 210-215 are provided. Furthermore, P-type transistors 216-218 are provided in a column in another region. Furthermore, control units 220 and 221 are provided in the center of each of circuit groups 190 and 191. In this embodiment, as in FIG. 8, it is possible to inspect for interference defects between columns over a wide range and for short-circuit defects between signal lines within the same column. Furthermore, it is possible to suppress an increase in the number of control lines.

[0078] In this embodiment, for example, signals RES1a to RES1d are set to low level, signals RES2a to RES2d are set to high level, and signals RES3a to RES3d are set to low level. Also, signals RES4a to RES4d are set to high level, signals RES5a to RES5d are set to low level, and signals RES6a to RES6d are set to high level. This provides different signals to adjacent signal lines 30 to 35, making it possible to inspect for short-circuit defects between signal lines within the same column.

[0079] In this embodiment, for example, signals RES1a to RES6a are set to low level and signals RES1b to RES6b are set to high level. Also, signals RES1c to RES6c are set to low level and signals RES1d to RES6d are set to high level. This allows different signals to be applied to signal lines 30, 36 to 38, making it possible to inspect for interference defects between columns over a wide range.

[0080] Furthermore, in this embodiment, by arranging control units 220 and 221 in the center of each of circuit groups 190 and 191, it is possible to suppress an increase in the number of control lines. Specifically, six control lines are provided in the circuit area where P-type transistor 210 is arranged to transmit signals RES1a to RES6a. Furthermore, six control lines are provided in the circuit area where P-type transistor 216 is arranged to transmit signals RES1b to RES6b. Six control lines are provided in the circuit area where P-type transistor 217 is arranged to transmit signals RES1c to RES6c. Furthermore, six control lines are provided in the circuit area where P-type transistor 218 is arranged to transmit signals RES1d to RES6d. By providing six control lines in each circuit area in this way, two types of inspections, interference failure and short-circuit failure, can be performed.

[0081] Example 7 This embodiment can be applied to any of Embodiments 1 to 6. FIG. 14(a) is a schematic diagram illustrating an apparatus 9191 including a semiconductor device 930 of this embodiment. The apparatus 9191 including the semiconductor device 930 will be described in detail. As described above, the semiconductor device 930 can include a package 920 that houses the semiconductor device 910, in addition to the semiconductor device 910 having the semiconductor layer 10. The package 920 can include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 can further include bonding members such as bonding wires and bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0082] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a memory device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0083] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0084] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0085] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0086] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in transportation equipment can be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0087] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0088] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0089] [Modified Example] The present disclosure is not limited to the above-described embodiment, and various modifications are possible.

[0090] For example, the pixel 10 is not limited to that shown in FIG. 3. The capacitance of the floating diffusion 420 may be switchable. The pixel 10 may also be configured such that multiple photodiodes share the floating diffusion 420. Multiple photodiodes 400, 401 may be formed under the same microlens to form a pixel capable of detecting a phase difference. When multiple signal lines 30 are provided in one pixel column, multiple selection transistors 440 may be provided. An additional transistor and storage capacitance may be provided in the electrical path between the photodiode 400 and the transfer transistor 410 to provide a global shutter function.

[0091] Furthermore, although the photoelectric conversion unit provided in the pixel 10 has been shown as a photodiode that accumulates electric charge, the present invention is not limited to this example. For example, an avalanche photodiode that performs avalanche multiplication may be used. When an avalanche photodiode is used, a single-photon counting type, known as a SPAD (Single Photon Avalanche Diode), may be used. In the case of a SPAD, the avalanche photodiode is provided on the first substrate 1. The second substrate 2 is provided with a quench element that controls the avalanche multiplication of the avalanche photodiode, a waveform shaping circuit (inverter) to which the output of the avalanche photodiode is applied, and a counter that counts the output pulses of the waveform shaping circuit. The count result obtained by this counter is obtained as a digital signal corresponding to the amount of light incident on the avalanche photodiode. In such a case, the multiple signal processing circuits include the waveform shaping circuit and the counter. The junction of the first substrate 1, to which the avalanche photodiode is connected, and the junction (input section) of the second substrate 2, to which the waveform shaping circuit is connected, are joined together to form an electrical connection. A transistor 20 that supplies the predetermined voltage described in this embodiment is connected between the waveform shaping circuit and the input section. This allows inspection of the second substrate 2, as in the above-described embodiment. Inspection for interference defects and short-circuit defects can also be performed in a similar manner.

[0092] Furthermore, the comparator 60 may be configured to further include a capacitor and a switch for setting the operating point of the comparator, ie, for performing a so-called auto-zero operation.

[0093] Furthermore, examples in which part of the configuration of any one of the embodiments is added to another embodiment, or examples in which part of the configuration of another embodiment is replaced with another embodiment, are also included in the embodiments of the present disclosure.

[0094] The above examples are merely examples of specific embodiments for carrying out the present disclosure, and should not be construed as limiting the technical scope of the present disclosure. In other words, the present disclosure can be carried out in various forms without departing from its technical idea or main features.

[0095] The above-described embodiments can be modified as appropriate without departing from the spirit and scope of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, it can be said that the specification discloses that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration. [Explanation of symbols]

[0096] 1. First substrate (pixel substrate) 2 Second board (circuit board) 3 Pixel Array 10 pixels 20~24 Transistor (N-type) 110~114 Junction (input section) P1~P4 signal processing circuit

Claims

1. A circuit board for laminating to another substrate, A plurality of signal lines; a plurality of input units connected to the plurality of signal lines and receiving signals from outside the circuit board; a plurality of signal processing circuits connected to the plurality of input units via the plurality of signal lines; a plurality of transistors that supply a predetermined voltage to the plurality of signal lines when no external signal is input to the plurality of input sections; Equipped with a plurality of current sources connected to the plurality of signal lines; a plurality of second transistors are provided in each of the plurality of signal lines, which switch between conduction and non-conduction of an electrical path between a corresponding input unit among the plurality of input units and a corresponding signal processing circuit among the plurality of signal processing circuits; a corresponding transistor among the plurality of transistors and a corresponding current source among the plurality of current sources are connected to one node of each of the plurality of second transistors; The other node of each of the plurality of second transistors is connected to a corresponding one of the plurality of signal processing circuits. A circuit board comprising:

2. Some of the plurality of transistors are connected to a first control line; 2. The circuit board according to claim 1, wherein another part of the plurality of transistors is connected to a second control line that is different from the first control line.

3. 3. The circuit board according to claim 1, wherein each of the plurality of signal processing circuits includes an AD converter that converts a predetermined voltage supplied by the plurality of transistors into a digital signal.

4. 4. The circuit board according to claim 3, wherein the digital signals generated by each of the plurality of signal processing circuits are output to the outside of the circuit board.

5. 4. The circuit board according to claim 3, further comprising a circuit for comparing the digital signal with an expected value.

6. 6. The circuit board according to claim 5, wherein the circuit outputs a signal indicating that a difference between the digital signal and the expected value is greater than a predetermined amount to an outside of the circuit board.

7. The circuit board according to any one of claims 1 to 6, characterized in that a power supply voltage is supplied to one main node of the plurality of transistors, and the plurality of transistors are switches that switch between supplying and not supplying the predetermined voltage based on the power supply voltage to the plurality of signal lines.

8. The circuit board according to claim 1, wherein the plurality of transistors perform source follower operation together with the plurality of current sources.

9. a plurality of third transistors connected to the plurality of signal lines, each of which switches between supplying and not supplying a second voltage different from the predetermined voltage; the plurality of transistors are transistors of a first conductivity type, 9. The circuit board according to claim 1, wherein the plurality of third transistors are transistors of a second conductivity type different from the first conductivity type.

10. each of the plurality of pixels includes a photoelectric conversion unit and is arranged across a plurality of rows and a plurality of columns, and is configured such that signals output from a plurality of pixels arranged on the separate circuit board are input to the plurality of input units; 10. The circuit board according to claim 1, wherein at least two of the plurality of input sections are provided corresponding to pixels in one of the plurality of columns.

11. The circuit board according to any one of claims 1 to 9, characterized in that the plurality of signal processing circuits include a waveform shaping circuit and a counter that process signals output by avalanche photodiodes provided on the other substrate.

12. 12. The circuit board according to claim 1, wherein the circuit board is manufactured by a manufacturing apparatus different from the manufacturing apparatus for the other substrate.

13. 13. The circuit board according to claim 12, wherein the circuit board is manufactured by a manufacturing device having a finer process rule than the process rule of the manufacturing device for the other substrate.

14. The circuit board according to any one of claims 1 to 13; A semiconductor device in which the other substrate is stacked.

15. An apparatus comprising the semiconductor device according to claim 14, an optical device corresponding to the semiconductor device; a control device for controlling the semiconductor device; a processing device that processes a signal output from the semiconductor device; a display device that displays information obtained by the semiconductor device; a storage device that stores information obtained by the semiconductor device; and and a mechanical device that operates based on information obtained by the semiconductor device.

16. 1. A method of driving a circuit board for lamination to another board, comprising: The circuit board includes: A plurality of signal lines; a plurality of input units connected to the plurality of signal lines and receiving signals from outside the circuit board; a plurality of signal processing circuits connected to the plurality of input units via the plurality of signal lines; a plurality of transistors; a plurality of current sources connected to the plurality of signal lines; a plurality of second transistors are provided in each of the plurality of signal lines, which switch between conduction and non-conduction of an electrical path between a corresponding input unit among the plurality of input units and a corresponding signal processing circuit among the plurality of signal processing circuits; a corresponding transistor among the plurality of transistors and a corresponding current source among the plurality of current sources are connected to one node of each of the plurality of second transistors; a corresponding signal processing circuit among the plurality of signal processing circuits is connected to the other node of each of the plurality of second transistors; A method for driving a circuit board, wherein the plurality of transistors supply a predetermined voltage to the plurality of signal lines when no external signal is input to the plurality of input sections.

17. 17. The method for driving a circuit board according to claim 16, wherein the circuit board is evaluated based on signals obtained by processing the predetermined voltage by the plurality of signal processing circuits.

18. A method for manufacturing a semiconductor device in which a circuit board and a substrate other than the circuit board are stacked on the circuit board, The circuit board includes: A plurality of signal lines; a plurality of input units connected to the plurality of signal lines and receiving signals from outside the circuit board; a plurality of signal processing circuits connected to the plurality of input units via the plurality of signal lines; a plurality of transistors; a plurality of current sources connected to the plurality of signal lines; a plurality of second transistors are provided in each of the plurality of signal lines, which switch between conduction and non-conduction of an electrical path between a corresponding input unit among the plurality of input units and a corresponding signal processing circuit among the plurality of signal processing circuits; a corresponding transistor among the plurality of transistors and a corresponding current source among the plurality of current sources are connected to one node of each of the plurality of second transistors; a corresponding signal processing circuit among the plurality of signal processing circuits is connected to the other node of each of the plurality of second transistors; a first step of supplying a predetermined voltage to the plurality of signal lines by the plurality of transistors in a state where no signal is input from the outside to the plurality of input ports; a second step of processing the predetermined voltage by the plurality of signal processing circuits; a third step of laminating the circuit board and the other substrate after the second step; 1. A method for manufacturing a semiconductor device, comprising:

Images