Optical transmitter, communication device, and bias control method for optical modulator

Abstract

To provide an optical transmitter that has an influence of phase variation due to disturbance noise suppressed to maintain quality of a main signal.SOLUTION: An optical transmitter has an optical modulator, a monitor circuit which monitors output light of the optical modulator, and a processor which uses a monitor result of the monitor circuit to control a bias voltage of the optical modulator, and the processor superposes a first dither signal of first frequency and a second dither signal of second frequency different from the first frequency on the bias voltage, calculates a first control error based upon a variation component of the first frequency and a second control error based upon a variation component of the second frequency from the monitor result, and uses the first control error and the second control error to control the bias voltage.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to an optical transmitter, a communication device, and a bias control method for an optical modulator. [Background technology]

[0002] Coherent optical transceivers that perform quadrature phase modulation using Mach-Zehnder optical modulators (MZMs) are used in optical communications. In MZMs that perform quadrature phase modulation, two MZMs called child MZMs are nested to form one MZM called a parent MZM. As a prerequisite for applying phase modulation, it is necessary that the two child MZMs and the parent MZM are each maintained at the appropriate phase. Each MZM is controlled to the appropriate phase by an externally applied bias voltage.

[0003] It is known that optical modulators experience operating point drift due to changes in the operating environment, such as temperature and wavelength, as well as changes over time. When the operating point drifts, the phase of each MZM deviates from its ideal value, degrading the performance of the main signal. For this reason, feedback control is performed to compensate for the drift in parallel with signal modulation during operation (see, for example, Patent Document 1). A configuration has been proposed in which noise contained in an optically modulated pilot signal is extracted and removed from the synchronous detection signal, thereby appropriately controlling the operating point of the optical modulator (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-211936 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-310288 Summary of the Invention [Problem to be solved by the invention]

[0005] External noise can also disrupt the phase of an optical modulator. In communication devices that include plug-in units equipped with coherent optical transceivers, switching noise from the power supply and noise from the pulse width modulation (PWM) circuit used to control the cooling fan speed can disrupt the phase of the optical modulator. Compared to operating point drift, the amount of phase variation caused by external noise is minute, so its impact on the quality of the main signal has been negligible. However, as the modulation level increases to expand communication capacity, the symbol interval becomes narrower, and the impact of minute phase variations caused by external noise on the main signal becomes more apparent. For example, in modulation using 16QAM (Quadrature Amplitude Modulation) technology, the impact of external noise on the quality of the main signal is sufficiently small. However, when the level increases to 64QAM, the impact of external noise on the main signal becomes significant.

[0006] An object of one aspect of the present invention is to provide an optical transmitter in which the influence of phase fluctuations due to disturbance noise is reduced and the quality of the main signal is maintained. [Means for solving the problem]

[0007] In one embodiment, an optical transmitter includes an optical modulator, a monitor circuit that monitors output light from the optical modulator, and a microprocessor that controls a bias voltage of the optical modulator using a monitoring result of the monitor circuit; The microprocessor superimposes a first dither signal of a first frequency and a second dither signal of a second frequency different from the first frequency on the bias voltage in a time-division manner, calculates a first control error based on a fluctuation component of the first frequency and a second control error based on a fluctuation component of the second frequency from the monitoring result, and determines a control value for controlling the bias voltage using the first control error and the second control error. [Effects of the Invention]

[0008] In the optical transmitter, the influence of phase fluctuations due to disturbance noise is suppressed, and the quality of the main signal is maintained. [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 1 is a diagram of a general bias control. [Figure 1B] FIG. 1B is a diagram illustrating the influence of disturbance noise on the configuration of FIG. 1A. [Figure 2] FIG. 1 is a schematic diagram of an optical transmitter according to a first embodiment. [Figure 3] 3 is a diagram illustrating an example of calculation processing for bias control in the optical transmitter of FIG. 2. [Figure 4] 10 is a diagram illustrating another example of the calculation process for bias control in the optical transmitter of FIG. 2. [Figure 5] FIG. 10 is a schematic diagram of an optical transmitter according to a second embodiment. [Figure 6] FIG. 6 is a diagram illustrating an example of calculation processing for bias control in the optical transmitter of FIG. 5. [Figure 7] FIG. 10 is a diagram illustrating an example of a control value storage table. [Figure 8] 4 is a basic flowchart of bias control according to the embodiment. [Figure 9] 10 is a flowchart of bias control for each arm. [Figure 10] 10 is a flowchart of a specific process of the bias control in FIG. 9. [Figure 11] FIG. 10 is a diagram illustrating an outline and effect of each calculation process. [Figure 12] FIG. 10 is a diagram for confirming the effect, showing a monitor signal and a phase fluctuation amount when there is no disturbance. [Figure 13] FIG. 10 is a diagram for confirming the effect, showing a monitor signal and a phase fluctuation amount when disturbance noise occurs in conventional bias control. [Figure 14] 10A and 10B are diagrams for confirming the effect, showing a monitor signal and a phase fluctuation amount when disturbance noise occurs in bias control according to the embodiment. [Figure 15] 1 is a schematic diagram of a communication device using an optical transmitter according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Before describing the configuration and bias control of the optical transmitter according to the embodiment in detail, a technical problem discovered by the inventors, namely, the manifestation of the effects of external noise, will be explained with reference to FIGS. 1A and 1B. FIG. 1A illustrates a typical bias control, and FIG. 1B illustrates the effects of external noise in the configuration of FIG. 1A. The optical modulator modulates continuous light incident from a laser diode (LD) with a data signal generated by a digital signal processor (DSP) and outputs a modulated optical signal. Automatic bias control (ABC) is performed to control each MZM constituting the optical modulator to an appropriate phase.

[0011] A portion of the modulated optical signal output from the optical modulator is branched off and monitored by a photodetector (PD). The ABC circuit calculates a bias control value based on the monitoring result, and the monitoring result is fed back to the optical modulator. The bias control value is converted to a voltage value by a digital-to-analog converter (DAC) and applied to the optical modulator as a direct current (DC) bias. A dither signal for bias control is superimposed on this DC bias. A single frequency is generally used as the dither signal. The DC bias is controlled so that the frequency component of the monitor light that is the same as the dither signal is minimized.

[0012] In communications equipment equipped with optical transceivers, electrical amplitude changes occurring in the electrical or electronic components around the optical transceiver, such as the power supply and PWM circuit, are mixed into the monitor PD as external noise (electromagnetic waves). The occurrence and level of external noise is irregular, and it is not known when and at what level noise will occur.

[0013] The effect of noise is greatest when the frequency of the external noise matches the frequency of the dither signal used for bias control. This is because a phase shift can be detected even when there is no bias shift, or a slight bias shift can be detected as the maximum phase shift. When the multilevel level is low, the effect of external noise on the main signal is small enough to be ignored, but as the multilevel level increases and the symbol interval on the complex plane becomes smaller, erroneous detection of the phase shift due to external noise cannot be ignored.

[0014] The PD output is a minute photocurrent on the order of 0.01 mA, and has low resistance to noise. This minute photocurrent is converted to a voltage by the subsequent transimpedance amplifier (TIA), which is given a large gain of more than 10,000 times. After the bandpass filter (BPF) extracts components containing the dither frequency from the voltage signal, the amplifier (AMP) gives it a further gain of more than 10 times. If external noise is introduced into the PD output, the noise is greatly amplified along with the detected dither frequency component, causing the bias control by the ABC circuit to become unstable.

[0015] Figure 1B shows the effect of external noise on the quality of the main signal. When external noise is introduced into the PD output due to power supply switching or PWM control of the cooling fan, the PD output fluctuates. Minute current changes in the PD output due to external noise are greatly amplified by a high-gain electric amplifier, increasing the amount of phase fluctuation estimated by the ABC circuit. In high-level modulation with a short symbol interval, minute phase fluctuations due to external noise have a significant impact on the quality of the main signal. In a Mach-Zehnder IQ modulator that performs quadrature phase modulation, the bias voltages of the I arm, Q arm, and parent modulator must be controlled to optimal points, but the effects of external noise can appear at any bias voltage.

[0016] In order to suppress the influence of external noise that becomes apparent as the modulation multilevel level increases, in this embodiment, dither signals of multiple frequencies are superimposed on one bias voltage in a time-division manner during bias control of an optical modulator. A bias control value (control error) is calculated from the monitoring results for each of the multiple frequencies, and the bias control values (control errors) obtained at the multiple frequencies are subjected to arithmetic processing to determine a final bias control value. The arithmetic processing is a process for reducing the influence of noise, and involves calculating the moving average, root-sum average, variance, etc. of the bias control values obtained at the multiple frequencies. By determining a final bias control value that is less influenced by noise from the multiple bias control values obtained at different frequencies, the influence of noise on the bias control of the optical modulator is suppressed.

[0017] First Embodiment 2 is a schematic diagram of an optical transmitter 10A according to the first embodiment. The optical transmitter 10A includes an optical modulator 13, a monitor circuit 105 that monitors the output light of the optical modulator 13, and a microprocessor 15A that controls the bias voltage of the optical modulator 13 using the monitoring results of the monitor circuit 105. The optical transmitter 10A also includes a light source 11 that supplies light to the optical modulator 13, and a DSP 12 that inputs a data signal to the optical modulator 13. In the following description, the terms "bias" and "bias voltage" refer to DC bias voltage unless otherwise specified.

[0018] The monitor circuit 105 includes a PD 16 that detects a portion of the output light from the optical modulator 13, a TIA 17 that converts the photocurrent output from the PD 16 into a voltage signal and amplifies it, and BPFs 18-1 and 18-2 that extract fluctuation components of a predetermined frequency included in the voltage signal output from the TIA 17. The monitor circuit 105 may also include amplifiers 19-1 and 19-2 that amplify the outputs of the BPF 18-1 and PBF 18-2, respectively.

[0019] The optical modulator 13 is, for example, an MZ modulator that performs quadrature phase modulation. An MZM 131 that handles in-phase signals and an MZM 132 that handles quadrature phase signals are nested together to form a parent MZM 133. MZM 131 is called the "I-arm MZM 131," and MZM 132 is called the "Q-arm MZM 132."

[0020] The microprocessor 15A applies a bias voltage to each MZM of the optical modulator 13 via the DAC 14. The microprocessor 15A controls the bias voltages applied to the I-arm MZM 131, the Q-arm MZM 132, and the parent MZM 133 to maintain each MZM at an appropriate phase. The appropriate phase is one in which, with no signal input, the phase difference between the two waveguides of the I-arm MZM 131 is 180°, the phase difference between the two waveguides of the Q-arm MZM 132 is 180°, and the phase difference between the I-arm and Q-arm is 90°. By maintaining this phase state, quadrature phase modulation representing 2 bits and 4 values is performed based on the input data signal.

[0021] A high-speed data signal is input from the DSP 12 via an RF signal terminal to the I-arm MZM 131 and Q-arm MZM 132, and optical modulation is performed in each arm. A phase difference of 90° is given between the light modulated by the I-arm and the light modulated by the Q-arm, and they are combined, and a modulated optical signal is output from the optical modulator 13.

[0022] The phase state of the optical modulator 13 is monitored even during operation, and individual bias voltages are applied to the I-arm MZM 131, Q-arm MZM 132, and parent MZM 133 via the DC bias terminals from the DAC 14. The bias voltage applied to the I-arm MZM 131 is called "I bias," the bias voltage applied to the Q-arm MZM 132 is called "Q bias," and the bias voltage applied to the parent MZM 133 is called "Φ bias."

[0023] In this embodiment, the same dither signal is used to control the I bias, Q bias, and Φ bias. The dither signal is a low-frequency signal that fluctuates with a small amplitude. "Small amplitude" refers to an amplitude of, for example, several mV to several tens of mV. "Low frequency" refers to a frequency of approximately several Hz to 1 kHz, which is sufficiently low compared to the drive amplitude of the optical modulator 13.

[0024] A dither signal with multiple different frequencies is used, and the frequency of the dither signal superimposed on one bias voltage is switched. For each of the I bias, Q bias, and Φ bias, a section where a dither signal with a first frequency f1 is superimposed and a section where a dither signal with a second frequency f2 is superimposed are provided. For example, the first frequency f1 is 300 Hz and the second frequency f2 is 1 kHz. The combination of dither signal frequencies is not limited to this example; it can be appropriately selected, such as 200 Hz and 800 Hz, or 400 Hz and 1 kHz, so long as at least one frequency does not overlap with the frequency of external noise.

[0025] The dither signal of the first frequency f1 and the dither signal of the second frequency f2 vary, for example, around the bottom voltage of the modulation curve (voltage vs. power characteristic). When the bias voltage of each MZM is at the optimum point (the bottom of the modulation curve in this example), the output of the optical modulator 13 contains a component that varies at twice the frequency of f1 or f2. If the bias voltage of each MZM deviates from the bottom of the modulation curve, a dither component that varies at the same frequency as f1 or f2 appears in the output of the optical modulator 13. This deviation in bias voltage is detected as a control error (deviation).

[0026] Since two dither signals with different frequencies are superimposed on one bias voltage in a time-division manner, even if external noise occurs during bias control, the effects of the external noise are avoided at least at one of the frequencies.

[0027] Since dither signals of different frequencies are superimposed on a single bias voltage, a configuration is required to extract power fluctuation components at each dither frequency from the output of PD 16. In monitor circuit 105, BPF 18-1 (labeled "BPF1" in the figure) that extracts the f1 component and BPF 18-2 (labeled "BPF2" in the figure) that extracts the f2 component are provided after TIA 17, but this example is not limiting. Using a frequency-variable BPF, switching of the dither frequency by microprocessor 15A and switching of the passband of the frequency-variable BPF may be synchronized.

[0028] The frequency component extracted by the BPF 18-1 is amplified by the amplifier 19-1 and input to the microprocessor 15 A. The frequency component extracted by the BPF 18-2 is amplified by the amplifier 19-2 and input to the microprocessor 15 A.

[0029] The microprocessor 15A has a dither generation circuit 151, ADCs 152a and 152b, control error calculation circuits 153a and 153b, a memory 154, an arithmetic unit 155A, a selector 158A, a bias value calculation circuit 159, a dither superimposition circuit 161, and a user interface (I / F) 162.

[0030] The dither generation circuit 151 generates dither signals of at least two different frequencies f1 and f2. The dither superimposition circuit 161 switches between superimposing the dither signals of frequencies f1 and f2 on the DC biases applied to the I-arm MZM 131, Q-arm MZM 132, and parent MZM 133 of the optical modulator 13.

[0031] The ADC 152a digitally samples the fluctuation component of frequency f1 contained in the output optical signal of the optical modulator 13 and inputs the digital value of the f1 fluctuation component to the control error calculation circuit 153a. The ADC 152b digitally samples the fluctuation component of frequency f2 contained in the output optical signal of the optical modulator 13 and inputs the digital value of the f2 fluctuation component to the control error calculation circuit 153b.

[0032] The control error calculation circuit 153a synchronously detects the f1 component using the f1 dither signal generated by the dither generation circuit 151. The magnitude (amplitude) of the synchronously detected f1 component represents the phase shift of the bias control, i.e., the control error (deviation). The control error includes the magnitude and direction (sign) of the phase shift of the bias voltage. The detected control error of the f1 component is stored in the f1 processing memory 154a of the memory 154 for each cycle of bias control.

[0033] The control error calculation circuit 153b synchronously detects the f2 component using the f2 dither signal generated by the dither generation circuit 151. The magnitude (amplitude) of the synchronously detected f2 component represents the phase shift of the bias control, i.e., the control error (deviation). The control error includes the magnitude and direction (sign) of the phase shift of the bias voltage. The detected f2 component control error is stored in the f2 processing memory 154b of the memory 154 for each bias control cycle.

[0034] The calculator 155A reads out the stored control difference values from the f1 processing memory 154a and the f2 processing memory 154b for each calculation window size, and performs calculation for noise reduction. The window size can be set by the operator via the user I / F 162, for example.

[0035] In the first embodiment, the calculator 155A includes a simple average calculator 156 or a square-sum average calculator 157. The simple average calculator 156 calculates a moving average of the f1 component control error and the f2 component control error while shifting the window. When the square-sum average calculator 157 is used, the calculation result of the simple average is used, so both the simple average calculator 156 and the square-sum average calculator 157 are used. The calculation results of the simple average and the square-sum average are input to a selector 158A.

[0036] The selector 158A outputs the simple average or the root-sum average for each control cycle to the bias value calculation circuit 159. Which value to select may be determined in advance via the user I / F 162. For example, the simple average may be used in modulation schemes with a relatively low multilevel value, such as QPSK or 16QAM, where high-precision noise removal is not required, and the root-sum average may be used in modulation schemes with a relatively high multilevel value, such as 64QAM.

[0037] When the simple average is used in a fixed manner, the calculator 155A may sequentially output the simple average values to the selector 158A without operating the square sum average calculator 157. When the square sum average is used in a fixed manner, the square sum average values may be sequentially output to the selector 158A. The selector 158A is not essential, and the result of the simple average or square sum average determined in advance by an operator may be directly input from the calculator 155A to the bias value calculation circuit 159.

[0038] The bias value calculation circuit 159 calculates voltage correction values for each of the Φ bias, I bias, and Q bias as control values from the output value (control error representing the bias phase shift) of the calculator 155A or the selector 158A. The dither superimposition circuit 161 superimposes a dither signal of frequency f1 and a dither signal of frequency f2 on each corrected bias voltage in a time-division manner. The bias voltage including the dither signal is converted into an analog voltage by the DAC 14 and applied to the optical modulator 13 from the DC bias terminal.

[0039] <Simple averaging> 3 shows the operation of the simple average calculator 156. For each cycle of bias control, a dither signal with a frequency f1 and a dither signal with a frequency f2 are superimposed on each of Φ bias, I bias, and Q bias. For example, f1 is 300 Hz and f2 is 1 kHz. This simple average process calculates the average value of the control error for each predetermined window size while shifting the interval (cycle), which corresponds to calculating a moving average.

[0040] The window size is the total number of data used in one calculation. In the example of Figure 3, the window size is set to four data obtained in two cycles, but is not limited to this example. The control value (moving average) is calculated using the control error detected in each cycle for each bias of Φ, I, and Q using the following formula:

[0041]

number

[0042] where A N-1 is the control error of the f1 component in the previous cycle, B N-1 is the control error of the f2 component in the previous cycle, A N is the control error of the f1 component in this cycle, B N is the control error of the f2 component in this cycle. The average of a total of four data points, two control errors of the f1 component and two control errors of the f2 component, is used as the control value.

[0043] For each of the Φ bias, I bias, and Q bias, a control value is calculated by the simple average calculator 156 each time two cycles of control errors are stored in the memory 154. At the next timing, shifted by one cycle, a simple average is calculated using the control errors of the f1 component and the f2 component of the second cycle, and the control errors of the f1 component and the f2 component of the third cycle. If there is room in the buffer of the memory 154, a window size of three cycles or more and a total number of samples of six or more may be set.

[0044] <Mean sum of squares> FIG. 4 shows the operation of the square sum average calculator 157. For each cycle of bias control, a dither signal with a frequency f1 and a dither signal with a frequency f2 are superimposed on each of Φ bias, I bias, and Q bias. For example, f1 is 300 Hz and f2 is 1 kHz. The square sum average is calculated using a simple average value according to the following formula:

[0045]

number

[0046] By using the square sum averaging, the same level of noise reduction effect can be obtained with a smaller buffer size than by expanding the window size for simple averaging. By using at least two dither frequencies, the effects of external noise can be reduced even if external noise close to one of the frequencies is mixed in.

[0047] When starting up the optical transmitter 10A, the initial bias voltage may be set by repeatedly detecting the dither component using a test signal and calculating the moving average or the root-sum-of-squares average to obtain the simple average or root-sum-of-squares average value for setting. By using the simple average or root-sum-of-squares average, even if either the f1 or f2 dither component is significantly affected by noise, the influence of this noise can be reduced.

[0048] Second Embodiment 5 is a schematic diagram of an optical transmitter 10B according to the second embodiment. In the second embodiment, variance is calculated as a calculation process for noise reduction.

[0049] The optical transmitter 10B includes an optical modulator 13, a monitor circuit 105 that monitors the output light of the optical modulator 13, and a microprocessor 15B that controls the bias voltage of the optical modulator 13 using the monitoring results of the monitor circuit 105. The optical transmitter 10B also includes a light source 11 and a DSP 12. The second embodiment also uses dither signals with two different frequencies, f1 and f2. The monitor circuit 105 includes, after the TIA 17, a BPF 18-1 that extracts a component whose power fluctuates at the same frequency as f1 (the f1 component), and a BPF 18-2 that extracts a component whose power fluctuates at the same frequency as f2 (the f2 component). The frequency component extracted by the BPF 18-1 is amplified by an amplifier 19-1 and input to the microprocessor 15B. The frequency component extracted by the BPF 18-2 is amplified by an amplifier 19-2 and input to the microprocessor 15B.

[0050] The microprocessor 15B includes a dither generation circuit 151, ADCs 152a and 152b, control error calculation circuits 153a and 153b, a memory 164, an arithmetic unit 155B, a selector 158B, a bias value calculation circuit 159, and a dither superimposition circuit 161.

[0051] The dither generation circuit 151 generates dither signals of at least two different frequencies f1 and f2. The dither superimposition circuit 161 time-divisionally superimposes the dither signals of frequencies f1 and f2 on the DC biases applied to the I-arm MZM 131, Q-arm MZM 132, and parent MZM 133 of the optical modulator 13.

[0052] The ADC 152a digitally samples the fluctuation component of frequency f1 contained in the output optical signal of the optical modulator 13 and inputs the digital value of the f1 fluctuation component to the control error calculation circuit 153a. The ADC 152b digitally samples the fluctuation component of frequency f2 contained in the output optical signal of the optical modulator 13 and inputs the digital value of the f2 fluctuation component to the control error calculation circuit 153b.

[0053] The control error calculation circuit 153a synchronously detects the f1 component using the f1 dither signal generated by the dither generation circuit 151. The magnitude of the synchronously detected f1 component represents the phase shift of the bias control, i.e., the control error (deviation). The control error includes the magnitude and direction (sign) of the phase shift. The detected control error of the f1 component is stored in the f1 processing memory 164a of the memory 164 for each cycle of bias control.

[0054] The control error calculation circuit 153b synchronously detects the f2 component using the f2 dither signal generated by the dither generation circuit 151. The magnitude of the synchronously detected f2 component represents the phase shift of the bias control, i.e., the control error (deviation). The control error includes the magnitude and direction (sign) of the phase shift. The detected f2 component control error is stored in the f2 processing memory 164b of the memory 164 for each cycle of bias control.

[0055] The memories 164a and 164b store control errors for a predetermined number of cycles (N cycles, where N is a natural number) for each of Φ bias, I bias, and Q bias.

[0056] The calculator 155B reads out the stored control error values from the f1 processing memory 154a and the f2 processing memory 154b for each calculation window and performs calculations for noise reduction. The window size may be set in advance or may be set by an operator via the user I / F, as in Fig. 2.

[0057] The calculator 155B includes a variance calculator 171 that calculates the variance of the control error of the f1 component, a variance calculator 172 that calculates the variance of the control error of the f2 component, and a comparator 173 that compares the magnitude of the variance of the f1 component and the f2 component. The comparator 173 selects the smaller of the variance of the f1 component and the variance of the f2 component, and notifies the selector 158B of the frequency that results in the smaller variance.

[0058] Variance (σ 2 ) is calculated for each dither signal frequency and each type of bias voltage based on the following formula:

[0059]

number

[0060] The selector 158B receives the control error of interest from the f1 processing memory 164a and the f2 processing memory 164b for each cycle of bias control. Based on the comparison result of the comparator 173, the selector 158B selects the control error of the frequency component with the smaller variance, and outputs the selected control error to the bias value calculation circuit 159.

[0061] The bias value calculation circuit 159 calculates a voltage correction value for each of the Φ bias, I bias, and Q bias from the output value (control error representing the phase shift) of the selector 158B. A dither signal with a frequency f1 and a dither signal with a frequency f2 are superimposed on each corrected bias voltage in a time-division manner by the dither superimposition circuit 161. The bias voltage including the dither signal is converted into an analog voltage by the DAC 14 and applied to the optical modulator 13 from the DC bias terminal.

[0062] <Distributed processing> Figure 6 shows the distributed processing. In each control cycle, a dither signal with frequency f1 and a dither signal with frequency f2 are superimposed on Φ bias, I bias, and Q bias, respectively. For each bias, the control error (deviation) of the f1 component and the control error (deviation) of the f2 component are calculated by control error calculation circuits 153a and 153b. The calculated control errors are stored sequentially in a predetermined area of memory 164.

[0063] In the first cycle, for the Φ bias, the control error A_Φ_1 (181Φ) of the f1 component and the control error B_Φ_1 (182Φ) of the f2 component are obtained. Similarly, for the I bias, the control error A_I_1 (181I) of the f1 component and the control error B_I_1 (182I) of the f2 component are obtained, and for the Q bias, the control error A_Q_1 (181Q) of the f1 component and the control error B_Q_1 (182Q) of the f2 component are obtained.

[0064] 7 shows an example of a control value storage table in memory 164. For each type of bias (MZM arm), the control error when the dither frequency is f1 is sequentially recorded at the corresponding address in f1 processing memory 164a. The control error when the dither frequency is f2 is sequentially recorded at the corresponding address in f2 processing memory 164b.

[0065] Variance calculator 171 calculates the variance of the f1 control error from the n control errors related to the f1 component for each bias. Variance calculator 172 calculates the variance of the f2 control error from the n control errors related to the f2 component for each bias. The calculated variance values may be written back to the control value storage table.

[0066] The variance values of the two frequency components are compared, and the control error detected in the frequency component with the smaller variance is used for bias control. The control error detected in the frequency component with the larger variance is considered to be heavily influenced by external noise and is not used for bias control. For example, if the variance of the f1 component for the Φ bias is 0.23 and the variance of the f2 component is 0.01, the bias is controlled using the control error detected in the f2 component, which is less influenced by noise. The same applies to the I bias and Q bias.

[0067] The influence of noise is reduced by using the control error detected for each bias at the frequency component with the smaller variance. The configuration of the second embodiment performs bias control by distinguishing whether or not there is an influence of noise, or whether the influence is large or small, so that the noise suppression effect is high.

[0068] <Bias control processing> 8 is an overall flowchart of bias control in this embodiment. A first frequency (f1) is set for the dither signal superimposed on the DC bias of each arm of optical modulator 13 (S1), and bias control is performed using the f1 dither signal (S2). This bias control detects fluctuation components of the same frequency as the current frequency f1 of the dither signal from the output optical power of the optical modulator, and calculates a control error from the fluctuation components. The control error calculated for f1 is stored in a predetermined area of memory 154 or 164.

[0069] Next, a second frequency (f2) is set for the dither signal superimposed on the DC bias of each arm of the optical modulator 13 (S3), and bias control is performed using the f2 dither signal (S4). This bias control detects fluctuation components of the same frequency as the current frequency f2 of the dither signal from the output optical power of the optical modulator, and calculates a control error from the fluctuation components. The control error calculated for f2 is stored in a predetermined area of memory 154 or 164. The stored control errors for f1 and f2 are subjected to noise reduction processing to determine a correction value for the bias voltage of each arm. Steps S1 to S4 are repeated during operation of the optical transmitter 10A or 10B (hereinafter sometimes collectively referred to as "optical transmitter 10") (YES in S5).

[0070] 9 is a flowchart of the bias control process for each arm. The first bias of the optical modulator 13 is controlled (S11). In this example, the first bias is the Φ bias applied to the parent MZM. The Φ bias is a DC bias that maintains the phase difference between the light passing through the I arm and the light passing through the Q arm at 90° when there is no signal input.

[0071] The second bias of the optical modulator 13 is controlled (S12). In this example, the second bias is an I bias applied to the I arm. The I bias is a DC bias that maintains the phase difference of the light passing through the two waveguides of the I arm MZM at 180° when there is no signal input.

[0072] The third bias of the optical modulator 13 is controlled (S13). In this example, the third bias is a Q bias applied to the Q arm. The Q bias is a DC bias that maintains the phase difference of the light passing through the two waveguides of the Q arm MZM at 180° when there is no signal input.

[0073] When the Φ bias, I bias, and Q bias are controlled in a time-division manner, S11, S12, and S13 are performed in any order. When the Φ bias, I bias, and Q bias are controlled in parallel, the bias control microprocessors 15A and 15B are used in parallel to simultaneously control the Φ bias, I bias, and Q bias. While the optical transmitter 10 is operating (YES in S14), steps S11 to S13 are repeated.

[0074] Figure 10 is a specific flowchart of the bias control steps S11, S12, and S13 in Figure 9. First, a portion of the output optical signal from the optical modulator 13 is monitored by the PD 16 to extract a fluctuation component with the same frequency as the dither signal contained in the optical output power, and the control error of the bias voltage, i.e., the deviation, is calculated based on the amplitude of the fluctuation component (S21). Next, the sign is calculated (S22). The sign indicates the direction of control. If the control error is changing in a direction that reduces the control error, the control direction is correct and the sign is positive. If the control error is changing in a direction that increases the control error, the control direction is reversed and the sign is negative.

[0075] Next, the deviation (control error) obtained in S21 is used to perform calculation processing (S23). The calculation processing includes calculation of the moving average in FIG. 3, calculation of the square sum average in FIG. 4, and calculation of the variance (σ 2 ) or any other calculation process that can reduce noise. Finally, the current bias value is updated (S24) based on the code obtained in S22 and the control value obtained in the calculation process of S23. Whichever calculation process is used, a control value that reduces the influence of noise can be obtained, and deterioration of the quality of the main signal can be suppressed, especially in modulation methods with a high degree of multilevel modulation.

[0076] FIG. 11 shows an overview and effect of each calculation process used in the embodiment. The simple average is a moving average of a total of M control errors calculated for each of f1 and f2, as shown in FIG. 3. When two frequencies are used, M is an integer multiple of 2, and M / 2 control errors of the f1 component and M / 2 control errors of the f2 component are used. Even if noise occurs at a frequency close to one of the dither frequencies, the influence of the noise is reduced by taking the moving average. Furthermore, this is a simple calculation, which simplifies the calculation processing circuit.

[0077] As shown in Figure 4, the square sum average is calculated by using a total of M control errors calculated for each of f1 and f2, and then taking the simple average x of the f1 and f2 components. i When two frequencies are used, M is an integer that is an integer multiple of 2 and is equal to or greater than 4. Using M / 2 control errors of the f1 component and M / 2 control errors of the f2 component, the simple average x i The square root of the sum of squares is calculated from the average value x (bar) of the simple average. Even if noise occurs at a frequency close to one of the dither frequencies, the effect of the noise is reduced by calculating the average of the sum of squares. Compared to improving noise reduction by expanding the window size with simple averaging, the same level of noise reduction can be achieved with a smaller buffer.

[0078] The noise removal using variance is performed by using a total of M control errors calculated for each of f1 and f2 to calculate the variance (σ 2 ) is calculated. When two frequencies are used, M is an integer greater than or equal to 4, which is an integer multiple of 2. The variance of the f1 component is calculated using the control errors of M / 2 f1 components, and the variance of the f2 component is calculated using the control errors of M / 2 f2 components. The control value is determined using the control error of the dither frequency with the smallest variance. Even if one of the frequency components is affected by noise, the noise effect can be eliminated by not using this frequency component for bias control. The noise effect is highly effective because it is eliminated by determining whether or not there is a noise effect or whether the effect is large.

[0079] <Effectiveness check> 12 to 14 are diagrams for verifying the effects. Fig. 12 shows the monitor signal and the amount of phase fluctuation when there is no disturbance. Fig. 13 shows the monitor signal and the amount of phase fluctuation when disturbance noise occurs in conventional bias control. Fig. 14 shows the monitor signal and the amount of phase fluctuation when disturbance noise occurs in bias control of the embodiment.

[0080] In Figure 12(A), the horizontal axis represents time, the left vertical axis represents the PD current (mA), and the right vertical axis represents the amplifier output. When no external noise is present, a weak PD current is obtained as a monitor signal for the optical modulator. This PD current is amplified by the subsequent TIA and amplifier and then input to the ADC.

[0081] 12(B), the horizontal axis represents time, the left vertical axis represents the amount of phase fluctuation (degrees), and the right vertical axis represents the Q value (dB). Because there is no external noise, the amount of phase fluctuation is within a predetermined range, and the fluctuation of the Q value is also within a certain range.

[0082] In Figure 13(A), when external noise occurs under conventional bias control, i.e., bias control without noise suppression measures, a fluctuation component C1 appears in the PD current. External noise occurs irregularly depending on the environment in which the optical transmitter is placed. The fluctuation component C1 that appears in the PD current is converted into a large voltage fluctuation C2 by the TIA and amplifier.

[0083] As shown in Figure 13(B), when the bias control value is calculated based on the PD output, a large voltage fluctuation C2 is detected as a phase fluctuation C3. If bias control is performed while including the phase fluctuation C3, the bias control will not match the actual bias state, resulting in a significant decrease in the Q value. As a result, the operation of the optical modulator will become unstable.

[0084] In FIG. 14A, when external noise occurs during bias control in the embodiment, the PD current fluctuates, and a large voltage fluctuation C2 occurs in the signal input to the ADC of the microprocessor 15, as in FIG. 13A.

[0085] In Figure 14(B), when the bias control value is calculated based on the PD output, the effect of voltage fluctuation C2 is reduced by noise reduction calculations. Unlike Figure 13(B), as shown by circle C4, there is no significant change in the amount of phase fluctuation, and the Q value, which represents signal quality, is also maintained.

[0086] By using two or more frequencies for the dither signal superimposed on one bias, even when irregular disturbance noise occurs, the influence of disturbance noise can be avoided at least at one of the frequencies, thereby minimizing false detection. If the expected noise frequency is known in advance, the noise reduction effect can be further improved by selecting two or more frequencies of the dither signal that are not the noise frequency.

[0087] <Application to communication equipment> 15 is a schematic diagram of a communication device 100 using optical transmitters 10-1 and 10-2 according to an embodiment. The communication device 100 includes multiple plug-in units 111 and 112 and electric or electronic components related to the operation of the plug-in units 111 and 112. The electric or electronic components are, for example, a power supply 120, a blade control board 130, and a fan group 140 including multiple cooling fans. The plug-in units are components or subassemblies that are connected to the main body by being inserted into corresponding sockets.

[0088] The blade-type plug-in units 111 and 112 connected to the communication device 100 are controlled by a blade control board 130. The power supply 120 is controlled to be turned on and off when the plug-in units 111 and 112 are inserted, removed, replaced, or newly added. The fan group 140 may have a PWM circuit that controls the temperature of each cooling fan.

[0089] The plug-in unit 111 includes a coherent optical transceiver 20-1 having an optical transmitter 10-1, and a pluggable optical module group 110. The pluggable optical module group 110 includes a plurality of optical modules connected to optical fibers via optical connectors. The coherent optical transceiver 20-1 has a coherent optical receiver together with the optical transmitter 10-1, and detects the received modulated optical signal by utilizing interference with local oscillator light.

[0090] The optical transmitter 10-1 of the coherent optical transceiver 20-1 performs bias control to suppress the effects of external noise. Even if noise occurs due to switching of the power supply 120 around the plug-in unit 111 or the operation of the PWM circuit of the fan group 140, the effects of the noise are suppressed, and the quality of the optically modulated signal output from the optical transmitter 10-1 is maintained.

[0091] The plug-in unit 112 has a similar configuration to the plug-in unit 111, and includes a coherent optical transceiver 20-1 having an optical transmitter 10-2, and a pluggable optical module group 110. The optical transmitter 10-2 also performs bias control to suppress the influence of external noise, and transmits a modulated optical signal with good signal quality.

[0092] While the configuration and bias control of the optical transmitter 10 according to the embodiment have been described above based on a specific configuration example, the bias control technique of the present invention is not limited to the above configuration example. The monitor circuit 105 may have any configuration capable of extracting power fluctuation components that are the same as the frequency of the dither signal. The noise suppression calculation process may include the simple average, square-sum average, and variance described above, as well as appropriate smoothing and median filtering. Instead of controlling the Φ bias, I bias, and Q bias in a time-division manner, the microprocessor 15 may be divided into several functions to simultaneously control the Φ bias, I bias, and Q bias in parallel. The optical modulator is not limited to a quadrature phase modulator, but may also be a polarization-multiplexed quadrature phase modulator. In this case, the bias control described above is performed for each of the two orthogonal polarizations.

[0093] The following notes are added to the above explanation. (Appendix 1) an optical modulator; a monitor circuit for monitoring the output light of the optical modulator; a processor that controls a bias voltage of the optical modulator using the monitoring result of the monitor circuit; and the processor superimposes a first dither signal of a first frequency and a second dither signal of a second frequency different from the first frequency on the bias voltage in a time-division manner, calculates a first control error based on a fluctuation component of the first frequency and a second control error based on a fluctuation component of the second frequency from the monitoring result, and determines a control value for controlling the bias voltage using the first control error and the second control error. Optical transmitter. (Appendix 2) the optical modulator is a Mach-Zehnder optical modulator in which a first child modulator and a second child modulator are nested to form a parent modulator; the processor superimposes the first dither signal and the second dither signal on a first bias of the first child modulator, a second bias of the second child modulator, and a third bias of the parent modulator in a time-division manner, and controls the first bias, the second bias, and the third bias in a time-division manner; 10. The optical transmitter of claim 1. (Appendix 3) The monitor circuit includes a photodetector that detects a portion of the output light of the optical modulator; a first filter that extracts a component that fluctuates at the first frequency from the output of the photodetector; and a second filter that extracts components that fluctuate at the second frequency from the output of the photodetector. (Appendix 4) 4. The optical transmitter according to claim 1, wherein the processor has an arithmetic unit that performs arithmetic processing using the first control error and the second control error, and determines the control value based on the calculation result. (Appendix 5) the processor calculates a simple average or a root-sum average of the first control error and the second control error, and determines the control value based on the calculation result. 5. The optical transmitter of claim 1. (Appendix 6) 6. The optical transmitter according to claim 5, further comprising a selector that selects either the simple average or the square sum average according to a modulation multi-level degree. (Appendix 7) the processor calculates a variance value of the first control error and a variance value of the second control error, and determines the control value using the control error with the smaller variance value. 5. The optical transmitter of claim 1. (Appendix 8) 8. The optical transmitter of claim 7, further comprising a selector that selects either the first control error or the second control error based on a comparison result between the variance value of the first control error and the variance value of the second control error. (Appendix 9) an optical transceiver having an optical transmitter according to any one of Supplementary Notes 1 to 8; an electrical or electronic component used in the operation of the optical transceiver; A communication device having: (Appendix 10) a first dither signal having a first frequency and a second dither signal having a second frequency different from the first frequency are superimposed on a bias voltage of an optical modulator in a time-division manner; monitoring the output light of the optical modulator; calculating a first control error based on the fluctuation component of the first frequency and a second control error based on the fluctuation component of the second frequency from the monitoring results; determining a control value for controlling the bias voltage using the first control error and the second control error; A bias control method for an optical modulator. (Appendix 11) performing a calculation process using the first control error and the second control error; determining the control value based on the calculation result; A bias control method for an optical modulator according to claim 10. [Explanation of symbols]

[0094] 10A, 10B, 10-1, 10-2 Optical Transmitters 11 Light source 12 DSP 13 Optical Modulator 131 I-Arm MZM 132 Q Arm MZM 133 Parent MZM 14 DAC 15A, 15B Microprocessor (Processor) 151 Dither generation circuit 152a, 152b ADC 153a, 153b Control error calculation circuit 154 memory 155A, 155B computing unit 156 Simple Average Calculator 157 Sum of Squares Average Calculator 158A, 158B selector 159 Bias value calculation circuit 161 Dither superposition circuit 162 User Interface 171, 172 distributed calculator 173 Comparator 16PD 17 TIA 18-1 BPF (1st filter) 18-2 BPF (second filter) 19-1, 19-2 amplifier 20-1, 20-2 Coherent Optical Transceiver (Optical Transceiver) 100 Communication equipment 105 Monitor circuit 111, 112 Plug-in unit 120 Power supplies (electrical or electronic components) 130 Blade control board (electrical or electronic components) 140 Fan Group (Electric or Electronic Circuit)

Claims

1. an optical modulator; a monitor circuit for monitoring the output light of the optical modulator; a processor that controls a plurality of bias voltages of the optical modulator using the monitoring results of the monitor circuit; and the processor superimposes a first dither signal of a first frequency and a second dither signal of a second frequency different from the first frequency on each of a first bias voltage and a second bias voltage of the bias voltages in a time-division manner, calculates a first control error based on a fluctuation component of the first frequency and a second control error based on a fluctuation component of the second frequency from the monitoring result, and determines a control value for controlling each of the first bias voltage and the second bias voltage using the first control error and the second control error. Optical transmitter.

2. An optical modulator; a monitor circuit for monitoring the output light of the optical modulator; a processor that controls a bias voltage of the optical modulator using the monitoring result of the monitor circuit; and the processor superimposes a first dither signal of a first frequency and a second dither signal of a second frequency different from the first frequency on the bias voltage in a time-division manner, calculates a first control error based on a fluctuation component of the first frequency and a second control error based on a fluctuation component of the second frequency from the monitoring result, and determines a control value for controlling the bias voltage using the first control error and the second control error; the optical modulator is a Mach-Zehnder optical modulator in which a first child modulator and a second child modulator are nested to form a parent modulator; the processor superimposes the first dither signal and the second dither signal on a first bias of the first child modulator, a second bias of the second child modulator, and a third bias of the parent modulator in a time-division manner, and controls the first bias, the second bias, and the third bias in a time-division manner or in parallel; Optical transmitter.

3. An optical modulator; a monitor circuit for monitoring the output light of the optical modulator; a processor that controls a bias voltage of the optical modulator using the monitoring result of the monitor circuit; and the processor superimposes a first dither signal of a first frequency and a second dither signal of a second frequency different from the first frequency on the bias voltage in a time-division manner, calculates a first control error based on a fluctuation component of the first frequency and a second control error based on a fluctuation component of the second frequency from the monitoring result, calculates a simple average or a root-sum average of the first control error and the second control error, and determines a control value for controlling the bias voltage based on the calculation result; Optical transmitter.

4. An optical modulator; a monitor circuit for monitoring the output light of the optical modulator; a processor that controls a bias voltage of the optical modulator using the monitoring result of the monitor circuit; and the processor superimposes a first dither signal of a first frequency and a second dither signal of a second frequency different from the first frequency on the bias voltage in a time-division manner, calculates a first control error based on a fluctuation component of the first frequency and a second control error based on a fluctuation component of the second frequency from the monitoring result, calculates a variance value of the first control error and a variance value of the second control error, and determines a control value for controlling the bias voltage using the control error with the smaller variance value; Optical transmitter.

5. a selector that selects either the first control error or the second control error based on a comparison result between the variance value of the first control error and the variance value of the second control error; 5. The optical transmitter according to claim 4.

6. The monitor circuit includes a photodetector that detects a portion of the output light of the optical modulator; a first filter that extracts a component that fluctuates at the first frequency from the output of the photodetector; a second filter that extracts a component that fluctuates at the second frequency from the output of the photodetector; 6. The optical transmitter according to claim 1.

7. the processor has a calculator that performs calculations using the first control error and the second control error, and determines the control value based on the calculation results.

7. The optical transmitter according to claim 1.

8. an optical transceiver having the optical transmitter according to any one of claims 1 to 7; an electrical or electronic component used in the operation of the optical transceiver; A communication device having:

9. a first dither signal having a first frequency and a second dither signal having a second frequency different from the first frequency are superimposed on a first bias voltage and a second bias voltage of the bias voltages of the optical modulator in a time-division manner; monitoring the output light of the optical modulator; calculating a first control error based on the fluctuation component of the first frequency and a second control error based on the fluctuation component of the second frequency from the monitoring result; determining a control value for controlling each of the first bias voltage and the second bias voltage using the first control error and the second control error; A bias control method for an optical modulator.

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