Integrated circuits and power supply circuits

Abstract

To provide an integrated circuit capable of preventing a switching period of a transistor from changing rapidly, and to provide a power-supply circuit thereof.SOLUTION: A control IC 32 comprises: a transformer including a primary coil, a secondary coil and an auxiliary coil; and a power transistor for controlling a current flowing in the primary coil. An integrated circuit for switching a power transistor of a power-supply circuit for generating an output voltage from an input voltage comprises: a first terminal RT to which a first resistance 41 is connected; a first detection circuit 65 for detecting whether or not a load state of the power-supply circuit is overloaded; a second detection circuit 64 for detecting whether or not a current flowing in the power transistor is overcurrent; an oscillation circuit 66 for outputting an oscillation signal of a period corresponding to a resistance value Rrt of the first resistance; and a drive signal output circuit 67 for outputting a drive signal for tuning on the power transistor based on an oscillation signal Vct, and turning off the power transistor based on a feed-back voltage Vfb corresponding to the output voltage.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an integrated circuit and a power supply circuit. [Background technology]

[0002] There is a power supply circuit integrated circuit that realizes a drooping characteristic that reduces the output voltage when the load on the AC-DC converter becomes overloaded (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-131380 Summary of the Invention [Problem to be solved by the invention]

[0004] Some integrated circuits change their switching period depending on whether the load is overloaded or not. In this case, when the integrated circuit is set to a mode for when the load is overloaded, it operates so that the switching period is lengthened. However, when entering this mode, the switching period of the transistor may change suddenly.

[0005] The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to provide an integrated circuit that can suppress abrupt changes in the switching period of a transistor. [Means for solving the problem]

[0006] An aspect of the integrated circuit according to the present invention that solves the above-mentioned problems is an integrated circuit that switches the transistor of a power supply circuit that generates an output voltage from an input voltage, the integrated circuit comprising: a transformer including a primary coil, a secondary coil, and an auxiliary coil; and a transistor that controls a current flowing through the primary coil, the integrated circuit comprising: a first terminal to which a first resistor is connected; a first detection circuit that detects whether a load state of the power supply circuit is an overload; a second detection circuit that detects whether a current flowing through the transistor is an overcurrent; an oscillation circuit that outputs an oscillation signal having a period corresponding to a first resistance value of the first resistor; and a feedback voltage that turns on the transistor based on the oscillation signal and turns off the transistor based on the feedback voltage corresponding to the output voltage. and a drive signal output circuit that outputs a drive signal that turns off the transistor when the current flowing through the transistor becomes an overcurrent, and the oscillation circuit includes a first current source that outputs a first current based on the first resistance value, a second current source that outputs a second current based on the first resistance value, an adjustment circuit that adjusts the second current so that the second current becomes smaller when the load state becomes an overload state based on a voltage that corresponds to a period during which the transistor is on in the cycle of the drive signal, and a first output circuit that outputs the oscillation signal having an on period that corresponds to a current value of the first current and an off period that corresponds to a current value of the second current.

[0007] An aspect of the power supply circuit according to the present invention that solves the above-mentioned problems is a power supply circuit that generates an output voltage from an input voltage, and includes a transformer including a primary coil, a secondary coil, and an auxiliary coil, a transistor that controls a current flowing through the primary coil, and an integrated circuit that switches on the transistor, the integrated circuit having a first terminal to which a first resistor is connected, a first detection circuit that detects whether a load state of the power supply circuit is an overload, a second detection circuit that detects whether a current flowing through the transistor is an overcurrent, an oscillation circuit that outputs an oscillation signal having a period corresponding to a first resistance value of the first resistor, and a feedback voltage that turns on the transistor based on the oscillation signal and turns on the transistor based on the feedback voltage that corresponds to the output voltage. and a drive signal output circuit that outputs a drive signal to turn off the transistor when the current flowing through the transistor becomes an overcurrent, and the oscillation circuit includes: a first current source that outputs a first current based on the first resistance value; a second current source that outputs a second current based on the first resistance value; an adjustment circuit that adjusts the second current so that the second current becomes smaller when the load state becomes an overload state based on a voltage corresponding to a period during which the transistor is on in the cycle of the drive signal; and a first output circuit that outputs the oscillation signal having an on period corresponding to a current value of the first current and an off period corresponding to a current value of the second current. [Effects of the Invention]

[0008] It is possible to provide an integrated circuit that can suppress abrupt changes in the switching period of a transistor. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating an example of an AC-DC converter 10. FIG. [Figure 2] 1 is a diagram showing the drooping characteristics of the AC-DC converter 10. FIG. [Figure 3] FIG. 2 is a diagram illustrating an example of a control IC 32. [Figure 4] FIG. 2 is a diagram illustrating an example of the configuration of a signal generating circuit 63. [Figure 5] It is a diagram showing the relationship between the resistance value Rrt of the resistor 41 and the signals F1 to F3. [Figure 6] It is a diagram showing an example of the configuration of the detection circuit 65. [Figure 7] It is a diagram showing an example of the configuration of the oscillation circuit 66. [Figure 8] It is a diagram showing an example of the configuration of the current output circuit 100. [Figure 9] It is a diagram showing an example of the configuration of the current output circuit 101. [Figure 10] It is a diagram showing an example of the configuration of the output circuit 102. [Figure 11] It is a diagram showing the relationship between the signals F1 to F3 and the oscillation frequency Fosc. [Figure 12] It is a diagram showing the relationship between the feedback voltage Vfb and the oscillation frequency Fosc. [Figure 13] It is a diagram showing the relationship between the voltage Vvf and the oscillation frequency Fosc. [Figure 14] It is a diagram showing an example of the operation of the control IC 32 when the state of the load 11 is the rated load. [Figure 15] It is a diagram showing an example of the operation of the control IC 32 when the state of the load 11 is a light load. [Figure 16] It is a diagram showing the relationship between the drive voltage Vg and the inductor current IL1 when the state of the load 11 is the rated load or an overload. [Figure 17] It is a diagram showing an example of the operation of the control IC 32 when the state of the load 11 is an overload.

Embodiments for Carrying Out the Invention

[0010] From the descriptions in this specification and the attached drawings, at least the following matters become clear.

[0011] =====This Embodiment===== <<<Overview of the AC-DC Converter 10>>> 1 is a diagram showing an example of the configuration of an AC-DC converter 10 according to one embodiment of the present invention. The AC-DC converter 10 is a forward power supply circuit that generates an output voltage Vout at a target level from an AC voltage Vac of a commercial power supply, and the output voltage Vout has a drooping characteristic.

[0012] The AC-DC converter 10 includes a full-wave rectifier circuit 20, capacitors 21 and 52, a transformer 22, diodes 23, 50, and 51, a control block 24, a coil Ld, a constant voltage circuit 53, and a light-emitting diode 54. The load 11 is connected to the AC-DC converter 10 and is supplied with power by the AC-DC converter 10, to which the output voltage Vout is applied. The current flowing through the load 11 is referred to as a load current Iout.

[0013] The full-wave rectifier circuit 20 full-wave rectifies a predetermined AC voltage Vac, which is an input voltage, and applies the resulting voltage Vrec1 to the primary coil L1 and reset winding L3 of the transformer 22 and to the capacitor 21. The capacitor 21 smoothes the voltage Vrec1. The AC voltage Vac has an effective value of 100 to 240 V and a frequency of 50 to 60 Hz, for example.

[0014] The transformer 22 has a primary coil L1 provided on the input side, a secondary coil L2 magnetically coupled to the primary coil L1, a reset winding L3, and an auxiliary coil L4. The secondary coil L2, reset winding L3, and auxiliary coil L4 are wound so that the voltages generated in the secondary coil L2, reset winding L3, and auxiliary coil L4 have the same polarity as the voltage generated in the primary coil L1. The primary coil L1, reset winding L3, and auxiliary coil L4 are provided on the input side (primary side), and the secondary coil L2 is provided on the output side (secondary side).

[0015] The diode 23 is an element that resets, together with the reset winding L3, the magnetism remaining in the transformer 22 when the power transistor 30 (described later) is turned off. The diode 23 is provided between the ground terminal of the capacitor 21 and the reset winding L3. When the power transistor 30 is turned off, the diode 23 is turned on, and the current flowing through the diode 23 flows through the reset winding L3. In this case, the voltage Vds on the drain side of the power transistor 30 is twice the rectified voltage Vrec1.

[0016] After that, the inductor current IL1 flowing through the primary coil L1 on the primary side of the transformer 22 flows in the negative direction. As a result, the charge accumulated in the parasitic capacitance of the power transistor 30 is discharged. Then, the voltage Vds becomes the rectified voltage Vrec1. The operation of the AC-DC converter 10 will be described in detail later.

[0017] The control block 24 controls the voltage generated in the secondary coil L2 on the secondary side of the transformer 22 by controlling the inductor current IL1.

[0018] Diode 50 rectifies inductor current IL2 from secondary coil L2 of transformer 22 and supplies it to capacitor 52 via coil Ld. Similarly, diode 51 rectifies inductor current IL3 from secondary coil L2 and supplies it to capacitor 52 via coil Ld. Capacitor 52 is charged by the current from diodes 50 and 51, and an output voltage Vout is generated across the terminals of capacitor 52.

[0019] The constant voltage circuit 53 is a circuit that generates a constant DC voltage, and is configured using, for example, a shunt regulator.

[0020] The light-emitting diode 54 is an element that emits light with an intensity corresponding to the difference between the output voltage Vout and the output of the constant voltage circuit 53, and together with the phototransistor 40 described below, constitutes a photocoupler. In this embodiment, as the level of the output voltage Vout increases, the intensity of the light emitted from the light-emitting diode 54 increases.

[0021] <<<Overview of Control Block 24>>> The control block 24 is a circuit block for controlling the AC-DC converter 10. The control block 24 includes a power transistor 30, resistors 31, 33, 35, and 41, a control IC (Integrated Circuit) 32, capacitors 34, 36, 37, and 39, a diode 38, and a phototransistor 40.

[0022] The power transistor 30 is an NMOS transistor for controlling the power supplied to the load 11, and controls the inductor current IL1 flowing through the primary coil. In this embodiment, the power transistor 30 is a MOS (Metal Oxide Semiconductor) transistor, but is not limited to this. The power transistor 30 may be, for example, a bipolar transistor, etc., as long as it is a transistor that can control power.

[0023] The resistor 31 is a resistor for detecting an inductor current IL1 (i.e., a current flowing through the power transistor 30) that flows through the primary coil L1 when the power transistor 30 is on. One end of the resistor 31 is connected to the source electrode of the power transistor 30 and is also grounded, and the other end is connected to the anode of the diode 23.

[0024] The control IC 32 is an integrated circuit that switches the power transistor 30 to generate the output voltage Vout. Specifically, the control IC 32 switches the power transistor 30 based on the feedback voltage Vfb.

[0025] The control IC 32 is provided with terminals CS, FB, VF, OUT, VCC, RT, and GND, which will be described in detail later. The gate electrode of the power transistor 30 is connected to the terminal OUT, and the power transistor 30 is switched by a drive voltage Vg. The actual control IC 32 is also provided with other terminals, but these are omitted for convenience of explanation. The terminal GND is grounded via a resistor 31.

[0026] One end of capacitor 34 is connected to terminal CS, and the other end is connected to ground via resistor 31, and the voltage across resistor 31 generated by the flow of inductor current IL1 is applied via resistor 33. The resistor 33 and capacitor 34 form a low-pass filter, which stabilizes the voltage Vcs at terminal CS.

[0027] One end of the capacitor 36 is connected to the terminal VF and the other end is connected to ground via the resistor 31, and the drive voltage Vg is applied to the capacitor 36 via the resistor 35. The resistor 35 and the capacitor 36 form a low-pass filter and stabilize the voltage Vvf at the terminal VF. The voltage Vvf is a voltage that corresponds to the period during which the power transistor 30 is on within the cycle of the drive signal Vq1 (described later).

[0028] One end of the capacitor 37 is connected to the terminal VCC, and the other end is connected to the ground via the resistor 31. The anode of the diode 38 is connected to the auxiliary coil L4, and the cathode is connected to the terminal VCC.

[0029] Furthermore, the voltage Va generated in the auxiliary coil L4 is applied to a capacitor 37 via a diode 38. Note that a terminal VCC is connected to the capacitor 37 to which a voltage based on the voltage Va of the auxiliary coil L4 is applied when the power transistor 30 is on, and this voltage becomes the power supply voltage Vcc.

[0030] The capacitor 39 has one end connected to the terminal FB and the other end connected to ground via the resistor 31 to stabilize the voltage Vfb of the terminal FB. Also, the voltage Vfb is a feedback voltage corresponding to the output voltage Vout and is applied to the terminal FB.

[0031] The phototransistor 40 has one end connected to the terminal FB and the other end connected to ground via the resistor 31 and receives light from the light-emitting diode 54. Also, when the intensity of the light emitted by the light-emitting diode 54 increases, the phototransistor 40 allows a larger sink current Ia to flow into the terminal FB. As a result, although details will be described later, the feedback voltage Vfb decreases.

[0032] One end of the resistor 41 is connected to the terminal RT. The other end of the resistor 41 is connected to ground via the resistor 31. Note that the resistor 41 corresponds to the "first resistor", and the terminal RT corresponds to the "first terminal".

[0033] <<<Drop characteristics of the output voltage Vout output from the AC-DC converter 10>>> Although details will be described later, the AC-DC converter 10 of this embodiment supplies power to the load 11. And when a large load current Iout flows through the load 11 (that is, the state of the load 11 becomes a heavy load), if the AC-DC converter 10 continues to output the output voltage Vout at the target level Vout_target, there is a possibility that the load 11 will be damaged. In such a case, generally, the AC-DC converter 10 may give the output voltage Vout a droop characteristic.

[0034] Note that "the state of the load 11 is a heavy load" refers to, for example, a case where the current value of the load current Iout flowing through the load 11 is larger than a predetermined value (for example, 1A). Note that the predetermined value (for example, 1A) in this case is smaller than the predetermined value Iout_limit (described later). Also, "the state of the load 11 is an overload" refers to, for example, a case where the current value of the load current Iout flowing through the load 11 is larger than the predetermined value Iout_limit.

[0035] Furthermore, "the load 11 is in a light load state" refers to, for example, a case where the current value of the load current Iout flowing through the load 11 is less than a predetermined value (for example, 1 A). Furthermore, "the load 11 is in a no-load state" refers to a case where the current value of the load current Iout flowing through the load 11 is extremely small or 0 (zero) A. Furthermore, although it has been explained that the current value of the load current Iout for determining whether the load 11 is in a heavy load state or a light load state is, for example, 1 A, this current value can be set in various ways.

[0036] 2, when the load current Iout is smaller than a predetermined value Iout_limit, the AC-DC converter 10 maintains the output voltage Vout at a target level Vout_target. On the other hand, when the load current Iout is larger than the predetermined value Iout_limit, the AC-DC converter 10 reduces the output voltage Vout.

[0037] <<<Control IC32 Configuration>>> 3 is a diagram showing an example of the configuration of the control IC 32. The control IC 32 switches the power transistor 30 based on the feedback voltage Vfb to generate the output voltage Vout.

[0038] The control IC 32 includes a low voltage protection circuit (UVLO) 60, an internal power supply (REG) 61, a resistor 62, a signal generation circuit 63, comparators 64, 68, and 300, a detection circuit 65, an oscillation circuit 66, a drive signal output circuit 67, and a buffer 69.

[0039] Low Voltage Protection Circuit 60 The low-voltage protection circuit 60 outputs a signal rst based on the power supply voltage Vcc. Specifically, when the level of the voltage Vcc reaches a predetermined level Voff, the low-voltage protection circuit 60 outputs an “L” level signal rst that stops the switching of the power transistor 30.

[0040] On the other hand, when the level of the voltage Vcc reaches a predetermined level Von, which is higher than the predetermined level Voff, the low voltage protection circuit 60 outputs a signal rst of "H" level that allows the power transistor 30 to switch.

[0041] ==Internal power supply 61== The internal power supply 61 outputs a power supply voltage Vdd based on the power supply voltage Vcc.

[0042] ==Resistor 62== The resistor 62 is an element for generating the feedback voltage Vfb, and has one end to which the power supply voltage Vdd is applied and the other end to which the terminal FB is connected. A sink current Ia flows through the resistor 62, and the feedback voltage Vfb is generated based on the voltage generated across the resistor 62.

[0043] 1, when the intensity of light from the light-emitting diode 54 increases, the phototransistor 40 causes a large sink current Ia to flow through the terminal FB, which increases the voltage across the resistor 62 and decreases the feedback voltage Vfb.

[0044] ==Signal generation circuit 63== The signal generating circuit 63 outputs a signal that sets the oscillation frequency Fosc of the oscillation circuit 66 (described later). Specifically, the signal generating circuit 63 outputs signals F1 to F3 that set the oscillation frequency Fosc of the oscillation signals Vct and osc_out (described later) according to the resistance value Rrt of the resistor 41 connected to the terminal RT.

[0045] 4 is a diagram showing an example of the configuration of the signal generating circuit 63. The signal generating circuit 63 includes a constant current source 80 and a conversion circuit 81. The constant current source 80 supplies a constant current Irt to the resistor 41 via a terminal RT.

[0046] The conversion circuit 81 converts a voltage Vrt corresponding to the resistance value Rrt of the resistor 41 connected to the terminal RT into signals F1 to F3 that set the oscillation frequency Fosc of the oscillation signal Vct and osc_out (described later). The conversion circuit 81, which serves as an analog-to-digital converter, includes comparators 82 to 84.

[0047] Comparators 82-84 compare the voltage Vrt generated across resistor 41 with a reference voltage and output signals F1-F3, respectively. Specifically, when voltage Vrt corresponding to resistance value Rrt of resistor 41 is higher than reference voltage Vref_f1, comparator 82 outputs high-level (hereinafter referred to as "H" level) signal F1. On the other hand, when voltage Vrt is lower than reference voltage Vref_f1, comparator 82 outputs low-level (hereinafter referred to as "L" level) signal F1.

[0048] Similarly, when the voltage Vrt is higher than the reference voltage Vref_f2, the comparator 83 outputs a signal F2 at an “H” level. On the other hand, when the voltage Vrt is lower than the reference voltage Vref_f2, the comparator 83 outputs a signal F2 at an “L” level.

[0049] When the voltage Vrt is higher than the reference voltage Vref_f3, the comparator 84 outputs a signal F3 at a high level. On the other hand, when the voltage Vrt is lower than the reference voltage Vref_f3, the comparator 84 outputs a signal F3 at a low level. Here, the relationship is reference voltage Vref_f1>reference voltage Vref_f2>reference voltage Vref_f3.

[0050] From the above, when the resistance value Rrt of the resistor 41 is one of the resistance values Rrt0 to Rrt3, the signal generating circuit 63 outputs signals F1 to F3 according to the resistance value Rrt, as shown in Fig. 5. The resistance value Rrt corresponds to the "first resistance value."

[0051] Here, the resistance values Rrt are set so that Rrt0>Rrt1>Rrt2>Rrt3, and the voltage Vrt corresponding to the resistance values Rrt is determined so that the signal generating circuit 63 can output signals F1 to F3 as shown in Fig. 5. The relationship between the signals F1 to F3 and the oscillation frequency Fosc will be described later. The signals F1 to F3 correspond to "digital values."

[0052] ==Comparator 64== Returning to Fig. 3, the comparator 64 will be described. The comparator 64 detects an overcurrent flowing through the power transistor 30 by using the voltage Vcs generated in response to the inductor current IL1, and determines whether the current flowing through the power transistor is an overcurrent. Note that since the connection point between the power transistor 30 and the resistor 31 is grounded, the voltage Vcs is a negative voltage.

[0053] Specifically, when the voltage Vcs falls below the reference voltage Vref_ocp, that is, when the negative voltage generated across the resistor 31 in accordance with the inductor current IL1 falls below the reference voltage Vref_оcp, the comparator 64 outputs a signal оcp indicating that an overcurrent has been detected.

[0054] On the other hand, if the voltage Vcs is higher than the reference voltage Vref_оcp, the comparator 64 outputs a signal оcp indicating that an overcurrent is not detected. Note that since the voltage Vcs is a negative voltage, the reference voltage Vref_оcp is also a negative voltage.

[0055] 3, for the sake of convenience, the reference voltage Vref_ocp is a negative voltage. However, the voltage Vcs may be level-shifted to a positive voltage, and the positive voltage Vcs may be compared with the positive reference voltage Vref_ocp. The comparator 64 corresponds to the "second detection circuit," and the signal ocp corresponds to the "detection result."

[0056] ==Detection Circuit 65== 1 is in an overload state. Specifically, when the comparator 64 outputs a signal ocp indicating that an overcurrent has been detected, or when the feedback voltage Vfb exceeds a reference voltage Vtholp_h (described later), the detection circuit 65 outputs a signal olp indicating an overload.

[0057] On the other hand, when the comparator 64 outputs a signal ocp indicating that an overcurrent is not detected and the feedback voltage Vfb does not exceed a reference voltage Vtholp_h (described later), the detection circuit 65 outputs a signal olp indicating that there is no overload.

[0058] 6 is a diagram showing an example of the configuration of the detection circuit 65. The detection circuit 65 includes a hysteresis comparator 90 and an output circuit 91.

[0059] ====Hysteresis Comparator 90==== The hysteresis comparator 90 detects whether the load 11 is in an overload state based on the feedback voltage Vfb. Specifically, the hysteresis comparator 90 generates a reference voltage Vtholp_h that is higher than the reference voltage Vtholp, and a reference voltage Vtholp_l that is lower than the reference voltage Vtholp_h. The hysteresis comparator 90 then compares the feedback voltage Vfb with the reference voltage Vtholp_h.

[0060] If the feedback voltage Vfb exceeds the reference voltage Vtholp_h, the hysteresis comparator 90 outputs a signal indicating an overload. On the other hand, if the feedback voltage Vfb does not exceed the reference voltage Vtholp_h, the hysteresis comparator 90 outputs a signal indicating that an overload does not occur. Furthermore, if the feedback voltage Vfb is lower than the reference voltage Vtholp_h, the hysteresis comparator 90 outputs a signal indicating that an overload does not occur. The reference voltage Vtholp_h corresponds to a "third voltage," and the hysteresis comparator 90 corresponds to a "comparison circuit."

[0061] ====Output circuit 91==== The output circuit 91 outputs a signal olp indicating whether the load 11 is in an overload state based on the comparison result of the hysteresis comparator 90 or the signal ocp. Specifically, when the hysteresis comparator 90 outputs a signal indicating an overload or when the comparator 64 in Fig. 3 outputs a signal ocp indicating an overcurrent, the output circuit 91 outputs the signal olp indicating an overload. On the other hand, when the hysteresis comparator 90 outputs a signal indicating no overload and the comparator 64 outputs a signal ocp indicating no overcurrent, the output circuit 91 outputs the signal olp indicating no overload.

[0062] The output circuit 91 includes D flip-flops 92 and 95, an OR element 93, and an inverter 94. The D flip-flop 92 detects whether the load 11 is in an overload state based on whether an overcurrent flows through the power transistor 30 in Fig. 1. Specifically, when the power transistor 30 is turned off (i.e., at the falling edge of the signal Vq1 (described later) in Fig. 3), if the comparator 64 outputs a signal ocp indicating an overcurrent, the D flip-flop 92 outputs a signal indicating an overload.

[0063] On the other hand, if the comparator 64 outputs a signal ocp indicating that there is no overcurrent when the power transistor 30 is turned off, the D flip-flop 92 outputs a signal indicating that there is no overload. The above describes the case where the low-voltage protection circuit 60 in Fig. 3 outputs a reset signal rst at an "H" level. On the other hand, if the low-voltage protection circuit 60 outputs a reset signal rst at an "L" level, the D flip-flop 92 is reset to output a signal indicating that there is no overload.

[0064] The OR element 93 outputs a signal indicating an overload based on the outputs of the hysteresis comparator 90 and the D flip-flop 92. Specifically, when either the hysteresis comparator 90 or the D flip-flop 92 outputs a signal indicating an overload, the OR element 93 outputs a signal indicating an overload.

[0065] On the other hand, when both the hysteresis comparator 90 and the D flip-flop 92 output a signal indicating that there is no overload, the OR element 93 outputs a signal indicating that there is no overload.

[0066] The inverter 94 inverts the logic level of the signal Vq 1 and outputs a clock signal for the D flip-flop 95 .

[0067] The D flip-flop 95 detects whether or not there is an overload based on the output of the OR element 93. Specifically, if the OR element 93 outputs a signal indicating an overload when the power transistor 30 is turned on (i.e., when the signal Vq1 rises), the D flip-flop 95 outputs a signal olp indicating an overload.

[0068] On the other hand, if the OR element 93 outputs a signal indicating that there is no overload when the power transistor 30 is turned on, the D flip-flop 95 outputs a signal olp indicating that there is no overload. The above describes the case where the low-voltage protection circuit 60 in FIG. 3 outputs a reset signal rst at an "H" level. On the other hand, if the low-voltage protection circuit 60 outputs a reset signal rst at an "L" level, the D flip-flop 95 is reset to output a signal olp indicating that there is no overload. The detection circuit 65 corresponds to a "first detection circuit," the output circuit 91 corresponds to a "second output circuit," and the signal olp corresponds to a "detection result."

[0069] ==Oscillator Circuit 66== Returning to Fig. 3, the oscillation circuit 66 will be described. The oscillation circuit 66 outputs an oscillation signal Vct,osc_out having a period corresponding to the resistance value of the resistor 41. Specifically, when the load 11 in Fig. 1 is not in an overload state, the oscillation circuit 66 outputs the oscillation signal Vct,osc_out based on the resistance value Rrt of the resistor 41 and the feedback voltage Vfb.

[0070] On the other hand, when the load 11 is in an overload state, the oscillation circuit 66 outputs the oscillation signal Vct,osc_out based on the resistance value Rrt of the resistor 41 and the voltage Vvf.

[0071] 7 is a diagram showing an example of the configuration of the oscillation circuit 66. The oscillation circuit 66 includes current output circuits 100 and 101, and an output circuit 102. The current output circuit 100 outputs currents Ib0 and Ib1 based on the resistance value Rrt of the resistor 41 and a voltage V1.

[0072] ===Current output circuit 100=== 8 is a diagram showing an example of the configuration of the current output circuit 100. The current output circuit 100 outputs currents Ib0 and Ib1 that correspond to a voltage V1 based on signals F1 to F3 that correspond to a resistance value Rrt of a resistor 41.

[0073] The current output circuit 100 includes an operational amplifier 110, an NPN transistor 111, a variable resistor 112, and PMOS transistors 113-115.

[0074] A voltage V1 is applied to the non-inverting input terminal of the operational amplifier 110. The inverting input terminal of the operational amplifier 110 is connected to one end of a variable resistor 112 for detecting a current Ia0 flowing through the NPN transistor 111 and the PMOS transistor 113, and to the emitter terminal of the NPN transistor 111.

[0075] The operational amplifier 110 controls the NPN transistor 111 so that the voltage at the inverting input terminal becomes the voltage V1 applied to the non-inverting input terminal.

[0076] The variable resistor 112 has a resistance value R1 in response to the signals F1 to F3. The variable resistor 112 includes resistors 120 to 123 and NMOS transistors 124 to 126.

[0077] Furthermore, the resistance value R1 of the variable resistor 112 changes in response to the signals F1 to F3 from the signal generating circuit 63 in Fig. 4. Specifically, as shown in Fig. 5, the signals F1 to F3 go to "L" level in order, and the resistance value R1 increases stepwise as the number of signals F1 to F3 that are at "L" level increases. Note that the variable resistor 112 corresponds to a "second resistor," and the resistance value R1 corresponds to a "second resistance value."

[0078] Under the control of the operational amplifier 110, a voltage V1 is applied to the variable resistor 112, and a current Ia0 determined by the voltage V1 and the resistance value R1 of the variable resistor 112 flows through the diode-connected PMOS transistor 113.

[0079] Furthermore, the PMOS transistor 113 and the PMOS transistor 114 form a current mirror circuit. Therefore, a current Ib0 corresponding to the current Ia0 flowing through the PMOS transistor 113 flows through the PMOS transistor 114.

[0080] That is, the PMOS transistors 113 and 114 output the current Ib0 based on the resistance value Rrt of the resistor 41 in Fig. 1. In other words, the PMOS transistors 113 and 114 output the current Ib0 according to the resistance value R1 and the voltage V1. Note that the voltage V1 corresponds to a "first voltage," the current Ib0 corresponds to a "first current," and the PMOS transistors 113 and 114 correspond to a "first current source."

[0081] Similarly, the PMOS transistor 113 and the PMOS transistor 115 form a current mirror circuit. Therefore, a current Ib1 corresponding to the current Ia0 flowing through the PMOS transistor 113 flows through the PMOS transistor 115.

[0082] That is, the PMOS transistors 113 and 115 output the current Ib1. The current Ib1 corresponds to a "third current," and the PMOS transistors 113 and 115 correspond to a "third current source."

[0083] The transistor size of the PMOS transistor 115 is assumed to be sufficiently smaller than the transistor size of the PMOS transistor 114, and as a result, the current Ib1 is assumed to be sufficiently smaller than the current Ib0.

[0084] Furthermore, the resistance value R1 of the variable resistor 112 increases stepwise as the number of signals F1 to F3 that are at the "L" level increases, and as a result, the currents Ia0, Ib0, and Ib1 decrease stepwise according to the signals F1 to F3.

[0085] ===Current output circuit 101=== 9 is a diagram showing an example of the configuration of the current output circuit 101. The current output circuit 101 outputs a current Ib2 based on a signal olp, a feedback voltage Vfb, and a voltage Vvf. Specifically, when the load 11 in FIG. 1 is not in an overload state, the current output circuit 101 outputs the current Ib2 based on the feedback voltage Vfb. On the other hand, when the load 11 is in an overload state, the current output circuit 101 outputs the current Ib2 based on the voltage Vvf.

[0086] The current output circuit 101 includes voltage conversion circuits 130 and 131, an adjustment circuit 132, a variable resistor 133, and PMOS transistors 134 and 135.

[0087] ====Voltage conversion circuit 130==== The voltage conversion circuit 130 converts the feedback voltage Vfb to a voltage Vfb2. Specifically, when the load 11 is in a light load state, the voltage conversion circuit 130 converts the level of the feedback voltage Vfb to the level of the voltage Vfb2 so that the level of the voltage Vfb2 becomes the same as the level of the voltage V0 input to an operational amplifier 180 (described later).

[0088] The voltage conversion circuit 130 includes an operational amplifier 140 and resistors 141 and 142. A feedback voltage Vfb2 is input to the non-inverting input terminal of the operational amplifier 140. On the other hand, a voltage at a connection point between a resistor 141, one end of which is connected to the output of the operational amplifier 140, and a resistor 142, one end of which is applied with a voltage Vref_offset, is applied to the inverting input terminal of the operational amplifier 140.

[0089] When the voltage Vfb decreases, the voltage at the connection point of the resistors 141 and 142 decreases, and as a result, the voltage Vfb2 also decreases. On the other hand, when the voltage Vfb increases, the voltage at the connection point of the resistors 141 and 142 increases, and as a result, the voltage Vfb2 also increases. Note that the voltage conversion circuit 130 is designed so that when the load 11 becomes light and the voltage Vfb becomes voltage Vfb2_v0, the voltage Vfb2 becomes a voltage at the same level as the voltage V0 input to the operational amplifier 180.

[0090] ====Voltage conversion circuit 131==== The voltage conversion circuit 131 converts the voltage Vvf to a voltage Vvf2. Specifically, when the load 11 is in a light load state, the voltage conversion circuit 131 converts the level of the voltage Vvf to the level of the voltage Vvf2 so that the level of the voltage Vvf2 becomes the same as the level of the voltage V0 input to the operational amplifier 180.

[0091] The voltage conversion circuit 131 includes a current source 150, a PNP transistor 151, an NPN transistor 152, and resistors 153 and 154.

[0092] A voltage Vvf is applied to the base electrode of the PNP transistor 151, and a current source 150 is connected to the collector electrode. The emitter electrode is grounded. When the voltage Vvf decreases, the current from the current source 150 flows to the ground via the PNP transistor 151. As a result, the voltage at the connection point between the current source 150 and the PNP transistor 151 decreases.

[0093] When the voltage at the connection point between current source 150 and PNP transistor 151 drops, the on-resistance of NPN transistor 152 increases, and the current flowing through resistors 153 and 154 connected in series decreases. As a result, the voltage Vvf2 generated at the connection point between resistors 153 and 154 drops.

[0094] On the other hand, when the voltage Vvf increases, the voltage Vvf2 increases inversely to when the voltage Vvf decreases. Note that the voltage conversion circuit 131 is designed so that when it is determined that the load 11 is overloaded and the voltage Vvf becomes the voltage Vvf2_v0, the voltage Vvf2 becomes the same level as the voltage V0 input to the operational amplifier 180.

[0095] ====Adjustment circuit 132==== The adjustment circuit 132 adjusts the current value of the current Ib2. Specifically, when the load 11 in Fig. 1 is in an overload state, the adjustment circuit 132 adjusts the level of the voltage V2 based on the voltage Vvf to reduce the current Ib2, thereby adjusting the current Ib2. On the other hand, when the load 11 is not in a heavy load state and the output voltage Vout increases, the adjustment circuit 132 adjusts the level of the voltage V2 based on the feedback voltage Vfb to reduce the current Ib2, thereby adjusting the current Ib2.

[0096] =====Selection circuit 160===== The adjustment circuit 132 is configured to include a selection circuit 160 and an output circuit 161. The selection circuit 160 selects the voltage Vfb2 when the load 11 is not in an overload state, and selects the voltage Vvf2 when the load 11 is in an overload state. The selection circuit 160 is configured to include analog switches 170 and 171, and an inverter 172.

[0097] When the detection circuit 65 outputs a signal olp indicating that there is no overload, the analog switch 170 outputs the voltage Vfb2 to the operational amplifier 180. On the other hand, when the detection circuit 65 outputs a signal olp indicating that there is an overload, the analog switch 170 does not output the voltage Vfb2 to the operational amplifier 180.

[0098] Furthermore, when the detection circuit 65 outputs a signal olp indicating that there is no overload, the analog switch 171 does not output the voltage Vvf2 to the operational amplifier 180. On the other hand, when the detection circuit 65 outputs a signal olp indicating that there is an overload, the analog switch 171 outputs the voltage Vvf2 to the operational amplifier 180.

[0099] The inverter 172 inverts the logic level of the signal olp and outputs it to the analog switches 170 and 171 .

[0100] =====Output circuit 161===== The output circuit 161 outputs a voltage V2 based on the voltage selected by the selection circuit 160. Specifically, the output circuit 161 outputs, as the voltage V2, the voltage V0 or a voltage selected by the selection circuit 160 that reduces the current Ib2.

[0101] The output circuit 161 includes an operational amplifier 180 and an NPN transistor 181. Based on the voltage V0 and the voltage selected by the selection circuit 160, the operational amplifier 180 sets the voltage at the connection point between the NPN transistor 181 and the variable resistor 133 to a voltage V2.

[0102] A voltage V0 is applied to a first non-inverting input terminal of the operational amplifier 180, and a voltage selected by the selection circuit 160 is applied to a second non-inverting input terminal of the operational amplifier 180. The voltage at the connection point between the NPN transistor 181 and the variable resistor 133 (i.e., voltage V2) is applied to the inverting input terminal of the operational amplifier 180.

[0103] The operational amplifier 180 sets the voltage V2 at the inverting input terminal to the voltage applied to the non-inverting input terminal, and a current Ia1 based on the voltage V2 and the resistance value of a variable resistor 133 (described later) flows through the NPN transistor 181.

[0104] Furthermore, the current output circuit 101 outputs the current Ib2 based on the lower of the voltage V0 and the voltage selected by the selection circuit 160. The output circuit 161 corresponds to a "third output circuit," and the voltage V0 corresponds to a "predetermined voltage."

[0105] ====Variable Resistor 133==== The variable resistor 133 has a resistance value R2 in response to the signals F1 to F3. The variable resistor 133 includes resistors 190 to 193 and NMOS transistors 194 to 196.

[0106] 4, the resistance value R2 of the variable resistor 133 changes in the same way as the variable resistor 112. Specifically, since the current Ib2 is determined as will be described later, the currents Ia1 and Ib2 decrease in stages as the resistance value R2 increases in stages in accordance with the signals F1 to F3.

[0107] When the voltage V1 applied to the current output circuit 100 and the voltage V0 used in the current output circuit 101 are the same, the variable resistors 112 and 133 are designed so that the resistance value R1 of the variable resistor 112 is smaller than the resistance value R2 of the variable resistor 133. Furthermore, the resistance value R2 corresponds to the "third resistance value," and the variable resistor 133 corresponds to the "third resistor."

[0108] ====PMOS transistors 134, 135==== The PMOS transistors 134 and 135 form a current mirror circuit, so that a current Ib2 corresponding to the current Ia1 flowing through the PMOS transistor 134 flows through the PMOS transistor 135.

[0109] That is, the PMOS transistors 134 and 135 output a current Ib2 smaller than the current Ib0 based on the resistance value Rrt of the resistor 41 in FIG. 1. In other words, the PMOS transistors 134 and 135 output a current Ib2 according to the resistance value R2 and the voltage V2. The voltage V2 corresponds to a "second voltage," the current Ib2 corresponds to a "second current," and the PMOS transistors 134 and 135 correspond to a "second current source."

[0110] ===Output circuit 102=== The output circuit 102 outputs the oscillation signal Vct,osc_out based on the currents Ib0 to Ib2. Specifically, the output circuit 102 outputs the oscillation signal Vct,osc_out having an on period corresponding to the current value of the current Ib0 and an off period corresponding to the current value of the current Ib2.

[0111] 10 is a diagram showing an example of the configuration of the output circuit 102. The output circuit 102 includes an adder circuit 200, a PMOS transistor 201, an NMOS transistor 202, a capacitor 203, an oscillation signal output circuit 204, and an inverter 205.

[0112] ====Adder circuit 200==== The adder circuit 200 adds the current Ib1 and the current Ib2 to obtain a current Ib3. Specifically, when the load 11 in FIG. 1 is in a light load or overload state, the adder circuit 200 adds the current Ib2 output based on the decreasing feedback voltage Vfb or voltage Vvf to the current Ib1 output based on the voltage V1.

[0113] The adder circuit 200 includes NMOS transistors 210 to 213. The NMOS transistor 210 and the NMOS transistor 211 form a current mirror circuit. Therefore, a current corresponding to the current Ib2 flowing through the NMOS transistor 210 flows through the NMOS transistor 211.

[0114] Furthermore, the NMOS transistor 212 and the NMOS transistor 213 form a current mirror circuit. Therefore, a current corresponding to the current Ib1 flowing through the NMOS transistor 212 flows through the NMOS transistor 213.

[0115] Then, at the node where the drain electrode of the NMOS transistor 211 and the drain electrode of the NMOS transistor 213 are connected, a current corresponding to the current Ib1 and a current corresponding to the current Ib2 are added together to become a current Ib3. Note that the current Ib3 corresponds to the "fourth current."

[0116] ====PMOS transistor 201 and NMOS transistor 202==== The PMOS transistor 201 and the NMOS transistor 202 control the charging and discharging of the capacitor 203. Specifically, the PMOS transistor 201 is turned on while the oscillation signal osc_out that determines the on-period of the power transistor 30 in Fig. 1 is being output. Then, the current Ib0 flows through the PMOS transistor 201, thereby charging the capacitor 203.

[0117] On the other hand, the NMOS transistor 202 is turned on while the oscillation signal osc_out that determines the off period of the power transistor 30 is being output. Then, the current Ib3 flows through the NMOS transistor 202, and the capacitor 203 is discharged.

[0118] ====Capacitor 203==== The capacitor 203 is charged with a current Ib0 during the ON period determined by the oscillation signal osc_out, and is discharged with a current Ib3 during the OFF period determined by the oscillation signal osc_out.

[0119] ====Oscillation signal output circuit 204==== The oscillation signal output circuit 204 outputs an oscillation signal osc_out based on the voltage Vct generated across the capacitor 203. Specifically, when the voltage Vct becomes the voltage Vref_on, the oscillation signal output circuit 204 outputs the oscillation signal osc_out that determines the on-period of the power transistor 30. On the other hand, when the voltage Vct becomes the voltage Vref_off, the oscillation signal output circuit 204 outputs the oscillation signal osc_out that determines the off-period of the power transistor 30. Note that the voltage Vref_off is lower than the voltage Vtholp_h.

[0120] The oscillation signal output circuit 204 includes comparators 220 and 221 and an SR flip-flop 222. The comparator 220 outputs an "H" level signal when the voltage Vct becomes the voltage Vref_off. On the other hand, the comparator 220 outputs an "L" level signal when the voltage Vct is lower than the voltage Vref_off.

[0121] When the voltage Vct becomes the voltage Vref_on, the comparator 221 outputs a signal of the "H" level. On the other hand, when the voltage Vct is higher than the voltage Vref_on, the comparator 221 outputs a signal of the "L" level.

[0122] The SR flip-flop 222 outputs an oscillation signal osc_out. Specifically, when the comparator 220 outputs a signal of “H” level, the SR flip-flop 222 outputs an oscillation signal osc_out of “L” level, which determines the off period of the power transistor 30.

[0123] On the other hand, when the comparator 221 outputs a signal of "H" level, the SR flip-flop 222 outputs an oscillation signal osc_out of "H" level, which determines the on-period of the power transistor 30.

[0124] The inverter 205 controls the PMOS transistor 201 and the NMOS transistor 202. Specifically, when the oscillation signal output circuit 204 outputs an oscillation signal osc_out at an “H” level, the inverter 205 turns the PMOS transistor 201 on.

[0125] On the other hand, when the oscillation signal output circuit 204 outputs the oscillation signal osc_out at the “L” level, the inverter 205 turns on the NMOS transistor 202 .

[0126] Fig. 11 is a diagram showing the relationship between the signals F1 to F3 and the oscillation frequency Fosc. As shown in Fig. 5, when the resistance value Rrt of the resistor 41 in Fig. 1 is set, the signal generating circuit 63 outputs the signals F1 to F3 in accordance with the resistance value Rrt.

[0127] The current output circuit 100 outputs currents Ib0 and Ib1 that decrease stepwise as the number of "L" level signals among the signals F1 to F3 increases. Similarly, the current output circuit 101 outputs current Ib2 that decreases stepwise as the number of "L" level signals among the signals F1 to F3 increases. As a result, the adder circuit 200 outputs current Ib3 that decreases stepwise as the number of "L" level signals among the signals F1 to F3 increases.

[0128] Therefore, the currents Ib0 and Ib3 that charge and discharge capacitor 203 become smaller as the number of signals F1 to F3 that are at "L" level increases, and the cycle of voltage Vct becomes longer as the number of signals F1 to F3 that are at "L" level increases. Therefore, as shown in Fig. 11, the oscillation frequency Fosc decreases in stages as the number of signals F1 to F3 that are at "L" level increases.

[0129] As described above, the oscillation frequency Fosc is determined based on the signals F1 to F3, but the current Ib2 is determined not only by the signals F1 to F3 but also by the feedback voltage Vfb or the voltage Vvf, depending on whether the state of the load 11 in Figure 1 is an overload or not.

[0130] Furthermore, in the forward AC-DC converter 10, the residual magnetism of the transformer 22 must be eliminated during the period when the power transistor 30 is turned off. For this reason, the maximum on-duty of the power transistor 30 is determined. To comply with the maximum on-duty, the current output circuits 100 and 101 are designed so that the current Ib0 is larger than the currents Ib2 and Ib3. The output circuit 102 corresponds to the "first output circuit."

[0131] 12 is a diagram showing the relationship between the feedback voltage Vfb and the oscillation frequency Fosc. When the load 11 is not in an overload state, the selection circuit 160 in FIG. 9 selects the voltage Vfb2, and the current output circuit 101 outputs the current Ib2 in accordance with the voltage Vfb2.

[0132] In this case, as the load 11 becomes lighter, the feedback voltage Vfb decreases. As shown in FIG. 12, the feedback voltage Vfb decreases to voltage Vfb2_v0. When voltage Vfb2 becomes lower than voltage V0, the operational amplifier 180 in FIG. 9 adjusts voltage V2 to decrease based on voltage Vfb2. Therefore, the current output circuit 101 outputs current Ib2, which decreases in accordance with voltage Vfb2, and the oscillation frequency Fosc of the oscillation circuit 66 gradually decreases from oscillation frequency Foscx. The oscillation frequency Foscx is determined by the resistance value Rrt (i.e., Rrt0 to Rrt3) of the resistor 41. Here, "x" represents "0 to 3" corresponding to each of Rrt0 to Rrt3.

[0133] As will be described in detail later, when the feedback voltage Vfb falls below the voltage Vref_stop, the comparator 68 in Fig. 3 outputs a signal stop0 that stops the switching of the power transistor 30 in Fig. 1. Therefore, when the feedback voltage Vfb falls below the voltage Vref_stop, the switching of the power transistor 30 is stopped.

[0134] 13 is a diagram showing the relationship between the voltage Vvf and the oscillation frequency Fosc. When the load 11 is in an overload state, the selection circuit 160 selects the voltage Vvf2, and the current output circuit 101 outputs the current Ib2 in accordance with the voltage Vvf2.

[0135] In this case, as will be described in detail later, when the load 11 is in an overload state, more power is supplied to the secondary side of the transformer 22 in FIG. 1, and therefore the inductor current IL1 flowing through the power transistor 30 has a larger DC offset component.

[0136] The "DC offset component" refers to the current value of the inductor current IL1 that flows the instant the power transistor 30 is turned on. The current value of the inductor current IL1 when the power transistor 30 is turned on is the DC offset component plus the current value of the current that increases over time depending on the inductance value of the primary coil L1 and the rectified voltage Vrec1.

[0137] Therefore, when the load 11 is in an overload state, the period from when the power transistor 30 is turned on until the comparator 64 in Fig. 1 detects an overcurrent becomes shorter. Therefore, when the load 11 is in an overload state, the period during which the power transistor 30 is on becomes shorter.

[0138] Furthermore, since the voltage Vvf corresponds to the period during which the power transistor 30 is on, when the load 11 is in an overload state, the voltage Vvf gradually decreases. Then, as shown in FIG. 13, when the voltage Vvf decreases and reaches voltage Vvf2_v0, voltage Vvf2 becomes lower than voltage V0, and the operational amplifier 180 in FIG. 9 adjusts the voltage V2 to decrease based on voltage Vvf2. Therefore, the current output circuit 101 outputs current Ib2, which decreases in accordance with voltage Vvf2, and the oscillation frequency Fosc of the oscillation circuit 66 gradually decreases from oscillation frequency Foscx. Then, as will be described in detail later, when the voltage Vvf reaches voltage Vvf2_low, the comparator 300 outputs a signal stop1 to stop the switching of the power transistor 30. Therefore, when the feedback voltage Vvf falls below voltage Vvf2_low, the switching of the power transistor 30 is stopped.

[0139] ==Drive signal output circuit 67== 3, a description will be given of the drive signal output circuit 67. The drive signal output circuit 67 outputs a drive signal Vq1 that turns on the power transistor 30 based on the oscillation signal osc_out and turns off the power transistor 30 based on the feedback voltage Vfb.

[0140] Furthermore, when the inductor current IL1 flowing through the power transistor 30 becomes an overcurrent and the comparator 64 outputs a signal ocp indicating the overcurrent, the drive signal output circuit 67 outputs a drive signal Vq1 that turns the power transistor 30 off.

[0141] The drive signal output circuit 67 includes a comparator 70, a one-shot circuit 71, SR flip-flops 72 and 73, and an AND element 74.

[0142] As will be described in detail later, when the oscillation circuit 66 outputs an oscillation signal osc_out at an “H” level, the power transistor 30 turns on. Then, when the oscillation signal Vct reaches the feedback voltage Vfb, the comparator 70 outputs a signal Vr that turns the power transistor 30 off.

[0143] Furthermore, the one-shot circuit 71 outputs a pulse signal Vp1 based on the oscillation signal osc_out at the "H" level.

[0144] A pulse signal Vp1 is input to a set terminal of the SR flip-flop 72 and a reset terminal of the SR flip-flop 73.

[0145] Therefore, when the one-shot circuit 71 outputs the pulse signal Vp1, a signal that turns on the power transistor 30 is output from the Q output of the SR flip-flop 72 and the Q bar output of the SR flip-flop 73.

[0146] The SR flip-flop 72 receives the signal Vr from the comparator 70 at its reset terminal, and the SR flip-flop 73 receives the signal ocp from the comparator 64 at its set terminal.

[0147] When the comparator 70 outputs a signal Vr that turns off the power transistor 30, a signal that turns off the power transistor 30 is output from the Q output of the SR flip-flop 72. When the comparator 64 outputs a signal ocp that indicates an overcurrent, a signal that turns off the power transistor 30 is output from the Q bar output of the SR flip-flop 73.

[0148] The AND element 74 outputs a drive signal Vq1 based on the oscillation signal osc_out from the oscillation circuit 66, the Q output of the SR flip-flop 72, and the Q-bar output of the SR flip-flop 73. Specifically, while the oscillation signal osc_out of the "H" level is being input, if a signal to turn on the power transistor 30 is output from the Q output of the SR flip-flop 72 and the Q-bar output of the SR flip-flop 73, the AND element 74 outputs a drive signal Vq1 of the "H" level that turns on the power transistor 30.

[0149] On the other hand, when the comparator 70 outputs a signal Vr that turns off the power transistor 30 while the oscillation signal osc_out of the "H" level is being input, the AND element 74 outputs a drive signal Vq1 of the "L" level that turns off the power transistor 30. Similarly, when the comparator 64 outputs a signal ocp that indicates an overcurrent, the AND element 74 outputs a drive signal Vq1 of the "L" level that turns off the power transistor 30.

[0150] Although the case where the oscillation signal osc_out is input at "H" level has been described above, when the oscillation signal osc_out is input at "L" level, the AND element 74 outputs the drive signal Vq1 at "L" level, which turns off the power transistor 30. Therefore, the oscillation signal osc_out functions as a signal that determines the maximum on-width of the power transistor 30. That is, when the feedback voltage Vfb increases and reaches the voltage Vref_off, the on-width of the power transistor 30 becomes the maximum on-width. Then, when the feedback voltage Vfb further increases and exceeds the voltage Vtholp_h, the detection circuit 65 outputs a signal olp indicating an overload.

[0151] ==Comparator 68== 1 becomes a light load state and the feedback voltage Vfb drops to a predetermined level, the comparator 68 stops the switching of the power transistor 30. Specifically, when the feedback voltage Vfb drops to the voltage Vref_stop, the comparator 68 outputs a signal stop0 that stops the switching of the power transistor 30. On the other hand, when the feedback voltage Vfb is higher than the voltage Vref_stop, the comparator 68 outputs a signal stop0 that causes the power transistor 30 to switch.

[0152] ==Comparator 300== When the load 11 is in an overload state and the feedback voltage Vvf drops to a predetermined level, the comparator 300 stops the switching of the power transistor 30. Specifically, when the voltage Vvf drops to the voltage Vvf2_low, the comparator 300 outputs a signal stop1 that stops the switching of the power transistor 30. On the other hand, when the voltage Vvf is higher than the voltage Vvf2_low, the comparator 300 outputs the signal stop1 that causes the power transistor 30 to switch.

[0153] ==Buffer 69== The buffer 69 outputs the drive voltage Vg based on the drive signal Vq1. Specifically, based on the drive signal Vq1 that turns on the power transistor 30, the buffer 69 changes the level of the drive voltage Vg to the level of the power supply voltage Vcc.

[0154] On the other hand, the buffer 69 changes the level of the drive voltage Vg to the ground voltage based on the drive signal Vq1 that turns off the power transistor 30. When the comparator 68 outputs a signal stop0 that stops the switching of the power transistor 30, the buffer 69 changes the level of the drive voltage Vg to the ground voltage. Similarly, when the comparator 300 outputs a signal stop1 that stops the switching of the power transistor 30, the buffer 69 changes the level of the drive voltage Vg to the ground voltage.

[0155] <<<Operation of AC-DC converter 10 when load 11 is at rated load>>> Fig. 14 is a diagram showing an example of the operation of the control IC 32 when the load 11 is in a rated load state. Note that although the voltage Vcs generated at the terminal CS by the inductor current IL1 is a negative voltage, in Fig. 14, the voltage Vcs is also depicted as a positive voltage, just like the inductor current IL1. Furthermore, "the load 11 is in a rated load state" refers to a state of the load 11 in which the AC-DC converter 10 is designed to operate efficiently.

[0156] At time t0 when the oscillation signal Vct reaches voltage Vref_on, the oscillation circuit 66 outputs an oscillation signal osc_out at the "H" level, causing the one-shot circuit 71 to output a pulse signal Vp1, and as a result, the buffer 69 changes the level of the drive voltage Vg to the level of the power supply voltage Vcc.

[0157] When the level of the drive voltage Vg changes to the level of the power supply voltage Vcc, the power transistor 30 turns on and the voltage Vds becomes the ground voltage. Then, the inductor current IL1 starts to flow in the primary coil L1. When the inductor current IL1 starts to flow, the diode 50 turns on and the inductor current IL2 starts to flow because the primary coil and the secondary coil have the same winding direction. Meanwhile, the diode 51 is off and the inductor current IL3 does not flow. In this case, the voltage Vld of the inductor Ld becomes a positive voltage.

[0158] At time t1 when the voltage Vct becomes the feedback voltage Vfb, the comparator 70 outputs a signal Vr to turn off the power transistor 30. As a result, the buffer 69 changes the level of the drive voltage Vg to the ground voltage.

[0159] When the level of the drive voltage Vg changes to the ground voltage level, the power transistor 30 turns off and the voltage Vds rises. In this case, an electromotive force is generated in the primary coil L1 in the direction opposite to when the power transistor 30 is on, and a current flows from the primary coil L1 to the reset winding L3 via the capacitor 21 and the diode 23. As a result, the voltage Vds becomes the sum of the voltages generated in the primary coil L1 and the reset winding L3.

[0160] Furthermore, when the power transistor 30 is turned off, the inductor current IL1 decreases. Similarly, the diode 50 is turned off, and the inductor current IL2 decreases. Meanwhile, the diode 51 is turned on, and the inductor current IL3 begins to flow. In this case, the voltage Vld of the inductor Ld becomes a negative voltage.

[0161] At time t2 when the voltage Vct becomes the voltage Vref_off, the oscillation circuit 66 outputs the oscillation signal osc_out at the "L" level.

[0162] At time t3, when the current flowing from the primary coil L1 through the capacitor 21 and the diode 23 to the reset winding L3 decreases, the voltage Vds begins to decrease.

[0163] Then, at time t4 when the current flowing from the primary coil L1 through the capacitor 21 and the diode 23 to the reset winding L3 ceases, the voltage Vds becomes the rectified voltage Vrec1.

[0164] Furthermore, at time t5 when the oscillation signal Vct becomes voltage Vref_on, the oscillation circuit 66 outputs an oscillation signal osc_out at "H" level. After time t5, the operation from time t0 to time t4 is repeated.

[0165] <<<Operation of AC-DC Converter 10 When Load 11 is in a Light Load State>>> Fig. 15 is a diagram showing an example of the operation of the control IC 32 when the load 11 is in a light load state. In Fig. 15, similarly to Fig. 14, the voltage Vcs is also depicted as a positive voltage, as is the inductor current IL1.

[0166] Furthermore, times t10 and t15 correspond to times t0 and t5, respectively, and time t11 corresponds to time t1, and times t12 and t13 correspond to times t3 and t4, respectively, and time t14 corresponds to time t2.

[0167] Furthermore, the feedback voltage Vfb is lower than when the load 11 is in the rated load state, resulting in a decrease in the on-period of the power transistor 30. This reduces the power supplied to the secondary side of the transformer 22, causing the output voltage Vout to decrease.

[0168] The AC-DC converter 10 is a forward power supply circuit, and since the inductance value of the transformer 22 is large, it operates in a continuous current mode even when the load 11 is in a light load state.

[0169] However, when the load 11 is in a light load state compared to when the load 11 is in a rated load state, the DC offset component of the inductor current IL1 when the power transistor 30 is turned on decreases.

[0170] <<<On-period of power transistor 30 when load 11 is in an overload state>>> Fig. 16 is a diagram showing the relationship between the drive voltage Vg and the inductor current IL1 when the load 11 is in a rated load or overload state. Note that in Fig. 16, similar to Figs. 14 and 15, the voltage Vcs is also depicted as a positive voltage, as is the inductor current IL1.

[0171] 16, when the load 11 is in an overload state, generally, in order to maintain the output voltage Vout, it is necessary to supply more power to the secondary side of the transformer 22. Therefore, when the load 11 is in an overload state, the DC offset component IL1b of the inductor current IL1 when the power transistor 30 is turned on increases compared to the DC offset component IL1a when the load 11 is in a rated load state.

[0172] As a result, the AC-DC converter 10 normally maintains the output voltage Vout at a target level. However, when the load 11 is in an overload state, the control IC 32 of this embodiment controls the AC-DC converter 10 to reduce the output voltage Vout.

[0173] Furthermore, when the power transistor 30 is turned on, the inductor current IL1 increases from the increased DC offset component IL1b at a gradient that depends on the inductance value of the primary coil L1 and the rectified voltage Vrec1. Note that this gradient remains approximately the same regardless of the state of the load 11.

[0174] Therefore, even if the voltage Vcs does not become the voltage Vrec_ocp when the load 11 is in a rated load state, the voltage Vcs becomes the voltage Vrec_ocp when the load 11 is in an overload state.

[0175] Furthermore, when the voltage Vcs reaches the voltage Vrec_ocp, the comparator 64 outputs a signal ocp to turn off the power transistor 30. As a result, the on-period of the power transistor 30 is reduced compared to the on-period when the load 11 is in the rated load state.

[0176] As a result, when the load 11 is in an overload state, the control IC 32 reduces the power supplied to the secondary side of the transformer 22, thereby reducing the output voltage Vout.

[0177] <<<Operation of AC-DC Converter 10 When Load 11 is in an Overload State>>> Fig. 17 is a diagram showing an example of the operation of the control IC 32 when the load 11 is in an overload state. In Fig. 17, similarly to Figs. 14 to 16, the voltage Vcs is also depicted as a positive voltage, similar to the inductor current IL1.

[0178] Furthermore, time t20 corresponds to time t10, and times t22 to t25 correspond to times t12 to t15. In this case, the output voltage Vout decreases, and therefore the feedback voltage Vfb becomes higher than the voltage Vref_off.

[0179] At time t21, when the voltage Vcs becomes the voltage Vref_ocp, the comparator 64 outputs a signal ocp to turn off the power transistor 30. As a result, the buffer 69 changes the level of the drive voltage Vg to the ground voltage level, thereby turning off the power transistor 30. Note that from time t25 onwards, the operation from time t20 to time t24 is repeated.

[0180] ===Summary=== The AC-DC converter 10 of this embodiment has been described above. The control IC 32 includes a detection circuit 65, a comparator 64, an oscillation circuit 66, and a drive signal output circuit 67. The oscillation circuit 66 also includes PMOS transistors 113 and 114, PMOS transistors 134 and 135, an adjustment circuit 132, and an output circuit 102. When the load 11 is in an overload state, the DC offset component of the inductor current IL1 increases, shortening the on-period of the power transistor 30. This reduces the voltage Vvf2 corresponding to the on-period of the drive signal Vq1. When the load 11 is in an overload state, the oscillation circuit 66 outputs an oscillation signal osc_out with a reduced oscillation frequency Fosc to reduce the output voltage Vout. When the oscillation frequency Fosc of the oscillation signal osc_out is reduced, the current Ib2 is reduced based on the voltage Vvf2, thereby achieving a drooping characteristic of the output voltage Vout with a simple circuit. This makes it possible to provide an integrated circuit that can suppress abrupt changes in the switching period of a transistor.

[0181] The control IC 32 includes a signal generating circuit 63 and variable resistors 112 and 133. The resistance values R1 and R2 of the variable resistors 112 and 133 are set discretely based on the signals F1 to F3 from the signal generating circuit 63. The current values of the currents Ib0 to Ib3 are set based on the resistance values R1 and R2 of the variable resistors 112 and 133. The oscillation circuit 66 outputs an oscillation signal osc_out determined according to the currents Ib0 to Ib3. Therefore, when the load 11 is in a rated load state, the oscillation frequency Fosc of the oscillation signal osc_out also becomes discrete. This makes it possible to suppress fluctuations in the period of the drive signal Vq1 when the output voltage Vout starts to decrease.

[0182] The variable resistors 112 and 133 are designed so that the current Ib0 is greater than the current Ib2 when the voltages V1 and V2 are at the same voltage level. This makes it possible to easily satisfy the maximum on-duty condition of the power transistor 30 in a forward power supply circuit.

[0183] The oscillation circuit 66 includes PMOS transistors 113 and 115. The output circuit 102 includes an adder circuit 200, a capacitor 203, and an oscillation signal output circuit 204. As a result, even if the load 11 is in an overload state, the voltage Vvf drops, and the current Ib2 decreases, the capacitor 203 is discharged. In other words, the current value corresponding to the current Ib1 can be set to the minimum value of the discharge current of the capacitor 203.

[0184] The detection circuit 65 includes a hysteresis comparator 90 and an output circuit 91. This makes it possible to detect that the load 11 is in an overload state based on either a drop in the output voltage Vout or an overcurrent flowing through the power transistor 30.

[0185] The adjustment circuit 132 includes a selection circuit 160 and an output circuit 161. As a result, even if the load 11 is in a light load or overload state, the oscillation frequency Fosc of the oscillation signal osc_out is reduced with a simple circuit. Furthermore, the configuration of the selection circuit 160 and the output circuit 161 can prevent the switching period of the power transistor 30 from changing suddenly.

[0186] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit thereof, and the present invention includes equivalents thereof. [Explanation of symbols]

[0187] 10 AC-DC converter 11 Load 20 Full wave rectifier circuit 21, 34, 36, 37, 39, 52, 203 Capacitors 22 Transformer 23, 38, 50, 51 Diodes 24 control blocks 30 Power transistor 31, 33, 35, 41, 62, 120-123, 141, 142, 153, 154, 190-193 Resistance 40 Phototransistor 53 Constant voltage circuit 54 Light-emitting diode 60 Low voltage protection circuit 61 Internal power supply 63 Signal generation circuit 64, 68, 70, 82 to 84, 220, 221, 300 Comparator 65 Detection circuit 66 Oscillator Circuit 67 Drive signal output circuit 69 buffers 71 One-shot circuit 72, 73, 222 SR flip-flop 74 AND elements 80 constant current source 81 Conversion circuit 90 Hysteresis Comparator 91,102,161 Output circuit 92,95 D flip-flops 93 OR element 94,172,205 Inverter 100,101 Current output circuit 110,140,180 Op-amps 111,152,181 NPN transistor 112,133 variable resistor 113~115,134,135,201 PMOS transistors 124~126,194~196,202,210~213 NMOS transistors 130,131 Voltage conversion circuit 132 Adjustment circuit 150 current source 151 PNP transistor 160 Selection circuit 170,171 Analog switches 200 Addition Circuit 204 Oscillation signal output circuit

Claims

1. An integrated circuit for switching a transistor in a power supply circuit that generates an output voltage from an input voltage, the integrated circuit comprising: a transformer including a primary coil, a secondary coil, and an auxiliary coil; and a transistor that controls a current flowing through the primary coil, a first terminal to which a first resistor is connected; a first detection circuit for detecting whether the load state of the power supply circuit is overloaded; a second detection circuit for detecting whether the current flowing through the transistor is an overcurrent; an oscillation circuit that outputs an oscillation signal having a period corresponding to a first resistance value of the first resistor; a drive signal output circuit that outputs a drive signal that turns on the transistor based on the oscillation signal and turns off the transistor based on a feedback voltage corresponding to the output voltage; Equipped with The drive signal output circuit When the current flowing through the transistor becomes an overcurrent, the drive signal for turning off the transistor is output. The oscillator circuit comprises: a first current source that outputs a first current based on the first resistance value; a second current source that outputs a second current based on the first resistance value; an adjustment circuit that adjusts the second current so as to reduce the second current when the load state becomes an overload state, based on a voltage corresponding to a period during which the transistor is on in the cycle of the drive signal; a first output circuit that outputs the oscillation signal having an on-period corresponding to a current value of the first current and an off-period corresponding to a current value of the second current; Including, Integrated circuit.

2. 10. The integrated circuit of claim 1, a conversion circuit that converts a voltage according to the first resistance value into a digital value; a second resistor having a second resistance value in response to the digital value; a third resistor having a third resistance value in response to the digital value; Including, The first current source is outputting the first current according to the second resistance value and a first voltage; The second current source is outputting the second current according to the third resistance value and the second voltage; Integrated circuit.

3. 3. The integrated circuit of claim 2, the level of the first voltage is equal to the level of the second voltage, The first current is greater than the second current. Integrated circuit.

4. The integrated circuit according to any one of claims 2 to 3, The oscillator circuit comprises: a third current source that outputs a third current; The first output circuit an adder circuit that adds the third current and the second current to obtain a fourth current; a capacitor that is charged with the first current during the on-period and discharged with the fourth current during the off-period; an oscillation signal output circuit that outputs the oscillation signal based on the voltage generated in the capacitor; Including, Integrated circuit.

5. The integrated circuit according to any one of claims 2 to 4, The first detection circuit a comparison circuit for comparing the feedback voltage with a third voltage for detecting an overload; a second output circuit that outputs a detection result indicating whether the load state is an overload state or not based on the comparison result of the comparison circuit or the detection result of the second detection circuit; Including, Integrated circuit.

6. An integrated circuit according to any one of claims 2 to 5, The adjustment circuit and when the load state is not a heavy load and the output voltage increases, the level of the second voltage is adjusted based on the feedback voltage so that the second current is reduced. Integrated circuit.

7. 7. An integrated circuit according to claim 6, comprising: The adjustment circuit a selection circuit that selects a voltage corresponding to the feedback voltage when the load state is not heavy, and selects a voltage corresponding to a period during which the transistor is on when the load state is heavy; a third output circuit that outputs, as the second voltage, a voltage selected by the selection circuit or a predetermined voltage such that the second current becomes smaller; Including, Integrated circuit.

8. A power supply circuit that generates an output voltage from an input voltage, a transformer including a primary coil, a secondary coil, and an auxiliary coil; a transistor for controlling a current flowing through the primary coil; an integrated circuit for switching the transistor; Equipped with The integrated circuit comprises: a first terminal to which a first resistor is connected; a first detection circuit for detecting whether the load state of the power supply circuit is overloaded; a second detection circuit for detecting whether the current flowing through the transistor is an overcurrent; an oscillation circuit that outputs an oscillation signal having a period corresponding to a first resistance value of the first resistor; a drive signal output circuit that outputs a drive signal that turns on the transistor based on the oscillation signal and turns off the transistor based on a feedback voltage corresponding to the output voltage; Equipped with The drive signal output circuit When the current flowing through the transistor becomes an overcurrent, the drive signal for turning off the transistor is output. The oscillator circuit comprises: a first current source that outputs a first current based on the first resistance value; a second current source that outputs a second current based on the first resistance value; an adjustment circuit that adjusts the second current so as to reduce the second current when the load state becomes an overload state, based on a voltage corresponding to a period during which the transistor is on in the cycle of the drive signal; a first output circuit that outputs the oscillation signal having an on-period corresponding to a current value of the first current and an off-period corresponding to a current value of the second current; Including, power circuit.

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