Ceramic electronic component, mounting substrate, and method for manufacturing ceramic electronic component

Abstract

To suppress the lowering of transverse intensity while achieving a low profile and suppressing the reduction of reliability.SOLUTION: According to one aspect, a ceramic electronic component includes: an element assembly having a dielectric; an internal electrode, a first surface, and a second surface opposite to the first surface; and an external electrode. The external electrode includes: a base layer that connects to the inner electrode, contains metal, and has a first end on outer side of the element on the second side; a plating layer laminated on the base layer and having a second end face that is layered with the first end face outside the element on the second face side; and a protective film covering the first face and the second end face.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a ceramic electronic component, a mounting substrate, and a method for manufacturing a ceramic electronic component. [Background technology]

[0002] As electronic devices become smaller and more sophisticated, the density of electronic components mounted on a mounting board is increasing. To reduce the mounting area on the mounting surface of IC (Integrated Circuit) chips, a method has been proposed in which the height of a multilayer ceramic capacitor is reduced and it is mounted on the side opposite the mounting surface of the IC chip (land-side capacitor (LSC)).

[0003] When the element body is thinned to reduce the height of the multilayer ceramic capacitor, the flexural strength of the multilayer ceramic capacitor decreases, which may cause the multilayer ceramic capacitor to crack when mounted.

[0004] In order to reduce the height of a multilayer ceramic capacitor without thinning the element body, Patent Document 1 discloses a configuration in which terminal electrodes are not substantially formed on the bottom surface of the element body, which is located on the opposite side in the stacking direction from the top surface of the element body.

[0005] In addition, Patent Document 2 discloses a configuration in which first and second external electrodes electrically connected to the first and second internal electrodes of a multilayer ceramic capacitor are arranged on both side surfaces and the bottom surface that form both end surfaces in the length direction of the ceramic body, but are not arranged on the top surface. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2020-21930 [Patent Document 2] Japanese Patent Application Publication No. 2017-228757 Summary of the Invention [Problem to be solved by the invention]

[0007] However, in the configurations disclosed in Patent Documents 1 and 2, the layer structure of the external electrodes is exposed on the surface on which the external electrodes are not formed, which makes it easy for moisture to penetrate into the interior through the exposed surface of the layer structure, easily causing insulation deterioration.

[0008] Therefore, an object of the present invention is to provide a ceramic electronic component, a mounting substrate, and a method for manufacturing a ceramic electronic component that can suppress a decrease in flexural strength, achieve a low profile, and suppress a decrease in reliability. [Means for solving the problem]

[0009] In order to solve the above problems, a ceramic electronic component according to one aspect of the present invention includes an element body having a dielectric, an internal electrode, a first surface, and a second surface opposite the first surface; a base layer connected to the internal electrode and containing a metal, the base layer having a first end surface outside the element body on the second surface side; a plating layer stacked on the base layer, the plating layer having a second end surface that forms a layer structure with the first end surface outside the element body on the second surface side; and an external electrode having a protective film that covers the first end surface and the second end surface.

[0010] Furthermore, in a ceramic electronic component according to one aspect of the present invention, the plating layer has a laminated structure of multiple plating layers having different metal components, and on the second surface side, end faces of the multiple plating layers form a layered structure outside the base body.

[0011] In addition, in the ceramic electronic component according to one aspect of the present invention, the outermost layer of the plating layers is a Sn plating layer.

[0012] In addition, in a ceramic electronic component according to an aspect of the present invention, the protective film is a Sn plating layer that is continuous with the outermost Sn plating layer of the plating layers.

[0013] In the ceramic electronic component according to one aspect of the present invention, the outermost Sn plating layer of the plating layers has a thickness of 5 μm or more, and the Sn plating layer of the protective film has a thickness of 5 μm or less.

[0014] In a ceramic electronic component according to an aspect of the present invention, the protective film is a metal film.

[0015] In a ceramic electronic component according to an aspect of the present invention, the metal is Sn, Cu, Ni, Ti, or Cr.

[0016] In a ceramic electronic component according to an aspect of the present invention, the protective film is a deposited film of a metal or an insulator.

[0017] In a ceramic electronic component according to an aspect of the present invention, the protective film is a resin coating film.

[0018] In a ceramic electronic component according to one aspect of the present invention, the first end face and the second end face are polished surfaces.

[0019] Furthermore, in a ceramic electronic component according to one aspect of the present invention, the base body includes a dielectric layer containing the dielectric, and first internal electrode layers and second internal electrode layers stacked alternately with the dielectric layer interposed therebetween, and the external electrode includes a first external electrode connected to the first internal electrode layer and extended to a third surface perpendicular to both the first surface and the second surface, and a second external electrode connected to the second internal electrode layer and extended to a fourth surface opposite the third surface.

[0020] Furthermore, according to a mounting substrate according to one aspect of the present invention, any of the ceramic electronic components described above is mounted on the mounting substrate via a solder layer, and the solder layer wets up onto the side surface of the external electrode while being spaced apart from the second surface of the element body.

[0021] Furthermore, a method for manufacturing a ceramic electronic component according to one embodiment of the present invention includes the steps of forming a base body having a dielectric and internal electrodes, applying a base material for the external electrodes to the side surfaces of the base body and four surfaces perpendicular to the side surfaces, firing the base material to form a base layer for the external electrodes, stacking a plating layer on the base layer, removing the base layer and plating layer on one of the four surfaces, and forming a protective film in the area from which the previous base layer and previous plating layer have been removed.

[0022] Furthermore, according to a method for manufacturing a ceramic electronic component according to one embodiment of the present invention, the base layer and plating layer on one of the four surfaces are removed by physically polishing the one of the four surfaces.

[0023] Furthermore, in the method for manufacturing a ceramic electronic component according to one aspect of the present invention, the protective film is formed by electrolytic plating of the same metal as the outermost layer of the plating layer.

[0024] In addition, in a method for manufacturing a ceramic electronic component according to one aspect of the present invention, the protective film is formed by a dry film formation method for a metal or an insulator. [Effects of the Invention]

[0025] According to the present invention, it is possible to reduce the height while suppressing a decrease in the bending strength, and also to suppress a decrease in reliability. [Brief explanation of the drawings]

[0026] [Figure 1] 1 is a perspective view showing an example of the configuration of a multilayer ceramic capacitor in accordance with a first embodiment. [Figure 2A] 2 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 cut in the longitudinal direction. [Figure 2B] 2 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 1 cut in the width direction at the position of an external electrode. [Figure 3A] 2 is a top view showing a configuration example of the multilayer ceramic capacitor of FIG. 1. FIG. [Figure 3B] 2 is a bottom view showing an example of the configuration of the multilayer ceramic capacitor of FIG. 1. FIG. [Figure 4] 3 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5A] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5B] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5C] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5D] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5E] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5F] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5G] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5H] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5I] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5J] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 5K] 2A to 2C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. [Figure 6A] 5 is a cross-sectional view showing an example of a method for removing external electrodes on the upper surface side of the element body of the multilayer ceramic capacitor in accordance with the first embodiment. FIG. [Figure 6B] 5 is a cross-sectional view showing an example of a method for removing external electrodes on the upper surface side of the element body of the multilayer ceramic capacitor in accordance with the first embodiment. FIG. [Figure 6C]5 is a cross-sectional view showing an example of a method for removing external electrodes on the upper surface side of the element body of the multilayer ceramic capacitor in accordance with the first embodiment. FIG. [Figure 7A] 5A to 5C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the second embodiment. [Figure 7B] 5A to 5C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the second embodiment. [Figure 7C] 5A to 5C are cross-sectional views illustrating a method for manufacturing the multilayer ceramic capacitor in accordance with the second embodiment. [Figure 8] FIG. 10 is a cross-sectional view showing an example of the configuration of a mounting substrate on which the multilayer ceramic capacitor in accordance with the third embodiment is mounted. [Figure 9] FIG. 10 is a perspective view showing an example of the configuration of the multilayer ceramic capacitor in accordance with a fourth embodiment. [Figure 10A] 10 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 9 cut in the longitudinal direction. [Figure 10B] 10 is a cross-sectional view of the multilayer ceramic capacitor of FIG. 9 cut in the width direction at the position of an external electrode. [Figure 11A] 10 is a top view showing an example of the configuration of the multilayer ceramic capacitor of FIG. [Figure 11B] 10 is a bottom view showing an example of the configuration of the multilayer ceramic capacitor of FIG. [Figure 12] FIG. 10 is a cross-sectional view showing an example of the configuration of the multilayer ceramic capacitor in accordance with a fifth embodiment. [Figure 13A] FIG. 10 is a cross-sectional view of the multilayer ceramic capacitor in accordance with a sixth embodiment, cut in the lengthwise direction. [Figure 13B] FIG. 10 is a cross-sectional view of the multilayer ceramic capacitor in accordance with the sixth embodiment, taken in the width direction at the position of the external electrodes. [Figure 14] FIG. 12 is a cross-sectional view showing an example of the configuration of a mounting substrate on which the multilayer ceramic capacitor in accordance with the seventh embodiment is mounted. [Figure 15] FIG. 13 is a perspective view showing an example of the configuration of a ceramic electronic component according to an eighth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the present invention, and not all combinations of features described in the embodiments are necessarily essential to the configuration of the present invention. The configuration of the embodiments may be modified or changed as appropriate depending on the specifications of the device to which the present invention is applied and various conditions (such as usage conditions and usage environment). The technical scope of the present invention is determined by the claims and is not limited by the individual embodiments described below. Furthermore, the drawings used in the following description may differ in scale and shape from the actual structure to make each configuration easier to understand.

[0028] (First embodiment) Fig. 1 is a perspective view showing an example of the configuration of the multilayer ceramic capacitor according to the first embodiment, Fig. 2A is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1 cut in the lengthwise direction, Fig. 2B is a cross-sectional view of the multilayer ceramic capacitor of Fig. 1 cut in the widthwise direction at the position of an external electrode, Fig. 3A is a top view showing the example of the configuration of the multilayer ceramic capacitor of Fig. 1, and Fig. 3B is a bottom view showing the example of the configuration of the multilayer ceramic capacitor of Fig. 1. In this embodiment, a multilayer ceramic capacitor is used as an example of a ceramic electronic component.

[0029] 1, 2A, 2B, 3A, and 3B, a multilayer ceramic capacitor 1A includes an element body 2 and external electrodes 6A and 6B. The element body 2 includes a laminate 2A, a lower cover layer 5A, and an upper cover layer 5B. The laminate 2A includes internal electrode layers 3A and 3B and a dielectric layer 4.

[0030] A lower cover layer 5A is provided on the lower layer of the laminate 2A, and an upper cover layer 5B is provided on the upper layer of the laminate 2A. The internal electrode layers 3A, 3B are alternately stacked with dielectric layers 4 interposed between them. While FIGS. 1, 2A, and 2B show an example in which a total of six internal electrode layers 3A, 3B are stacked, the number of stacked internal electrode layers 3A, 3B is not particularly limited. In this case, the shape of the element body 2 and the laminate 2A can be a substantially rectangular parallelepiped. In the following description, the direction in which the end faces of the element body 2 face each other may be referred to as the length direction DL, the direction in which the front and rear faces of the element body 2 face each other may be referred to as the width direction DW, and the direction in which the top and bottom faces of the element body 2 face each other may be referred to as the stacking direction (height direction) DS. The end faces (third and fourth faces) of the element body 2 are perpendicularly connected to the four faces of the element body 2 (the lower face (first face), upper face (second face), front face (fifth face), and rear face (sixth face)). In this case, the first and second surfaces face each other, the third and fourth surfaces face each other, and the fifth and sixth surfaces face each other. The first surface can be disposed at a position facing the mounting surface of a mounting board on which the multilayer ceramic capacitor 1A is mounted.

[0031] The element body 2 is chamfered along the ridge lines of the element body 2. In this case, the element body 2 has curved surfaces R where the corners are chamfered. The radius of curvature C of the curved surfaces R where the corners of the element body 2 are chamfered is preferably 5 μm or more and 20 μm or less, and more preferably 10 μm or more and 20 μm or less. Note that this radius of curvature C can be defined, for example, by the radius of curvature C of the curved surfaces R of the corners of the cross section of the element body 2 when the element body 2 is cut perpendicularly along the longitudinal direction DL.

[0032] Here, by setting the radius of curvature C of the curved surface R of the element body 2 to 10 μm or more, the amount of wrapping of the base layer 7 around the upper surface of the element body 2 along the curved surface R can be increased, improving the adhesion between the base layer 7 and the element body 2 and keeping the boundary of the base layer 7 on the upper surface of the element body 2 away from the solder used to mount the multilayer ceramic capacitor 1A. This makes it possible to prevent the base layer 7 from peeling off from the element body 2 due to the contraction stress of the solder used to mount the multilayer ceramic capacitor 1A. Furthermore, by setting the radius of curvature C of the curved surface R of the element body 2 to 20 μm or less, damage to the internal electrode layers 3A, 3B can be suppressed when the curved surface R with chamfered corners of the element body 2 is barrel polished.

[0033] The surface roughness Sa of the upper surface of the element body 2 is smaller than the surface roughness Sa of the lower surface of the element body 2. The surface roughness Sa of the upper surface of the element body 2 is preferably 0.20 μm or less. For example, the average surface roughness Sa of the lower surface of the element body 2 can be Sa > 0.50 μm, and the average surface roughness Sa of the upper surface of the element body 2 can be Sa < 0.20 μm. By setting the surface roughness Sa of the upper surface of the element body 2 to 0.20 μm or less, even when the upper surface of the element body 2 is polished, scratches on the upper surface of the element body 2 can be made less likely to occur, and cracks in the element body 2 originating from scratches can be suppressed.

[0034] The external electrodes 6A, 6B are formed on the element body 2 so as to face each other and be separated from each other in the longitudinal direction DL. Here, each external electrode 6A, 6B is formed continuously from the underside of the element body 2 to the end faces that connect perpendicularly to the underside via the curved surface R, and is not present on the upper side of the element body 2. Furthermore, each external electrode 6A, 6B may also be formed on the front and rear faces that face each other and are perpendicular to both the underside and end faces of the element body 2. The thickness of each external electrode 6A, 6B is, for example, 10 to 40 μm.

[0035] Here, by ensuring that the external electrodes 6A, 6B are not present on the upper surface side of the element body 2, the height of the multilayer ceramic capacitor 1A can be reduced without reducing the number of stacked internal electrode layers 3A, 3B, and LSC mounting can be achieved without reducing the capacitance of the multilayer ceramic capacitor 1A.

[0036] In the longitudinal direction DL, the internal electrode layers 3A and 3B are alternately arranged at different positions within the laminate 2A. In this case, the internal electrode layer 3A can be arranged on one end face side of the element body 2 relative to the internal electrode layer 3B, and the internal electrode layer 3B can be arranged on the other end face side of the element body 2 relative to the internal electrode layer 3A. An end of the internal electrode layer 3A is drawn to an end of the dielectric layer 4 at one end face side in the longitudinal direction DL of the element body 2 and connected to the external electrode 6A. An end of the internal electrode layer 3B is drawn to an end of the dielectric layer 4 at the other end face side in the longitudinal direction DL of the element body 2 and connected to the external electrode 6B. On the other hand, in the width direction DW of the element body 2, the ends of the internal electrode layers 3A, 3B are covered with the dielectric layer 4. In the width direction DW, the positions of the ends of the internal electrode layers 3A, 3B may be aligned.

[0037] The thickness of each of the internal electrode layers 3A, 3B and the dielectric layer 4 in the stacking direction DS can be within a range of 0.05 μm to 5 μm, for example, 0.3 μm. The material of the internal electrode layers 3A, 3B can be selected from metals such as Cu (copper), Ni (nickel), Ti (titanium), Ag (silver), Au (gold), Pt (platinum), Pd (palladium), Ta (tantalum), and W (tungsten), or may be an alloy containing these metals.

[0038] The material of the dielectric layer 4 can be, for example, mainly composed of a ceramic material having a perovskite structure. The main component may be contained at a ratio of 50 at% or more. The ceramic material of the dielectric layer 4 can be selected from, for example, barium titanate, strontium titanate, calcium titanate, magnesium titanate, barium strontium titanate, barium calcium titanate, calcium zirconate, barium zirconate, calcium titanate zirconate, and titanium oxide.

[0039] The material of lower cover layer 5A and upper cover layer 5B can be mainly composed of a ceramic material, for example. In this case, the main component of the ceramic material of lower cover layer 5A and upper cover layer 5B may be the same as the main component of the ceramic material of dielectric layer 4. The thickness of lower cover layer 5A and upper cover layer 5B is preferably 5 μm or more and 30 μm or less.

[0040] Each external electrode 6A, 6B includes an underlayer 7 formed on the element body 2 and a plating layer 9 laminated on the underlayer 7. The underlayers 7 are formed on the element body 2 so as to face each other while being separated from each other in the longitudinal direction DL. The underlayer 7 is formed continuously from the lower surface of the element body 2 across the curved surface R to the end surfaces, but is not formed on the upper surface of the element body 2. The underlayer 7 may also be formed continuously from the lower surface to the front and rear surfaces of the element body 2. The thickness of the underlayer 7 is preferably 3 μm or more and 6 μm or less. By setting the thickness of the underlayer 7 to 3 μm or more, the underlayer 7 can be formed continuously and stably from the lower surface to the end surfaces of the element body 2 so as to cover the curved surface R of the element body 2. Setting the thickness of the underlayer 7 to 6 μm or less prevents an increase in the thickness of each external electrode 6A, 6B, thereby enabling the multilayer ceramic capacitor 1A to have a low profile.

[0041] The metal used as the conductive material of the underlayer 7 may be primarily composed of a metal or alloy containing at least one selected from Cu, Fe (iron), Zn (zinc), Al (aluminum), Ni, Pt, Pd, Ag, Au, and Sn (tin). The underlayer 7 may also contain a common material containing a metal. The common material, when present in the underlayer 7 in the form of islands, can reduce the difference in thermal expansion coefficient between the element body 2 and the underlayer 7 and relieve stress on the underlayer 7. The common material may be, for example, a ceramic component that is the primary component of the dielectric layer 4. The underlayer 7 may also contain a glass component. The glass component, when present in the underlayer 7, can densify the underlayer 7. The glass component may be, for example, an oxide of Ba (barium), Sr (strontium), Ca (calcium), Zn, Al, Si (silicon), or B (boron).

[0042] The underlayer 7 may contain a metal component contained in the element body 2. This metal component is, for example, Mg (which may contain trace amounts of Ni, Cr, Sr, Al, Na, and Fe). In this case, the underlayer 7 may contain, for example, a compound containing Mg, Ni, and O as a compound of the metal used as the conductive material of the underlayer 7, the metal contained in the element body 2, and oxygen.

[0043] Here, the underlayer 7 is preferably composed of a sintered body of a coating film containing a dielectric material. This allows the underlayer 7 to be thickened while ensuring adhesion between the element body 2 and the underlayer 7, thereby ensuring the strength of each external electrode 6A, 6B and electrical continuity with the internal electrode layers 3A, 3B. The underlayer 7 may also include a sputtered film formed by sputtering on the sintered underlayer of the coating film on the lower surface to increase the electrode area and improve adhesion with a conductive material such as solder during mounting. In this case, the sputtered film does not contain the metal components contained in the element body 2 and can be formed of a metal or alloy such as Cu or Ni. Alternatively, the underlayer 7 may be formed solely from a sputtered film to reduce its thickness.

[0044] The plating layer 9 is formed continuously for each external electrode 6A, 6B so as to cover the base layer 7, and is not formed on the upper surface of the element body 2. The plating layer 9 is electrically connected to the internal electrode layers 3A, 3B via the base layer 7. The plating layer 9 is also electrically connected to the terminals of the mounting board via solder. To ensure the strength of each external electrode 6A, 6B and to ensure reliable electrical connection between the base layer 7 and the terminals of the mounting board, the thickness of the plating layer 9 is preferably 10 μm or more.

[0045] The plating layer 9 is primarily made of a metal such as Cu, Ni, Al, Zn, or Sn, or an alloy of two or more of these metals. The plating layer 9 may be made of a single metal or multiple metals. The plating layer 9 may have a three-layer structure, including a Cu plating layer 9A formed on the base layer 7, a Ni plating layer 9B formed on the Cu plating layer 9A, and a Sn plating layer 9C formed on the Ni plating layer 9B. The Cu plating layer 9A improves adhesion of the plating layer 9 to the base layer 7. The Ni plating layer 9B improves the heat resistance of the external electrodes 6A and 6B during soldering. The Sn plating layer 9C improves the solder wettability of the plating layer 9. For example, if the base layer 7 is 4.5 μm thick, the Cu plating layer 9A may be 3 μm thick, the Ni plating layer 9B may be 2 μm thick, and the Sn plating layer 9C may be 6 μm thick.

[0046] Here, on the top surface side of the element body 2, the end face (first end face) of the base layer 7 and the end face (second end face) of the plating layer 9 form a layered structure outside the element body 2. Also, on the top surface side of the element body 2, the end face of the Cu plating layer 9A, the end face of the Ni plating layer 9B, and the end face of the Sn plating layer 9C form a layered structure outside the base layer 7. In this case, the layered structure of the base layer 7, Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C stacked on the end face of the element body 2 is cut horizontally on the top surface side of the element body 2. At this time, the base layer 7 has an end face MU that protrudes outside the element body 2 on the top surface side. The Cu plating layer 9A has an end face MA that protrudes outside the end face MU on the top surface side of the element body 2. The Ni plating layer 9B has an end face MB that protrudes outside the end face MA on the top surface side of the element body 2. The Sn plating layer 9C has an end face MC that extends outward from the end face MB on the upper surface side of the element body 2.

[0047] The end faces MU, MA, MB, and MC can be located in the same plane including the top surface of the element body 2. In this case, the normal direction of each end face MU, MA, MB, and MC can be the same as the normal direction of the top surface of the element body 2. In this case, each end face MU, MA, MB, and MC can be a flat surface. Note that each end face MU, MA, MB, and MC may be a polished surface, a cut surface, or an etched surface. Furthermore, the height of the end faces MU, MA, MB, and MC when the bottom surface of the element body 2 is used as the reference may be lower than the height of the top surface of the element body 2.

[0048] The underlayer 7 also wraps around the curved surface R on the top side of the element body 2, with the end face MU reaching the top surface of the element body 2. The amount of wrapping of the underlayer 7 on the top side of the element body 2 can be made equal to the radius of curvature C of the curved surface R on the top side of the element body 2. Alternatively, as shown in FIG. 3A , the underlayer 7 may wrap around the ridges of the front and rear surfaces of the element body 2 inward toward the inside of the element body 2. The amount of wrapping can be changed by the magnitude of the radius of curvature C of the curved surface R or the thickness of each layer of the external electrodes 6A, 6B. Furthermore, the Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C also wrap around the underlayer 7 so that their end faces MA, MB, and MC reach the top surface of the element body 2. However, unlike FIG. 1 , the Sn plating layer 9C may extend outside the element body 2, and the length of the end face MC in the longitudinal direction DL may be longer than the length in the longitudinal direction DL of the Sn plating layer 9C on the end face side of the element body 2. In this case, the Sn plating layer 9C can prevent the solder from wetting up onto the element body 2 during mounting, depending on whether it spreads outward from the element body 2.

[0049] Here, the ends of the base layer 7 are exposed from the Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C on the upper surface side of the element body 2. At this time, the layer structure of the external electrodes 6A, 6B is exposed to the outside of the multilayer ceramic capacitor 1A. Meanwhile, the ends of the base layer 7 are covered with the Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C on the lower surface side of the element body 2.

[0050] Here, by providing end faces MU, MA, MB, and MC on the underlayer 7, Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C on the upper surface of the element body 2, respectively, it is possible to fabricate a multilayer ceramic capacitor 1A without external electrodes 6A and 6B on the upper surface of the element body 2, without fracture of the external electrodes 6A and 6B. This prevents a decrease in the flexural strength of the multilayer ceramic capacitor 1A while achieving a low profile. It also prevents non-uniformity in the cross-sectional shapes of the external electrodes 6A and 6B on the upper surface of the element body 2, thereby preventing a decrease in the adhesive strength between the external electrodes 6A and 6B and the element body 2. Furthermore, if the external electrodes 6A and 6B fracture, plating will precipitate in the height direction from the fractured surfaces of the external electrodes 6A and 6B. On the other hand, the multilayer ceramic capacitor 1A does not fracture the external electrodes 6A and 6B, so it is possible to reliably achieve a low profile.

[0051] Furthermore, by providing the base layer 7, Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C with end faces MU, MA, MB, and MC, respectively, on the top surface side of the element body 2, it is possible to maintain uniformity in the film thickness of the Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C from the end face side to the cut surface on the top surface side of the element body 2. This makes it possible to prevent a decrease in the strength of each external electrode 6A, 6B, and also to prevent a decrease in conductivity between the base layer 7 and the terminals of the mounting board.

[0052] Furthermore, the entire upper surface of the multilayer ceramic capacitor 1A can be flattened by positioning the end faces MU, MA, MB, and MC in the same plane including the upper surface of the element body 2. This eliminates unevenness on the upper surface of the multilayer ceramic capacitor 1A, stabilizes the posture of the multilayer ceramic capacitor 1A when it is picked up by the nozzle of the mounter, and reduces mounting errors.

[0053] Furthermore, by wrapping the base layer 7 around the curved surface R on the upper surface of the element body 2, it is possible to improve the adhesion between the base layer 7 and the element body 2, and to distance the boundary of the base layer 7 on the upper surface of the element body 2 from the solder used to mount the multilayer ceramic capacitor 1A. This makes it possible to prevent the base layer 7 from peeling off from the element body 2 due to the contraction stress of the solder used to mount the multilayer ceramic capacitor 1A.

[0054] Each of the external electrodes 6A, 6B is provided with a protective film 10 covering the end faces MU, MA, MB, and MC. The protective film 10 is, for example, a metal film. The material of this metal film is preferably Sn, Cu, Ni, Ti, or Cr. The protective film 10 is preferably a solderable metal film.

[0055] The protective film 10 may be a Sn-plated layer. The protective film 10 may be, for example, an alloy-plated layer containing Sn and Zn. In this case, the Sn-plated layer used as the protective film 10 may cover the end faces MU, MA, MB, and MC and the Sn-plated layer 9C. The Sn-plated layer used as the protective film 10 may be continuous with the Sn-plated layer 9C. The thickness of the Sn-plated layer 9C is preferably 5 μm or more to ensure reliability during solder mounting. The thickness of the Sn-plated layer used as the protective film 10 is preferably 5 μm or less to prevent an increase in the height of the multilayer ceramic capacitor 1A.

[0056] Here, by providing a protective film 10 on each external electrode 6A, 6B that covers the end faces MU, MA, MB, and MC, the end faces MU, MA, MB, and MC can be prevented from being exposed to the outside. Therefore, even when the external electrodes 6A, 6B are provided with end faces MU, MA, MB, and MC, it is possible to prevent moisture from penetrating into the interior through the end faces MU, MA, MB, and MC, and to prevent deterioration of the insulation between the internal electrode layers 3A and 3B. As a result, it is possible to reduce the height of the multilayer ceramic capacitor 1A while preventing a decrease in its flexural strength and to prevent a decrease in reliability.

[0057] The external dimensions of the multilayer ceramic capacitor 1A may be, for example, length > width > height, or length > width = height. In this case, in order to reduce the height of the multilayer ceramic capacitor 1A, the height of the multilayer ceramic capacitor 1A is preferably 150 μm or less. The height of the multilayer ceramic capacitor 1A is equal to the thickness of the multilayer ceramic capacitor 1A from the lower surfaces of the external electrodes 6A, 6B to the upper surface of the element body 2.

[0058] By setting the height of the multilayer ceramic capacitor 1A to 150 μm or less, the height of the multilayer ceramic capacitor 1A can be made smaller than the diameter of the solder balls on the mounting substrate. Therefore, the multilayer ceramic capacitor 1A can be mounted on the solder ball-formed side of the mounting substrate, and the mounting substrate can be mounted on a motherboard via the solder balls. As a result, the multilayer ceramic capacitor 1A can be disposed on the backside of a semiconductor chip placed on the mounting substrate, enabling the multilayer ceramic capacitor 1A to be mounted in close proximity to the semiconductor chip and increasing the mounting area on the mounting surface of the semiconductor chip. This allows for an improved mounting density of the semiconductor chips mounted on the mounting substrate while effectively eliminating noise from the semiconductor chips.

[0059] For example, if the thickness of each of the external electrodes 6A, 6B is 15 μm, the required height of the multilayer ceramic capacitor 1A is 80 μm. In this case, if the thickness of the protective film 10 is 5 μm, the thickness of the element body 2 can be 50 μm or more and 60 μm or less. Alternatively, if the required height of the multilayer ceramic capacitor 1A is 60 μm, if the thickness of the protective film 10 is 5 μm, the thickness of the element body 2 can be 30 μm or more and 40 μm or less. This makes it possible to reduce the height of the multilayer ceramic capacitor 1A while suppressing a decrease in the flexural strength of the multilayer ceramic capacitor 1A and improve the resistance of the multilayer ceramic capacitor 1A to impacts during mounting and various stresses after mounting.

[0060] Fig. 4 is a flowchart showing the method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment, and Fig. 5A to Fig. 5K are cross-sectional views showing the method for manufacturing the multilayer ceramic capacitor in accordance with the first embodiment. Note that Fig. 5C to Fig. 5K show an example in which three layers of internal electrode layers 3A and 3B are alternately stacked with dielectric layers 4 interposed therebetween.

[0061] In S1 of FIG. 4, an organic binder and an organic solvent serving as a dispersant and a molding aid are added to a dielectric material powder, which is then pulverized and mixed to produce a mud-like slurry. The dielectric material powder may include, for example, ceramic powder. The dielectric material powder may also include additives. The additives may be, for example, oxides or glass of Mg, Mn, V, Cr, Y, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Co, Ni, Li, B, Na, K, or Si. The organic binder may be, for example, polyvinyl butyral resin or polyvinyl acetal resin. The organic solvent may be, for example, ethanol or toluene.

[0062] Next, as shown in S2 of Fig. 4 and Fig. 5A, a slurry containing ceramic powder is applied to a carrier film in sheet form and dried to produce a green sheet 24. The carrier film is, for example, a PET (polyethylene terephthalate) film. The slurry can be applied using a doctor blade method, a die coater method, a gravure coater method, or the like.

[0063] Next, as shown in S3 of FIG. 4 and FIG. 5B, the conductive paste for internal electrodes is applied in a predetermined pattern to a green sheet 24 of a layer that will form the internal electrode layers 3A and 3B among the multiple green sheets, thereby forming the internal electrode pattern 23. At this time, multiple internal electrode patterns 23 separated in the longitudinal direction of the green sheet 24 can be formed on one green sheet 24. The conductive paste for internal electrodes contains powder of the metal used as the material for the internal electrode layers 3A and 3B. For example, if the metal used as the material for the internal electrode layers 3A and 3B is Ni, the conductive paste for internal electrodes contains Ni powder. The conductive paste for internal electrodes also contains a binder, a solvent, and, if necessary, an auxiliary agent. The conductive paste for internal electrodes may contain a ceramic material, which is the main component of the dielectric layer 4, as a co-material. The conductive paste for internal electrodes can be applied using a screen printing method, an inkjet printing method, a gravure printing method, or the like.

[0064] Next, as shown in S4 of Fig. 4 and Fig. 5C, a laminated block is produced by stacking a plurality of green sheets 24 on which the internal electrode pattern 23 has been formed and green sheets 25A, 25B for outer layers on which the internal electrode pattern 23 has not been formed in a predetermined order. The thickness of the green sheets 25A, 25B for outer layers is greater than the thickness of the green sheet 24 on which the internal electrode pattern 23 has been formed. At this time, the green sheets 24 are stacked so that the internal electrode patterns 23A, 23B of adjacent green sheets 24 in the stacking direction are alternately shifted in the longitudinal direction of the green sheets 24. Also, there are portions where only the internal electrode pattern 23A is stacked in the stacking direction, portions where the internal electrode patterns 23A, 23B are alternately stacked in the stacking direction, and portions where only the internal electrode pattern 23B is stacked in the stacking direction.

[0065] Next, as shown in S5 and 5D of Fig. 4, the laminated block obtained in the molding step S4 of Fig. 4 is pressed to pressure-bond the green sheets 24, 25A, and 25B. As a method for pressing the laminated block, for example, a method of sandwiching the laminated block between resin films and isostatically pressing can be used.

[0066] Next, as shown in S6 of Fig. 4 and Fig. 5E, the pressed laminated block is cut and separated into rectangular parallelepiped elements. The laminated block is cut at a portion where only the internal electrode patterns 23A are stacked in the stacking direction and at a portion where only the internal electrode patterns 23B are stacked in the stacking direction. For example, a method such as blade dicing can be used to cut the laminated block.

[0067] At this time, as shown in FIG. 5F, the singulated element body 2" has internal electrode layers 3A and 3B stacked alternately with dielectric layers 4 interposed therebetween, and cover layers 5A and 5B are formed on the bottom and top layers. The internal electrode layer 3A is drawn out from the surface of the dielectric layer 4 at one end face of the element body 2", and the internal electrode layer 3B is drawn out from the surface of the dielectric layer 4 at the other end face of the element body 2". Note that FIG. 4F shows one singulated element body of FIG. 4E enlarged in the length direction.

[0068] Next, as shown in S7 of Fig. 4, the binder contained in the element body 2'' that was singulated in S6 of Fig. 4 is removed. To remove the binder, the element body 2'' is heated in an N2 atmosphere at about 350°C, for example.

[0069] Next, as shown in S8 of FIG. 4 and FIG. 5G, the element body 2″ is chamfered to form an element body 2″ having curved surfaces R with a curvature radius C at the corners of the element body 2″. The element body 2″ can be chamfered by, for example, barrel polishing.

[0070] Next, as shown in S9 of FIG. 4, a conductive paste for the base layer is applied to both end faces of the element body 2′ chamfered in S8 of FIG. 4 and the four peripheral faces (top, bottom, front, and rear) of each end face, and then dried. The conductive paste for the base layer can be applied by, for example, a dipping method. The conductive paste for the base layer contains a powder or filler of a metal used as the conductive material for the base layer 7. For example, if the metal used as the conductive material for the base layer 7 is Ni, the conductive paste for the base layer contains Ni powder or filler. The conductive paste for the base layer also contains, as a co-material, a ceramic component that is the main component of the dielectric layer 4. For example, the conductive paste for the base layer contains particles of an oxide ceramic (e.g., having a D50 particle size of 0.8 μm to 4 μm) whose main component is barium titanate as a co-material. The conductive paste for the base layer also contains a binder and a solvent.

[0071] Next, as shown in S10 of Fig. 4 and Fig. 5H, the element body 2' to which the conductive paste for the base layer has been applied in S9 of Fig. 4 is fired to integrate the internal electrode layers 3A, 3B and the dielectric layer 4, and to form an element body 7' integrated with the element body 2'. The element body 2' and the conductive paste for the base layer are fired, for example, in a firing furnace at 1000 to 1400°C for 10 minutes to 2 hours. When a base metal such as Ni or Cu is used for the internal electrode layers 3A, 3B, firing can be performed in a reducing atmosphere in the firing furnace to prevent oxidation of the internal electrode layers 3A, 3B.

[0072] Next, as shown in S11 of FIG. 4 and FIG. 5I, a Cu plating layer 9A', a Ni plating layer 9B', and a Sn plating layer 9C' are sequentially formed on the base layer 7'. At this time, a multilayer ceramic capacitor 1A' is produced in which the external electrodes 6A', 6B' are located on the bottom and top surfaces of the element body 2'. In forming the plating layers 9', for example, the Cu plating layer 9A', the Ni plating layer 9B', and the Sn plating layer 9C' can be sequentially formed. At this time, the element body 2' on which the base layer 7' has been formed is placed in a barrel together with a plating solution, and the barrel is rotated while current is applied, thereby forming the plating layer 9'.

[0073] Next, as shown in S12 of FIG. 4 and FIG. 5J, the upper surface of the element body 2′ is physically polished to remove the underlayer 7′, Cu plating layer 9A′, Ni plating layer 9B′, and Sn plating layer 9C′ from the upper surface of the element body 2′. At this time, a multilayer ceramic capacitor 1A″ is produced in which the underlayer 7, Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C are formed on the element body 2 whose upper surface has been polished. Here, the surface roughness Sa of the upper surface of the element body 2 on which the underlayer 7, Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C are formed can be smaller than the surface roughness Sa of the lower surface of the element body 2. At this time, unlike FIG. 5J, the Sn plating layer 9C may extend outside the element body 2.

[0074] Here, when manufacturing the multilayer ceramic capacitor 1A" of FIG. 5J, the multilayer ceramic capacitor 1A' of FIG. 5I can be used. In this case, the manufacturing process of the multilayer ceramic capacitor 1A" of FIG. 5J can be directly used for manufacturing the multilayer ceramic capacitor 1A' of FIG. 5I. Therefore, in order to manufacture the multilayer ceramic capacitor 1A" of FIG. 5J, it is sufficient to add the step S12 of FIG. 4 to the manufacturing line for the multilayer ceramic capacitor 1A' of FIG. 5I, and there is no need to modify the manufacturing line for the multilayer ceramic capacitor 1A' of FIG. 5I.

[0075] Furthermore, the thickness of the element bodies 2, 2', 2'' can be increased while the height of the multilayer ceramic capacitor 1A'' is reduced. This prevents the element bodies 2, 2', 2'' from becoming difficult to handle, and stabilizes the production of the multilayer ceramic capacitor 1A''.

[0076] Next, as shown in S13 of FIG. 4 and FIG. 5K, a protective film 10 is formed to cover the end faces MU, MA, MB, and MC of the multilayer ceramic capacitor 1A". The protective film 10 may be formed, for example, by electrolytic plating of Sn. The Sn plating layer formed as the protective film 10 is also formed as a solderable exterior plating layer on the side and lower surfaces of the Sn plating layer 9C on the upper surface of which the end face MC is formed. At this time, the multilayer ceramic capacitor 1A" is placed in a barrel together with a plating solution, and the barrel is rotated while current is applied, thereby manufacturing the multilayer ceramic capacitor 1A on which the protective film 10 is formed.

[0077] Here, when manufacturing the multilayer ceramic capacitor 1A of FIG. 5K, the multilayer ceramic capacitor 1A" of FIG. 5J can be used. In this case, the manufacturing process of the multilayer ceramic capacitor 1A of FIG. 5K can be directly applied to the manufacturing process of the multilayer ceramic capacitor 1A" of FIG. 5J.

[0078] Furthermore, the thickness of the element bodies 2, 2', and 2'' can be increased while the height of the multilayer ceramic capacitor 1A is reduced. This prevents the element bodies 2, 2', and 2'' from becoming difficult to handle, and stabilizes the production of the multilayer ceramic capacitor 1A.

[0079] Furthermore, by forming the protective film 10 based on Sn electroplating, even when the protective film 10 is formed on the side and underside of the Sn plating layer 9C having the end face MC formed on the upper side, the solder wettability of each external electrode 6A, 6B can be ensured, and problems with the mounting of the multilayer ceramic capacitor 1A can be prevented.

[0080] 6A to 6C are cross-sectional views showing an example of a method for removing the external electrodes on the upper surface side of the element body of the multilayer ceramic capacitor in accordance with the first embodiment. In FIG. 6A, an adhesive sheet 42 is attached to one side of a flat substrate 41. Then, a plurality of multilayer ceramic capacitors 1A' shown in FIG. 5I are arranged on the adhesive sheet 42, and the lower surfaces of the external electrodes 6A', 6B' are attached to the adhesive sheet 42. At this time, in order to improve the holding ability of the multilayer ceramic capacitor 1A' on the adhesive sheet 42, the lower surfaces of the external electrodes 6A', 6B' may be sunk into the adhesive sheet 42. The substrate 41 may be, for example, a glass substrate. The adhesive sheet 42 may be, for example, a double-sided adhesive foam release sheet or a UV release tape.

[0081] 6B, an abrasive material 44 such as a file is attached to one side of a flat base 43. The abrasive material 44 can be attached to the base 43 using tape or the like. The base 43 can be, for example, a glass plate.

[0082] Then, the substrate 41 is placed on the base 43 so that the upper surfaces of the external electrodes 6A', 6B' of the multilayer ceramic capacitor 1A' arranged on the adhesive sheet 42 are pressed against the abrasive 44. Here, a load WT can be applied to the substrate 41 so that the upper surfaces of the external electrodes 6A', 6B' are pressed against the abrasive 44 under predetermined conditions.

[0083] Then, the upper surfaces of the external electrodes 6A', 6B' are physically polished based on the minute oscillation VB of at least one of the substrate 41 and the base 43, thereby removing the upper surfaces of the external electrodes 6A', 6B' from the element body 2'. At this time, the upper surface of the element body 2' is also polished, and the surface roughness Sa of the upper surface of the element body 2' can be reduced.

[0084] As a result, as shown in FIG. 6C, a multilayer ceramic capacitor 1A is manufactured in which an underlayer 7, a Cu plating layer 9A, a Ni plating layer 9B and a Sn plating layer 9C are formed on the element body 2 whose upper surface side is polished.

[0085] 6B, only the external electrodes 6A', 6B' are polished, and the hard element body 2' containing ceramic is hardly polished at all, so the curved surface R of the element body 2 after polishing is maintained almost unchanged. For example, when the external electrodes 6A', 6B' and the element body 2' are polished under the same conditions, the polishing rate of the element body 2' relative to the polishing rate of the external electrodes 6A', 6B' (amount removed per unit time) is 1 / 20 to 25. In this case, even if the element body 2' is polished under conditions that polish only the external electrodes 6A', 6B' by 15 μm, only 0.50 to 0.75 μm can be removed.

[0086] The polishing grains and weight WT are adjusted taking into consideration the strength of the multilayer ceramic capacitor 1A'. Experimental verification has shown that the polishing grains should be fine grains of #2000 to #6000, and the weight per multilayer ceramic capacitor 1A' should preferably be set at 1 to 5 g / piece. In addition to these conditions, the polishing oscillation speed and processing time are adjusted based on the thickness (amount polished) and layer structure (hardness) of the external electrodes 6A', 6B' to be polished.

[0087] The polishing of the external electrodes 6A', 6B' may be performed by blast polishing or CMP (Chemical Mechanical Polishing) in addition to mechanically scraping off the upper surfaces of the external electrodes 6A', 6B'.

[0088] (Second embodiment) Figures 7A to 7C are cross-sectional views showing a method for manufacturing a multilayer ceramic capacitor in accordance with the second embodiment. Figures 7A to 7C show a portion of the external electrodes, which differs from the manufacturing method shown in Figures 5I to 5K.

[0089] 7A, a plating layer 9′ in which a Sn plating layer 9C1 is provided is formed in place of the Sn plating layer 9C′ in FIG. 5I. At this time, the thickness of the Sn plating layer 9C1 is made thinner than the Sn plating layer 9C′ by the thickness TC of the Sn plating layer 9C2 when the Sn plating layer 9C2 is formed as the protective film 10 in the step of FIG. 7C.

[0090] Next, as shown in FIG. 7B, the upper surface of the element body 2′ is physically polished to remove the base layer 7′, Cu plating layer 9A′, Ni plating layer 9B′, and Sn plating layer 9C1 on the upper surface of the element body 2′, thereby forming end faces MU, MA, MB, and MC.

[0091] Next, as shown in FIG. 7C , the Sn plating layer 9C2 used as the protective film 10 is formed by electroplating Sn. At this time, the Sn plating layer 9C2 covers not only the end faces MU, MA, MB, and MC but also the side and underside of the Sn plating layer 9C1. Therefore, the sum of the thicknesses of the Sn plating layer 9C1 and the Sn plating layer 9C2 on the Ni plating layer 9B can be made equal to the thickness of the Sn plating layer 9C' shown in FIG. 5I. As a result, even when the protective film 10 is formed by electroplating Sn, the thickness of the Sn plating layer on the Ni plating layer 9B can be set to the intended target. Furthermore, by making the thickness of the Sn plating layer 9C1 thinner than the Sn plating layer 9C', the protrusion of the Sn plating layer 9C2 on the end face MC can be reduced, preventing it from interfering with the reduction in the height of the multilayer ceramic capacitor.

[0092] (Third embodiment) FIG. 8 is a cross-sectional view showing an example of the configuration of a mounting substrate on which the multilayer ceramic capacitor in accordance with the third embodiment is mounted. 8, land electrodes 42A, 42B, 44A, and 44B are formed on the back surface of a mounting substrate 41. The multilayer ceramic capacitor 1A is connected to the land electrodes 42A and 42B via solder layers 43A and 43B that are respectively attached to the plating layers 9 of the external electrodes 6A and 6B. At this time, the solder layers 43A and 43B wet up onto the end faces of the external electrodes 6A and 6B while remaining separated from the upper surface of the element body 2. Solder balls 47A and 47B are formed on the land electrodes 44A and 44B on the back surface of the mounting substrate 41.

[0093] On the other hand, a semiconductor chip (not shown) is mounted on the front surface of the mounting substrate 41. This semiconductor chip may be a microprocessor, a semiconductor memory, an FPGA (Field-Programmable Gate Array), or an ASIC (Application Specific Integrated Circuit).

[0094] Land electrodes 46A and 46B are formed on the back surface of mounting substrate 45. Mounting substrates 41 and 45 are connected to each other via solder balls 47A and 47B. Mounting substrate 45 can be used as a motherboard on which mounting substrate 41 is mounted.

[0095] The mounting substrates 41 and 45 are spaced apart by a constant distance via the solder balls 47A and 47B. At this time, a resin 48 is provided between the mounting substrates 41 and 45 to seal the multilayer ceramic capacitor 1A. The resin 48 is, for example, an epoxy resin. After the mounting substrates 41 and 45 are connected to each other via the solder balls 47A and 47B, the resin 48 may be injected between the mounting substrates 41 and 45 and allowed to harden. At this time, the resin 48 covers the multilayer ceramic capacitor 1A, the solder layers 43A and 43B, and the solder balls 47A and 47B, and is in close contact with the upper surface of the element body 2.

[0096] Here, by mounting the multilayer ceramic capacitor 1A on the back surface side of the mounting substrate 41, the multilayer ceramic capacitor 1A can be arranged on the back surface side of the semiconductor chip mounted on the front surface side of the mounting substrate 41. This makes it possible to mount the multilayer ceramic capacitor 1A close to the semiconductor chip mounted on the front surface side of the mounting substrate 41, and makes it possible to effectively remove noise that is applied to the semiconductor chip.

[0097] Furthermore, by making the height of the multilayer ceramic capacitor 1A 150 μm or less, the multilayer ceramic capacitor 1A can be accommodated in the gap between the mounting substrates 41 and 45 connected to each other via the solder balls 47A and 47B, and the multilayer ceramic capacitor 1A can be placed on the back side of the semiconductor chip placed on the front side of the mounting substrate 41.

[0098] Furthermore, the layered structure of the base layer 7, Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C at the end faces of the upper surface of the element body 2 makes it possible to reduce the height of the multilayer ceramic capacitor 1A while suppressing a decrease in its flexural strength, and to maintain uniformity in the film thickness of the Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C. This makes it possible to mount the multilayer ceramic capacitor 1A on the mounting substrate 41 while preventing cracks in the multilayer ceramic capacitor 1A, and to suppress a decrease in conductivity between the base layer 7 and the land electrodes 42A and 42B.

[0099] Furthermore, by providing the protective film 10 covering the end faces MU, MA, MB, and MC on each of the external electrodes 6A and 6B, it is possible to prevent the end faces MU, MA, MB, and MC from coming into direct contact with the resin 48. This makes it possible to prevent moisture from penetrating into the interior through the end faces MU, MA, MB, and MC, and to suppress insulation deterioration of the multilayer ceramic capacitor 1A.

[0100] (Fourth embodiment) FIG. 9 is a perspective view showing an example of the configuration of the multilayer ceramic capacitor according to the fourth embodiment, FIG. 10A is a cross-sectional view of the multilayer ceramic capacitor of FIG. 9 cut in the length direction, FIG. 10B is a cross-sectional view of the multilayer ceramic capacitor of FIG. 9 cut in the width direction at the position of an external electrode, FIG. 11A is a top view of the example of the configuration of the multilayer ceramic capacitor of FIG. 9, and FIG. 11B is a bottom view of the example of the configuration of the multilayer ceramic capacitor of FIG. 9.

[0101] 9, 10A, 10B, 11A, and 11B, the multilayer ceramic capacitor 1B includes a protective film 11 instead of the protective film 10 of the multilayer ceramic capacitor 1A of FIG. 1. The protective film 11 covers the end faces MU, MA, MB, and MC. The protective film 11 may extend to the upper surface side of the element body 2. The protective film 11 is, for example, a deposited film of a metal or an insulator. Examples of the metal used for the protective film 11 include Sn, Cu, Ni, Ti, and Cr. Examples of the insulator used for the protective film 11 include silicon oxide, silicon nitride, and aluminum oxide. The deposition method of the protective film 11 may be a dry film formation method such as sputtering or vapor deposition. The protective film 11 may also be a coated film of a resin. The thickness of the protective film 11 is preferably 5 μm or less, and more preferably 3 μm or less.

[0102] If the material of the protective film 11 is metal, the protective film 11 can be deposited while masking the center of the element body 2 across the width direction DW, and the protective film 11 can be separated for each external electrode 6A, 6B. If the material of the protective film 11 is an insulator, it is not necessarily necessary to separate the protective film 11 for each external electrode 6A, 6B, and the protective film 11 may be formed on the end faces MU, MA, MB, MC and the entire upper surface of the element body 2. In this case, the protective film 11 is formed so as not to wrap around to the underside of the element body 2.

[0103] Here, by forming the protective film 11 from a deposited film of a metal or an insulator, it is possible to reduce the thickness of the protective film 11 while improving the uniformity of the film thickness of the protective film 11. As a result, it is possible to improve the reliability without interfering with the reduction in the height of the multilayer ceramic capacitor 1B.

[0104] In addition to depositing the protective film 11 by a dry film formation method such as sputtering or vapor deposition, a method of spraying a metal, ceramic, or resin by thermal spraying may also be used. Alternatively, an inorganic or resin-based impregnating material may be impregnated into the gaps between the end faces MU, MA, MB, and MC to seal the gaps between the end faces MU, MA, MB, and MC.

[0105] (Fifth embodiment) FIG. 12 is a cross-sectional view showing an example of the configuration of the multilayer ceramic capacitor in accordance with the fifth embodiment. In FIG. 12, the multilayer ceramic capacitor 1C has an element body 2C instead of the element body 2 of the multilayer ceramic capacitor 1A of FIG. 2A. In the multilayer ceramic capacitor 1C, the center of the upper surface of the element body 2C is raised relative to the end faces MU, MA, MB, and MC. In this case, the cross-sectional shape of the upper surface of the element body 2CB along the longitudinal direction DL can be an arc or arch shape. The amount of rise HS of the center of the upper surface of the element body 2C relative to the end faces MU, MA, MB, and MC is preferably 3 μm or less.

[0106] In this case, by changing the fixing state of the multilayer ceramic capacitor 1A' (such as the adhesive state of the adhesive sheet 42 in FIG. 6A) when polishing the external electrodes 6A', 6B', the tilt of the element body 2' on the adhesive sheet 42 can be periodically changed based on the minute oscillation VB in FIG. 6B. In this polishing, the amount of polishing at the end portions of the upper surface of the element body 2' can be made greater than the amount of polishing at the center, and the center of the element body 2C can also be made into a gently rising arc shape. In this case, the positions of the external electrodes 6A, 6B are lower than the center of the element body 2C. In this case, the center of the element body 2C may be flat.

[0107] Here, by raising the center of the top surface of the element body 2C, the flexural strength of the multilayer ceramic capacitor 1C can be improved. Furthermore, as part of the manufacturing process after the polishing process, the multilayer ceramic capacitor 1C may be inspected and taped by machine. In this case, even if the orientation of the multilayer ceramic capacitor 1C is random and the top surface of the element body 2C faces downward, the end faces MU, MA, MB, and MC of the external electrodes 6A and 6B can be prevented from being rubbed by various parts (such as the feeder surface) of the inspection and taping equipment. Therefore, even if the layer structure of the external electrodes 6A and 6B is exposed on the top surface of the element body 2C, damage to the layer structure of the external electrodes 6A and 6B can be prevented.

[0108] Furthermore, by making the thickness of the protective film 10 covering the end faces MU, MA, MB, and MC equal to or less than the protrusion amount HS at the center of the upper surface of the element body 2C, it is possible to prevent an increase in the height of the multilayer ceramic capacitor 1C when mounted, even when the protective film 10 is provided on each of the external electrodes 6A and 6B. This makes it possible to improve the flexural strength and reliability without interfering with the reduction in height of the multilayer ceramic capacitor 1C.

[0109] (Sixth embodiment) FIG. 13A is a cross-sectional view of the multilayer ceramic capacitor in accordance with the sixth embodiment taken in the lengthwise direction, and FIG. 13B is a cross-sectional view of the multilayer ceramic capacitor in accordance with the sixth embodiment taken in the widthwise direction at the position of an external electrode.

[0110] 13A and 13B, the multilayer ceramic capacitor 1D has an element body 2D and external electrodes 6AD and 6BD instead of the element body 2 and external electrodes 6A and 6B of the multilayer ceramic capacitor 1A in FIG. 2A. The surface roughness Sa of the upper surface of the element body 2D is equal to the surface roughness Sa of the lower surface of the element body 2D. The surface roughness Sa of the upper and lower surfaces of the element body 2D is preferably 0.20 μm or less. The rest of the configuration of the element body 2D can be the same as that of the element body 2.

[0111] The external electrodes 6AD, 6BD are formed on the element body 2D so as to face each other while being separated from each other in the longitudinal direction DL. Here, the external electrodes 6AD, 6BD are formed on the end surfaces and are not present on the top or bottom surfaces of the element body 2D. The external electrodes 6AD, 6BD may also be formed on the front and rear surfaces that are opposed to each other and perpendicular to both the bottom and end surfaces of the element body 2D.

[0112] Here, by ensuring that the external electrodes 6AD, 6BD are not present on the upper and lower surfaces of the element body 2D, the height of the multilayer ceramic capacitor 1D can be further reduced without reducing the number of stacked internal electrode layers 3A, 3B, and LSC mounting can be achieved without reducing the capacitance of the multilayer ceramic capacitor 1D.

[0113] Each external electrode 6AD, 6BD includes an underlayer 7D formed on the element body 2D and a plating layer 9D laminated on the underlayer 7D. The underlayers 7D are formed on the element body 2D so as to face each other while being separated from each other in the longitudinal direction DL. In this case, the underlayers 7D are formed on the end faces of the element body 2D, and are not formed on the top or bottom surfaces of the element body 2D. The underlayers 7D may also be formed on the front and back surfaces of the element body 2D.

[0114] The plating layer 9D is continuously formed for each external electrode 6AD, 6BD so as to cover the base layer 7D, but is not formed on the upper or lower surface of the element body 2D. The plating layer 9D is electrically connected to the internal electrode layers 3A, 3B via the base layer 7D. The plating layer 9D is also electrically connected to the terminals of the mounting board via solder. The plating layer 9D can have a three-layer structure, for example, consisting of a Cu plating layer 9AD laminated on the base layer 7D, a Ni plating layer 9BD laminated on the Cu plating layer 9AD, and a Sn plating layer 9CD laminated on the Ni plating layer 9BD.

[0115] Here, on the upper and lower surfaces of the element body 2D, the end faces of the base layer 7 and the plating layer 9 form a layered structure outside the element body 2D. Also, on the upper and lower surfaces of the element body 2D, the end faces of the Cu plating layer 9A, the Ni plating layer 9B, and the Sn plating layer 9C form a layered structure outside the base layer 7. In this case, the layered structure of the base layer 7D, Cu plating layer 9AD, Ni plating layer 9BD, and Sn plating layer 9CD stacked on the end faces of the element body 2D is cut horizontally on the upper and lower surfaces of the element body 2D. At this time, the base layer 7D has end faces MU and KU that protrude outward from the element body 2D on the upper and lower surfaces, respectively. The Cu plating layer 9AD has end faces MA and KA that protrude outward from the end faces MU and KU on the upper and lower surfaces, respectively, of the element body 2D. The Ni plating layer 9BD has end faces MB and KB that protrude outward from the end faces MA and KA on the upper and lower surfaces of the element body 2D, respectively. The Sn plating layer 9CD has end faces MC and KC that protrude outward from the end faces MB and KB on the upper and lower surfaces of the element body 2D, respectively.

[0116] The end faces MU, MA, MB, and MC can be located in the same plane including the top surface of the element body 2D. In this case, the normal direction of each end face MU, MA, MB, and MC can be the same as the normal direction of the top surface of the element body 2D. In this case, each end face MU, MA, MB, and MC can be a flat surface.

[0117] The end faces KU, KA, KB, and KC can be located in the same plane including the bottom surface of the element body 2D. In this case, the normal direction of each end face KU, KA, KB, and KC can be the same as the normal direction of the bottom surface of the element body 2D. In this case, each end face KU, KA, KB, and KC can be a flat surface.

[0118] Furthermore, the base layer 7D wraps around along the curved surface R on the upper surface of the element body 2D, with its end face MU reaching the upper surface of the element body 2D. The base layer 7D wraps around along the curved surface R on the lower surface of the element body 2D, with its end face KU reaching the lower surface of the element body 2D. The wraparound amounts of the base layer 7D on each of the upper and lower surfaces of the element body 2D can be made equal to the radius of curvature C of the curved surface R on the upper and lower surfaces of the element body 2D.

[0119] Here, the ends of the base layer 7D are exposed from the plating layer 9AD, the Ni plating layer 9BD, and the Sn plating layer 9CD on the upper surface of the element body 2D. At this time, the layer structure of the external electrodes 6AD, 6BD is exposed to the outside of the multilayer ceramic capacitor 1D on the upper surface of the element body 2D. Also, the ends of the base layer 7D are exposed from the plating layer 9AD, the Ni plating layer 9BD, and the Sn plating layer 9CD on the lower surface of the element body 2D. At this time, the layer structure of the external electrodes 6AD, 6BD is exposed to the outside of the multilayer ceramic capacitor 1D on the lower surface of the element body 2D.

[0120] The rest of the configuration of the underlayer 7D, Cu plating layer 9AD, Ni plating layer 9BD, and Sn plating layer 9CD can be configured in the same way as the underlayer 7, Cu plating layer 9A, Ni plating layer 9B, and Sn plating layer 9C.

[0121] Here, by providing end faces MU, KU, MA, KA, MB, KB, MC, and KC on the base layer 7D, Cu plating layer 9AD, Ni plating layer 9BD, and Sn plating layer 9CD on the upper and lower surfaces of the element body 2D, respectively, it is possible to produce a multilayer ceramic capacitor 1D that does not have external electrodes 6AD, 6BD on the upper and lower surfaces of the element body 2D without causing fracture of the external electrodes 6AD, 6BD. This makes it possible to further reduce the height while suppressing a decrease in the flexural strength of the multilayer ceramic capacitor 1D, and to suppress non-uniformity in the cross-sectional shapes of the external electrodes 6AD, 6BD on the upper and lower surfaces of the element body 2D, thereby suppressing a decrease in the adhesion strength between the external electrodes 6AD, 6BD and the element body 2D.

[0122] Furthermore, by providing the base layer 7D, Cu plating layer 9AD, Ni plating layer 9BD, and Sn plating layer 9CD with end faces MU, KU, MA, KA, MB, KB, MC, and KC on the top and bottom surfaces of the element body 2D, the Cu plating layer 9AD, Ni plating layer 9BD, and Sn plating layer 9CD can maintain uniform thicknesses, which prevents a decrease in the strength of the external electrodes 6AD and 6BD and a decrease in conductivity between the base layer 7D and the terminals of the mounting board.

[0123] Furthermore, by eliminating the external electrodes 6AD, 6BD on the upper and lower surfaces of the element body 2D, the shape of the multilayer ceramic capacitor 1D can be made symmetrical from top to bottom, eliminating the need to distinguish between the top and bottom of the multilayer ceramic capacitor 1D. This eliminates the need to align the multilayer ceramic capacitor 1D so that its top surface faces upward when it is picked up by the nozzle of the mounter, thereby preventing an increase in the number of steps required to mount the multilayer ceramic capacitor 1D.

[0124] Each of the external electrodes 6AD, 6BD is provided with a protective film 10A covering the end faces MU, MA, MB, and MC, and a protective film 10B covering the end faces KU, KA, KB, and KC. Each of the protective films 10A, 10B is, for example, a metal film. The material of this metal film is preferably Sn, Cu, Ni, Ti, or Cr. Each of the protective films 10A, 10B is preferably a solderable metal film.

[0125] Each of the protective films 10A, 10B may be a Sn-plated layer. In this case, the Sn-plated layer used as each of the protective films 10A, 10B may cover the end faces MU, MA, MB, MC, KU, KA, KB, and KC and the Sn-plated layer 9CD. Here, the Sn-plated layer used as each of the protective films 10A, 10B may be continuous with the Sn-plated layer 9CD. Furthermore, it is preferable that the thickness of the Sn-plated layer 9CD is 5 μm or more, and that the thickness of the Sn-plated layer used as each of the protective films 10A, 10B is 5 μm or less.

[0126] (Seventh embodiment) FIG. 14 is a cross-sectional view showing an example of the configuration of a mounting substrate on which the multilayer ceramic capacitor in accordance with the seventh embodiment is mounted. 14, a multilayer ceramic capacitor 1D is mounted on a mounting substrate 41 in place of the multilayer ceramic capacitor 1A of FIG. 8. In this case, the bottom surface of an element body 2D of the multilayer ceramic capacitor 1D may be in contact with land electrodes 42A and 42B. The multilayer ceramic capacitor 1D is connected to the land electrodes 42A and 42B via solder layers 43AD and 43BD attached to the plating layers 9D of the external electrodes 6AD and 6BD, respectively. In this case, the connection between the multilayer ceramic capacitor 1D and the mounting substrate 41 is ensured via the external electrodes 6AD and 6BD on each end surface of the element body 2D.

[0127] Note that the solder layers 43AD, 43BD may be allowed to wet onto the external electrodes 6AD, 6BD on the front and rear surfaces of the element body 2D in order to improve the mounting strength of the multilayer ceramic capacitor 1D on the mounting board 41. In order to increase the amount of the solder layers 43AD, 43BD that wet onto the external electrodes 6AD, 6BD on the front and rear surfaces of the element body 2D, the lengths of the external electrodes 6AD, 6BD on the front and rear surfaces of the element body 2D may be increased.

[0128] (Eighth embodiment) Fig. 15 is a perspective view showing a configuration example of a ceramic electronic component according to an eighth embodiment. In Fig. 15, a chip inductor is taken as an example of the ceramic electronic component. 15, chip inductor 61 includes an element body 62 and external electrodes 66A and 66B. The element body 62 includes a coil pattern 63, internal electrode layers 63A and 63B, and a magnetic material 64. The magnetic material 64 is also used as a dielectric that insulates the internal electrode layers 63A and 63B. The shape of the element body 62 can be a substantially rectangular parallelepiped.

[0129] The element body 62 is chamfered along the ridgeline of the element body 62. At this time, the element body 62 has a curved surface R where the corners are chamfered. The surface roughness Sa of the upper surface of the element body 62 is smaller than the surface roughness Sa of the lower surface of the element body 62.

[0130] The coil pattern 63 and the internal electrode layers 63A and 63B are covered with a magnetic material 64. However, an end of the internal electrode layer 63A is drawn out from the magnetic material 64 on one end surface side of the element body 62 and connected to an external electrode 66A. An end of the internal electrode layer 63B is drawn out from the magnetic material 64 on the other end surface side of the element body 62 and connected to an external electrode 66B.

[0131] The material of the coil pattern 63 and the internal electrode layers 63A, 63B can be selected from metals such as Cu, Ni, Ti, Ag, Au, Pt, Pd, Ta, and W, or may be an alloy containing these metals. The magnetic material 64 is, for example, ferrite.

[0132] The external electrodes 66A, 66B are located on opposing end surfaces of the element body 62, separated from each other in the longitudinal direction DL of the element body 62. Here, each external electrode 66A, 66B is formed continuously from the underside of the element body 62 to the end surface that connects perpendicularly to the underside via the curved surface R, and is not present on the upper surface of the element body 62. Furthermore, each external electrode 66A, 66B may also be formed on opposing front and rear surfaces that are perpendicular to both the underside and end surfaces of the element body 62.

[0133] The external electrodes 66A, 66B include an underlayer 67 formed on the element body 62 and a plating layer 69 formed on the underlayer 67. The underlayer 67 may include a common material containing a metal. The common material is, for example, a ferrite component, which is the main component of the magnetic material 64. The plating layer 69 may have a three-layer structure, for example, a Cu plating layer 69A formed on the underlayer 67, a Ni plating layer 69B formed on the Cu plating layer 69A, and a Sn plating layer 69C formed on the Ni plating layer 69B.

[0134] The base layer 67 is formed continuously from the lower surface side of the element body 62 through the curved surface R to the end face, and is not formed on the upper surface side of the element body 62. The base layer 67 may also be formed continuously from the lower surface side to the front surface side and rear surface side of the element body 62. The plating layer 69 is formed continuously for each external electrode 66A, 66B so as to cover the base layer 67, and is not formed on the upper surface side of the element body 62.

[0135] Here, on the top surface side of element body 62, the end face of base layer 67 and the end face of plating layer 69 form a layer structure outside of element body 62. Also, on the top surface side of element body 62, the end face of Cu plating layer 69A, the end face of Ni plating layer 69B, and the end face of Sn plating layer 69C form a layer structure outside of base layer 67. In this case, the layered structure of base layer 67, Cu plating layer 69A, Ni plating layer 69B, and Sn plating layer 69C stacked on the end face of element body 62 is cut horizontally on the top surface side of element body 62. At this time, base layer 67 has an end face PU that protrudes outside of element body 62 on the top surface side of element body 62. Cu plating layer 69A has an end face PA that protrudes outside of end face PU on the top surface side of element body 62. Ni plating layer 69B has an end face PB that protrudes outside of end face PA on the top surface side of element body 62. The Sn plating layer 69C has an end surface PC that projects outward from the end surface PB on the upper surface side of the element body 62.

[0136] The end faces PU, PA, PB, and PC can be located in the same plane including the upper surface of the element body 62. In this case, the normal direction of each end face PU, PA, PB, and PC can be the same as the normal direction of the upper surface of the element body 62. In this case, each end face PU, PA, PB, and PC can be a flat surface. Furthermore, the base layer 67 wraps around along the curved surface R on the upper surface side of the element body 62, so that the end face PU reaches the upper surface of the element body 62.

[0137] Here, the end of the base layer 67 is exposed from the plating layer 69A, the Ni plating layer 69B, and the Sn plating layer 69C on the upper surface side of the element body 62. At this time, the layer structure of the external electrodes 66A, 66B is exposed to the outside of the chip inductor 61. Meanwhile, the end of the base layer 67 is covered with the Cu plating layer 69A, the Ni plating layer 69B, and the Sn plating layer 69C on the lower surface side of the element body 62.

[0138] Each of the external electrodes 66A, 66B also includes a protective film 70 covering the end faces PU, PA, PB, and PC. The protective film 70 is, for example, a metal film. The material of the metal film is preferably Sn, Cu, Ni, Ti, or Cr. The protective film 70 is preferably a solderable metal film.

[0139] This protective film 70 may be a Sn-plated layer. In this case, the Sn-plated layer used as the protective film 70 may cover the end faces PU, PA, PB, and PC and the Sn-plated layer 69C. Here, the Sn-plated layer used as the protective film 70 may be continuous with the Sn-plated layer 69C. Furthermore, it is preferable that the thickness of the Sn-plated layer 69C is 5 μm or more, and the thickness of the Sn-plated layer used as the protective film 70 is 5 μm or less.

[0140] The external size of the chip inductor 61 may be, for example, length > width > height, or length > width = height. In this case, in order to reduce the height of the chip inductor 61, the height of the chip inductor 61 is preferably 150 μm or less. [Explanation of symbols]

[0141] 1. Multilayer ceramic capacitors 2 Base 2A laminate 3A, 3B Internal electrode layer 4 Dielectric Layer 5A, 5B cover layer 6A, 6B external electrode 7 Base layer 9 Plating layer 10 Protective film

Claims

1. an element body having a dielectric, an internal electrode, a first surface, and a second surface opposite to the first surface; a base layer connected to the internal electrode and containing a metal, the base layer having a first end face outside the element body on the second surface side; a plating layer laminated on the base layer and having a second end face that forms a layer structure with the first end face outside the element body on the second surface side; and an external electrode having a protective film that covers the first end face and the second end face.

2. the plating layer has a laminated structure of a plurality of plating layers having different metal components, 2. The ceramic electronic component according to claim 1, wherein on the second surface side, end faces of the plurality of plating layers form a layer structure outside the element body.

3. 3. The ceramic electronic component according to claim 2, wherein the outermost layer of the plating layer is a Sn plating layer.

4. 4. The ceramic electronic component according to claim 3, wherein the protective film is a Sn plating layer that is continuous with the outermost Sn plating layer of the plating layers.

5. 5. The ceramic electronic component according to claim 4, wherein the thickness of the outermost Sn plating layer of the plating layer is 5 [mu]m or more, and the thickness of the Sn plating layer of the protective film is 5 [mu]m or less.

6. 6. The ceramic electronic component according to claim 1, wherein the protective film is a metal film.

7. 7. The ceramic electronic component according to claim 6, wherein the material of the metal film is Sn, Cu, Ni, Ti or Cr.

8. 6. The ceramic electronic component according to claim 1, wherein the protective film is a deposited film of a metal or an insulator.

9. 6. The ceramic electronic component according to claim 1, wherein the protective film is a resin coating film.

10. 10. The ceramic electronic component according to claim 1, wherein the first end face and the second end face are polished surfaces.

11. 11. The ceramic electronic component according to claim 1, wherein the heights of the first end face and the second end face relative to the first face are lower than the height of the second face.

12. The element body is a dielectric layer containing the dielectric; The dielectric layer is formed between first and second internal electrode layers, and the first and second internal electrode layers are alternately stacked with the dielectric layer interposed therebetween. The external electrode is a first external electrode connected to the first internal electrode layer and extending to a third surface perpendicular to both the first surface and the second surface; 12. The ceramic electronic component according to claim 1, further comprising: a second external electrode connected to the second internal electrode layer and extending to a fourth surface opposite to the third surface.

13. A mounting substrate on which the ceramic electronic component according to any one of claims 1 to 12 is mounted via a solder layer, The mounting substrate, wherein the solder layer wets and rises onto the side surfaces of the external electrodes while being spaced apart from the second surface of the element body.

14. forming an element body provided with a dielectric and internal electrodes; a step of applying a base material for external electrodes to the end faces of the element body and four faces perpendicular to the end faces; firing the base material to form base layers for the external electrodes; laminating a plating layer on the underlayer; removing the underlayer and plating layer on one of the four surfaces; and forming a protective film in the area where the previous underlayer and previous plating layer have been removed.

15. 15. The method for manufacturing a ceramic electronic component according to claim 14, wherein the base layer and the plating layer on one of the four surfaces are removed by physically polishing the one of the four surfaces.

16. 16. The method for manufacturing a ceramic electronic component according to claim 14, wherein the protective film is formed by electrolytic plating of the same metal as the outermost layer of the plating layer.

17. 16. The method for manufacturing a ceramic electronic component according to claim 14, wherein the protective film is formed by a dry film-forming method using a metal or an insulator.

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