Nonvolatile Analog Resistive Memory Cell Implementing a Ferroelectric Select Transistor

Abstract

The device includes a non-volatile analog resistive memory cell. The non-volatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has an adjustable conductance. The select transistor is a ferroelectric field effect transistor (FeFET) device including a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to a first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.

Description

[Technical Field]

[0001] The present disclosure generally relates to nonvolatile analog resistive memory cells for neuromorphic computing, and techniques for conductance tuning of resistive memory devices in nonvolatile analog resistive memory cells. [Background technology]

[0002] Information processing systems, such as neuromorphic computing systems and artificial neural network (ANN) systems, are used in a variety of applications, including machine learning and inference processing for cognitive recognition and computing. These systems are hardware-based systems that typically contain a large number of highly interconnected processing elements (referred to as "artificial neurons") operating in parallel to perform various types of computations. Artificial neurons (e.g., pre-synaptic and postsynaptic neurons) are connected using artificial synapse devices, which provide synaptic weights that represent the connection strength between the artificial neurons. Synaptic weights can be implemented using analog memory elements, such as tunable resistive memory devices, which exhibit non-volatile and multilevel memory characteristics. Summary of the Invention

[0003] Embodiments of the present disclosure include non-volatile analog resistive memory cells including ferroelectric select transistors and resistive memory devices, methods for programming and reading non-volatile analog resistive memory cells including ferroelectric select transistors and resistive memory devices, and computing systems including arrays of non-volatile analog resistive memory cells including ferroelectric select transistors and resistive memory devices.

[0004] In an exemplary embodiment, the device includes a nonvolatile analog resistive memory cell. The nonvolatile analog resistive memory device includes a resistive memory device and a select transistor. The resistive memory device includes a first terminal and a second terminal. The resistive memory device has an adjustable conductance. The select transistor includes a ferroelectric field effect transistor (FeFET) device including a gate terminal, a source terminal, and a drain terminal. The gate terminal of the FeFET device is connected to a word line. The source terminal of the FeFET device is connected to a source line. The drain terminal of the FeFET device is connected to a first terminal of the resistive memory device. The second terminal of the resistive memory device is connected to a bit line.

[0005] Another exemplary embodiment includes a method including applying programming pulses on a word line to program a nonvolatile analog resistive memory cell coupled to the word line. The nonvolatile analog resistive memory cell includes a select transistor including an FeFET device connected to the word line and a resistive memory device connected to the FeFET device. The application of the programming pulses adjusts a polarization state of the FeFET device in response to the programming pulses applied to the FeFET device from the word line, where adjusting the polarization state of the FeFET device causes an adjustment of a programming current to adjust the conductance of the resistive memory device. Adjusting the polarization state and adjusting the conductance of the resistive memory device by progressively changing the conductance of the resistive memory device with the adjusted programming current generated upon activation of the FeFET device in response to each programming pulse applied to the FeFET device.

[0006] Other embodiments are described in the following detailed description of illustrative embodiments, which should be read in connection with the accompanying figures. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 illustrates a schematic diagram of a computing system including an array of non-volatile analog resistive memory cells that can implement ferroelectric select transistors and resistive memory devices, according to an exemplary embodiment of the present disclosure. [Figure 2A] FIG. 2 is a schematic diagram illustrating the forward pass operation of a backpropagation process that can be performed using the computing system of FIG. [Figure 2B] FIG. 2 is a diagram illustrating schematically the backward pass operation of a backpropagation process that can be performed using the computing system of FIG. [Figure 2C] FIG. 2 is a diagram illustrating schematically the weight update operations of a backpropagation process that can be performed using the computing system of FIG. [Figure 3] FIG. 1A is a diagram illustrating a schematic diagram of a non-volatile analog resistive memory cell implementing a ferroelectric select transistor and a resistive memory device, according to an exemplary embodiment of the present disclosure. [Figure 4] FIG. 1A is a schematic diagram illustrating a resistive memory device that can be implemented in a non-volatile analog resistive memory cell, according to an exemplary embodiment of the present disclosure. [Figure 5] FIG. 10 is a schematic diagram illustrating a resistive memory device that can be implemented in a non-volatile analog resistive memory cell, according to another exemplary embodiment of the present disclosure. [Figure 6] FIG. 1 is a schematic diagram of an FeFET device that can be implemented as a select transistor in a non-volatile analog resistive memory cell, according to an exemplary embodiment of the present disclosure. [Figure 7A] FIG. 10 is a graph showing the channel conductance of an FeFET device as a function of pulse number for multiple identical programming pulses applied to the gate electrode of the FeFET device, according to an exemplary embodiment of the present disclosure. [Figure 7B]7A and 7B schematically illustrate a method of utilizing multi-domain partial polarization switching in a ferroelectric layer of an FeFET device to tune the channel conductance of the FeFET device, according to an exemplary embodiment of the present disclosure. 7C and 7D schematically illustrate different polarization states of the ferroelectric layer of the FeFET resulting from partial polarization switching as a function of increasing numbers of boost pulses, according to an exemplary embodiment of the present disclosure. [Figure 7C] 7A and 7B schematically illustrate a method of utilizing multi-domain partial polarization switching in a ferroelectric layer of a FeFET device to tune the channel conductance of the FeFET device, according to an exemplary embodiment of the present disclosure; and FIG. 7C schematically illustrates different polarization states of a ferroelectric layer of a FeFET resulting from partial polarization switching in response to an increasing number of boost pulses having polarities opposite to those shown in FIG. 7A and FIG. 7D, according to another exemplary embodiment of the present disclosure. [Figure 8A] FIG. 10 is a timing diagram illustrating a method of programming a non-volatile analog resistive memory cell implementing a ferroelectric select transistor and a resistive memory device according to an exemplary embodiment of the present disclosure. [Figure 8B] 10 is a timing diagram illustrating a method for reading the state of a non-volatile analog resistive memory cell implementing a ferroelectric select transistor and a resistive memory device according to an exemplary embodiment of the present disclosure. [Figure 9] FIG. 10 is a diagram that schematically illustrates a non-volatile analog resistive memory cell implementing a ferroelectric select transistor and a resistive memory device, according to another exemplary embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram that schematically illustrates a non-volatile analog resistive memory cell implementing a ferroelectric select transistor and a resistive memory device, according to another exemplary embodiment of the present disclosure. [Figure 11A] 11 is a timing diagram illustrating a method of programming the nonvolatile analog resistive memory cell of FIG. 10 using an enhancing pulse stream to increase the conductance of the resistive memory device, according to an exemplary embodiment of the present disclosure. [Figure 11B]11 is a timing diagram illustrating a method of programming the nonvolatile analog resistive memory cell of FIG. 10 using a falling pulse stream to decrease the conductance of the resistive memory device, according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0008] Embodiments of the present invention are now described in further detail with respect to non-volatile analog resistive memory cells including ferroelectric select transistors and resistive memory devices, methods for programming and reading non-volatile analog resistive memory cells including ferroelectric select transistors and resistive memory devices, and computing systems including arrays of non-volatile analog resistive memory cells including ferroelectric select transistors and resistive memory devices. As described in further detail below, the ferroelectric select transistors (alternatively referred to herein as ferroelectric select transistors) are configured to enhance linearity in the conductance adjustment of the analog resistive memory devices using a programming pulse scheme including identical programming pulses (e.g., the same amplitude and pulse width).

[0009] It should be understood that the various features shown in the accompanying drawings are schematic diagrams and not drawn to scale. Moreover, for ease of illustration and description, one or more layers, structures, regions, features, etc. of a type commonly used to implement FeFET devices, resistive memory devices, and other devices or structures and system components as schematically shown in the drawings may not be explicitly shown in a given drawing. This does not imply that any layers, structures, regions, features, etc. not explicitly shown are omitted from the actual device or structure. Moreover, the same or similar reference numbers may be used throughout the drawings to indicate the same or similar features, elements, or structures, and thus, detailed descriptions of the same or similar features, elements, or structures may not be repeated in each drawing. Furthermore, as used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" should not be construed as preferred or advantageous over other embodiments or designs. The term "above," as used herein to describe the orientation of a given feature relative to another feature, means that the given feature may be positioned or formed "directly above" (i.e., in direct contact with) the other feature, or that the given feature may be positioned or formed "indirectly above" the other feature with one or more intermediate features disposed between the given feature and the other feature.

[0010] An exemplary embodiment of the present disclosure includes a computing system or computational memory system that utilizes an array of nonvolatile analog memory cells for the dual purpose of storing data and processing this data to perform some computational task. The nonvolatile analog memory cells (e.g., a resistive processing unit (RPU)) implement resistive memory devices, such as resistive random access memory (ReRAM) devices or phase change memory (PCM) devices, that have tunable conductance (G) with variable conductance states ranging from a minimum conductance (Gmin) to a maximum conductance (Gmax). As noted above, neuromorphic computing systems and ANN systems are types of in-memory computing systems in which artificial neurons are connected using artificial synaptic devices to provide synaptic weights that represent the connection strength between two artificial neurons. The synaptic weights can be implemented using tunable resistive memory devices, and the variable conductance states represent the synaptic weights and are used to perform computations (e.g., vector-matrix multiplication). The conductance states of the analog resistive memory device are encoded or otherwise mapped to synaptic weights.

[0011] Various types of artificial neural networks, such as deep neural networks (DNNs) and convolutional neural networks (CNNs), implement neuromorphic computing architectures for machine learning applications such as image recognition, object recognition, and speech recognition. The in-memory computations associated with such neural networks include, for example, training computations in which the synaptic weights of resistive memory cells are optimized by processing a training data set, and forward inference computations in which the trained neural network is used to process input data for purposes such as classifying the input data or predicting events based on the input data.

[0012] DNN training generally relies on a backpropagation algorithm, which involves three iterative cycles: forward, backward, and weight update, which are repeated multiple times until a convergence criterion is met. The forward and backward cycles primarily involve computing forward and backward vector-matrix multiplications. This operation can be performed on a 2D array of analog resistive memory cells. In the forward cycle, the stored conductance values of the resistive memory devices in the 2D array form a matrix, and an input vector is sent as a voltage pulse through each input row of the 2D array. In the backward cycle, voltage pulses are applied as inputs from the columns, and a vector-matrix product is calculated based on the matrix transpose. The weight update involves computing a vector-vector cross product, which consists of multiplication operations and incremental weight updates performed locally at each resistive memory cell in the 2D array.

[0013] A stochastically trained DNN containing an array of RPU cells can have synaptic weights implemented using tunable resistive memory devices. To properly train a DNN and achieve high accuracy, the operating characteristics of the tunable resistive devices should satisfy a strict set of specifications for acceptable RPU device parameters that a given DNN algorithm can tolerate without significant error penalty. These specifications may include, for example, the minimum incremental conductance change (±Δg) due to a single potentiation pulse. min ), including variations in the switching characteristics of resistive memory devices, such as symmetry in the up and down conductance changes, and the tunable range of conductance values.

[0014] In particular, one important specification for DNN training is that the RPU cell should have an adjustable conductance with a resolution (or dynamic range) of at least 1000 levels (or steps) of conductance, and the conductance level can be switched (via a 1-ns pulse) from the lowest to the highest conductance state in an analog, symmetric, and gradual manner (at least one order of magnitude of the conductance difference between the maximum and minimum conductance states (on / off ratio)). To achieve symmetry in the up and down transition of the minimum unit weight value in the RPU cell (±Δw min ), each incremental increase in the level of the relevant conductance of the RPU cell (step-up,

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[0015] Despite these requirements, however, tunable resistive devices can exhibit limited dynamic range and resolution, as well as variability in tuning / programming characteristics, making it difficult to achieve symmetric weight updates across a range of conductance levels (minimum–maximum). Therefore, hardware implementation of an RPU architecture is nontrivial. More specifically, in reality, most resistive memory devices do not exhibit symmetric switching behavior; rather, they exhibit a highly nonlinear evolution of conductance as a function of the number of consecutively applied pulses. This introduces significant errors in weight updates. On the other hand, linearity of resistance change, representing identical gradual adjustment of synaptic weights with repeated input pulses, is highly desirable for fast learning in simple neuron circuits operating by determining synaptic weight changes using only pulse counting. Symmetric adjustment of synaptic weights for synaptic potentiation and depression is also preferable, as it allows the neuron circuit to generate voltage pulses with the same amplitude and duration (e.g., referred to as the identical programming pulse scheme) but with opposite polarity for potentiation and depression.

[0016] It is well known that resistive memory devices exhibit nonlinear conductance modulation when using boost / drop programming schemes with identical programming pulses. Therefore, to achieve linearity in the conductance modulation of such resistive memory devices, boost / drop pulse schemes typically implement non-uniform pulse schemes that involve adjusting either the amplitude or pulse width of the boost / drop pulses. For example, adjusting the pulse amplitude involves increasing the pulse amplitude (at a fixed pulse width) for each successive programming pulse applied to the resistive memory device to linearly increase (boost) or decrease (drop) the conductance of the resistive memory device in the same incremental adjustment step. On the other hand, adjusting the pulse width involves increasing the pulse width (at a fixed amplitude) for each successive programming pulse applied to the resistive memory device to linearly increase (boost) or decrease (drop) the conductance of the resistive memory device in the same incremental adjustment step. These non-uniform pulse schemes add overhead in terms of peripheral circuitry and processing required to implement the amplitude and / or pulse width adjustment. Additionally, pulse width modulation increases the latency of the programming operation.

[0017] As described in further detail below, exemplary embodiments of the present disclosure exploit the dynamics of voltage-controlled partial polarization switching in the ferroelectric layer of an FeFET utilized as a select transistor in a nonvolatile analog resistive memory cell to adjust the channel conductance of an FeFET device during a programming operation in which a uniform increase or decrease pulse scheme is applied to adjust the conductance of the resistive memory device (e.g., synaptic weight update). Adjusting the channel conductance of the FeFET device during a programming operation serves to improve the linearity in adjusting the conductance of the resistive memory device using a uniform programming pulse scheme.

[0018] FIG. 1 schematically illustrates a computing system 100 including an array of analog resistive memory cells implementing ferroelectric select transistors and resistive memory devices according to an exemplary embodiment of the present disclosure. In particular, FIG. 1 schematically illustrates a neuromorphic computing system implemented using a crossbar array of resistive processing units. The computing system 100 includes a two-dimensional (2D) crossbar array of RPU cells 110 arranged in multiple rows R1, R2, R3, ..., Rm and multiple columns C1, C2, C3, ..., Cn. The RPU cells 110 in each row R1, R2, R3, ..., Rm are commonly connected to a respective row control line RL1, RL2, RL3, ..., RLm (collectively, row control line RL). The RPU cells 110 in each column C1, C2, C3, ..., Cn are commonly connected to a respective column control line CL1, CL2, CL3, ..., CLn (collectively, column control line CL). Each RPU cell 110 is connected at (and between) the crosspoints (or intersections) of respective row and column lines. In one exemplary embodiment, RPU system 100 includes a 4,096 x 4,096 array of RPU cells 110.

[0019] Computing system 100 further includes peripheral circuitry 120 connected to row control lines RL1, RL2, RL3, ..., RLm, and peripheral circuitry 130 connected to column control lines CL1, CL2, CL3, ..., CLn. Additionally, peripheral circuitry 120 is connected to a data input / output (I / O) interface block 125, and peripheral circuitry 130 is connected to a data I / O interface block 135. Computing system 100 further includes control signal circuitry 140, which includes various types of circuit blocks, such as power, clock, bias, and timing circuits, that provide power distribution, control signal, and clocking signals for operation of computing system 100.

[0020] In some embodiments, each RPU cell 110 in computing system 100 includes a non-volatile analog resistive memory cell that implements a ferroelectric select transistor and a resistive memory device. In some embodiments, RPU cell 110 is implemented using one of the exemplary embodiments of the non-volatile analog resistive memory cell frameworks shown generally in Figures 3, 4, 5, 6, 7A-7C, 9, and 10 and discussed in further detail below. In some embodiments, each RPU cell 110 implements a resistive memory device, such as a ReRAM device or PCM device, with an adjustable conductance value that represents the matrix element or weight of the RPU cell 110.

[0021] In neuromorphic computing applications, the RPU cells 110 include artificial synapses that provide weighted connections between pre-neurons and post-neurons. Multiple pre-neurons and post-neurons are connected through a 2D crossbar array of RPU cells 110, which inherently represents a fully connected neural network. In some embodiments, the computing system 100 is configured to perform DNN or CNN computations, and the conductance of each RPU cell 110 is represented by a matrix element or weight w that can be updated or accessed through the operation of the peripheral circuits 120 and 130. ij (where w ij (where x denotes the weight value in the ith row and jth column in the array of RPU cells 110). As described above, DNN training generally relies on a backpropagation process that includes three iterative cycles: a forward cycle, a backward cycle, and a weight update cycle. Computing system 100 can be configured to perform all three cycles of the backpropagation process in parallel, potentially providing significant acceleration in DNN training with lower power and reduced computational resources. Computing system 100 can be configured to perform vector-matrix multiplication operations in parallel in the analog domain.

[0022] 1 as a single line for ease of illustration, it should be understood that each row and column control line may include two or more control lines connected to RPU cells 110 in their respective rows and columns, depending on the implementation and specified architecture of RPU cells 110. For example, in some embodiments, each row control line RL may include a complementary pair of word lines for a given RPU cell 110. Furthermore, each column control line CL may include multiple control lines, including, for example, one or more source lines (SL) and one or more bit lines (BL).

[0023] Peripheral circuits 120 and 130 are connected to respective rows and columns in the 2D array of RPU cells 110 and include various circuit blocks configured to perform vector-matrix multiplication functions, matrix-vector multiplication functions, and cross-product update operations to perform forward, backward, and weight update operations of the backpropagation process (for neural network training) and inference processing using the trained neural network. For example, in some embodiments, to support RPU cell read / sensing operations (e.g., reading the weight value of a given RPU cell 110), peripheral circuits 120 and 130 include pulse-width modulation (PWM) circuitry and read pulse driver circuitry to generate and apply PWM read pulses to RPU cells 110 in response to input vector values (read input values) received during the forward / reverse cycle.

[0024] More specifically, in some embodiments, the peripheral circuits 120 and 130 include digital-to-analog (D / A) conversion circuitry configured to receive a digital input vector (applied to a row or column) and convert the digital input vector into an analog input vector value represented by an input voltage with a varying pulse width. In some embodiments, a time-encoding scheme is used where the input vector is represented by a fixed-amplitude Vin=1V pulse with an adjustable duration (e.g., the pulse duration is a multiple of 1 ns and proportional to the value of the input vector). The input voltages applied to the rows (or columns) generate output vector values represented by output currents, and the weights of the RPU cells 110 are read out by measuring the output currents.

[0025] The peripheral circuits 120 and 130 detect the accumulated read current (I READ ) and converts the integrated current to a digital value (readout value) for subsequent calculation. In particular, the currents generated by the RPU cells 110 are summed by column (or row), and this total current is integrated over the measurement time tmeas by the current readout circuits of the peripheral circuits 120 and 130. The current readout circuits include current integrators and analog-to-digital (A / D) converters. In some embodiments, each current integrator includes an operational amplifier that integrates the current output from a given column (or row) (or differential current from a pair of RPU cells implementing negative and positive weights) on a capacitor, and the analog-to-digital (A / D) converter converts the integrated current (e.g., analog value) to a digital value.

[0026] Additionally, peripheral circuits 120 and 130 include voltage generators and driver circuits configured to generate programming voltages used during programming operations that update the conductance values of resistive memory devices implemented in the RPU cells. In some embodiments, peripheral circuits 120 and 130 perform exemplary programming operations as discussed in further detail below with reference to Figures 7A, 7B, 7C, and 8A.

[0027] The data I / O interfaces 125 and 135 are configured to connect to the digital processing cores, which are configured to process input / output to the computing system 100 (neural cores) and route data between different RPU arrays. The data I / O interfaces 125 and 135 are configured to (i) receive external control signals and data from the digital processing cores and provide the received control signals and data to the peripheral circuits 120 and 130, and (ii) receive digital readout output values from the peripheral circuits 120 and 130 and send the digital readout output values to the digital processing cores for processing. In some embodiments, the digital processing cores implement nonlinear function circuits that calculate activation functions (e.g., sigmoid neuron functions, softmax, etc.) and other arithmetic operations based on data provided to the next or previous layer of the neural network.

[0028] As known in the art, a fully connected DNN includes a stack of fully connected layers in which signals propagate from the input layer to the output layer through a series of linear and nonlinear transformations. The entire DNN represents a single differentiable error function that maps input data to class scores at the output layer. Typically, DNNs are trained using a simple stochastic gradient descent (SGD) method, in which the error gradient with respect to each parameter is calculated using the backpropagation algorithm. The backpropagation algorithm consists of three cycles: forward, backward, and weight update, which are repeated multiple times until a convergence criterion is met. The forward and backward cycles primarily involve computing forward and backward vector-matrix multiplication operations using the 2D crossbar array of RPU device cells 110 in the computing system shown in Figure 1.

[0029] In the computing system 100 of FIG. 1, the conductance value g in the 2D crossbar array of RPU cells is ij is the weight value w ij In the forward cycle (FIG. 2A), an input vector (in the form of a voltage pulse) is sent through each of the input rows in the 2D crossbar array, resulting in a vector-matrix multiplication in the RPU cell 110. In the reverse cycle (FIG. 2B), voltage pulses from the columns are input to the RPU cell 110, and a vector-matrix product is calculated based on the transpose of the weight matrix W values. In contrast to the forward and reverse cycles, performing weight updates on a 2D crossbar array of resistive devices requires computing vector-vector cross products, which consist of multiplication operations and incremental weight updates performed locally at each crosspoint RPU device in the array. FIGS. 2A, 2B, and 2C schematically illustrate the respective forward pass, backward pass, and weight update operations of the backpropagation algorithm, which can be performed using the computing system 100 of FIG. 1.

[0030] For a single fully connected layer, in which N input neurons are connected to M output (or hidden) neurons, the forward pass (Figure 2A) involves computing a vector-matrix multiplication y = Wx, where vector x of length N represents the input neuron activity and matrix W of size M × N stores the weight values between each pair of input and output neurons. The resulting vector y of length M is further processed by performing nonlinear activation on each of its elements and then passed to the next layer. Once the information reaches the final output layer, an error signal is computed and backpropagated through the network. In the forward cycle, the conductance values stored in the crossbar array of RPU cell 110 form a matrix, while the input vector is sent as voltage pulses through each of the input rows R1, R2, R3, ..., Rm.

[0031] The reverse cycle on a single layer (Fig. 2B) also involves a weight matrix z = W T The reverse cycle involves a vector-matrix multiplication based on the transpose of δ, where W denotes the weight matrix, the vector δ of length M represents the error calculated by the output neuron, and the vector z of length N is further processed using the derivative of the neuron's nonlinearity and then passed to the previous layer. In the reverse cycle, voltage pulses are provided as inputs to the RPU cell 110 from columns CL1, CL2, CL3, ..., CLn, and the vector-matrix product is calculated based on the transpose of the weight matrix W.

[0032] Finally, in the update cycle (Figure 2C), the weight matrix W is updated by performing a cross product of the two vectors used in the forward and reverse cycles. In particular, performing weight updates locally and all in parallel on a 2D crossbar array of resistive devices, regardless of the size of the array, requires the computing system of Figure 1 to compute vector-vector cross products, consisting of multiplication operations and incremental weight updates performed locally at each crosspoint (RPU cell 110). As shown schematically in Figure 2C, the weight update process begins with computing the weight matrix W. ij ←w ij +ηx i ×δ jwhere w ij represents the weight value in the ith row and jth column (the layer index is omitted for simplicity), and x i is the activity at the input neuron, and δ j is the error computed by the output neuron, and η denotes the global learning rate.

[0033] In summary, all operations based on the weight matrix W can be implemented using a 2D crossbar array of two-terminal RPU devices with M rows and N columns where the conductance values stored in the crossbar array form the matrix W. In the forward cycle, the input vector x is sent as a voltage pulse through each of the rows and the resulting vector y can be read out as a current signal from the columns. Similarly, when a voltage pulse is fed as an input from the columns in the reverse cycle, then the vector-matrix product is calculated to produce the weight matrix W. T Finally, in the update cycle, voltage pulses representing vectors x and δ are supplied simultaneously from the rows and columns. In the update cycle, each RPU cell 110 performs local multiplication and addition operations by processing voltage pulses coming from the columns and rows, thereby achieving a gradual weight update.

[0034] To determine the product of the x and δ vectors for a weight update cycle, the stochastic transformation circuits in peripheral circuits 120 and 130 are utilized to generate stochastic bit streams representing the input vectors x and δj. The stochastic bit streams for vectors x and δj are fed through the rows and columns of a 2D crossbar array of RPU cells, and the conductance of a given RPU cell changes depending on the match of the x and δj stochastic pulse streams input to the given RPU cell. The vector cross-product operation for the weight update operation is implemented based on the known concept that match detection (using an AND logic gate operation) of stochastic streams representing real numbers is equivalent to a multiplication operation. All three operating modes described above allow the RPU cells forming the neural network to be active in all three cycles, allowing a highly efficient implementation of the backpropagation algorithm to calculate the updated weight values of the RPU cells during the DNN training process.

[0035] FIG. 3 schematically illustrates an analog resistive memory cell implementing a ferroelectric select transistor and a resistive memory device according to an exemplary embodiment of the present disclosure. In particular, FIG. 3 schematically illustrates a nonvolatile analog resistive memory cell 300 including an FeFET device 310 and a resistive memory device 320. The memory cell 300 includes a 1T-1R architecture (alternatively, a 1F-1R architecture) in which the FeFET device 310 operates as the select transistor for the memory cell 300 and the resistive memory device 320 operates as the storage element for the memory cell 300. In particular, the resistive memory device 320 is a programmable resistive memory element depicted as a variable resistor. As shown in FIG. 3, the FeFET device 310 (also referred to herein as the FeFET select transistor 310 or the ferroelectric select transistor 310) includes a gate G terminal, a drain D terminal, and a source S terminal. The gate G terminal is connected to a word line WL, the source S terminal is connected to a source line SL, and the drain D terminal is connected to a terminal of the resistive memory device 320. The resistive memory device 320 is connected between the drain D terminal and a bit line BL.

[0036] Memory cell 300 can be implemented as, for example, an RPU cell of computing system 100 ( FIG. 1 ) to implement an artificial neural network or a neuromorphic computing system, etc. Resistive memory device 320 may be implemented using any suitable type of resistive memory device (e.g., a resistive switching device (interfacial or filament switching), ReRAM, memristor, PCM, etc.) having an adjustable conductance (or adjustable resistance level) that can be programmably adapted within a range of different conductance levels to adjust the weight of non-volatile analog resistive memory cell 300. As described in further detail below, FeFET device 310 enhances the linear response of the conductance adjustment of resistive memory device 320 during programming operations (e.g., the weight update phase of the SGD training process) performed to adapt the weight of non-volatile analog resistive memory cell 300.

[0037] FIG. 4 schematically illustrates a resistive memory device that can be implemented as a storage element in a nonvolatile analog resistive memory cell that implements a ferroelectric select transistor, according to an exemplary embodiment of the present disclosure. In particular, FIG. 4 schematically illustrates a resistive-switching device 400 (e.g., a resistive random-access memory (ReRAM) device) that includes an insulating layer 410 disposed between a first electrode 420 and a second electrode 430. In some embodiments, the insulating layer 410 includes an oxide layer (insulating layer) formed of a transition metal oxide material or a silicon oxide material (e.g., SiON). The insulating layer 410 serves as a programmable element (resistive-switching layer) that exhibits variable conductance (or different resistance states), where the change in conductance is achieved by altering (e.g., forming, rupturing, dissolving, etc.) the configuration of a conductive filament (CF) 412 within the insulating layer 410 between the first electrode 420 and the second electrode 430. Depending on the structural arrangement, the resistive-switching device 400 can be a single-level resistive device or a multi-level resistive memory device.

[0038] More specifically, an "electroforming" process is typically performed on the resistance-switching device 400 to first create one or more conductive filaments before using the resistance-switching device 400 for repeatable resistance switching. Depending on the configuration, the resistance-switching device 400 exhibits switching behavior that allows the device 400 to switch between a low resistance state (LRS) (or high conductance state), a high resistance (HRS) (or low conductance state), and multiple intermediate resistance states (IRS) by controlling the magnitude and / or duration of a write voltage signal applied across the first and second electrodes 420, 430. Switching between the HRS and LRS is controlled by a RESET voltage (e.g., a negative pulse having a given magnitude (e.g., −1.8 V) and duration (e.g., 100 nanoseconds)) and a SET voltage (e.g., a positive pulse having a given magnitude (e.g., +1.7 V) and duration (e.g., 100 nanoseconds)).

[0039] During a SET operation, application of a SET voltage across electrodes 420 and 430 of resistive-switching device 400 results in the formation of one or more localized conductive filaments 412 in insulating layer 410, and resistive-switching device 400 is switched (SET) to the LRS or "ON state" with an increase in conductance. To transition to another state, a RESET operation is performed by applying a RESET voltage across electrodes 420 and 430 of resistive-switching device 400 to cause the conductive filaments 412 to melt / break / rupture and place resistive-switching device 400 in the HRS or "OFF state." Resistive-switching device 400 can be interchangeably switched among all resistance states, including (i) SET switching from the HRS state to the IRS or LRS state, (ii) RESET switching from the LRS state to the IRS or HRS state, and (iii) SET / RESET switching from the IRS state to the LRS or HRS state, by controlling the magnitude of the applied write voltage signal. The thickness of conductive filament 412 can be controlled (e.g., formed, dissolved, ruptured) in different ways to enable resistive-switching device 400 to exhibit continuously variable conductance values.

[0040] FIG. 4 schematically illustrates an exemplary embodiment of a filamentary resistance-switching device. In other embodiments, an interfacial resistance-switching device can be implemented as a storage element in a non-volatile analog resistive memory cell that implements a ferroelectric select transistor according to exemplary embodiments described herein. Generally, an interfacial resistance-switching device includes one or more layers of insulating material disposed between a first electrode and a second electrode, and the magnitude of current flowing through the insulating layer is based on a barrier height at the interface (i.e., metal-insulator junction) between the insulating layer and the electrode. The interfacial barrier height can be modified by a control pulse, resulting in binary or multiple resistance states of the interfacial resistance-switching device, as will be understood by those skilled in the art.

[0041] FIG. 5 schematically illustrates a resistive memory device that can be implemented as a storage element in a nonvolatile analog resistive memory cell that implements a ferroelectric select transistor according to another exemplary embodiment of the present disclosure. In particular, FIG. 5 schematically illustrates a phase-change memory (PCM) device 500 including a first (bottom) electrode 510, an insulating layer 520, a heater electrode 530, a layer of phase-change material 540, and a second (top) electrode 550. The layer of phase-change material 540 includes a first region 542 of material in an amorphous state (or, alternatively, amorphous region 542) and a second region 544 of material in a crystalline state (or alternatively, crystalline region 544). The amorphous region 542 tends to have a high electrical resistivity, while the crystalline region 544 exhibits a low resistivity (e.g., several orders of magnitude lower). In the PCM device 500, data is stored based on the contrast in electrical resistance between the low-conductivity amorphous region 542 and the high-conductivity crystalline region 544 of the layer of phase-change material 540. Because the resistance contrast is large, the change in read current is relatively large, and the PCM device 500 can be implemented to provide multiple analog levels for MLC operation.

[0042] The phase change material 540 can be switched from a low conductivity state to a high conductivity state, and vice versa, by applying current pulses to the PCM device 500, which progressively change the size of the first regions 542 of material in the amorphous state. For example, a first type of pulse (e.g., a SET pulse, or a crystallization pulse) having a first magnitude and a first duration can be applied to the PCM device 500 to progressively decrease the size of the first regions 542, thus progressively decreasing the resistance (or increasing the conductance) of the PCM device 500. On the other hand, a second type of pulse (e.g., a RESET pulse, or an amorphization pulse) having a second magnitude and a second duration can be applied to the PCM device 500 to progressively increase the size of the first regions 542, thus progressively increasing the resistance (or decreasing the conductance) of the PCM device 500. The change in resistance of PCM device 500 is the result of the initiation of a Joule heating process that occurs due to an increase in current density in narrow heater electrode 530 when a current pulse is applied across electrodes 550 and 510. In this Joule heating process, a region of phase change material 540 near heater electrode 530 (e.g., first region 542) heats due to an internal temperature increase, causing crystallization of the phase change material while the temperature is held below the melting point of the phase change material. In this regard, programming PCM device 500 involves applying power through an applied voltage, resulting in an internal temperature change that either melts and then rapidly quenches a volume of amorphous material (RESET) or holds the volume at a slightly lower temperature for a sufficient time for recrystallization (SET). Because a low voltage is used to sense the device resistance (READ), the state of the device is not disturbed. Due to the stochastic nature of the crystallization of phase change material 540, there is significant randomness associated with weight updates.

[0043] FIG. 6 is a schematic diagram of a FeFET device 600 that can be implemented as a select transistor in a nonvolatile analog resistive memory cell according to an exemplary embodiment of the present disclosure. The FeFET device 600 includes a semiconductor substrate 610, a first source / drain region 612, a second source / drain region 614, and a gate structure 620. The gate structure 620 includes an interface layer 630, a ferroelectric layer 640, and a gate electrode 650. The substrate 610 includes a "channel region" disposed below the gate structure 620 between the first source / drain region 612 and the second source / drain region 614. The FeFET device 600 has a structure similar to a metal-oxide-semiconductor field-effect transistor (MOSFET) device, except that the gate structure 620 of the FeFET device 600 includes a ferroelectric layer 640 disposed between the gate electrode layer 650 and the top surface of the semiconductor substrate 610.

[0044] The ferroelectric layer 640 comprises a ferroelectric material that has the ability to spontaneously polarize in the presence of an electric field (referred to as the coercive field) and retain a remnant polarization in the absence of a bias. Remnant polarization refers to the polarization charge that remains positive or negative in a ferroelectric material after an external bias is removed. The remnant polarization state of the ferroelectric layer 640 affects the channel conductance of the FeFET device 600, and a change in the polarization state (e.g., a change in magnitude and / or polarity) of the ferroelectric layer 640 causes a change in the channel conductance of the FeFET device 600. As described in further detail below, exemplary embodiments of the present disclosure exploit this conductance-polarization characteristic of the FeFET device 600 by utilizing the FeFET device 600 as a select transistor in a non-volatile analog resistive memory cell to improve the linearity of the conductance adjustment of the resistive memory device, for example, during a weight update process.

[0045] The substrate 610 is formed of a semiconductor material, such as silicon or other suitable semiconductor material. The substrate 610 can be a bulk substrate or a doped well formed in a bulk substrate. The substrate 610 can be doped to have a first conductivity type (e.g., N-type) or a second conductivity type (e.g., P-type). The first and second source / drain regions 612 and 614 are doped regions in the substrate 610 that have a conductivity type opposite that of the substrate 610. For example, an N-type FeFET device would have the substrate 610 having P-type conductivity and the first and second source / drain regions 612 and 614 having N-type conductivity (e.g., N + A P-type FeFET device has a substrate 610 with N-type conductivity and first and second source / drain regions 612 and 614 with P-type conductivity (e.g., P + The doping is a function of the source / drain region 612. The doping is a function of the drain region 614. ... drain region 614. The doping is a function of the source / drain region 612. The doping is a function of the drain region 614. The doping is a function of the drain region

[0046] In some embodiments, the substrate 610 (i.e., body) includes a separate "body terminal" through which an appropriate bias voltage (e.g., ground voltage) can be applied to the substrate 610 during programming and read operations. For example, in some embodiments, the body terminal is connected to the source region 612 to ensure that there is zero voltage across the source / substrate junction and to prevent a threshold voltage (V T ) changes as a result of the voltage difference between the source and body of the FeFET device 600.

[0047] In some embodiments, the interfacial layer 630 comprises a thin layer of insulating material, including, but not limited to, a silicon oxide material (e.g., silicon dioxide), a silicon nitride material (e.g., SiN, SiON), or other suitable types of insulating material. The ferroelectric layer 640 comprises a ferroelectric material, including, but not limited to, polycrystalline alloy films of hafnium oxide (HfO), zirconium oxide (ZrO), hafnium zirconium oxide (HfZrO), and other types of high-k dielectric materials (e.g., hafnium oxide doped with aluminum, silicon, or yttrium) that can be formed with a crystalline microstructure that exhibits ferroelectric properties (e.g., an orthorhombic ferroelectric phase). The interfacial layer 630 is an optional layer utilized for various purposes, such as providing a buffer layer to enhance the quality of the interface between the surface of the substrate 610 and the ferroelectric layer 640, reducing the amount of charge trapping, and preventing reactions between the different materials of the ferroelectric layer 640 and the substrate 610. In some non-limiting embodiments, the ferroelectric layer 640 has a thickness ranging from about 2 nanometers (nm) to about 20 nm. In some embodiments, the ferroelectric layer 640 is formed directly on the surface of the silicon substrate 610 (e.g., a highly doped Si substrate).

[0048] The gate electrode 650 comprises a conductive material, including, but not limited to, titanium (Ti), titanium nitride (TiN), titanium silicide (TiSi), tantalum nitride (TaN), tungsten (W), tungsten silicide (WSi), ruthenium (Ru), rhenium (Re), nickel (Ni), platinum (Pt), iridium (Ir), or other types of conductive materials suitable for a given application. In some embodiments, the material of the gate electrode 650 is selected to achieve a given work function that affects the coercive voltage of the ferroelectric layer 640 to improve the performance of the FeFET device 600, for example, when used as a select (or access) transistor in a non-volatile analog resistive memory cell.

[0049] It should be understood that Figure 6 is a high-level schematic diagram of a FeFET device presented for ease of illustration and discussion. FeFET device 600 could include other elements, such as one or more insulating layers (e.g., gate sidewall spacers, gate capping layers, pre-metal dielectric (PMD) layers, etc.) encapsulating gate structure 620, a gate contact formed in contact with the top surface of gate electrode 650, source / drain contacts formed in contact with first and second source / drain regions 612 and 614, a body region formed in substrate 610, and a body contact formed in contact with the body region. Additionally, gate electrode 650 may include a multi-layer structure including a first gate electrode layer (e.g., a work function metal layer) formed on ferroelectric layer 640 and a second gate electrode layer (e.g., a low-resistivity metal layer) formed on the first gate electrode layer.

[0050] In some embodiments, the ferroelectric layer 640 is formed to have a polycrystalline microstructure that results in the ferroelectric layer 640 having multiple ferroelectric domains. The polycrystalline microstructure comprises a mosaic of small crystallites (or grains) of varying sizes that are randomly distributed and have no preferred orientation (i.e., a random texture and no grain direction). In some embodiments, various conditions and parameters of the manufacturing process for the ferroelectric layer 640 can be selected so that the grains (or crystallites) of the ferroelectric layer 640 grow with a targeted arrangement to result in a grain texture. The ferroelectric domains in the ferroelectric layer 640 can correspond to different grains or groups of grains within the polycrystalline structure of the ferroelectric layer 640.

[0051] In the context of the exemplary embodiments described herein, the term "ferroelectric domain" refers to a region of the ferroelectric layer 640 within which a permanently oriented spontaneous polarization can be obtained by applying a coercive field (e.g., a coercive voltage) to the given region. In this regard, a given ferroelectric domain having the ferroelectric layer 640 can become spontaneously polarized in the presence of a coercive field. The permanent spontaneous polarization includes a remnant polarization (or remnant polarization charge), either positive or negative, that remains within a given region of the ferroelectric material after the coercive field is removed. The coercive field indicates the magnitude of an electric field, when applied to the ferroelectric material, sufficient to induce a switch from positive polarization charge to negative polarization charge, or vice versa. In general, the coercive voltage is a function of the thickness of the ferroelectric film multiplied by the coercive field value.

[0052] As described above, the remanent polarization state of the ferroelectric layer 640 affects the channel conductance of the FeFET device 600, and a change in the polarization state of the ferroelectric layer 640 (e.g., a change in magnitude and / or polarity) causes a change in the channel conductance of the FeFET device 600. Exemplary embodiments of the present disclosure exploit the dynamics of voltage-controlled partial polarization switching in the ferroelectric layer 640 of an FeFET device 600 utilized as a select transistor in a non-volatile analog resistive memory cell to adjust the channel conductance of the FeFET device 600 during a programming operation (e.g., a synaptic weight update process) to improve the linearity in the conductance adjustment of the resistive memory device during the programming operation. For example, FIGS. 7A and 7B illustrate the threshold voltage (V) of the FeFET device 600 by applying a sequence of voltage pulses of the same amplitude and pulse width to the gate electrode 650, according to exemplary embodiments of the present disclosure. T 7A and 7B schematically illustrate a process utilizing switching of the partial polarization of multiple domains in the ferroelectric layer 640 of the FeFET device 600 to modulate the drain-source (channel) conductance of the FeFET device 600. The exemplary embodiment of FIGS. 7A and 7B assumes that the FeFET device 600 is an N-type FeFET device.

[0053] More specifically, FIG. 7A illustrates a graph of the channel conductance G of an FeFET device as a function of the number of programming pulses applied to the gate of the FeFET device, according to an exemplary embodiment of the present disclosure. DS In particular, FIG. 7A graphically illustrates the channel conductance G (units: microsiemens (μS)) of the FeFET device 600. DS 7 shows a curve 700 illustrating the increase in V as a function of pulse number for a pulse pattern including a boost pulse applied in the boost period 710 and a drop pulse applied in the drop period 720. In the boost period 710, the same amplitude +V P A sequence of boost pulses having a voltage (e.g., +3.7 V) and a pulse width W (e.g., 75 ns) is applied to the gate electrode 650 of the FeFET device 600, and during the fall period 720, the same amplitude -V D A sequence of falling pulses having a voltage (eg, −3.2 V) and a pulse width W (eg, 75 ns) is applied to the gate electrode 650 of the FeFET device 600 .

[0054] As shown in FIG. 7A, the potentiation pulses result in an asymmetric channel conductance response, and the first portion 710-1 of the potentiation period 710 exhibits a large increase in channel conductance G for a small number of initial potentiation pulses. DS where the second portion 710-2 of the enhancement period 710 shows a steep increase in the channel conductance G over a number of successive enhancement pulses. DS Also, during the second portion 710-2 of the enhancement period 710, the channel conductance G DS There is a relatively small linear increase in G, e.g., from about 30 μS to less than 40 μS, during the second portion 710-2 of the boost period 710, with a G of about 40 / 30=1.3. max / G min It becomes a ratio.

[0055] As further shown in FIG. 7A, the application of a fall pulse (following the build-up period 710) results in an asymmetric channel conductance response, with the first portion 720-1 of the fall period 720 exhibiting a small increase in the channel conductance G for the initial fall pulse. DS The second portion 720-2 of the fall period 720 shows a rapid decrease in the channel conductance G over a number of successive fall pulses. DS Also, during the second portion 720-2 of the drop period 720, the channel conductance G DS There is a relatively small linear decrease in

[0056] The channel conductance G shown in Figure 7A DS The change in threshold voltage V of the FeFET device 600 is due to partial polarization switching of the ferroelectric domains in the ferroelectric layer 640 of the FeFET device 600. T (Hence the channel conductance G DS ) during the potentiation period (same amplitude +V P FIG. 7B schematically illustrates different polarization states 700-1, 700-2, and 700-3 of FeFET device 600, each resulting in a different threshold voltage V of FeFET device 600. T Corresponds to.

[0057] More specifically, FIG. 7B schematically illustrates an initial polarization state 700-1 of FeFET device 600, in which the ferroelectric domains of ferroelectric layer 640 have a remanent polarization with a "first polarity" (e.g., negative ferroelectric polarization), and the electric dipoles across ferroelectric layer 640 are oriented such that the positive pole is directed toward gate electrode 650 and the negative pole is directed toward the channel region of substrate 610 of FeFET device 600. Polarization state 700-1 imparts a net negative charge to the entire channel region at the top surface of substrate 610, such that positive (majority) charge carriers from substrate 610 accumulate at the surface of substrate 610 in the channel region. The net effect of polarization state 700-1 is that FeFET device 600 reaches a first threshold voltage V T 1. The increase in threshold voltage of the FeFET device 600 having

[0058] 7B also schematically illustrates a polarization state 700-2 of the FeFET device 600 resulting from applying one or more initial boost pulses to the gate electrode 650, in which the remanent polarization of some of the ferroelectric domains in the ferroelectric layer 640 is switched from a first polarity to a second polarity (e.g., positive ferroelectric polarization), and the electric dipoles in the ferroelectric domains are oriented such that the negative polarity is directed toward the gate electrode 650 and the positive polarity is directed toward the channel region of the substrate 610. Compared to the initial polarization state 700-1, the polarization state 700-2 contributes more negative charge (less net positive charge) to the top surface of the substrate 610 in the channel region, resulting in a decrease in the threshold voltage of the FeFET device 600 and, therefore, an increase in the channel conductance relative to the initial polarization state 700-1.

[0059] 7B also schematically illustrates a polarization state 700-3 of the FeFET device 600 resulting from applying one or more additional enhancement pulses to the gate electrode 650, in which the remanent polarization of some of the ferroelectric domains in the ferroelectric layer 640 further switches from a first polarity to a second polarity, and more of the electric dipoles of the ferroelectric domains are oriented with their negative polarities pointing toward the gate electrode 650 and their positive polarities pointing toward the channel region of the substrate 610. Compared to polarization state 700-2, polarization state 700-3 contributes more negative charges to the top surface of the substrate 610 in the channel region, resulting in a further decrease in the threshold voltage of the FeFET device 600 and, therefore, a further increase in the channel conductance relative to the previous polarization state 700-2.

[0060] FIG. 7B shows that increasing the number of boost pulses (increasing the pulse count) with the same amplitude +Vp and pulse width W applied to the gate electrode 650 of the FeFET device 600 increases the partial polarization switching of the ferroelectric domains from the first polarity to the second polarity. The partial polarization switching gradually decreases the threshold voltage Vt of the FeFET device 600, and therefore the channel conductance G of the FeFET device 600. DS Exemplary embodiments of the present disclosure exploit this conductance-polarization property of FeFET device 600 by utilizing FeFET device 600 as a select transistor in a non-volatile analog resistive memory cell to improve the linearity in the conductance adjustment of a resistive memory device during a programming operation (e.g., a synaptic weight update process) in which the conductance adjustment of the resistive memory device is performed using a sequence of identical programming pulses.

[0061] As noted above, the exemplary embodiments of FIGS. 7A and 7B assume that the FeFET device is an N-type FeFET device. It should be understood that the same or similar principles apply to a P-type FeFET device. For example, FIG. 7C schematically illustrates an initial polarization state 701-1 of FeFET device 600, where FeFET device 600 is assumed to be a P-type FeFET device, and the ferroelectric domains of ferroelectric layer 640 have a remnant polarization with a "second polarity" (e.g., positive ferroelectric polarization) in which the electric dipole throughout ferroelectric layer 640 is oriented with its negative pole facing toward gate electrode 650 and its positive pole facing toward the channel region of substrate 610 of FeFET device 600. Polarization state 701-1 imparts a net positive charge to the entire channel region at the top surface of substrate 610, causing negative (majority) charge carriers from substrate 610 to accumulate at the surface of substrate 610 in the channel region. The net effect of polarization state 701-1 is that FeFET device 600 has a first threshold voltage −V T 1. The increase in the negative threshold voltage of the FeFET device 600 having a

[0062] Furthermore, FIG. 7C schematically illustrates polarization states 701-2 and 701-3 of P-type FeFET device 600 resulting from applying a negative polarity boost pulse to gate electrode 650, increasing the partial switching of the remanent polarization of a portion of the ferroelectric domains in ferroelectric layer 640 from the second polarity to the first polarity, and orienting the electric dipoles in the ferroelectric domains with their positive polarity pointing toward gate electrode 650 and their negative polarity pointing toward the channel region of substrate 610. FIG. 7C also illustrates that increasing the number of negative boost pulses (increasing the pulse count) with the same amplitude -Vp and pulse width W applied to gate electrode 650 of P-type FeFET device 600 increases the partial polarization switching of the ferroelectric domains from the second polarity to the first polarity. The partial polarization switching gradually decreases the negative threshold voltage Vt of FeFET device 600, and thus decreases the channel conductance G of FeFET device 600. DSTo return the P-type FeFET device 600 to its initial polarization state 700-1, one or more positive falling pulses (opposite in polarity to the falling pulses shown in FIG. 7A) are applied to the gate electrode 650 of the FeFET device 600.

[0063] It is well known that resistive memory devices, such as the resistive switching device 400 of FIG. 4 and the PCM device of FIG. 5, exhibit nonlinear conductance adjustment when using boost / drop programming schemes with identical programming pulses. Therefore, to achieve linearity in the conductance adjustment of such resistive memory devices, the boost / drop pulse schemes typically implement non-uniform pulse schemes that involve adjusting either the amplitude or pulse width of the boost / drop pulses. For example, adjusting the pulse amplitude involves increasing the amplitude of the pulse (at a fixed pulse width) with each successive programming pulse applied to the resistive memory device to linearly increase (boost) or decrease (drop) the conductance of the resistive memory device in the same gradual adjustment step. On the other hand, adjusting the pulse width involves increasing the pulse width of the pulse (at a fixed amplitude) with each successive programming pulse applied to the resistive memory device to linearly increase (boost) or decrease (drop) the conductance of the resistive memory device in the same gradual adjustment step. These non-uniform pulse schemes add overhead in terms of peripheral circuitry and processing required to implement the amplitude and / or pulse width adjustment. Additionally, pulse width modulation increases the latency of the programming operation.

[0064] 8A and 8B are timing diagrams illustrating a method for programming and reading a nonvolatile analog resistive memory cell implementing a ferroelectric select transistor according to an exemplary embodiment of the present disclosure. For illustrative purposes, FIGS. 8A and 8B are discussed in the context of the nonvolatile analog resistive memory cell 300 of FIG. 3. FIG. 8A illustrates a method 800 for programming the resistive memory cell 300 to adjust the conductance of the resistive memory device 320 using a pulse scheme of identical pulses. In particular, FIG. 8A illustrates a sequence of programming pulses 802 applied to the word line WL, and thus to the gate electrode G of the FeFET select transistor 310, during a pre-cycle period 800-1 and a conductance adjustment period 800-2. FIG. 8A further illustrates an increase control voltage 804 (or first conductance adjustment control voltage) applied to the bit line BL to increase the conductance of the resistive memory device 320, or a decrease control voltage 806 (or second conductance adjustment control voltage) applied to the bit line BL to decrease the conductance of the resistive memory device 320.

[0065] During pre-cycle period 800-1, both the bit line BL and the source line SL are held at ground voltage GND (e.g., V=0), while a relatively small number of programming pulses 802 (e.g., 1-5 pulses) are applied to the word line WL to adjust (e.g., increase) the conductance of the FeFET select transistor 310 to a desired level. The programming pulses 802 have a magnitude +VP and duration sufficient to cause a partial polarization switch of the ferroelectric domains within the ferroelectric layer of the FeFET select transistor 310. For example, in the context of the exemplary embodiment described above in conjunction with FIGS. 7A and 7B, pre-cycle period 800-1 is performed to change the polarization state of the FeFET select transistor 310 from an initial state (e.g., state 700-1, FIG. 7B) to a target polarization state (e.g., state 700-3) in which the FeFET select transistor 310 has a reduced threshold voltage, thereby increasing the channel conductance G of the FeFET select transistor 310. DSThe behavior of the FeFET select transistor 310 will fall within the second portion 710-2 (FIG. 7A) of the build-up period 710. In this way, the FeFET select transistor 310 will have a channel conductance G DS will exhibit a relatively small, gradually linear increase with the additional programming pulse +VP applied from word line WL to the gate electrode during conductance adjustment period 800-2.

[0066] During conductance adjustment period 800-2, the boost process can be initiated by applying a boost control signal 804 to the bit line BL. The boost control signal 804 has a magnitude +VBP and duration (pulse width) sufficient to incrementally increase the conductance of the resistive memory device 320 in response to each programming pulse 802 applied to the word line WL during conductance adjustment period 800-2. The assertion of each programming pulse on the word line WL during conductance adjustment period 800-1 turns on the FeFET select transistor 310, allowing programming current to flow through the resistive memory device 320 from the bit line BL to the source line SL, incrementally increasing the conductance of the resistive memory device 320.

[0067] On the other hand, during conductance adjustment period 800-2, the drop process can be initiated by applying a drop control signal 806 to the bit line BL. The drop control signal 806 has a magnitude -VBP and duration (pulse width) sufficient to progressively decrease the conductance of the resistive memory device 320 in response to each programming pulse 802 applied to the word line WL during conductance adjustment period 800-2. The assertion of each programming pulse on the word line WL during conductance adjustment period 800-1 turns on the FeFET select transistor 310, allowing programming current to flow through the resistive memory device 320 from the source line SL to the bit line BL, progressively decreasing the conductance of the resistive memory device 320.

[0068] The FeFET select transistor 310 serves to increase the linear response of the incremental conductance change of the resistive memory device 320 while using a programming pulse scheme in which the programming pulses 802 are identical in amplitude and pulse width. The identical programming pulses 802 applied to the gate electrode of the FeFET select transistor 310 adjust the polarization (and threshold voltage V) of the FeFET select transistor 310 in a manner that helps adjust and control the programming current generated during the conductance adjustment period 800-1 to incrementally change the conductance of the resistive memory device 320 in a more linear manner. T ) and acts to regulate it.

[0069] More specifically, as described above, during the pre-cycle period 800-1, the polarization (and threshold voltage V) of the FeFET select transistor 310 T ) indicates a relatively small, gradual increase in channel conductance and threshold voltage V in response to further partial polarization switching that occurs in response to a programming pulse applied to the gate of FeFET select transistor 310 during conductance adjustment period 800-2. T The polarization / V of the FeFET device shows a relatively small gradual decrease T The pre-cycle period 800-1 is adjusted by the application of a relatively small number of programming pulses 802 to place the FeFET select transistor 310 in an operating state where the channel conductance G of the FeFET select transistor 310 remains relatively flat. DS and threshold voltage V T This is done to ensure that there are no sudden changes in

[0070] Also, during conductance adjustment period 800-2, as programming pulses are applied to word line WL to adjust the conductance of resistive memory device 320, each programming pulse applied to the gate of FeFET select transistor 310 causes a small change in the polarization state of ferroelectric layer 640, thereby adjusting the threshold voltage V of FeFET select transistor 310. T This is because, for example, V GS -V T (or +VP-V T ) increases, the channel conductance G of the FeFET select transistor 310 DS slightly increase the channel current (I DS ) to increase

[0071] In this manner, the channel conductivity of FeFET select transistor 310 (and thus the channel current I) increases with each subsequent programming pulse during conductance adjustment period 800-2. DS The increase in the channel conductance G of the FeFET select transistor 310 during the conductance adjustment period 800-2 serves to gradually increase the amount of programming current to program to adjust the resistive memory device 320. DS and threshold voltage V T The adjustment of ω serves to increase the linear response in adjusting the conductance of the resistive memory device 320 while using a programming pulse scheme in which the programming pulses 802 are identical in amplitude and pulse width. In other words, the implementation of the FeFET select transistor 310 and the channel conductance G of the FeFET select transistor 310 DS and threshold voltage V T The gradual adjustment of, in conjunction with the uniform programming pulse scheme, substantially emulates a programming scheme in which the programming current is adjusted using a non-uniform pulse scheme applied to the resistive memory cell to adjust the conductance of the resistive memory device.

[0072] It should be understood that programming pulse 802 shown in Figure 8A (and exemplary programming pulses 1102 and 1112 shown in Figures 11A and 11B) is presented for purposes of illustrating the principles of operation of programming an analog resistive memory device using FeFET devices as select transistors. Programming pulse 802 in Figure 8A (and programming pulses 1102 and 1112 in Figures 11A and 11B) can be generated using any suitable technique for performing weight update or memory programming operations in, for example, an RPU crossbar array, a non-volatile analog resistive memory, a neuromorphic computing system, etc. For example, in an RPU crossbar array system, to support an RPU cell weight update operation (e.g., updating the conductance value of the resistive memory device of a given RPU cell 110 in FIG. 1), a probabilistic update process can be implemented whereby programming pulses in conductance adjustment period 800-2 of FIG. 8A (and in conductance adjustment periods 1100-2 and 1110-2 of FIGS. 11A and 11B) are generated in response to a match detection between probabilistic bit streams representing input vectors xi and δj (e.g., see FIG. 2C), and the conductance of a given RPU cell is gradually changed (increased or decreased) in response to a match between the probabilistic pulse streams of xi and δj associated with the given RPU cell, the details of which will be well understood by those skilled in the art. Also, the programming pulses generated for pre-cycle period 800-1 of FIG. 8A (and pre-cycle periods 1100-1 and 1110-1 of FIGS. 11A and 11B) are generated by pulse generation circuitry in the peripheral circuitry, and in some embodiments, a predefined number of programming pulses (having a given magnitude and pulse width) are applied to the row lines to "prime" the FeFET select transistors to the target polarization state.

[0073] FIG. 8B illustrates a method 810 for reading the state of the resistive memory cell 300. In particular, FIG. 8B illustrates a read control pulse 812 applied to the word line WL, and thus to the gate electrode G of the FeFET select transistor 310, during an initialization period 810-1 and a weight read period 810-2. FIG. 8B further illustrates a read current (e.g., I) that is sensed to determine the conductance or resistance state (e.g., synaptic weight) of the resistive memory device 320. READ ) is applied to the bit line BL. In the initialization period 810-1, both the bit line BL and the source line SL are held at the ground voltage GND (e.g., V=0), while the polarization initialization pulse -V INIT (or a reset pulse) is applied to word line WL to switch the polarization of FeFET select transistor 310 to an initial polarization state. For example, in some embodiments, FeFET select transistor 310 is programmed to the initial polarization state 700-1 shown in FIG. 7B, where FeFET select transistor 310 will have an increased threshold voltage and a lower channel conductance.

[0074] In some embodiments, assuming FeFET select transistor 310 is an N-type device, a polarization initialization pulse -V applied to the gate electrode of FeFET select transistor 310 INIT is negative in magnitude and abruptly switches the net polarization of the ferroelectric layer of the FeFET select transistor 310 from the second polarity to the first polarity, thereby placing the channel in a low conductance state (or high V T For example, as shown in FIG. 7A, applying a negative falling pulse to the gate electrode of the FeFET device during the initial period 720-1 of the falling period 720 decreases the channel conductance G of the FeFET device. DS decreases suddenly (hence the threshold voltage V T(a sudden increase in the polarity of the FeFET select transistor 310). Thus, the initialization phase 810-1 reads the state of the memory cell by applying a small read voltage to the bit line BL and places the FeFET select transistor 310 in a preferred operating mode (increased threshold voltage and low channel conductance) to place the FeFET select transistor 310 in an initial polarization state to facilitate programming of the memory cell 300 in the following pre-cycle period 800-1 and conductance adjustment period 800-2.

[0075] 8B further shows that a weighted read period 810-2 is initiated by asserting a read voltage signal 814 having a magnitude +VBR on the bit line BL following the initialization period 810-1. During the weighted read period 810-2, following the assertion of the read voltage signal 814, a read control pulse 812 of a magnitude +VR is applied to the word line WL. The read control pulse +VR turns on the FeFET select transistor 310 to generate a read current I READ The read voltage signal 814 has a magnitude and duration (pulse width) sufficient to allow a voltage V to flow through the resistive memory device 320 from the bit line BL to the source line SL. In this process, the magnitude +VBR of the read voltage signal 814 is selected to have a magnitude smaller than the magnitude +VBP of the boost control signal 804 so that the read voltage signal 814 does not disturb the state of the resistive memory device 320 (i.e., cause a change in conductance). In the read process, the low conductance state of the FeFET select transistor 310 and the small magnitude +VBR of the read voltage signal 814 result in a relatively small read current I that is sufficient to read the state of the memory cell 300 without changing the state of the resistive memory device 320. READ will be generated.

[0076] In some embodiments, the programming and reading operations in FIGS. 8A and 8B are performed by V GS >V T and V DS ≧(V GS -V TThis is done by the FeFET select transistor 310 operating in "saturation mode," where V GS and V T For the drain current I D is V DS In this manner, operating FeFET select transistor 310 in, for example, saturation mode during programming operations allows for further control of the programming current that FeFET select transistor 310 contributes to the overall programming current used to adjust the conductance of resistive memory device 320.

[0077] It should be noted that the characteristics and behavior of the exemplary FeFET device, as discussed above in conjunction with FIGS. 7A, 7B, and 7C, are presented for illustrative purposes to explain the principles of FeFET transistor operation and the use of an FeFET device as a select transistor in a non-volatile resistive memory cell to improve the linearity of conductance adjustment in an analog resistive memory device that inherently has non-linear conductance switching characteristics. In this regard, the exemplary embodiments shown in, for example, FIGS. 7A, 7B, and 7C should not be construed in any limiting manner. For example, the conductance curve shown in FIG. 7A is merely illustrative, and the conductance characteristics of an FeFET device can vary depending on, for example, the structural and electrical characteristics of the FeFET device, the magnitude and pulse width of the pulse used to adjust the polarization of the FeFET device, etc.

[0078] 8A and 8B (and as shown in FIGS. 11A and 11B), it should be understood that the magnitude, polarity, pulse width, etc. of the various control signals shown in FIGS. 8A and 8B (and as shown in FIGS. 11A and 11B) will vary depending on a variety of factors, including, but not limited to, the structural and electrical characteristics of (i) the FeFET device (used as a select transistor) and (ii) the resistive memory device used as the storage element in the non-volatile analog resistive memory cell, the dynamic range (e.g., number) of conductance states of the tunable resistive memory device, etc. For example, the magnitude and pulse width of the programming pulses used to adjust the polarization state of the FeFET device (used as a select transistor) and to adjust the conductance tuning of the resistive memory device can be optimized to achieve the desired conductance tuning behavior as needed for a given application. In other words, the magnitude and duration of the programming pulse (for the same pulse regime) can be designed to achieve a target response of the FeFET device in terms of partial polarization switching of the Fe domains in the ferroelectric layer to improve the linearity in the conductance tuning of the resistive memory device based on the principles discussed herein, and thus achieve a desired behavior / response in threshold voltage and conductance tuning of the FeFET device that makes the FeFET device useful for its purpose as a select transistor.

[0079] Furthermore, while FIG. 3 schematically illustrates an exemplary embodiment of a nonvolatile analog resistive memory cell 300 including a 1T-1R architecture, it should be understood that the same or similar techniques discussed herein for utilizing ferroelectric select transistors to enhance the linearity of analog memory elements can be implemented in other analog resistive memory cell architectures. For example, FIG. 9 schematically illustrates a nonvolatile analog resistive memory cell implementing a ferroelectric select transistor according to another exemplary embodiment of the present disclosure. In particular, FIG. 9 schematically illustrates a nonvolatile analog resistive memory cell 900 that combines first and second 1T-1R memory cells 900-1 and 900-2 (two unit cells) to implement a 2T-2R architecture (alternatively, a 2F-2R architecture) including two ferroelectric select transistors and two resistive memory devices.

[0080] In particular, as shown in FIG. 9 , the first resistive memory cell 900-1 includes a first FeFET select transistor 910-1 and a first resistive memory device 920-1. The first FeFET select transistor 910-1 includes a gate G terminal connected to a word line WL, a source S terminal connected to a first source line SL1, and a drain D terminal connected to one terminal of the first resistive memory device 920-1. The first resistive memory device 920-1 is connected between the drain D terminal and a first bit line BL1. The second resistive memory cell 900-2 includes a second FeFET select transistor 910-2 and a second resistive memory device 920-2. The second FeFET select transistor 910-2 includes a gate G terminal connected to a word line WL, a source S terminal connected to a second source line SL2, and a drain D terminal connected to one terminal of the second resistive memory device 920-2. The second resistive memory device 920-2 is connected between the drain D terminal and the second bit line BL2.

[0081] FIG. 9 illustrates a nonvolatile analog resistive memory cell 900 having a first conductance value G + and the second conductance value G- 9, an exemplary embodiment is provided that includes a pair of identical resistive memory cells 900-1 and 900-2 that store a conductance value based on the difference between a first conductance value G and a second conductance value G. In particular, as shown in FIG. - and the overall conductance value of the 2F-2R analog resistive memory cell 900 is the difference between the first conductance value and the second conductance value, i.e., G + -G - is proportional to.

[0082] In some embodiments, the first and second resistive memory cells 900-1 and 900-2 are adjacent memory cells in a given row of a 2D array of analog resistive memory cells (e.g., adjacent RPU cells 110 in RPU array 100 of FIG. 1). In such embodiments, the gate G terminals of the first and second FeFET select transistors 910-1 and 910-2 are connected to the same word line WL, while the source S terminals of the first and second FeFET select transistors 910-1 and 910-2 are connected to separate (adjacent) source lines SL1 and SL2, respectively, and the first and second resistive memory devices 920-1 and 920-2 are connected to separate (adjacent) bit lines BL1 and BL2, respectively. In another embodiment, the first and second resistive memory cells 900-1 and 900-2 are arranged in the same location in a pair of separate and identical 2D arrays of analog resistive memory cells (e.g., two separate and identical RPU arrays), where the first 2D array is configured to encode positive weight values and the second 2D array is used to encode negative weight values. The first and second pairs of 2D arrays can be stacked together in a wiring structure.

[0083] The exemplary embodiment of FIG. 9 can be implemented in instances where resistive memory technologies of the type used to implement analog resistive memory cells do not readily support bidirectional adjustment. For example, PCM devices are typically configured to support one-way conductance adjustment (e.g., boost) to provide many intermediate conductance states to support MLC, while the opposite-way conductance adjustment (e.g., drop) is abrupt and returns to the extreme conductance state after one or several pulses, thereby not providing intermediate conductance states. Furthermore, because conductance values cannot be negative in resistive memory devices, the exemplary embodiment of FIG. 9 can be implemented in instances where a given application (e.g., SGD for deep learning of neural networks) requires signed weights.

[0084] The first and second 1F-1R memory cells 900-1 and 900-2 of the 2F-2R nonvolatile analog resistive memory cell 900 operate in the same or similar manner as described above in conjunction with Figures 7A, 7B, 8A, and 8B. The first memory cell 900-1 supports boost tuning by applying a boost control signal (e.g., +VBP signal 804, Figure 8A) to the first bit line BL1 to adjust the conductance of the first resistive memory device 920-1, while the second memory cell 900-2 supports boost tuning by applying a boost control signal 806 (Figure 8A) to the second bit line BL2 to adjust the conductance of the second resistive memory device 920-2. The overall conductance value G of the 2F-2R nonvolatile analog resistive memory cell 900 is G + -G - and as will be appreciated by those skilled in the art, the sign of G corresponds to G + -G - If it is >0, it is considered positive, and G + -G -<0 is considered negative. The conductance state of resistive memory devices 920-1 and 920-2 can be "reset" back to their initial conductance state when needed (e.g., a reset (amorphization) pulse applied to the PCM devices to initialize them to HRS). Also, the first and second FeFET select transistors 910-1 and 910-2 can be reset by connecting the source lines SL1 and SL2 and the first and second bit lines BL1 and BL2 to ground GND (e.g., V=0V) and applying a negative initialization pulse to the word line WL (e.g., -V INT The polarization state is periodically refreshed (initialized to the target polarization state) (pulse, Figure 8B).

[0085] FIG. 10 schematically illustrates a nonvolatile analog resistive memory cell implementing a ferroelectric select transistor according to another exemplary embodiment of the present disclosure. In particular, FIG. 10 schematically illustrates a nonvolatile analog resistive memory cell 1000 including a first FeFET select transistor 1010-1, a second FeFET select transistor 1010-2, and a resistive memory device 1020. The first FeFET select transistor 1010-1 is an N-type FeFET device, while the second FeFET select transistor 1010-2 is a P-type FeFET device. The first FeFET select transistor 1010-1 includes a gate G terminal connected to a first word line WL1, and the second FeFET select transistor 1010-2 includes a gate G terminal connected to a second word line WL2, with the first and second word lines WL1 and WL2 comprising complementary word lines for the nonvolatile analog resistive memory cell 1000. First and second FeFET select transistors 1010-1 and 1010-2 have source S terminals connected to respective first and second source lines SL1 and SL2 and drain D terminals connected to one terminal of resistive memory device 1020. Resistive memory device 1020 is connected between the drain D terminals and bit line BL.

[0086] In the exemplary embodiment of FIG. 10, the resistive memory device 1020 is envisioned to have bidirectionally tunable conductance characteristics. For example, in some embodiments, the resistive memory device 1020 includes a resistance-switching device, such as an interfacial resistance-switching device or a filamentary resistance-switching device, as shown in FIG. 4. In bidirectional conductance tuning, the resistance of the resistive memory device 1020 increases or decreases based on the polarity of the programming pulses and voltages applied to the word lines WL1 and WL2 and the bit line BL, and the conductance of the resistive memory device 1020 can increase by potentiation or decrease by depression. The first FeFET select transistor 1010-1 is utilized for potentiation, and the second FeFET select transistor 1010-2 is utilized for depression. Although the bidirectional conductance adjustment of the resistive memory device 1020 may be nonlinear under conditions where the same pulse stream for increasing or decreasing is applied to the resistive memory device 1020, the first and second FeFET select transistors 1010-1 and 1010-2 act to improve the linearity of the bidirectional conductance adjustment of the resistive memory device 1020 based on principles as discussed herein.

[0087] For example, FIG. 11A is a timing diagram illustrating a method for programming the nonvolatile analog resistive memory cell 1000 of FIG. 10 using a boost pulse stream to increase the conductance of the resistive memory device 1020, according to an exemplary embodiment of the present disclosure. More specifically, FIG. 11A illustrates an exemplary programming operation 1100 in which a first FeFET select transistor 1010-1 (N-type) is utilized to increase the conductance of the resistive memory device 1020. The programming operation 1100 includes a pre-cycle period 1100-1 and a conductance adjustment (boost) period 1100-2. FIG. 11A illustrates an exemplary sequence of programming pulses 1102 applied to the first word line WL1 and a boost control voltage 1104 applied to the bit line BL during the programming operation 1100. The second word line WL2 and the first and second source lines SL1 and SL2 are all held at ground GND voltage (e.g., V=0) during the entire programming operation 1100. In this manner, the second FeFET select transistor 1010-2 (P-type) remains in an "off" state during the programming operation 1100.

[0088] The programming operation 1100 begins with a pre-cycle period 1100-1 in which the polarization state of the first FeFET select transistor 1010-1 (N-type) is adjusted using one or more programming pulses prior to the conductance adjustment (boost) period 1100-2. At the start of the pre-cycle period 1100-1, the first FeFET select transistor 1010-1 is assumed to have an initial polarization state, e.g., initial polarization state 700-1 as shown in FIG. 7B. Based on the principles of operation as described above, the pre-cycle period 1100-1 begins with the first FeFET select transistor 1010-1 adjusting its channel conductance G in response to subsequent programming pulses applied on the first word line WL1 during the conductance adjustment period 1100-2. DSThis is done to place the first FeFET select transistor 1010-1 in a partial polarization state that exhibits a relatively small, linear increase in V. During the pre-cycle period 1100-1, the boost control voltage 1104 on the bit line BL is held at ground voltage GND (e.g., V=0), while a relatively small number of programming pulses 1102 (e.g., 1-5 pulses) are applied to the first word line WL1 to adjust the polarization state of the first FeFET select transistor 1010-1 to a desired level (e.g., decrease the threshold voltage and increase the channel conductance).

[0089] Following the pre-cycle period 1100-1, a conductance adjustment (boost) period 1100-2 begins by increasing the boost control voltage 1104 on the bit line BL from ground GND to a target programming voltage level (e.g., +Vdd). During the conductance adjustment period 1100-2, a sequence of one or more identical programming pulses 1102 having positive polarity (e.g., +Vdd) and a given pulse width W is applied to the first word line WL1, progressively increasing the conductance of the resistive memory device 1020 in response to each programming pulse applied to the first word line WL1 during the conductance adjustment (boost) period 1100-2. Each assertion of a programming pulse on the first word line WL1 during the conductance adjustment period 1100-2 turns on the first FeFET select transistor 1010-1, allowing programming current to flow from the bit line BL to the first source line SL1 through the resistive memory device 1020, thereby progressively increasing the conductance of the resistive memory device 1020. Additionally, each assertion of a programming pulse on the first word line WL1 during the conductance adjustment period 1100-2 further adjusts the polarization of the first FeFET select transistor 1010-1, thereby slightly increasing the channel conductance of the first FeFET select transistor 1010-1, which, for the reasons discussed above, serves to improve the linearity of the enhancement adjustment of the resistive memory device 1020.

[0090] Next, FIG. 11B is a timing diagram illustrating a method for programming the nonvolatile analog resistive memory cell 1000 of FIG. 10 using a falling pulse stream to decrease the conductance of the resistive memory device 1020, according to an exemplary embodiment of the present disclosure. More specifically, FIG. 11B illustrates an exemplary programming operation 1110 in which the second FeFET select transistor 1010-2 (P-type) is utilized to decrease the conductance of the resistive memory device 1020. The programming operation 1110 includes a pre-cycle period 1110-1 and a conductance adjustment (fall) period 1110-2. FIG. 11B illustrates an exemplary sequence of programming pulses 1112 applied to the second word line WL2 and a falling control voltage 1114 applied to the second source line SL2 during the programming operation 1110. The first word line WL1, the first source line SL1, and the bit line BL are all held at ground GND voltage (e.g., V=0) during the entire programming operation 1110. In this manner, the first FeFET select transistor 1010-1 (N-type) remains in an "off" state during the programming operation 1110.

[0091] The programming operation 1110 begins with a pre-cycle period 1110-1 during which the polarization state of the second FeFET select transistor 1010-2 (P-type) is adjusted using one or more programming pulses prior to the conductance adjustment (fall) period 1110-2. At the start of the pre-cycle period 1110-1, the second FeFET select transistor 1010-2 is assumed to have an initial polarization state, such as the initial polarization state 701-1 shown in FIG. 7C. Based on the above-described operational principles, the pre-cycle period 1110-1 begins with the second FeFET select transistor 1010-2 adjusting its channel conductance G in response to subsequent programming pulses applied on the second word line WL2 during the conductance adjustment period 1110-2. DSThis is done to place the second FeFET select transistor 1010-2 in a partial polarization state exhibiting a relatively small, linear increase in V. During the pre-cycle period 1110-1, the drop control voltage 1114 on the second source line SL2 is held at ground voltage GND (e.g., V=0), while a relatively small number of programming pulses 1112 (e.g., 1 to 5 pulses) are applied to the second word line WL2 to adjust the polarization state of the second FeFET select transistor to a desired level (e.g., decrease the threshold voltage and increase the channel conductance). As shown in FIG. 11B, the programming pulses in the pre-cycle period 1110-1 have a negative polarity amplitude (e.g., −Vdd) and a given pulse width W.

[0092] Following the pre-cycle period 1110-1, a conductance adjustment (fall-down) period 1110-2 begins by increasing the fall control voltage 1114 on the second source line SL2 from ground GND to a target programming voltage level (e.g., +Vdd). During the conductance adjustment period 1110-2, a sequence of one or more identical programming pulses 1102 is applied to the second word line WL2 to progressively decrease the conductance of the resistive memory device 1020 in response to each programming pulse applied to the second word line WL2 during the conductance adjustment (fall-down) period 1110-2. 11B, the programming pulses in the conductance adjustment (fall) period 1110-2 are "low activity" pulses (as opposed to the "high activity" programming pulses in the conductance (boost) period 1100-2), and the programming pulses have a magnitude of GND voltage (e.g., V=0) and a given width W, as shown in FIG. 11B. In this regard, the assertion of each programming pulse on the second word line WL2 (e.g., transition from WL2 to GND voltage) during the conductance adjustment period 1120-2 turns on the second FeFET select transistor 1010-2, allowing programming current to flow through the resistive memory device 1020 from the second source line SL2 to the bit line BL, thereby progressively decreasing the conductance of the resistive memory device 1020. Additionally, each assertion of a programming pulse on the second word line WL2 during the conductance adjust period 1110-2 further adjusts the polarization of the second FeFET select transistor 1010-2, thereby slightly increasing the channel conductance of the second FeFET select transistor 1010-2, which, for the reasons discussed above, serves to improve the linearity of the drop adjustment of the resistive memory device 1020.

[0093] In some embodiments, the method of reading the nonvolatile analog resistive memory cell 1000 of FIG. 10 is similar to the method shown in FIG. 8B. In particular, in some embodiments, the conductance state of the nonvolatile analog resistive memory cell 1000 of FIG. 10 is set using the first FeFET select transistor 1010-1 (N-type), while the second FeFET select transistor 1010-2 (P-type) is maintained in an "off" state during the read operation. For example, before performing a read operation, the first FeFET select transistor 1010-1 is initialized to an initial polarization state (e.g., state 700-1, FIG. 7B). This initialization process begins by connecting each of the bit line BL, the first and second source lines SL1 and SL2, and the second word line WL2 to a ground GND voltage (e.g., V=0), and applying a polarization initialization pulse -V INIT This is done by applying a reset pulse (or reset pulse) (see, for example, FIG. 8B) to the first word line WL1 to switch the polarization of the first FeFET select transistor 1010-1 back to its initial polarization state.

[0094] Following initialization, a read operation is initiated by asserting a read voltage signal (see, for example, FIG. 8B) having a magnitude +VBR on the bit line BL and then applying a read control pulse on the first word line WL1. The read control pulse turns on the first FeFET select transistor 1010-1, causing a read current I READ 10. The read voltage signal has a magnitude and duration (pulse width) sufficient to allow a voltage signal I to flow from the bit line BL to the first source line SL1 through the resistive memory device 1020. In the read process, the low conductance state of the first FeFET select transistor 1010-1, together with the small magnitude of the read voltage signal on the bit line BL, allows a relatively small read current I to flow through the resistive memory device 1020. READ This results in the generation of

[0095] The second FeFET select transistor 1010-2 (P-type) is periodically initialized to an initial polarization state (e.g., state 701-1, FIG. 7C) so that the second FeFET select transistor 1010-2 is ready for a pre-cycle operation (e.g., 1110-1, FIG. 11B) that precedes a conductance drop trim operation. In some embodiments, the second FeFET select transistor 1010-2 is initialized to a polarization initialization pulse +V INIT The second FeFET select transistor 1010-2 (P-type) is initialized to the initial polarization state by applying an initialization pulse +V (or reset pulse) to the second word line WL2 to switch the polarization of the second FeFET select transistor 1010-2 to the initial polarization state. INIT However, the net polarization of the ferroelectric layer of the second FeFET select transistor 1010-2 is such that the second FeFET select transistor 1010-2 is in a low conductance state (or high V T 7C). The polarization polarity of the polarized light has a positive magnitude and duration (pulse width) sufficient to abruptly switch to the polarization polarity (e.g., polarization state 701-1, see FIG. 7C) in the polarized state (polarized state 701-2).

[0096] It should be understood that the exemplary nonvolatile analog resistive memory devices described herein can be employed in a variety of applications, hardware, or electronic systems, or combinations thereof. Suitable hardware and systems for implementing the exemplary embodiments disclosed herein include, but are not limited to, personal computers, communications networks, electronic commerce systems, portable communications devices (e.g., mobile phones), solid-state media storage devices, functional circuits, and the like. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein.

[0097] The description of various embodiments of the present disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art that do not depart from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, practical applications or technical improvements found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A device comprising a non-volatile analog resistive memory cell, the non-volatile analog resistive memory cell comprising: a resistive memory device including a first terminal and a second terminal; a first select transistor comprising a first ferroelectric field effect transistor (FeFET) device including a gate terminal, a source terminal, and a drain terminal; a second select transistor including a second FeFET device including a gate terminal, a source terminal, and a drain terminal; the gate terminal of the first FeFET device is connected to a first word line and the gate terminal of the second FeFET device is connected to a second word line; the source terminal of the first FeFET device is connected to a first source line and the source terminal of the second FeFET device is connected to a second source line; the drain terminals of the first and second FeFET devices are connected to the first terminal of the resistive memory device; The second terminal of the resistive memory device is connected to a bit line.

2. 10. The device of claim 1, wherein the first FeFET device comprises an N-type device, the second FeFET device comprises a P-type device, and the resistive memory device comprises a resistive switching device having bidirectional tunable conductance.

3. 1. A system comprising a computing system, the computing system including a non-volatile resistive memory including an array of non-volatile analog resistive memory cells, each non-volatile analog resistive memory cell comprising: a resistive memory device including a first terminal and a second terminal, the resistive memory device having a continuously adjustable conductance; at least a first select transistor comprising a first ferroelectric field effect transistor (FeFET) device including a gate terminal, a source terminal, and a drain terminal; a second select transistor including a second FeFET device including a gate terminal, a source terminal, and a drain terminal; the gate terminal of the first FeFET device is connected to a first word line; the source terminal of the first FeFET device is connected to a first source line; the drain terminal of the FeFET device is connected to the first terminal of the resistive memory device; the second terminal of the resistive memory device is connected to a bit line; the gate terminal of the second FeFET device is connected to a second word line; the source terminal of the second FeFET device is connected to a second source line; The drain terminal of the second FeFET device is connected to the first terminal of the resistive memory device.

4. 4. The system of claim 3, wherein the computing system comprises a neuromorphic computing system, and the non-volatile analog resistive memory cells comprise artificial synaptic elements that store synaptic weights representing connection strengths between artificial neurons of the neuromorphic computing system, the synaptic weights being encoded by conductance values of the resistive memory devices of the non-volatile analog resistive memory cells.

5. 4. The system of claim 3, wherein the first FeFET device comprises an N-type device, the second FeFET device comprises a P-type device, and the resistive memory device comprises a resistive switching device having bidirectional tunable conductance.

6. 1. A method comprising: applying a programming pulse on a word line to program a non-volatile analog resistive memory cell coupled to the word line, the non-volatile analog resistive memory cell comprising: a select transistor comprising a ferroelectric field effect transistor (FeFET) device connected to the word line; and a resistive memory device connected to the FeFET device; The application of the programming pulse comprises: adjusting a polarization state of the FeFET device in response to the programming pulse applied to the FeFET device from the word line, the adjustment of the polarization state of the FeFET device causing an adjustment of a programming current to adjust the conductance of the resistive memory device; adjusting the conductance of the resistive memory device by gradually changing the conductance of the resistive memory device with the adjusted programming current generated upon activation of the FeFET device in response to each programming pulse applied to the FeFET device; A method of causing

7. The method of claim 6 , wherein the programming pulses comprise a sequence of voltage pulses having the same amplitude and the same pulse width.

8. 8. The method of claim 6 or claim 7, further comprising performing a pre-cycling process to adjust the polarization state of the FeFET device before adjusting the conductance of the resistive memory device, the pre-cycling process comprising applying one or more pulses from the word line to the FeFET device to adjust the polarization state of the FeFET device from an initial polarization state to a target polarization state without turning on the FeFET device during the pre-cycling process.

9. 9. The method of claim 8, wherein the target polarization state corresponds to a target threshold voltage and associated channel conductance of the FeFET device, and wherein, starting from the target polarization state, the FeFET device exhibits a substantially linear increase in the channel conductance of the FeFET device in response to the programming pulses applied to the FeFET device to adjust the programming current generated to further adjust the polarization of the FeFET device and thereby tune the conductance of the resistive memory device.

10. performing a read operation to determine a conductance state of the nonvolatile analog resistive memory cell, the read operation comprising: performing an initialization process including applying an initialization control pulse on the word line while maintaining the FeFET device in an off state to change the polarization state of the FeFET device to an initial polarization state; 10. The method of claim 6, further comprising: performing a read process following the initialization process, the read process comprising applying a read pulse on the word line to activate the FeFET device and generate a read current representative of the conductance state of the resistive memory device.

11. Adjusting the conductance of the resistive memory device comprises: applying an enhancement tuned control voltage to a bit line, the resistive memory device being connected in series between the bit line and the FeFET device; and progressively increasing the conductance of the resistive memory device in response to each programming pulse applied to the FeFET device.

12. Adjusting the conductance of the resistive memory device comprises: applying a drop-adjust control voltage to a bit line, the resistive memory device being connected in series between the bit line and the FeFET device; and progressively decreasing the conductance of the resistive memory device in response to each programming pulse applied to the FeFET device.

13. The method of any of claims 6 to 12, wherein the resistive memory device comprises a resistive switching device.

14. 13. The method of any of claims 6 to 12, wherein the resistive memory device comprises a phase change memory device.

15. 1. A method comprising: applying a programming pulse to one of a first word line and a second word line to program a non-volatile analog resistive memory cell coupled to the first word line and the second word line, the non-volatile analog resistive memory cell comprising: a first select transistor comprising a first ferroelectric field effect transistor (FeFET) device connected to the first word line; a second select transistor comprising a second FeFET device connected to the second word line; and a resistive memory device connected to the first and second FeFET devices; applying the programming pulse to the first word line adjusting a polarization state of the first FeFET device in response to the programming pulse applied to the first FeFET device from the word line, the adjustment of the polarization state of the first FeFET device causing an adjustment of a programming current to adjust the conductance of the resistive memory device; adjusting the conductance of the resistive memory device by progressively increasing the conductance of the resistive memory device with the adjusted programming current generated upon activation of the first FeFET device in response to each programming pulse applied to the first FeFET device while the second FeFET device is maintained in an off state; applying the programming pulse to the second word line adjusting a polarization state of the second FeFET device in response to the programming pulse applied to the second FeFET device from the word line, the adjustment of the polarization state of the second FeFET device causing an adjustment of a programming current to adjust the conductance of the resistive memory device; adjusting the conductance of the resistive memory device by progressively decreasing the conductance of the resistive memory device with the adjusted programming current generated upon activation of the second FeFET device in response to each programming pulse applied to the second FeFET device while the first FeFET device is maintained in an off state; A method of causing

16. 16. The method of claim 15, wherein the programming pulses comprise a sequence of voltage pulses having the same amplitude and the same pulse width.

17. performing a first pre-cycle process to adjust the polarization state of the first FeFET device prior to adjusting the conductance of the resistive memory device, the first pre-cycle process including applying one or more pulses from the first word line to the first FeFET device to adjust the polarization state of the first FeFET device from a first initial polarization state to a first target polarization state without turning on the first and second FeFET devices during the first pre-cycle process; 17. The method of claim 15 or claim 16, further comprising: performing a second pre-cycle process to adjust the polarization state of the second FeFET device prior to adjusting the conductance of the resistive memory device, the second pre-cycle process applying one or more pulses from the second word line to the second FeFET device to adjust the polarization state of the second FeFET device from a second initial polarization state to a second target polarization state without turning on the first and second FeFET devices during the second pre-cycle process.

18. the first target polarization state corresponds to a first target threshold voltage and associated channel conductance of the first FeFET device, and starting from the first target polarization state, the first FeFET device exhibits a substantially linear increase in the channel conductance of the first FeFET device in response to the programming pulses applied to the first FeFET device from the first word line to adjust the programming current generated to further adjust the polarization of the first FeFET device and thereby tune the conductance of the resistive memory device; 18. The method of claim 17, wherein the second target polarization state corresponds to a second target threshold voltage and associated channel conductance of the second FeFET device, and wherein, starting from the second target polarization state, the second FeFET device exhibits a substantially linear increase in the channel conductance of the second FeFET device in response to the programming pulses applied to the second FeFET device from the second word line to adjust the programming current generated to further adjust the polarization of the second FeFET device, thereby tuning the conductance of the resistive memory device.

19. performing a read operation to determine a conductance state of the nonvolatile analog resistive memory cell, the read operation comprising: performing an initialization process including applying an initialization control pulse on the first word line to change the polarization state of the first FeFET device to an initial polarization state while maintaining the first and second FeFET devices in an off state; 19. The method of claim 15, further comprising: performing a read process following the initialization process, the read process comprising applying a read pulse on the first word line to activate the first FeFET device while maintaining the second FeFET device in an off state, to generate a read current representative of the conductance state of the resistive memory device.

20. 20. The method of claim 15, wherein the first FeFET device comprises an N-type device, the second FeFET device comprises a P-type device, and the resistive memory device comprises a resistive switching device having bidirectional tunable conductance.

21. 21. A computer program comprising program code adapted to perform the steps of the method according to any of claims 6 to 20 when said program is run on a computer.

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