Packaging substrate and semiconductor device including same

Abstract

To provide a packaging substrate that is further integrated by applying a glass substrate, and a semiconductor apparatus including the same.SOLUTION: A semiconductor apparatus 100 includes a semiconductor element unit 30 including semiconductor elements 32, 34 and 36; and a packaging substrate 20 electrically connected to the semiconductor element unit. The semiconductor apparatus, with a glass substrate adopted as a core of the packaging substrate, thereby can significantly improve electrical properties such as a signal transmission rate by connecting the semiconductor element and a motherboard 10 to be closer to each other so that electrical signals are transmitted through as short a path as possible. Therefore, it can significantly improve electrical properties such a signal transmission rate, substantially prevent generating of parasitic element, and simplify a process of treatment for an insulating layer, and thus provides a packaging substrate applicable to a high-speed circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The embodiment relates to a packaging substrate and a semiconductor device including the same.

[0002] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0003] This application claims the benefit of priority from U.S. Provisional Patent Application No. 62 / 814,941, filed March 7, 2019, and U.S. Provisional Patent Application No. 62 / 816,965, filed March 12, 2019, the contents of which are incorporated herein by reference. [Background technology]

[0004] In the production of electronic components, the process of creating circuits on semiconductor wafers is called the front-end process (FE), and the process of assembling the wafers so that they can be used in actual products is called the back-end process (BE), which includes the packaging process.

[0005] The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, including nano-level line widths, more than 10 million cells, high-speed operation, and high heat dissipation, but the technology to perfectly package this has been relatively lacking. Therefore, the electrical performance of semiconductors is sometimes determined by packaging technology and the resulting electrical connections rather than the performance of the semiconductor technology itself.

[0006] Ceramic or resin is used as the material for the packaging substrate. Ceramic substrates have high resistance or dielectric constant, making it difficult to mount high-performance, high-frequency semiconductor devices. Resin substrates can mount relatively high-performance, high-frequency semiconductor devices, but there is a limit to how much the wiring pitch can be reduced.

[0007] In recent years, research into the application of silicon and glass to high-end packaging substrates has been ongoing. By forming through-holes in silicon or glass substrates and filling these with conductive materials, the length of the wiring between the device and the motherboard can be shortened, resulting in superior electrical characteristics.

[0008] Related prior literature includes: Korean Patent Publication No. 10-2019-0008103, Korean Patent Publication No. 10-2016-0114710, Korean Patent Registration No. 10-1468680. Summary of the Invention [Problem to be solved by the invention]

[0009] An object of the embodiment is to provide a more integrated packaging substrate and a semiconductor device including the same by applying a glass substrate.

[0010] [Means for solving the problem]

[0011] To achieve the above object, a semiconductor device according to one embodiment includes: a semiconductor device unit in which one or more semiconductor devices are located; a packaging substrate electrically connected to the semiconductor devices; and a motherboard electrically connected to the packaging substrate, transmitting external electrical signals to the semiconductor devices and connecting the semiconductor devices to each other; the packaging substrate includes a core layer and an upper layer positioned on the core layer; the core layer includes a glass substrate and a core via; the glass substrate has a first surface and a second surface facing each other; The core vias penetrate the glass substrate in a thickness direction, and a large number of the core vias are arranged. the core layer includes a core distribution layer located on a surface of the glass substrate or a core via; the core distribution layer includes an electrically conductive layer, at least a portion of which electrically couples the electrically conductive layer on the first surface to the electrically conductive layer on the second surface through the core via; the core via includes a first opening, a second opening, and a minimum inner diameter portion; the first opening is an opening that contacts the first surface, the second opening is an opening that contacts the second surface, the minimum inner diameter portion is located between the first opening and the second opening and is a portion having a narrowest diameter; When the distance from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core via is taken as 100%, the thickness of the electrically conductive layer is about 90% or more.

[0012] In one embodiment, at an opening where the larger of the diameters of the first side opening and the second side opening is located, the thickness of the electrically conductive layer may be 90% or more when the distance from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%.

[0013] the core distribution layer includes a first surface core pattern, which is an electrically conductive layer located on at least a portion of the first surface; a second surface core pattern, which is an electrically conductive layer located on at least a portion of the second surface; and a core via pattern, which is an electrically conductive layer that electrically connects the first surface core pattern and the second surface core pattern to each other through the core vias; The core via pattern has an average distance of 1 μm or less between one surface of the core via pattern that is closest to the inner diameter surface of the core via and the inner diameter surface of the core via.

[0014] The upper layer includes an upper insulating layer and an upper distribution pattern.

[0015] the upper insulating layer is located on the first surface; The upper distribution pattern is embedded in the upper insulating layer as an electrically conductive layer, at least a portion of which is electrically connected to the core distribution layer, the upper distribution pattern includes a fine pattern in at least a portion thereof; The width and spacing of the fine patterns are each less than 4 μm.

[0016] In one embodiment, when the distance from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core via at the position of the smallest inner diameter portion is taken as 100%, the thickness of the electrically conductive layer is about 95% or more.

[0017] In the core via pattern, an average distance between one surface of the core via pattern that is close to the inner diameter surface of the core via and the inner diameter surface of the core via may be 1 μm or less.

[0018] The glass substrate may have a surface roughness (Ra) of 10 angstroms or less.

[0019] When the distance from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core via is taken as 100%, the thickness of the electrically conductive layer may be approximately 90% or more at the position of the larger of the first opening and the second opening.

[0020] The packaging substrate may include a lower layer disposed below the core layer.

[0021] The lower layer may include a lower distribution layer and a lower connection layer.

[0022] The lower distribution layer may include a lower insulating layer, at least a portion of which contacts the second surface, and a lower distribution pattern embedded in the lower insulating layer, having a predetermined pattern, at least a portion of which is electrically connected to the core distribution layer.

[0023] The lower connection layer may include a lower connection electrode and a lower connection pattern.

[0024] The bottom connection electrode may be electrically connected to the bottom connection pattern.

[0025] At least a portion of the lower connection pattern may be electrically connected to the lower distribution pattern, and at least a portion of the lower connection pattern may be exposed on one surface of the lower insulating layer.

[0026] In one embodiment, the packaging substrate has a resistance of about 27.5×10 when cut into a size of 100 μm×100 μm based on the top surface. -6 It may be Ω or less.

[0027] The electrically conductive layer of the core distribution layer may have an adhesive strength of 3 N / cm or more to the glass substrate.

[0028] The lower surface connecting pattern may be a non-fine pattern. [Effects of the Invention]

[0029] The packaging substrate and the semiconductor device including the packaging substrate of the embodied example can connect the semiconductor device and the motherboard more closely, allowing electrical signals to be transmitted over the shortest possible distance, thereby significantly improving electrical characteristics such as signal transmission speed.

[0030] In addition, the glass substrate used as the core of the substrate is itself an insulator, so there is almost no risk of parasitic elements occurring compared to existing silicon cores, which simplifies the insulating film processing process and makes it applicable to high-speed circuits.

[0031] In addition, unlike silicon, which is manufactured in the form of a round wafer, glass substrates are manufactured in the form of large panels, which makes mass production relatively easy and further improves economic efficiency. [Brief explanation of the drawings]

[0032] [Figure 1] 1 is a conceptual diagram illustrating a cross section of a semiconductor device according to an embodiment; [Figure 2] FIG. 10 is a conceptual diagram illustrating a cross section of a packaging substrate according to another embodiment; [Figure 3] 10A and 10B are conceptual diagrams illustrating the cross section of a core via applied in the embodiment. [Figure 4] 1 is a conceptual diagram illustrating a state in which a core distribution pattern is formed on a glass substrate and the thickness of an electrically conductive layer in a cross section. [Figure 5] FIG. 2 is a detailed conceptual diagram illustrating a part of a cross section of a packaging substrate according to an embodiment. [Figure 6] FIG. 2 is a detailed conceptual diagram illustrating a part of a cross section of a packaging substrate according to an embodiment. [Figure 7] 1 is a flowchart illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment. [Figure 8] 1 is a flowchart illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment. [Figure 9] 1 is a flowchart illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0033] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The following detailed description of the preferred embodiments will be made with reference to the accompanying drawings so that those skilled in the art can easily understand the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. The same reference numerals are used throughout the specification to refer to similar parts.

[0034] Throughout this specification, the term "combinations thereof" contained in a Markush expression means a mixture or combination of one or more selected from the group consisting of each component described in the Markush expression, and means including one or more selected from the group consisting of each component.

[0035] Throughout this specification, terms such as "first," "second," "A," and "B" are used to distinguish between identical terms, and singular expressions include plural expressions unless the context clearly dictates otherwise.

[0036] In this specification, the term "based on" may mean that the compound includes "a compound corresponding to" or "a derivative of."

[0037] In this specification, "B is located on A" means that B is located on A in direct contact with A, or that B is located on A with another layer located therebetween, and is not to be interpreted as being limited to B being located in contact with the surface of A.

[0038] In this specification, when B is linked to A, it means that A and B are directly linked or that A and B are linked via another component therebetween, and unless otherwise specified, it is not to be interpreted as being limited to A and B being directly linked.

[0039] In this specification, unless otherwise specified, the singular expression is to be construed as including the singular or plural as the context requires.

[0040] In the process of developing a semiconductor device that is more integrated and can achieve high performance despite its thinness, the inventors recognized that not only the element itself but also the packaging is an important factor in improving performance. Through their research into this, they found that, unlike existing interposers and organic substrates, which use two or more layers of cores on a motherboard as a packaging substrate, by applying a single layer of glass core and controlling the shape of the through vias and the electrically conductive layer formed thereon, it is possible to make the packaging substrate thinner and improve the electrical characteristics of the semiconductor device, thereby completing the invention.

[0041] Figure 1 is a conceptual diagram illustrating a cross section of a semiconductor device according to an embodiment, and Figure 2 is a conceptual diagram illustrating a cross section of a packaging substrate according to another embodiment. Figures 3(a) and 3(b) are conceptual diagrams illustrating the cross section of a core via applied in an embodiment, Figure 4 is a conceptual diagram illustrating the state in which a core distribution pattern is formed on a glass substrate and the thickness of an electrically conductive layer in cross section, and Figures 5 and 6 are detailed conceptual diagrams illustrating a portion of the cross section of a packaging substrate according to an embodiment. Hereinafter, embodiments will be described in more detail with reference to Figures 1 to 5.

[0042] To achieve the above object, the semiconductor device 100 according to the embodiment includes a semiconductor device unit 30 in which one or more semiconductor devices 32, 34, and 36 are located; a packaging substrate 20 electrically connected to the semiconductor devices; and a motherboard 10 electrically connected to the packaging substrate, transmitting external electrical signals to the semiconductor devices, and connecting the semiconductor devices to each other.

[0043] The packaging substrate 20 according to another embodiment includes a core layer 22 and a top layer 26 .

[0044] The semiconductor element section 30 refers to each element mounted on the semiconductor device, and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, the semiconductor element section 30 may be, for example, a computing element such as a CPU or a GPU (first element: 32, second element: 34), a storage element such as a memory chip (third element, 36), or the like, but any semiconductor element mounted on a semiconductor device may be used without any restrictions.

[0045] The motherboard 10 may be a printed circuit board, a printed wiring board, or the like.

[0046] The packaging substrate 20 includes a core layer 22 and a top layer 26 located on one side of the core layer.

[0047] The packaging substrate 20 may optionally further include a lower layer 29 located below the core layer.

[0048] The core layer 22 includes a glass substrate 21; a number of core vias 23 penetrating the glass substrate in the thickness direction; and a core distribution layer 24 on the surface of the glass substrate or the core vias, in which an electrically conductive layer is located, at least a portion of which electrically connects the electrically conductive layers on the first surface and the second surface through the core vias.

[0049] The glass substrate 21 has a first surface 213 and a second surface 214 facing each other, the two surfaces being generally parallel to each other, and has a constant thickness throughout the glass substrate.

[0050] The glass substrate 21 has a core via 23 that penetrates through the first surface and the second surface.

[0051] Conventionally, packaging substrates for semiconductor devices have been formed by stacking a silicon substrate and an organic substrate. Silicon substrates, due to their semiconductor characteristics, have drawbacks, such as the risk of parasitic elements occurring when applied to high-speed circuits, resulting in relatively large power losses. Furthermore, organic substrates require larger areas to form increasingly complex distribution patterns, which is not in line with the trend toward miniaturized electronic devices. Forming complex distribution patterns within a given size requires substantial pattern miniaturization, but the characteristics of materials, such as polymers, used in organic substrates have substantial limitations on pattern miniaturization.

[0052] In this embodiment, to solve this problem, a glass substrate 21 is used as a support for the core layer 22. In addition, by using a core via 23 formed through the glass substrate together with the glass substrate, the length of electrical flow is further shortened, providing a packaging substrate 20 that is more compact, has faster response, and has lower loss characteristics.

[0053] The glass substrate 21 is preferably a glass substrate used in semiconductors, and examples of glass substrates that can be used include, but are not limited to, borosilicate glass substrates and alkali-free glass substrates.

[0054] The thickness of the glass substrate 21 may be 1,000 μm or less, 100 μm to 1,000 μm, or 100 μm to 700 μm. More specifically, the thickness of the glass substrate 21 may be 100 μm to 500 μm. Forming a thinner packaging substrate is advantageous in that it can transmit electrical signals more efficiently, but since it must also function as a support, it is preferable to use a glass substrate 21 having the above thickness. Here, the thickness of the glass substrate refers to the thickness of the glass substrate itself, excluding the thickness of the electrically conductive layer located on the glass substrate.

[0055] The core via 23 may be formed by removing a predetermined region of the glass substrate 21, specifically, by etching the glass plate using physical and / or chemical methods.

[0056] Specifically, when forming the core via 23, a defect (groove) may be formed on the surface of the glass substrate using a laser or other method, followed by chemical etching, laser etching, etc., but is not limited thereto.

[0057] The core via 23 includes a first opening 233 in contact with the first surface; a second opening 234 in contact with the second surface; and a minimum inner diameter portion 235 which is the area with the narrowest inner diameter in the entire core via connecting the first opening and the second opening.

[0058] The diameter of the first opening (CV1) and the diameter of the second opening (CV2) may be substantially different or may be substantially the same.

[0059] The minimum inner diameter portion may be located at the first opening or the second opening, and the core via may be cylindrical or (truncated) triangular pyramidal. In this case, the diameter (CV3) of the minimum inner diameter portion corresponds to the diameter of the smaller one of the first opening and the second opening.

[0060] The minimum inner diameter portion may be located between the first opening and the second opening, and the core via may be a barrel-type core via. In this case, the diameter (CV3) of the minimum inner diameter portion may be smaller than the larger of the diameters of the first opening and the second opening.

[0061] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass substrate through through vias, and a core insulating layer 223 that covers the core distribution pattern.

[0062] The core layer 22 has an electrically conductive layer formed therein through a core via, which serves as an electrical path across the glass substrate 21 and connects the top and bottom of the glass substrate over a relatively short distance, allowing for faster electrical signal transmission and low loss.

[0063] The core distribution pattern 241 is a pattern that electrically connects the first surface 213 and the second surface 214 of the glass substrate through core vias 23, and specifically includes a first surface distribution pattern 241a that is an electrically conductive layer located on at least a portion of the first surface 213, a second surface distribution pattern 241c that is an electrically conductive layer located on at least a portion of the second surface 214, and a core via distribution pattern 241b that is an electrically conductive layer that electrically connects the first surface distribution pattern and the second surface distribution pattern to each other through the core vias 23. Each of the electrically conductive layers may be, for example, a copper plating layer, but is not limited thereto.

[0064] The core via 23 includes a first opening 233 in contact with the first surface; a second opening 234 in contact with the second surface; and a minimum inner diameter portion 235 which is the area with the narrowest inner diameter in the entire core via connecting the first opening and the second opening.

[0065] The glass substrate 21 acts as an intermediate and mediator connecting the upper and lower portions of the semiconductor device part 30 and the motherboard 10, respectively, and the core vias 23 act as a path for transmitting electrical signals, thereby facilitating the transmission of signals.

[0066] The thickness of the electrically conductive layer measured at the larger of the diameter of the first side opening and the diameter of the second side opening may be equal to or thicker than the thickness of the electrically conductive layer formed on the portion of the core via having the smallest inner diameter.

[0067] The core distribution layer 24 is an electrically conductive layer formed on a glass substrate, and may have a value of 4B or more, specifically 5B or more, in the cross-cut adhesion test according to ASTM D3359. Furthermore, the electrically conductive layer serving as the core distribution layer 24 may have an adhesive strength of 3N / cm or more to the glass substrate, and a bonding strength of 4.5N / cm or more. When such a bonding strength is satisfied, the bonding strength between the substrate and the electrically conductive layer is sufficient for use as a packaging substrate.

[0068] An upper layer 26 is located on the first surface 213 .

[0069] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer, and the top surface of the upper layer 26 can be protected by a cover layer 60 having an opening formed therein to which the connection electrode of the semiconductor element portion can directly abut.

[0070] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface and an upper distribution pattern 251 having a predetermined pattern and embedded in the upper insulating layer as an electrically conductive layer, at least a portion of which is electrically connected to the core distribution layer 24.

[0071] The upper insulating layer 253 may be any material that can be used as an insulating layer for a semiconductor device or a packaging substrate, such as, but not limited to, an epoxy resin containing a filler.

[0072] The insulator layer may be formed by forming a coating layer and curing it, or by laminating an insulator film in an uncured or semi-cured state onto the core layer and curing it. In this case, if a pressure-sensitive lamination method is used, the insulator can be embedded even in the space inside the core via, allowing for efficient processing. Even when multiple insulator layers are stacked, it may be difficult to substantially distinguish between the insulator layers, and the multiple insulator layers are collectively referred to as the upper insulating layer. The core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, and in this case, the boundary between them may not be substantially distinct.

[0073] The upper distribution pattern 251 refers to an electrically conductive layer located in the upper insulating layer 253 in a predetermined shape, and may be formed, for example, by a build-up layer method. Specifically, an insulating layer is formed, unnecessary portions of the insulating layer are removed, and then an electrically conductive layer is formed by copper plating or the like, unnecessary portions of the electrically conductive layer are removed, and then an insulating layer is formed again on the electrically conductive layer, unnecessary portions are removed again, and then an electrically conductive layer is formed by plating or the like. By repeating this process, the upper distribution pattern 251 having an electrically conductive layer formed vertically or horizontally in a desired pattern may be formed.

[0074] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device part 30, and is formed to include a fine pattern at least in part so that electrical signals can be smoothly transmitted to the semiconductor device part 30 and the intended complex pattern can be sufficiently accommodated. In this case, the width and spacing of the fine pattern may be less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 μm to 2.3 μm, respectively. The spacing may be the spacing between adjacent fine patterns (the same applies to the fine pattern below).

[0075] In order to form the upper distribution pattern 251 to include a fine pattern, at least two methods are used in the embodiment.

[0076] One method is to use a glass substrate 21 as the glass substrate of the packaging substrate. The glass substrate 21 can have a surface roughness (Ra) of 10 angstroms or less and a fairly flat surface characteristic, thereby minimizing the influence of the surface morphology of the support substrate on the formation of the fine pattern.

[0077] Another method is based on the characteristics of the insulator. Insulators often incorporate a filler component along with a resin, and inorganic particles such as silica particles can be used as the filler. When inorganic particles are used as a filler in an insulator, the size of the inorganic particles can affect whether or not a fine pattern is formed. The insulator employed in the present embodiment includes a particulate filler having an average diameter of 150 nm or less, specifically, a particulate filler having an average diameter of 1 nm to 100 nm. These characteristics minimize the influence of the insulator itself on the formation of an electrically conductive layer having a width of several micrometers while maintaining the physical properties required for the insulator above a certain level, and the fine surface morphology facilitates the formation of a fine pattern with excellent adhesion on the surface.

[0078] The top connection layer 27 includes a top connection pattern 272 located on the upper insulating layer 253, at least a portion of which is electrically connected to the top distribution pattern 251, and a top connection electrode 271 electrically connecting the semiconductor device unit 30 and the top connection pattern 272. The top connection pattern 272 may be located on one surface of the upper insulating layer 253, or may be embedded with at least a portion thereof exposed on the upper insulating layer. For example, when the top connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by plating or the like. When the top connection pattern is embedded with a portion thereof exposed on the upper insulating layer, a copper plating layer may be formed, and then a portion of the insulating layer or the electrically conductive layer may be removed by surface polishing, surface etching, or the like.

[0079] The top surface connection pattern 272 may include a fine pattern at least in part, like the above-described upper distribution pattern 251. The top surface connection pattern 272 including such a fine pattern can electrically connect a larger number of devices in a small area, facilitate smooth connection of electrical signals between devices or with the outside, and enable more integrated packaging.

[0080] The upper surface connection electrode 271 may be directly connected to the semiconductor device part 30 using a terminal or the like, or may be connected to the semiconductor device part 30 using a device connection part 51 such as a solder ball.

[0081] The packaging substrate 20 is also connected to the motherboard 10. The motherboard 10 may be directly connected to a second surface distribution pattern 241c, which is a core distribution layer located on at least a portion of the second surface 214 of the core layer 22, through a terminal of the motherboard, or may be electrically connected to the second surface distribution pattern 241c through a board connection part such as a solder ball. In addition, the second surface distribution pattern 241c may be connected to the motherboard 10 through a lower layer 29 located below the core layer 22.

[0082] The lower layer 29 includes a lower distribution layer 291 and a lower connection layer 292 .

[0083] The lower distribution layer 291 includes: i) a lower insulating layer 291b, at least a portion of which contacts the second surface 214; and ii) a lower distribution pattern 291a, which is embedded in the lower insulating layer and has a predetermined pattern, and to which at least a portion of which is electrically connected the core distribution layer.

[0084] The lower connection layer 292 may include i) a lower connection electrode 292a electrically connected to the lower connection pattern, and ii) a lower connection pattern 292b electrically connected to at least a portion of the lower distribution pattern and at least a portion of which is exposed on one surface of the lower insulating layer.

[0085] The lower surface connection pattern 292b is a portion connected to the motherboard 10, and unlike the upper surface connection pattern 272, may be formed as a non-fine pattern having a width wider than a fine pattern for more efficient transmission of electrical signals.

[0086] One of the features of the present invention is that the packaging substrate 20 located between the semiconductor device part 30 and the motherboard 10 does not substantially include any additional substrate other than the glass substrate 21.

[0087] In the past, an interposer and an organic substrate were stacked together to connect a device to a motherboard. It is understood that this multi-layer structure was adopted for at least two reasons. One reason is that directly bonding the fine patterns of the device to the motherboard poses a scale problem. The other reason is that wiring damage may occur due to differences in thermal expansion coefficients during the bonding process or during operation of the semiconductor device. In this embodiment, these problems are solved by using a glass substrate with a thermal expansion coefficient similar to that of the semiconductor device, and forming a fine pattern with a scale fine enough for device mounting on the first surface of the glass substrate and its upper layer.

[0088] In an embodiment, the thickness of the electrically conductive layer constituting the core via distribution pattern 214b may be about 90% or more, about 93% to about 100%, or about 95% to about 100%, when the distance from the inner diameter surface of the core via 23 to the surface of the core via distribution pattern 214b is taken as 100%. More specifically, the thickness of the electrically conductive layer constituting the core via distribution pattern 214b may be about 97% to about 100%, or about 96% to about 100%, when the distance from the inner diameter surface of the core via 23 to the surface of the core via distribution pattern 214b is taken as 100%.

[0089] Specifically, when the distance (Dt3) from the inner diameter surface of the core via 23 to the surface of the core via distribution pattern 214b at the position of the smallest inner diameter is taken as 100%, the thickness (Tcv3) of the electrically conductive layer may be approximately 90% or more, approximately 93% to approximately 100%, approximately 95% to approximately 100%, or approximately 95.5% to approximately 99%.

[0090] Specifically, at the opening where the larger of the diameters of the first surface opening and the second surface opening is located, when the distance from the inner diameter surface of the core via 23 to the surface of the core via distribution pattern 214b (Dt2, assuming that the diameter of the second surface opening is even larger) is taken as 100%, the thickness (Tcv2) of the electrically conductive layer may be approximately 90% or more, may be approximately 93% to approximately 100%, may be approximately 95% to approximately 100%, or may be approximately 98% to approximately 99.9%.

[0091] In this way, when the thickness of the core via distribution pattern, which is an electrically conductive layer inside the core via, is formed substantially thick, smoother electrical conductivity can be obtained, and the process of connecting electrical signals from highly integrated devices to the motherboard can be made more efficient.

[0092] Also, one feature of the embodiment is that the electrically conductive layer formed on the inner diameter surface of the core via is located close to the surface of the glass substrate (the inner diameter surface of the core via).

[0093] Specifically, the core via pattern may have an average distance between i) one surface of the core via pattern closest to the inner diameter surface of the core via and ii) the inner diameter surface of the core via of approximately 1 μm or less, approximately 0.9 μm, or approximately 0.01 μm to approximately 0.9 μm.

[0094] The space corresponding to the distance may be filled with an inorganic material or an organic-inorganic composite material that improves adhesion between the core via pattern and the glass surface or serves as a seed during plating. The organic-inorganic composite material may have a layered structure that is continuously observed in its cross section, and in this case, the average thickness of the layered structure may correspond to the average distance. The organic-inorganic composite material may have a dotted structure in which particles are not continuously observed in its cross section but are regularly or irregularly spaced apart. When the organic-inorganic composite material has a dotted structure, the distance refers to an average value.

[0095] In the minimum inner diameter portion, the core via pattern may have a distance (F3) between i) one surface of the core via pattern closest to the inner diameter surface of the core via and ii) the inner diameter surface of the core via of about 1 μm or less, about 0.7 μm or less, or about 0.01 μm to about 0.7 μm. At this distance (F3), an organic layer, organic-inorganic composite layer, adhesive layer, etc. having a thickness of about 1 μm or more may not be formed between the inner diameter surface and the electrically conductive layer.

[0096] In the first opening, the core via pattern may have a distance (not shown) between i) one surface of the core via pattern closest to the inner diameter surface of the core via and ii) the inner diameter surface of the core via of about 1 μm or less, about 0.9 μm or less, or about 0.01 μm to about 0.9 μm. At this distance, a separate adhesive layer having a thickness of about 1 μm or more may not be formed between the inner diameter surface and the electrically conductive layer.

[0097] In the second opening, the core via pattern may have a distance (F2) between i) one surface of the core via pattern closest to the inner diameter surface of the core via and ii) the inner diameter surface of the core via of about 1 μm or less, about 0.9 μm or less, or about 0.01 μm to about 0.9 μm. With this distance (F2), a separate adhesive layer having a thickness of about 1 μm or more may not be formed between the inner diameter surface and the electrically conductive layer.

[0098] The distance (not shown) at the first opening, the distance (F2) at the second opening, and the distance (F3) at the minimum inner diameter portion respectively refer to the distance measured along an extension of the first surface of the glass substrate, the distance measured along an extension of the second surface, and the distance measured along an imaginary line substantially parallel to the first or second surface of the glass at the minimum inner diameter portion.

[0099] In this way, when the core via distribution pattern, which is an electrically conductive layer inside the core via, is formed close to the inner diameter surface, a substantially thicker electrically conductive layer can be manufactured under the same conditions, resulting in smoother electrical conductivity than intended and making the process of connecting electrical signals from highly integrated devices to the motherboard more efficient.

[0100] The semiconductor device 100 includes a packaging substrate 20 having a relatively thin thickness, which allows the overall thickness of the semiconductor device to be reduced, and by applying a fine pattern, the intended electrical connection pattern can be arranged even in a smaller area. Specifically, the thickness of the packaging substrate may be about 2000 μm or less, about 1500 μm or less, or about 900 μm. The thickness of the packaging substrate may also be about 120 μm or more, or about 150 μm or more. Due to the characteristics described above, the packaging substrate can electrically and structurally stably connect the device and the motherboard even with a relatively thin thickness, thereby contributing to the miniaturization and thinning of semiconductor devices.

[0101] The resistance value of a piece cut into a size of 100 μm×100 μm based on the upper surface of the packaging substrate 20 is about 2.6×10 -6 Ω or more, and may be about 3.6×10 -6 Ω or more, and may be approximately 20.6×10 -6 The resistance of the packaging substrate may be about 27.5×10 Ω or more. -6 Ω or less, and may be approximately 25.8×10 -6 Ω or less, and may be approximately 24.1×10 -6 The resistance may be Ω or less. Exemplarily, the resistance value is measured by measuring the resistance between the upper and lower electrically conductive layers of a piece cut to a certain size as described above, and is measured when the upper and lower electrically conductive layers are connected to each other by a core via pattern. The resistance value may be measured by the method described in the following experimental example. A packaging substrate satisfying the resistance value can easily transmit an electrical signal to the outside.

[0102] 7 to 9 are flow charts illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment. Hereinafter, a manufacturing method of a packaging substrate according to another embodiment will be described with reference to FIGS.

[0103] The method for manufacturing a packaging substrate of an embodiment includes a preparation step of forming defects at predetermined positions on the first and second surfaces of a glass substrate; an etching step of applying an etching solution to the glass substrate on which the defects have been formed to provide a glass substrate on which core vias have been formed; a core layer fabrication step of manufacturing a core layer by plating the surface of the glass substrate on which the core vias have been formed to form a core distribution layer, which is an electrically conductive layer; and an upper layer fabrication step of forming an upper distribution layer, which is an electrically conductive layer covered with an insulating layer, on one surface of the core layer, to manufacture the packaging substrate described above.

[0104] The core layer manufacturing step may include a pretreatment process of forming an organic-inorganic composite primer layer containing nanoparticles having amine groups on the surface of the glass substrate in which the core vias are formed, and providing the pretreated glass substrate; and a plating process of plating a metal layer on the pretreated glass substrate.

[0105] The core layer manufacturing step may include a pretreatment process of forming a metal-containing primer layer on the surface of the glass substrate having the core via formed thereon by sputtering to provide a pretreated glass substrate; and a plating process of plating a metal layer on the pretreated glass substrate.

[0106] An insulating layer forming step may be further included between the core layer forming step and the upper layer forming step.

[0107] The insulating layer forming step may be a step of forming the core insulating layer by positioning an insulating film on the core layer and then performing pressure-sensitive lamination.

[0108] The manufacturing method of the packaging substrate will be described in more detail below.

[0109] 1) Preparation step (glass defect formation process): A glass substrate 21a having flat first and second surfaces is prepared, and defects (grooves, 21b) are formed on the glass surface at predetermined positions for forming core vias. The glass substrate may be a glass substrate used for electronic device substrates, such as, but not limited to, an alkali-free glass substrate. Commercially available products manufactured by manufacturers such as Corning, Schott, and AGC may be used. The defects (grooves) may be formed by mechanical etching, laser irradiation, or other methods.

[0110] 2) Etching step (core via formation step): A core via 23 is formed in the glass substrate 21a with a defect (groove, 21b) through a physical or chemical etching process. During the etching process, a via is formed in the defective portion of the glass substrate, and the surface of the glass substrate 21a may also be etched at the same time. To prevent such etching of the glass surface, a masking film or the like may be applied. However, taking into consideration the complexity of the process of applying and removing the masking film, the glass substrate with the defect itself may be etched. In this case, the thickness of the glass substrate with the core via may be slightly thinner than the thickness of the original glass substrate.

[0111] 3-1) Core layer preparation step: An electrically conductive layer 21d is formed on a glass substrate. The electrically conductive layer may be a metal layer typically containing copper, but is not limited thereto.

[0112] The adhesive strength between the glass surface (including the surface of the glass substrate and the surface of the core via) and the copper metal surface is poor due to their different properties. In the present embodiment, the adhesive strength between the glass surface and the metal was improved by two methods: a dry method and a wet method.

[0113] The dry method is a method of applying sputtering, i.e., forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. When forming the seed layer, a different metal such as titanium, chromium, or nickel may be sputtered together with copper, etc. In this case, it is thought that the glass-metal adhesion is improved due to the anchor effect caused by the interaction between the glass surface morphology and the metal particles.

[0114] The wet method is a primer treatment method in which a primer layer 21c is formed by pretreating with a compound having a functional group such as an amine. Depending on the desired level of adhesion, pretreatment with a silane coupling agent may be followed by primer treatment with a compound or particles having an amine functional group. As mentioned above, the support substrate of the present embodiment must have high performance sufficient to form fine patterns, and this must be maintained even after primer treatment. Therefore, if such a primer contains nanoparticles, it is preferable that nanoparticles have an average diameter of 150 nm or less. For example, nanoparticles are preferably used as particles having an amine group. The primer layer may be formed by applying an adhesion improver, such as the CZ series manufactured by MEC Corporation.

[0115] The seed layer / primer layer 21c may selectively form an electrically conductive layer or a metal layer with or without removing portions where no electrically conductive layer is required. Furthermore, the seed layer / primer layer 21c may be selectively treated in an activated or deactivated state for metal plating, with portions where or where no electrically conductive layer is required, before proceeding with subsequent processes. For example, the activation or deactivation treatment may involve light irradiation treatment, such as a laser of a certain wavelength, or chemical treatment. The metal layer may be formed using, but is not limited to, a copper plating method commonly used in semiconductor device manufacturing.

[0116] During the metal plating, the thickness of the electroconductive layer formed can be controlled by adjusting various variables such as the concentration of the plating solution, the plating time, and the type of additives used.

[0117] If a portion of the core distribution layer is unnecessary, it may be removed, or after the seed layer is partially removed or passivated, metal plating may be carried out to form an electrically conductive layer in a predetermined pattern, thereby forming an etching layer 21e of the core distribution layer.

[0118] 3-2) Insulating Layer Forming Step: After the core distribution layer, which is the electrically conductive layer, is formed, the core via may undergo an insulating layer forming step in which the empty spaces are filled with an insulating layer. The insulating layer may be formed in the form of a film, for example, a film-shaped insulating layer formed by a pressure-sensitive lamination method. By carrying out the pressure-sensitive lamination in this manner, the insulating layer can be sufficiently filled into the empty spaces inside the core via, forming a core insulating layer without voids.

[0119] 4) Upper Layer Fabrication Step: This is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition forming the insulating layer 23a or by laminating an insulating film, but laminating an insulating film is preferred for simplicity. The insulating film lamination can be performed by laminating and curing the insulating film. If a pressure-sensitive lamination method is used, the insulating resin can be sufficiently embedded in layers without an electrically conductive layer inside the core via. The upper insulating layer also directly contacts at least a portion of the glass substrate, thereby providing sufficient adhesion. Specifically, the glass substrate and the upper insulating layer preferably have properties that satisfy an adhesion test value of 4B or higher according to ASTM D3359.

[0120] The upper distribution pattern may be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, etching unnecessary portions, and then forming an etching layer 23d of the electrically conductive layer. In the case of electrically conductive layers formed adjacent to each other with an insulating layer in between, the upper distribution pattern may be formed by forming blind vias 23b in the insulating layer and then performing a plating process. When forming the blind vias, dry etching methods such as laser etching and plasma etching, or wet etching methods using a masking layer and an etchant may be used.

[0121] 5) Top Connection Layer and Cover Layer Formation Step: The top connection patterns and top connection electrodes can also be formed using a process similar to that used to form the upper distribution layer. Specifically, the top connection patterns and top connection electrodes can be formed by forming an insulating layer 23f on an insulating layer 23e, then forming an electrically conductive layer 23g thereon, and then forming an electrically conductive layer 23h thereon. Alternatively, they can be formed by selectively forming only the electrically conductive layer without using an etching method. The cover layer can be formed by forming openings (not shown) at positions corresponding to the top connection electrodes to expose the top connection electrodes and enable direct connection to device connectors or device terminals.

[0122] 6) Lower surface connection layer and cover layer formation step: A lower distribution layer and / or a lower surface connection layer may be formed in a manner similar to the upper surface connection layer and cover layer formation step described above, and a cover layer (not shown) may optionally be formed.

[0123] The present invention will be described in more detail below through specific examples. The following examples are merely illustrative examples for the purpose of facilitating understanding of the present invention, and are not intended to limit the scope of the present invention.

[0124] <Manufacturing Example 1 - Manufacturing of packaging substrate>

[0125] 1) Preparation step (glass defect formation process): A glass substrate 21a having flat first and second surfaces was prepared, and defects (grooves, 21b) were formed on the glass surface at predetermined positions for the formation of core vias. Borosilicate glass (Corning) was used as the glass. Mechanical etching and laser irradiation were used to form the defects (grooves).

[0126] 2) Etching step (core via forming step): The glass substrate 21a having the defect (groove, 21b) formed therein was subjected to a physical or chemical etching process to form a core via 23. At this time, the core via was formed to have a first opening contacting the first surface, a second opening contacting the second surface, and a minimum inner diameter portion which is the area with the narrowest inner diameter of the entire core via connecting the first opening and the second opening.

[0127] 3-1) Core Layer Fabrication Step: An electrically conductive layer 21d was formed on a glass substrate. A metal layer containing copper was used as the electrically conductive layer. Adhesion between the surface of the glass substrate and the metal layer was improved using two methods: a dry method and a wet method. The dry method involves sputtering, i.e., forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. When forming the seed layer, at least one dissimilar metal selected from titanium, chromium, and nickel was sputtered along with copper. The wet method involves priming, forming a primer layer 21c by pretreating with a compound having a functional group such as an amine. After pretreatment with a silane coupling agent, a primer treatment was performed with a compound or particles having an amine functional group. Nanoparticles with an average diameter of 150 nm or less were used as the primer, and nanoparticles were used as the particles having an amine group. The primer layer was formed using an adhesion improver manufactured by MEC's CZ series.

[0128] The seed layer / primer layer 21c was selectively treated in an activated or deactivated state for metal plating in areas where an electrically conductive layer was required or not required. The activation or deactivation treatment was performed using light irradiation treatment such as a laser of a certain wavelength, chemical treatment, etc. The metal layer was formed using a copper plating method commonly used in semiconductor device manufacturing.

[0129] The seed layer was partially removed or passivated, and then metal plating was performed to form an electrically conductive layer in a predetermined pattern, forming an etching layer 21e of the core distribution layer. The electrically conductive layer had a thickness of 97% of the total distance from the inner diameter surface of the core via to the surface of the electrically conductive layer at the position of the smallest inner diameter of the core via. Furthermore, at the opening with the larger diameter of either the first opening or the second opening, the thickness of the electrically conductive layer was 97% of the total distance from the inner diameter surface of the core via to the surface of the electrically conductive layer. Furthermore, the average distance between the surface of the electrically conductive layer closest to the inner diameter surface of the core via and the inner diameter surface of the core via was 0.5 μm.

[0130] 3-2) Insulation layer formation step: After forming the core distribution layer, which is the electrically conductive layer, an insulation layer was formed to fill the empty space. At this time, the insulation layer was formed in the form of a film, and the film-shaped insulation layer was formed by a pressure-sensitive lamination method.

[0131] 4) Upper layer manufacturing step: A step of forming an upper insulating layer and an upper distribution layer including an upper distribution pattern on the core layer was carried out. The upper insulating layer was formed by laminating an insulating film and then curing the insulating film. The upper insulating layer also directly contacted at least a portion of the glass substrate, and thus had sufficient adhesion. Specifically, the glass substrate and the upper insulating layer had properties that satisfied an adhesion test value of 4B or higher according to ASTM D3359.

[0132] The upper distribution pattern was formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, etching unnecessary portions, and then forming an etching layer 23d of the electrically conductive layer. In the case of electrically conductive layers formed adjacent to each other with an insulating layer in between, blind vias 23b were formed in the insulating layer and then a plating process was carried out. Dry etching methods such as laser etching and plasma etching, or wet etching methods using a masking layer and an etching solution were used to form the blind vias.

[0133] 5) Top connection layer and cover layer formation step: An insulating layer etching layer 23f was formed on the insulating layer 23e, an electrically conductive layer 23g was formed on the insulating layer 23e, and an electrically conductive layer etching layer 23h was then formed. The cover layer was formed with openings (not shown) at positions corresponding to the top connection electrodes, exposing the top connection electrodes and allowing direct connection to the device connection parts or device terminals.

[0134] 6) Lower surface connection layer and cover layer formation step: A lower distribution layer and / or a lower surface connection layer was formed in a manner similar to the upper surface connection layer and cover layer formation step described above, and a cover layer (not shown) was optionally formed to manufacture a packaging substrate.

[0135] The packaging substrate 20 manufactured by the above method is

[0136] a core layer including a glass substrate 21 having a first surface and a second surface facing each other, a number of core vias 23 penetrating the glass substrate in a thickness direction, and a core distribution layer 24 on the surface of the glass substrate or the core vias, the core distribution layer having an electrically conductive layer at least a portion of which electrically connects the electrically conductive layers on the first surface and the second surface through the core vias; and

[0137] a top layer 26 located on the first surface and including an electrically conductive layer electrically connecting the core distribution layer to an external semiconductor device portion;

[0138] The upper layer includes an upper distribution layer 25 and an upper surface connecting layer 27 located on the upper distribution layer;

[0139] The upper distribution layer includes an upper insulating layer 253 located on the first surface; and an upper distribution pattern 251 having a predetermined pattern and embedded in the upper insulating layer as an electrically conductive layer, at least a portion of which is electrically connected to the core distribution layer 24;

[0140] The core via includes a first opening 233 in contact with the first surface; a second opening 234 in contact with the second surface; and a minimum inner diameter portion 235 that is a region in the entire core via connecting the first opening and the second opening and has the smallest inner diameter.

[0141] When the distance (Dt3) from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%, the thickness (Tcv3) of the electrically conductive layer of the core distribution layer is 97%,

[0142] In the opening having the larger diameter of the first opening and the second opening, when the distance (Dt2) from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%, the thickness (Tcv2) of the electrically conductive layer is 97%,

[0143] The average distance (F3) between the surface of the electrically conductive layer of the core distribution layer closest to the inner diameter surface of the core via and the inner diameter surface of the core via is 0.5 μm.

[0144]

[0145] <Manufacturing Example 2 - Manufacturing of packaging substrate>

[0146] In the packaging substrate of Manufacturing Example 1, when the distance (Dt3) from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%, the thickness (Tcv3) of the electrically conductive layer of the core distribution layer is 95%;

[0147] In the opening having the larger diameter of the first opening and the second opening, when the distance (Dt2) from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%, the thickness (Tcv2) of the electrically conductive layer is 95%;

[0148] A packaging substrate was manufactured using the same process as in Manufacturing Example 1, except that the average distance (F3) between one surface of the electrically conductive layer of the core distribution layer closest to the inner diameter surface of the core via and the inner diameter surface of the core via was set to 0.75 μm.

[0149] <Manufacturing Example 3 - Manufacturing of packaging substrate>

[0150] In the packaging substrate of Manufacturing Example 1, when the distance (Dt3) from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%, the thickness (Tcv3) of the electrically conductive layer of the core distribution layer is 93%;

[0151] In the opening having the larger diameter of the first opening and the second opening, when the distance (Dt2) from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%, the thickness (Tcv2) of the electrically conductive layer is 93%;

[0152] A packaging substrate was manufactured using the same process as in Manufacturing Example 1, except that the average distance (F3) between one surface of the electrically conductive layer of the core distribution layer closest to the inner diameter surface of the core via and the inner diameter surface of the core via was set to 1 μm.

[0153] <Manufacturing Example 4 - Manufacturing of packaging substrate>

[0154] In the packaging substrate of Manufacturing Example 1, when the distance (Dt3) from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%, the thickness (Tcv3) of the electrically conductive layer of the core distribution layer is 92%;

[0155] In the opening having the larger diameter of the first opening and the second opening, when the distance (Dt2) from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%, the thickness (Tcv2) of the electrically conductive layer is 92%;

[0156] A packaging substrate was manufactured using the same process as in Manufacturing Example 1, except that the average distance (F3) between one surface of the electrically conductive layer of the core distribution layer closest to the inner diameter surface of the core via and the inner diameter surface of the core via was set to 1.2 μm.

[0157] <Manufacturing Example 5 - Manufacturing of packaging substrate>

[0158] In the packaging substrate of Manufacturing Example 1, when the distance (Dt3) from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%, the thickness (Tcv3) of the electrically conductive layer of the core distribution layer is 87%;

[0159] In the opening having the larger diameter of the first opening and the second opening, when the distance (Dt2) from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%, the thickness (Tcv2) of the electrically conductive layer is 87%;

[0160] A packaging substrate was manufactured using the same process as in Manufacturing Example 1, except that the average distance (F3) between one surface of the electrically conductive layer of the core distribution layer closest to the inner diameter surface of the core via and the inner diameter surface of the core via was set to 2 μm.

[0161]

[0162] <Experimental Example - Measurement of Electrical Characteristics>

[0163] The packaging substrates of Preparation Examples 1 to 5 were cut into pieces of 100 μm×100 μm size based on the top surface, and the resistance value among the electrical properties was measured using a resistivity tester. The results are shown in Table 1.

[0164] [Table 1]

[0165] Referring to Table 1, in the packaging substrate, when the distance (Dt3) from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%, the thickness (Tcv3) of the electrically conductive layer of the core distribution layer is 90% or more, and when the distance (Dt2) from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core distribution layer is 100%, in the opening where the larger diameter of the first opening or the second opening is located, the thickness (Tcv2) of the electrically conductive layer is 90% or more, and the average distance (F3) between one surface of the electrically conductive layer of the core distribution layer closest to the inner diameter surface of the core via and the inner diameter surface of the core via is 1 μm or less, the resistance value is 24.1×10 -6 Ω~25.8×10 -6 A packaging substrate having such characteristics is considered to be able to transmit electrical signals sufficiently smoothly to elements disposed above or below it.

[0166] The packaging substrate of the embodiment utilizes excellent properties such as being able to serve as a thin yet strong substrate support without forming parasitic elements, which is common with glass substrates, as well as being able to form an electrically conductive layer with a thickness that is an appropriate ratio to the thickness of the glass substrate, thereby inducing efficient signal transmission.

[0167] Glass substrates are considered to have poor bonding properties with electrically conductive layers such as copper layers, and in order to form an electrically conductive layer of sufficient thickness by a method such as plating, it is necessary to form a seed layer or primer layer between the glass surface and the electrically conductive layer. However, if such a seed layer or primer layer is formed too thick, it may be difficult to form a sufficient electrically conductive layer within a specified core via diameter, which may have a negative impact on the electrical signal transmission speed between the top and bottom of the packaging substrate.

[0168] Considering these characteristics, for efficient transmission of electrical signals, it is preferable that the thickness of the seed layer or primer layer is applied as thin as possible within a range that satisfies a specific ratio, and it is considered preferable that the Tcv3 / Dt3 ratio and the Tcv2 / Dt2 ratio are 0.90 or more and F3 is 1.0 μm or less.

[0169] Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and many variations and improvements made by those skilled in the art using the basic concepts of the present invention as defined in the following claims also fall within the scope of the present invention. [Explanation of symbols]

[0170] 100: Semiconductor device 10: Motherboard 30: Semiconductor element section 32: First semiconductor element 34: Second semiconductor element 36: Third semiconductor element 20: Packaging substrate 22: Core layer 223: Core insulating layer 21, 21a: Glass substrate 213: 1st side 214: 2nd side 23: Core via 233: First opening 234: Second opening 235: Minimum inner diameter portion 24: Core distribution layer 241: Core distribution pattern 241a: First surface distribution pattern 241b: Core via distribution pattern 241c: Second surface distribution pattern 26: Upper layer 25: Upper distribution layer 251: Upper distribution pattern 252: Blind via 253: Upper insulating layer 27: Upper surface connection layer 271: Upper surface connection electrode 272: Top surface connection pattern 29: Bottom layer 291: Lower distribution layer 291a: Lower distribution pattern 291b: Lower insulating layer 292: Lower connection layer 292a: Bottom connection electrode 292b: Bottom connection pattern 50: Connection portion 51: Element connection portion 52: Board connection part 60: Cover layer 21b: Glass defects 21c: Seed layer, primer layer 21d: Core distribution layer 21e: Etching layer of the core distribution layer 23a: insulating layer 23b: etching layer of insulating layer 23c: Electrically conductive layer 23d: Etched layer of the electrically conductive layer 23e: insulating layer 23f: etching layer of insulating layer 23g: Electrically conductive layer 23h: Etched layer of the electrically conductive layer

Claims

1. a semiconductor device unit in which one or more semiconductor devices are located; a packaging substrate electrically connected to the semiconductor devices; and a motherboard electrically connected to the packaging substrate, transmitting external electrical signals to the semiconductor devices and connecting the semiconductor devices to each other; the packaging substrate includes a core layer and an upper layer positioned on the core layer; the core layer includes a glass substrate and a core via; the glass substrate has a first surface and a second surface facing each other; The core vias penetrate the glass substrate in a thickness direction, and a large number of the core vias are arranged. the core layer includes a core distribution layer located on a surface of the glass substrate or a core via; the core distribution layer includes an electrically conductive layer, at least a portion of which electrically connects the electrically conductive layer on the first surface and the electrically conductive layer on the second surface through the core via; the upper layer is located on the first surface and includes an electrically conductive layer electrically connecting the core distribution layer and the semiconductor device portion; the core via includes a first opening, a second opening, and a minimum inner diameter portion; the first opening is an opening that contacts the first surface, the second opening is an opening that contacts the second surface, the minimum inner diameter portion is located between the first opening and the second opening and is a portion having a narrowest diameter; When the distance from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core via is taken as 100%, the thickness of the electrically conductive layer at the position of the smallest inner diameter part is about 90% or more, the core distribution layer includes a first surface core pattern, a second surface core pattern, and a core via pattern; The first surface core pattern is an electrically conductive layer disposed on at least a portion of the first surface, the second surface core pattern is an electrically conductive layer disposed on at least a portion of the second surface; the core via pattern is an electrically conductive layer that electrically connects the first surface core pattern and the second surface core pattern to each other through the core via; In the core via pattern, an average distance between one surface of the core via pattern close to the inner diameter surface of the core via and the inner diameter surface of the core via is 1 μm or less; the upper layer includes an upper insulating layer and an upper distribution pattern; the upper insulating layer is an insulating layer disposed on the first surface, The upper distribution pattern is an electrically conductive layer, at least a portion of which is electrically connected to the core distribution layer, the upper distribution pattern is formed in the upper insulating layer and includes a fine pattern at least in a portion thereof; The width and spacing of the fine patterns are each less than about 4 μm; the packaging substrate includes a lower layer disposed below the core layer; the lower layer includes a lower distribution layer and a lower connection layer; the lower connection layer includes a lower connection electrode and a lower connection pattern; The semiconductor device, wherein the lower surface connection pattern is a non-fine pattern.

2. 2. The semiconductor device according to claim 1, wherein, at the position of the smallest inner diameter portion, when the distance from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core via is taken as 100%, the thickness of the electrically conductive layer is approximately 95% or more.

3. 2. The semiconductor device according to claim 1, wherein in said core via pattern, an average distance between one surface of said core via pattern closest to said inner diameter surface of said core via and said inner diameter surface of said core via is 1 [mu]m or less.

4. 2. The semiconductor device according to claim 1, wherein the glass substrate has a surface roughness (Ra) of 10 angstroms or less.

5. 2. The semiconductor device of claim 1, wherein when the distance from the inner diameter surface of the core via to the surface of the electrically conductive layer of the core via is taken as 100%, the thickness of the electrically conductive layer at the position of the larger of the first opening and the second opening is approximately 90% or more.

6. the lower distribution layer includes a lower insulating layer, at least a portion of which contacts the second surface; and a lower distribution pattern, which is embedded in the lower insulating layer and has a predetermined pattern, at least a portion of which is electrically connected to the core distribution layer; the lower surface connection electrode is electrically connected to the lower surface connection pattern; The semiconductor device of claim 1 , wherein at least a portion of the lower surface connection pattern is electrically connected to the lower distribution pattern and at least a portion of the lower surface connection pattern is exposed on one surface of the lower insulating layer.

7. The packaging substrate was cut into a size of 100 μm×100 μm based on the top surface, and the resistance value was about 27.5×10 －６ The semiconductor device according to claim 1 , wherein the resistance is Ω or less.

8. The semiconductor device according to claim 1 , wherein the electrically conductive layer of the core distribution layer has an adhesive strength of 3 N / cm or more to the glass substrate.

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