Automatic Memory Overclocking

Abstract

The automatic memory overclocking includes increasing the memory frequency settings of a memory module until a memory stability test fails, determining overclocked memory frequency settings that include the highest memory frequency setting that passes the memory stability test, and generating a profile that includes the overclocked memory frequency settings.

Description

[Background technology]

[0001] Memory module settings can be set according to vendor profiles and user-input specifications. These profiles are often generated and tested using system configurations that differ from the user's system. User-input specifications may also be limited using margins determined and tested using these different system configurations. [Brief explanation of the drawings]

[0002] [Figure 1] FIG. 1 is a block diagram of an exemplary processor for automatic memory overclocking, according to some embodiments. [Figure 2] 1 is a flowchart of an exemplary method for automatic memory overclocking, according to some embodiments. [Figure 3] 1 is a flowchart of an exemplary method for automatic memory overclocking, according to some embodiments. [Figure 4] 1 is a flowchart of an exemplary method for automatic memory overclocking, according to some embodiments. [Figure 5] 1 is a flowchart of an exemplary method for automatic memory overclocking, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0003] In some embodiments, a method for automatic memory overclocking includes increasing memory frequency settings of memory modules until a memory stability test fails, determining an overclocked memory frequency setting that includes the highest memory frequency setting that passes the memory stability test, and generating a profile that includes the overclocked memory frequency setting.

[0004] In some embodiments, increasing the memory frequency setting of the memory module until the memory stability test fails includes determining one or more memory timing settings, and the method further includes determining one or more overclocked memory timing settings including one or more memory timing settings corresponding to the overclocked memory frequency setting, and generating the profile includes generating a profile including the one or more overclocked memory timing settings. In some embodiments, the one or more memory timing settings include one or more of a column access strobe (CAS) latency, a row address strobe (RAS) to column address strobe (CAS) delay (write), a row address strobe (RAS) to column address strobe (CAS) delay (read), a row precharge time, and / or a row active time. In some embodiments, the method further includes determining one or more sub-timing settings based on the overclocked memory frequency setting and the overclocked memory timing setting, and generating the profile includes generating a profile including the one or more sub-timing settings. In some embodiments, the one or more sub-timing settings are based on one or more rules applied to the overclocked memory frequency setting and / or the one or more memory timing settings. In some embodiments, the method further includes storing the profile in a storage location. In some embodiments, the method further includes loading the profile from the storage location and applying the profile to the memory module.

[0005] In some embodiments, an apparatus for automatic memory overclocking performs steps including increasing memory frequency settings of memory modules until a memory stability test fails, determining an overclocked memory frequency setting that includes the highest memory frequency setting that passes the memory stability test, and generating a profile that includes the overclocked memory frequency setting.

[0006] In some embodiments, increasing the memory frequency setting of the memory module until the memory stability test fails includes determining one or more memory timing settings, and the step further includes determining one or more overclocked memory timing settings including one or more memory timing settings corresponding to the overclocked memory frequency setting, and generating the profile includes generating a profile including the one or more overclocked memory timing settings. In some embodiments, the one or more memory timing settings include one or more of a column access strobe (CAS) latency, a row address strobe (RAS) to column address strobe (CAS) delay (write), a row address strobe (RAS) to column address strobe (CAS) delay (read), a row precharge time, and / or a row active time. In some embodiments, the step further includes determining one or more sub-timing settings based on the overclocked memory frequency setting and the overclocked memory timing setting, and generating the profile includes generating a profile including the one or more sub-timing settings. In some embodiments, the one or more sub-timing settings are based on one or more rules applied to the overclocked memory frequency setting and / or the one or more memory timing settings. In some embodiments, the steps further include storing the profile in a storage location. In some embodiments, the steps further include loading the profile from the storage location and applying the profile to said memory module.

[0007] In some embodiments, a computer program product disposed on a non-transitory computer-readable storage medium includes computer program instructions for automatic memory overclocking that, when executed, cause a computer to perform steps including increasing memory frequency settings of memory modules until a memory stability test fails, determining overclocked memory frequency settings that include the highest memory frequency setting that passes the memory stability test, and generating a profile that includes the overclocked memory frequency settings.

[0008] In some embodiments, increasing the memory frequency setting of the memory module until the memory stability test fails includes determining one or more memory timing settings, and the step further includes determining one or more overclocked memory timing settings including one or more memory timing settings corresponding to the overclocked memory frequency setting, and generating a profile includes generating a profile including the one or more overclocked memory timing settings. In some embodiments, the one or more memory timing settings include one or more of a column access strobe (CAS) latency, a row address strobe (RAS) to column address strobe (CAS) delay (write), a row address strobe (RAS) to column address strobe (CAS) delay (read), a row precharge time, and / or a row active time. In some embodiments, the step further includes determining one or more sub-timing settings based on the overclocked memory frequency setting and the overclocked memory timing setting, and generating a profile includes generating a profile including the one or more sub-timing settings. In some embodiments, the one or more sub-timing settings are based on one or more rules applied to the overclocked memory frequency setting and / or the one or more memory timing settings. In some embodiments, the steps further include storing the profile in a storage location. In some embodiments, the steps further include loading the profile from the storage location and applying the profile to said memory module.

[0009] Automatic memory overclocking according to the present disclosure is generally implemented by a computer, i.e., an automated computing machine. Accordingly, for further explanation, FIG. 1 illustrates a block diagram of an automated computing machine, including an exemplary computer 100 configured for automatic memory overclocking. The computer 100 of FIG. 1 includes at least one computer processor 102 or "CPU" and random access memory 104 (RAM) coupled to the processor 102 and other components of the computer 100 via a high-speed memory bus 106 and a bus adapter 108.

[0010] Stored in RAM 104 is an operating system 110. Operating systems useful in a computer configured for automatic memory overclocking include UNIX, Linux, Microsoft Windows, and others that will occur to those skilled in the art. While the example operating system 110 of FIG. 1 is shown in RAM 104, many components of such software are typically also stored in non-volatile memory, such as data storage 112, e.g., a disk drive. Also stored in RAM is a configuration module 114, which is a module for automatic memory overclocking.

[0011] 1 includes a disk drive adapter 116 connected to processor 102 and other components of computer 100 via expansion bus 118 and bus adapter 108. Disk drive adapter 116 connects non-volatile data storage to computer 100 in the form of data storage 112. Disk drive adapters for use in computers configured for automatic memory overclocking include integrated drive electronic (IDE) adapters, small computer system interface (SCSI) adapters, and others as would occur to one skilled in the art. In some embodiments, the non-volatile computer memory is implemented as an optical disk drive, electrically erasable programmable read-only memory (so-called "EEPROM" or "flash" memory), a RAM drive, etc., as would occur to one skilled in the art.

[0012] The example computer 100 of FIG. 1 includes one or more input / output (“I / O”) adapters 120. I / O adapters implement user-oriented input / output through software drivers and computer hardware for controlling, for example, output to a display device, such as a computer display screen, and user input from user input devices 122, such as a keyboard and mouse. The example computer 100 of FIG. 1 also includes a video adapter 124, which is an example of an I / O adapter designed specifically for graphics output to a display device 126, such as a display screen, or computer monitor. The video adapter 124 is connected to the processor 102 via a high-speed video bus 128, the bus adapter 108, and a front-side bus 130, which is also a high-speed bus.

[0013] The example computer 100 of Figure 1 includes a communications adapter 132 for data communications with other computers and with a data communications network. Such data communications may be performed serially via an RS-232 connection, an external bus such as a Universal Serial Bus ("USB"), a data communications network such as an IP data communications network, and / or other methods as would occur to one skilled in the art. Communications adapters implement the hardware level of data communications by which one computer sends data communications to another computer directly or over a data communications network. Examples of communications adapters useful in a computer configured for automatic memory overclocking include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications, and 802.11 adapters for wireless data communications.

[0014] For further explanation, Figure 2 shows a flowchart illustrating an exemplary method for automatic memory overclocking, including increasing (202) the memory frequency setting of a memory module (e.g., by configuration module 114) until a memory stability test fails. A memory module is a set of one or more random access memory chips within the same circuit board (e.g., the same dual in-line memory module (DIMM)). The memory frequency setting is the clock speed of the memory module (e.g., 1000 megahertz, 3000 megahertz, etc.).

[0015] For example, the configuration module 114 may start from a baseline memory frequency setting (e.g., the memory module's current memory frequency setting, a predetermined minimum frequency setting, etc.) and increase the memory frequency setting at predetermined intervals (e.g., 100 megahertz or another interval). After increasing the memory frequency setting, the configuration module 114 may perform one or more memory stability tests on the memory module. The memory stability tests may be based on one or more data integrity checks, including error correction code checks or other approaches for intelligibly detecting bit errors. For example, the configuration module 114 may perform one or more reads and / or writes of data to the memory module and determine whether errors are observed in the read and / or written data.

[0016] If the memory module passes one or more memory stability tests, the configuration module 114 increases the memory frequency setting and runs one or more memory stability tests. This process is repeated until a memory stability test fails. In some embodiments, in response to a failed memory stability test, the configuration module 114 reduces the memory frequency setting to a memory frequency setting greater than the memory frequency setting that last passed the memory stability test but less than the memory frequency setting that failed the memory stability test. For example, assume that a memory module passes a memory stability test at 2800 megahertz. After increasing the memory frequency setting by a predetermined interval of 200 megahertz, the memory module fails a memory stability test at 3000 megahertz. Next, the configuration module 114 reduces the memory frequency setting to 2900 megahertz and runs a memory stability test. Those skilled in the art will appreciate that this iterative approach can efficiently search for the highest memory frequency setting that passes the memory stability test.

[0017] 2 also includes determining (204) overclocked memory frequency settings (e.g., by configuration module 114), including the highest memory frequency setting that passes a memory stability test. For example, assuming configuration module 114 increments the memory frequency setting of a memory module in 100 megahertz intervals, a memory frequency setting of 2900 megahertz passes the memory stability test, while a setting of 3000 megahertz fails. The overclocked memory frequency setting is then determined (204) to be 2900 megahertz.

[0018] The method of FIG. 2 also includes generating (206) (e.g., by configuration module 114) a profile 208 that includes the overclocked memory frequency setting. For example, profile 208 is generated (206) as data indicating one or more settings of a memory module, including the overclocked memory frequency setting. Those skilled in the art will appreciate that the method of FIG. 2 can be repeated for each memory module in a computing system, such that a profile 208 is generated for each memory module, or such that a profile 208 is generated indicating the settings of each memory module. Configuration module 114 is described as a software-based process (e.g., implemented in random access memory 104). Those skilled in the art will appreciate that in alternative embodiments, configuration module 114 is implemented at least in part in a memory controller or other hardware component.

[0019] For further explanation, FIG. 3 shows a flowchart illustrating an exemplary method for automatic memory overclocking that includes increasing (202) memory frequency settings of memory modules (e.g., by configuration module 114) until a memory stability test fails, determining (204) overclocked memory frequency settings that include the highest memory frequency setting that passes the memory stability test, and generating (206) a profile 208 that includes the overclocked memory frequency settings.

[0020] The method of Figure 3 differs from the method of Figure 2 in that increasing the memory frequency setting of the memory module (202) until the memory stability test fails further includes determining one or more memory timing settings (302), where the memory timing settings include one or more of a column access strobe (CAS) latency, a row address strobe (RAS) to column address strobe (CAS) delay (write), a row address strobe (RAS) to column address strobe (CAS) delay (read), a row precharge time, and / or a row active time.

[0021] In one embodiment, determining (302) one or more memory timing settings includes determining (302) one or more memory timing settings as one or more minimum timing settings. For example, a memory module includes default minimum threshold values for one or more memory timing settings. Then, one or more memory timing settings are determined as the minimum threshold values. In one embodiment, determining (302) one or more memory timing settings includes determining (302) one or more memory timing settings as a function of one or more other minimum timing settings. For example, a first memory timing setting is determined as the minimum timing setting, and a second memory timing setting is determined (e.g., using a formula or other rule) as a function of the first memory timing setting. After determining (302) one or more minimum timing settings, the memory timing settings are applied to the memory module before implementing the one or more memory timing settings.

[0022] In one embodiment, after failing a memory stability test at a given frequency, the configuration module 114 increases one or more memory timing settings until a memory timing setting threshold is reached or the memory stability test passes, and thus the memory frequency setting passes the memory stability test using the increased memory timing setting.

[0023] 3 also includes determining one or more overclocked memory timing configurations, including one or more memory timing settings corresponding to the overclocked memory frequency settings, i.e., the one or more overclocked memory timing settings are minimum memory timing settings to be applied to the memory module if the overclocked memory frequency settings pass a memory stability test.

[0024] The method of Figure 3 further differs from the method of Figure 2 in that generating 206 a profile 208 including an overclocked memory frequency setting also includes generating 306 a profile 208 including one or more overclocked memory timing settings. Thus, the generated 206 profile 208 indicates an overclocked memory frequency setting and one or more overclocked memory timing settings for the memory module.

[0025] For further explanation, FIG. 4 shows a flowchart illustrating an exemplary method of automatic memory overclocking that includes increasing (202) memory frequency settings of a memory module (e.g., by configuration module 114) until a memory stability test fails, which includes determining (302) one or more memory timing settings, determining (204) an overclocked memory frequency setting that includes the highest memory frequency setting that passes the memory stability test, determining (304) one or more overclocked memory timing settings that include the one or more memory timing settings corresponding to the overclocked memory frequency settings, and generating (306) a profile 208 that includes the overclocked memory frequency settings.

[0026] 4 differs from the method of FIG. 3 in that it further includes determining 402 one or more sub-timing settings based on an overclocked memory frequency setting and / or one or more overclocked timing settings. Examples of the sub-timing settings include a page timeline period setting, a RAS-to-RAS delay, a different bank group setting (e.g., a delay between activation of two rows between different bank groups), a RAS-to-RAS delay, a same bank group setting (e.g., a delay between activation of two rows within the same bank group), a four activation window setting (e.g., a time during which activation of four rows within the same rank may occur), a write-to-read delay, a different bank group setting (e.g., a delay between a successful write command and a read command between different bank groups), a write-to-read delay, a same bank group setting (e.g., a delay between a successful write command and a read command within the same bank group), a write recovery time setting (e.g., a delay between a successful write command and a precharge of an active bank), and other settings.

[0027] In one embodiment, one or more sub-timing settings are determined based on one or more overclocked memory timing settings. For example, a row cycle time setting is determined as the sum of a row precharge time setting and a row address strobe (RAS) active time setting of the overclocked memory frequency setting. In one embodiment, one or more sub-timing settings are determined based on one or more thresholds. For example, a setting determined via a below-threshold formula may instead be determined to be a threshold amount. In one embodiment, one or more sub-timing settings are determined based on one or more other sub-timing settings. For example, four activation window settings are determined as four times the RAS-to-RAS delay, different bank group settings. That is, one or more sub-timing settings are determined based on one or more rules.

[0028] The method of Figure 4 further differs from the method of Figure 3 in that generating 206 a profile 208 including an overclocked memory frequency setting further includes generating 404 a profile 208 including one or more sub-timing settings. Thus, the generated 206 profile 208 indicates an overclocked memory frequency setting, one or more overclocked memory timing settings, and one or more sub-timing settings for a memory module.

[0029] For further explanation, FIG. 5 shows a flowchart illustrating an exemplary method for automatic memory overclocking that includes increasing (202) memory frequency settings of memory modules (e.g., by configuration module 114) until a memory stability test fails, determining (204) overclocked memory frequency settings that include the highest memory frequency setting that passes the memory stability test, and generating (206) a profile 208 that includes the overclocked memory frequency settings.

[0030] 5 differs from the method of FIG. 2 in that it further includes storing (502) the profile in a storage location 504. In one embodiment, storage location 504 includes non-volatile memory of a computing system, including a memory module (e.g., disk storage, basic input / output system scratch tables, etc.). In another embodiment, storage location 504 includes non-volatile storage on the memory module itself, such as an on-module (e.g., dual in-line memory module (DIMM)) serial presence detect (SPD) Electrically Erasable Programmable Read-Only Memory (EEPROM).

[0031] The method of Figure 5 also includes loading 506 the profile from storage location 504. For example, profile 208 is loaded 506 from storage location 504 as part of a boot process of a computing system that includes the memory module. The method of Figure 5 also includes applying 508 the profile 208 to the memory module. Applying 508 the profile 208 to the memory module includes configuring the memory module to operate using the settings (e.g., overclocked memory frequency settings, overclocked memory timing settings, and / or sub-timing settings) indicated in profile 208.

[0032] In existing solutions, memory modules are configured using profiles provided by the memory module manufacturer or vendor. These profiles are tested with different configuration settings by end users (such as various chip or motherboard manufacturers or designers). Users can change the settings in these profiles, but are limited by margins based on these different configuration settings. Using the above approach, memory module configuration settings are determined and optimized based on the actual capabilities of the computing system in which the memory module is implemented.

[0033] In light of the above discussion, the reader will recognize that the benefits of automatic memory overclocking are as follows: Improve computing system performance by optimizing memory overclocking settings to reflect the current user system configuration and operating environment.

[0034] Exemplary embodiments of the present disclosure are described primarily with respect to a fully functional computer system for automatic memory overclocking. However, those skilled in the art will recognize that the present disclosure may also be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such a computer-readable storage medium may be any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact discs for optical drives, magnetic tape, and others that will occur to those skilled in the art. Those skilled in the art will readily recognize that any computer system with suitable programming means is capable of executing the steps of the disclosed methods embodied in a computer program product. Those skilled in the art will also recognize that, while some of the exemplary embodiments described herein are adapted for software installed and executed on computer hardware, alternative embodiments implemented as firmware or as hardware are nevertheless well within the scope of the present disclosure.

[0035] The present disclosure may be a system, a method, and / or a computer program product, which may include computer-readable storage medium(s) having computer-readable program instructions thereon for causing a processor to perform aspects of the present disclosure.

[0036] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or ridge structures in a groove having instructions recorded thereon, and any suitable combination of the above. As used herein, computer-readable storage media should not be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over electrical wires.

[0037] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface of each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within each computing / processing device.

[0038] The computer-readable program instructions for carrying out the operations of the present disclosure may be either source or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine language instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, or conventional procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to implement aspects of the present disclosure.

[0039] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0040] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to manufacture a machine such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, generate means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium having instructions stored therein that can direct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, including an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0041] Furthermore, computer-readable program instructions can be loaded into a computer, other programmable data processing apparatus, or other device to execute a series of operational steps on the computer, other programmable data processing apparatus, or other device, thereby creating a computer-implemented process in which the instructions executing on the computer, other programmable data processing apparatus, or other device perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0042] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions shown in the blocks may occur out of order (out of order) as shown in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by special-purpose hardware-based systems that perform the specified functions or acts, or a combination of special-purpose hardware and computer instructions.

[0043] From the foregoing description, it will be understood that modifications and variations may be made in various embodiments of the present disclosure. The descriptions herein are for illustrative purposes only and are not to be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. A method for automatic memory overclocking performed by a memory controller, comprising: the memory controller increasing a memory frequency setting of the memory module until a memory stability test fails; the memory controller determining overclocked memory frequency settings, including the highest memory frequency setting that passes the memory stability test; the memory controller generating a profile including the overclocked memory frequency setting and one or more memory timing settings corresponding to the overclocked memory frequency setting. How to automate memory overclocking.

2. increasing the memory frequency setting of the memory module until the memory stability test fails includes determining the one or more memory timing settings; The method comprises: determining one or more overclocked memory timing settings, the one or more memory timing settings corresponding to the overclocked memory frequency setting; generating the profile includes generating the profile including the one or more overclocked memory timing settings; the profile is specific to the memory module; 10. The method of claim 1.

3. the one or more memory timing settings include one or more of a column access strobe (CAS) latency, a row address strobe (RAS) to column address strobe (CAS) delay (write), a row address strobe (RAS) to column address strobe (CAS) delay (read), a row precharge time, and / or a row active time; The method of claim 2.

4. determining one or more sub-timing settings based on the overclocked memory frequency setting and the one or more overclocked memory timing settings; generating the profile includes generating the profile including the one or more sub-timing settings; The method of claim 2.

5. the one or more sub-timing settings are based on one or more rules that apply to the overclocked memory frequency setting and / or the one or more memory timing settings; The method of claim 4.

6. further comprising storing the profile in a storage location.

10. The method of claim 1.

7. loading the profile from the storage location; applying the profile to the memory module. The method of claim 6.

8. 1. An apparatus for automatic memory overclocking, comprising: A memory controller is provided. The memory controller Increasing the memory frequency setting of the memory module until the memory stability test fails; determining overclocked memory frequency settings, including the highest memory frequency setting that passes the memory stability test; and generating a profile including the overclocked memory frequency setting and one or more memory timing settings corresponding to the overclocked memory frequency setting; configured to: A device for automatic memory overclocking.

9. increasing the memory frequency setting of the memory module until the memory stability test fails includes determining the one or more memory timing settings; The memory controller configured to determine one or more overclocked memory timing settings, the one or more memory timing settings corresponding to the overclocked memory frequency setting; generating the profile includes generating the profile including the one or more overclocked memory timing settings; the profile is specific to the memory module; 9. The apparatus of claim 8.

10. the one or more memory timing settings include one or more of a column access strobe (CAS) latency, a row address strobe (RAS) to column address strobe (CAS) delay (write), a row address strobe (RAS) to column address strobe (CAS) delay (read), a row precharge time, and / or a row active time; 10. The apparatus of claim 9.

11. The memory controller configured to determine one or more sub-timing settings based on the overclocked memory frequency setting and the one or more overclocked memory timing settings; generating the profile includes generating the profile including the one or more sub-timing settings; 10. The apparatus of claim 9.

12. the one or more sub-timing settings are based on one or more rules that apply to the overclocked memory frequency setting and / or the one or more memory timing settings; 12. The apparatus of claim 11.

13. The memory controller configured to store the profile in a storage location; 9. The apparatus of claim 8.

14. The memory controller loading the profile from the storage location; applying the profile to the memory module; configured to:

14. The apparatus of claim 13.

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