Change control generation

Abstract

To provide improved methods of grasp determination.SOLUTION: A computer system comprises one or more processors and computer-readable memory, the memory storing executable instructions that cause the computer system to perform at least the following steps. By execution by the one or more processors, the computer system performs the steps of: using a first neural network to generate, from a three-dimensional point cloud, a set of grasp poses that allow a robot to grasp the object; using a second neural network to determine an evaluation of individual grasps in the set of grasp poses; and refining the individual grasps in the set of grasp poses on the basis of at least in part, a gradient of the evaluation determined by the second neural network to produce the set of refined grasp poses.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to variational grasp generation. [Background technology]

[0002] Robotic automation is an important field that, in various implementations, allows for improvements in productivity, safety, and economy when performing tasks. For robots that manipulate objects, generating a grasping pose is often a critical component of the task. Summary of the Invention [Problem to be solved by the invention]

[0003] In one example, a robot observes an object and determines where to position its gripper (3D position and 3D orientation, also called pose) so that the robot can pick up the object. The stability of each grasp may depend on the shape of the object and gripper, the mass distribution of the object, and surface friction. The shape around the object may impose further constraints by limiting the grasp points that can be reached in a scene without causing the robot's manipulator to collide with other objects. In some examples, this problem is addressed by shape-inspired heuristics for selecting reliable grasp points around the object, possibly followed by a more detailed shape analysis of the stability and reachability of sampled grasps. Many of these approaches rely on the availability of a complete 3D model of the object, which can be a severe limitation in realistic scenarios, for example, when the robot only observes the scene with a noisy depth camera. Therefore, improved grasp decision methods are needed. [Means for solving the problem]

[0004] According to one aspect of the present invention, 1. A computer system comprising: one or more processors; a computer-readable memory storing executable instructions that cause said computer system to at least: Equipped with The computer system, when executed by the one or more processors, generating, from the three-dimensional point cloud of the object, a set of grasping poses that enable the robot to grasp the object, using a first neural network; determining, using a second neural network, an evaluation of each grasp within the set of grasp poses; The computer system refines each grasp in the set of grasp poses based at least in part on the gradient of the evaluation determined by the second neural network, and generates the refined set of grasp poses. [Brief explanation of the drawings]

[0005] [Figure 1] 1A-1C illustrate examples of a robotic system for grasping various objects, according to one embodiment. [Figure 2] FIG. 10 illustrates an example of a predicted grasp on a mug, according to one embodiment. [Figure 3] FIG. 10 illustrates an example of a gripping coordinate frame, according to one embodiment. [Figure 4] FIG. 1 illustrates an example of a method for identifying a gripping pose, according to one embodiment. [Figure 5] FIG. 1 illustrates an example process for training a system to identify grip poses, according to one embodiment. [Figure 6] FIG. 10 illustrates an example of a refined grip pose, according to one embodiment. [Figure 7] FIG. 2 illustrates an example of training data generated using a physics simulator, according to one embodiment. [Figure 8] FIG. 10 illustrates the effect of latent space dimensionality on grasp success rate and coverage, according to one embodiment. [Figure 9]FIG. 10 illustrates the effect of the number of refinement steps on improving the accuracy and coverage of generated grasps, according to one embodiment. [Figure 10] FIG. 10 illustrates the effect of the number of sampled grasps on coverage rate, according to one embodiment. [Figure 11] FIG. 10 illustrates an example of a robotic gripper and assembled object used to test the system, according to one embodiment. [Figure 12] FIG. 10 illustrates examples of grasps generated using Grasp-Net and GPD, according to one embodiment. [Figure 13] 10A-10C show two tables of gripping experiment results, according to one embodiment. [Figure 14A] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 14B] FIG. 1 illustrates inference and / or training logic, according to at least one embodiment. [Figure 15] FIG. 1 illustrates training and deployment of a neural network, according to at least one embodiment. [Figure 16] FIG. 1 illustrates an exemplary data center system, according to at least one embodiment. [Figure 17A] FIG. 1 illustrates an example of an autonomous vehicle, according to at least one embodiment. [Figure 17B] 17B illustrates an example of the location and field of view of the cameras of the autonomous vehicle of FIG. 17A, according to at least one embodiment. [Figure 17C] FIG. 17B is a block diagram illustrating an example system architecture of the autonomous vehicle of FIG. 17A, according to at least one embodiment. [Figure 17D] FIG. 17B illustrates a system for communication between a cloud-based server and the autonomous vehicle of FIG. 17A, according to at least one embodiment. [Figure 18] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 19] FIG. 1 is a block diagram illustrating a computer system according to at least one embodiment. [Figure 20] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 21] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 22] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores, according to at least one embodiment. [Figure 23A] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores, according to at least one embodiment. [Figure 23B] FIG. 1 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores, according to at least one embodiment. [Figure 24A] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 24B] FIG. 10 illustrates additional exemplary graphics processor logic, according to at least one embodiment. [Figure 25] FIG. 1 illustrates a computer system according to at least one embodiment. [Figure 26A] FIG. 1 illustrates a parallel processor, according to at least one embodiment. [Figure 26B] FIG. 1 illustrates a partition unit, according to at least one embodiment. [Figure 26C] FIG. 1 illustrates a processing cluster, according to at least one embodiment. [Figure 26D] FIG. 1 illustrates a graphics multiprocessor according to at least one embodiment. [Figure 27] FIG. 1 is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment. [Figure 28] FIG. 1 illustrates a deep learning application processor, according to at least one embodiment. [Figure 29]FIG. 1 is a block diagram illustrating an exemplary neuromorphic processor, according to at least one embodiment. [Figure 30] FIG. 1 illustrates at least a portion of a graphics processor, according to at least one embodiment. [Figure 31] FIG. 1 illustrates at least a portion of a graphics processor, according to at least one embodiment. [Figure 32] FIG. 1 is a block diagram of at least a portion of a graphics processor core, according to at least one embodiment. [Figure 33A] FIG. 1 illustrates thread execution logic, according to at least one embodiment. [Figure 33B] FIG. 1 illustrates thread execution logic, according to at least one embodiment. [Figure 34] FIG. 1 illustrates a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 35] FIG. 1 illustrates a general purpose processing cluster (“GPC”), according to at least one embodiment. [Figure 36] FIG. 1 illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment. [Figure 37] FIG. 1 illustrates a streaming multiprocessor, according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0006] This paper describes a technique that frames the grasp generation problem as sampling a set of grasps using a variational autoencoder and then assesses and refines the sampled grasps using a grasp evaluator model. Both the grasp sampler and grasp refinement networks take as input 3D point clouds observed by a depth camera. Evaluation of this approach is provided in simulation and real-world robotic experiments. In one example, the technique described herein achieves an 88% success rate on a variety of commonly used objects with diverse appearances, sizes, and weights. The model is trained only in simulation and works in the real world without any extra steps.

[0007] 1. Introduction Grasp selection is a key problem in robotic manipulation. Here, a robot needs to observe an object and decide where to move its gripper (3D position and 3D orientation) to pick up this object (see Figure 1). Grasp selection can be complex because grasp stability depends on the object and gripper shape, the object's mass distribution, and surface friction. The shape around an object can impose further constraints on which grasp points can be reached in a scene without causing the robot's manipulator to collide with other objects (see Figure 2). In some instances, this problem is addressed by shape-inspired heuristics for selecting reliable grasp points around an object, optionally followed by a more detailed shape analysis of the safety and reachability of sampled grasps. Many of these approaches rely on the availability of a complete 3D model of the object, which can be a limitation in some realistic scenarios, for example, when the robot only observes the scene with a noisy depth camera. To overcome this limitation, some embodiments move the camera to generate a complete object model or perform shape completion, followed by shape-based grasp analysis. However, in some embodiments, moving the camera may not be possible in constrained spaces, and shape completion may not be accurate enough for grasp generation and evaluation.

[0008] In one embodiment, a deep learning technique is used to evaluate grasp quality from raw point cloud data. While this approach provides good grasp assessment, it still uses manually designed heuristics to sample grasps for evaluation or relies on black-box optimization techniques, such as cross-entropy method (CEM). Furthermore, this approach does not provide an efficient means for improving the sampled grasps. This specification introduces a learning-based framework to efficiently generate a diverse set of stable grasps for unknown objects. This approach introduces two network architectures that sample, evaluate, and improve grasps. Various embodiments include one or more of the following features.

[0009] A variational autoencoder (VAE) that can be trained to map a partial point cloud of an observed object to a diverse set of grasps of the object. Importantly, our VAE provides high coverage of all feasible working grasps while generating only a small number of unsuccessful grasps.

[0010] To improve the accuracy of the VAE sample, we introduce a grasp classifier network, which maps the observed object and robot gripper point clouds to a quality assessment of the 6D gripper pose. Importantly, we show that the gradient of this network can be used to improve the grasp sample, for example, to move the grasp sample to avoid collisions or to ensure that the gripper is well aligned with the object.

[0011] We demonstrate that our method outperforms previous methods, enabling the robot to lift 17 objects with an 88% success rate. Furthermore, we show that our method generates a diverse set of grasping samples while maintaining a high success rate.

[0012] This paper is structured as follows: First, we contrast related methods of grasping using deep learning, then we describe the different components of our grasp decision method: grasp sampling, evaluation, and refinement. Furthermore, to demonstrate the impact of different hyperparameters on various ablation studies, the techniques described here are evaluated on a real-world robotic platform.

[0013] 2. Alternative Embodiments Learning 6DOF Grasps. Some embodiments for solving robotic grasping problems are data-driven. Other embodiments are based on hand-crafted feature vectors. Further embodiments utilize convolutional architectures to operate on raw visual measurements. Many grasp synthesis techniques are enabled by representing grasps as oriented rectangles in the image. This 3DOF representation constrains gripper poses to be parallel to the image plane. However, drawbacks of such representations can include: such representations limit the variety of grasps, which can make it impossible to lift an object if further constraints are imposed by the arm or task; and for static image sensors, this can lead to an overly restricted workspace.

[0014] The techniques described herein address the problem of predicting a complete 6DOF pre-grasp pose, which can be challenging because portions of the object are occluded, affecting the success of the grasp. Various embodiments circumvent this problem by including the auxiliary task of reconstructing the shape of the target object. The primary task of predicting the 6DOF grasp outcome can then use the local shape that is not part of the measurement. Various embodiments learn a grasp score function, which is also used for grasp refinement.

[0015] While some implementations frame this problem as a regression to a single best grasp pose, these implementations inherently lack the ability to predict the diverse distribution of feasible grasps. For example, one implementation classifies 24 predefined orientations to select a 6DOF pre-grasp pose. This coarse decomposition, SO(3), necessarily leads to limited diversity in predicted grasps. In contrast, the grasp point detection method ("GPD") uses a denser sampling of candidate grasps. A point from the observed point cloud is randomly sampled to construct a Darboux frame aligned with the estimated surface normals and local orientations of the principal curvatures. While this heuristic produces a highly diverse set of candidate grasps, it is unable to generate grasps along thin structures, such as the rim of a mug, plate, or bowl, because it is difficult to estimate these surface normals from noisy measurements. The techniques described herein do not suffer from such biases. As a result, the techniques described herein can find grasps that GPD cannot.

[0016] Various embodiments frame the grasping problem as a reinforcement learning problem or an approximation thereof. The learned grasping policy is more expressive than describing only the final grasp pose. Nevertheless, the action space of many examples is typically se(2), limiting diversity to top-down grasping.

[0017] Deep neural networks for learning from 3D data. Various embodiments apply deep learning to 3D point cloud data. In some examples, the 3D data is represented as 3D voxels or as features extracted from 2.5 depth images and processed using convolutional neural networks. PointNet and PointNet++ can represent 3D data and efficiently extract representations. Other examples demonstrate significant improvements in pose estimation, semantic segmentation, and part segmentation of 3D objects using various variations of network architectures to represent 3D data. To estimate a successful grasp, the 6DOF pose of the grasp needs to be accurate. Operating on a single RGB image does not provide the required accuracy because the input and output are not in the same domain. Therefore, we generate grasps using 3D point cloud data. We use PointNet++ to learn representations for generating and evaluating grasps in SE(3).

[0018] Variational Autoencoders. Variational autoencoders ("VAEs") are one of the major categories of deep generative models. VAEs can be trained unsupervised to maximize the likelihood of the training data. VAEs have been applied to a variety of tasks, including future prediction, new viewpoint generation, and object segmentation. In this work, we use VAEs to sample a diverse set of grasps of SE(3).

[0019] The generator module is a VAE based on different samples from the latent space and the observed point cloud X. The generator module generates different grasping proposals, and an evaluation network (classifier) ​​accepts or rejects them based on how likely they are to be successful. Both the generator and classifier take the object's 3D point cloud X as part of their input.

[0020] 3.6DOF Grasp Pose Generation We construct grasp pose generation as a process of generating a set of robot gripper poses such that closing the gripper in any of these poses achieves a stable grasp of the object. Furthermore, this process should generate a diverse set of poses that ultimately encompasses all feasible ways in which an object can be grasped. The robot gripper pose is given by SE(3), which specifies the 3D translation and 3D orientation of the gripper. Here, we focus on generating grasp poses for a single object; further limitations due to the manipulator's reach and other objects in the scene are beyond the scope of this work and can be addressed by manipulator trajectory optimization techniques. Grasp pose generation is challenging due to the narrow subspace of successful grasps within the space of all feasible grasps. Small perturbations in the grasp pose can turn a successful grasp into a failed one. To generate a diverse set of stable grasps, our method uses a variational autoencoder network to sample grasp poses, followed by an iterative evaluation and refinement process. The input to our method is a point cloud of the object that the robot should lift.

[0021] Specifically, the posterior distribution P(G * |X), where G * represents the space of all successful grasps, and X is the partial point cloud of the object observed by the camera. * is denoted by (R,T)∈SE(3), where R∈SO(3) and

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[0022] G * Since the number of modes in is not known in advance, the number of successful grasping g∈G * We propose to learn a generator module that maximizes the likelihood of a grasp g∈G. Since the generator only observes successful grasps during training, the generator cannot detect unsuccessful grasps g∈G. - To detect and refine these negative grasps, an evaluation module is trained to predict P(S|g,X), i.e., the probability of success for a grasp g and the observed point cloud X. When applied to a sampled grasp, the evaluation module predicts the success of the grasp, and the success gradient is propagated back through the network to generate improved grasp poses. This process can be repeated. Discarding any grasps that remain below the threshold provides a final set of high-quality grasps.

[0023] 3.1. Variational Grasping Sampler The grasp sampler shown in Figure 5 is a sampler for P(G|X), i.e., a predefined set of successful grasps g∈G * is a generative model that maximizes the likelihood of a set of . Given a set of points X and a latent variable z, the sampler is a deterministic function that predicts a grasp. It is assumed that P(z), the probability density function of the latent space, is known and selected a priori. In our method, we use P(z)=N(0,1). Given a set of points X, different grasps are generated by sampling different z from P(z). The likelihood of the generated grasp can be written as: P(G|X)=∫P(G|X,z;Θ)P(z)dz (1) Each positive grasp g∈G *The optimization of equation (1) requires integrating over all values ​​in the latent space, which is intractable. To make equation (1) tractable, the encoder Q(z|X, g) maps each pair of points X and grasp g to a small subspace in the latent space z. Given a sampled z~Q, the decoder maps the grasps

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[0024] In this encoding and decoder architecture, each point has a 3D coordinate and a feature vector. Features at each layer are computed based on each point's features and their 3D relationships to each other. The features of each input point x∈X are concatenated into g=[R,T]. In the decoder, each point's features are concatenated with a latent variable z. The encoder learns to compress the relative information of the point cloud X and the latent variable g in a way that can be reconstructed by the decoder.

[0025] 3.2. Evaluation of grip posture The grasp sampler trains a continuous posterior distribution P(G|X,z) using only positive grasps. As a result, the grasp sampler may contain unsuccessful grasps between the modes of the distribution. These transient grasps and other false positives must be identified and removed. To do this, a grasp evaluation network is required, which assigns a success probability P(S|g,X) to each grasp. This network must infer grasps based on the observed point cloud X, while at the same time being able to extrapolate to unobserved portions of the object. Some embodiments learn to classify grasps based only on the observed local portions of the object. In practice, the observed point cloud of an object often has imperfections, such as missing or noisy depth values. To mitigate this problem, previous methods rely on the use of high-quality depth sensors or the use of multiple views, which limits the system's deployment outside of controlled environments. In this work, we classify each grasp using only the object's incomplete observed point cloud X.

[0026] The success of the grasp pose depends on the relative pose of the grasp with respect to the object. The inputs to the evaluator network are a point cloud X and a grasp g. As with the grasp sampler, we use the PointNet architecture for the grasp evaluator. There are several ways to classify grasps. First, a simple approach is to associate the 6D pose of the grasp g with features for each point x∈X in the first layer. Our experiments show that this representation leads to poor grasp classification accuracy. Instead, we propose representing the grasp g in a way that is more closely tied to the object point cloud. We approximate the robot gripper by a point cloud Xg rendered according to the 6D grasp pose g. We combine the object point cloud X and the gripper point cloud Xg into a single point cloud by using an additional binary feature that indicates whether the point belongs to the object or the gripper. In the PointNet architecture, the features of each point are a function of the point itself, its neighbors, and the relative spatial relationships of the points. By using the integrated point cloud X∪Xg, it becomes natural to classify grasps using all the relative information between the grasp pose g and the object point cloud X. The grasp evaluator: L 評価器 =-(ylog(s)+(1-y)log(1-s)) (4) is optimized using cross-entropy loss by optimizing where y is the ground truth binary label of the grasp indicating whether the grasp is successful or not, and s is the predicted probability of success by the evaluator.

[0027] To train a robust evaluator, the model needs to be trained using both positive and negative grasps. Since the space of all feasible 6D grasp poses is combinatorially large, it is impossible to sample all negative grasps. Instead, we perform hard negative mining to sample negative grasps. - The set of G is defined as grasps that have a similar pose to the positive grasp, but collide with the object or are too far from the object to grasp it. More formally, G - teeth, G - ={g - |∃g∈G * :L(g,g - )<∈} (5) is defined as where L(.,.) is defined in equation (3). During training, g ー is sampled from a pre-generated set of negative grasps and randomly perturbs the positive grasps, either causing the gripper mesh to collide with the object mesh or moving the gripper mesh away from the object.

[0028] 3.3. Repetitive Refinement of Grasp Posture The evaluation network rejects grasps that are unlikely to be realized, but most of the rejected grasps may be close to successful grasps. We can exploit this insight by searching for a transformation Δg∈SE(3)) that turns an unsuccessful grasp into a successful one. More formally, we search for a refinement transformation Δg that increases the probability of success, i.e., P(s=1|g+Δg)>P(s=1|g). The evaluation network represents a differentiable function of success s based on the point cloud X and the grasp g. The refinement transformation that leads to the greatest improvement in the success probability can be computed by taking the derivative of success with respect to the grasp transformation: ∂S / ∂g. The partial derivative ∂S / ∂g provides the transformation for each point in the gripper point cloud Xg that increases the probability of success. Because the derivative is computed independently for each point of the gripper, it may lead to a non-rigid transformation for Xg. To apply rigid body constraints, the transformed gripper point cloud Xg is computed by the Euler angles R g =(α g , β g , γ g ) and transformation T g is defined as a function of the grip orientation defined in g is computed as follows:

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[0029] Because the partial derivative ∂S / ∂g is only an approximation that is valid in a local neighborhood, we use a hyperparameter η to bound the size of the update at each step. In fact, we choose η in such a way that the maximum translational update of the grasp does not exceed 1 cm. Figure 6 shows the estimated refinement of the grasp at different iterations.

[0030] 4. Experiment Training Data for Grasping. To generate a reference set of successful grasps, we use the physics simulation FleX, which provides realistic simulation of grasps for arbitrary object shapes. Candidate grasps are sampled based on the object shape. Random points on the object's mesh surface are sampled, and the gripper's z-axis (see Figure 3) is aligned with the surface normal. The distance between the gripper and the object surface is uniformly sampled between zero and the length of the gripper's fingers. Orientations around the z-axis are also drawn from a uniform distribution. Only grasps that are collision-free and have a closure between the fingers intersect the object are simulated. A total of 206 objects from six categories in ShapeNet are used: boxes, cylinders (randomly generated), as well as balls, bottles, and mugs. A total of 10,816,720 candidate grasps are sampled, of which 7,074,038 (65.4%) are simulated, i.e., grasps that pass the non-empty closure test. The simulation consists of a floating parallel-jaw gripper and a floating object in the absence of gravity. Surface friction and object density are held constant. The gripper closes its fingers and then performs a predefined shaking motion. If the object is held between the fingers, the grasp is labeled successful. In total, we generate 2,104,894 successful grasps (19.4%). The resulting positive grasp labels are densely distributed, as shown in the example in Figure 7.

[0031] Training. Both the grasp generator and evaluator networks use PointNet++ and have similar architectures. Both modules consist of three sets of abstraction layers followed by a fully connected layer. Each batch of training data for the generator network consists of a rendering of the object from a random view and 64 grasps sampled using stratified sampling to ensure sufficient diversity in the sampled grasps. The weight of the KL divergence loss (α in Equation (2)) is set to 0.01. Each batch of training data for the evaluator network consists of 30% positive grasps, 30% negative grasps, and 40% hard negative grasps. The hard negative grasps are selected from the positive grasps perturbed by applying ±0.6 radians to each axis and ±3 cm to translation. Both models are trained with the Adam optimizer using a learning rate of 0.0001. All grasps were generated in simulation; no real data was used to train either model (see Section 4).

[0032] Network Architecture Details. Both the grasp generator and evaluator are based on the PointNet++ architecture. Both models consist of three set abstraction layers. Each set abstraction layer samples 128 points, 32 points, and all points. Each set abstraction layer samples points within 2 cm, 4 cm, infinity, and a radius of the sampled point. Each set abstraction layer computes features using three fully connected layers. The number of channels in each set abstraction layer is [64, 64, 128], [128, 128, 256], and [256, 256, 512], respectively. The set abstraction layers are followed by two fully connected layers with 1024 units. The grasp generator network outputs the rotation R and translation T, expressed as unit quaternions. The quaternions are generated by applying the L2 norm to a linear fully connected layer. No normalization is performed on the translation T. The evaluator network uses a softmax layer to predict a score for each grasp.

[0033] Evaluation Metrics. To quantitatively evaluate a grasping method, we use two metrics: success rate and coverage rate. The success rate is the percentage of successful grasps among all predicted grasps. This metric only considers the grasps that are executed and does not include any information about other grasps. Predicting only one grasp is not appropriate for 3D grasping, because the predicted grasp may lead to collisions between the robot and other objects in the environment, or there may be no feasible and valid robot joint configuration that can reach the predicted grasp. To achieve a feasible and successful grasp, it is necessary to generate a diverse set of grasps from different translations and orientations to check kinematic feasibility and collision avoidance. As a result, we can capture the grasp diversity and generate a positive grasp G. * We introduce a coverage ratio that measures how well the space of g is covered by the generated grasps.

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[0034] 4.1. Analysis and Ablation Studies We quantitatively evaluate the impact of different parameters and modules using the same physics simulations used to generate training data (Section 4). For the ablation study, we generate 86 object point cloud observations for 10 different objects held out during training. For each point cloud, 200 latent values ​​are sampled and refined over 10 iterations, resulting in 2200 grasps per viewpoint and 182,600 grasps in total.

[0035] Dimensionality of the latent space. There is an inherent tension when determining the dimension of the latent space that affects the quality of the generated grasps. The latent space must have sufficient capacity to allow the VAE to reconstruct the grasp. At the same time, a high-dimensional latent space can lead to overfitting, requiring significantly more training data coverage. It also degrades the quality of the grasps sampled during inference, especially if the latent values ​​sampled during inference were not seen by the generator network during training. To analyze this effect, we evaluate the generator network with increasing dimensionality of the latent space. Figure 8 shows the resulting success-coverage curves. As can be seen, one dimension has the lowest AUC because the latent space does not have sufficient capacity. Three- and four-dimensional latent spaces perform slightly better on the training data. vae However, this leads to poor performance during inference because the VAE cannot densely cover the latent space during training. Given these results, we choose a two-dimensional latent space for all subsequent evaluations.

[0036] Impact of refinement on grasp quality. Refining a grasp increases the probability of success based on the evaluator network, but this does not necessarily mean that the refined grasp will be successful during the test period. To analyze the actual improvement introduced by each refinement step, we evaluate the grasps in simulation. Figure 9 shows the grasp success-coverage curves computed at each refinement iteration. As can be seen, not only is the success rate of the generated grasps increasing, but so is the coverage rate. This means that as grasps improve, these grasps will be more likely to be successful during the test period. * The AUC of the curve reaches a plateau after the 10th iteration of refinement.

[0037] Effect of Sampled Grasps on Coverage. In the previous section, we performed the ablation study using 200 random latent values ​​because that was the largest batch size that fit into GPU memory and was the same setting we used for our robot experiments. Because the number of sampled latent values ​​was limited, the coverage ratio in Figure 9 was less than 0.5 even after 10 refinement steps. To investigate how the number of sampled grasps affects coverage, we sample 2000 grasps in 10 different batches for the same point cloud used in the previous ablation study. Figure 10 shows how the coverage ratio increases with increasing samples.

[0038] 4.2.Robot Experiments The ultimate test of the generated grasps will be to execute them in the real world, dealing with imperfect perception, robot joint limitations, control errors, and hard-to-model physical phenomena such as friction. We hope to demonstrate the following: (1) our method, trained only in simulation, scales to the real world; (2) the generated grasp distributions are diverse enough to find successful grasps even after discarding those that violate the robot's kinematic and collision constraints; and (3) our method's diverse grasp sampling leads to a higher success rate compared to alternative 6DOF grasp planners ("GPDs").

[0039] All experiments are performed using a 7DOF Franka Panda manipulator with an Intel RealSense D415 camera mounted on its parallel jaw gripper. A set of commonly used objects is chosen that are visually and physically challenging. The weights of the objects range from 42g (pepper shaker) to 618g (mustard bottle). The hardware setup and test set of objects are shown in Figure 11.

[0040] Protocol: Each object is placed on a table in front of the robot in three different stable poses. The robot's end effector is moved so that the hand-mounted depth camera has an unobstructed view of the table. A grasp is considered successful if the robot can lift the object 10 cm without dropping it.

[0041] The measured point cloud is filtered to remove the table plane and the remaining points are clustered. This extracted object point cloud serves as input to our method and to GPD. Both methods return a list of scored grasps. We use a motion planner to identify a collision-free path for each grasp pose and execute the grasp pose with the highest score. If none of the grasps in the returned set can be executed, the test is considered a failure. A total of 51 tests are run per method.

[0042] Results. Table 1 shows that our method outperforms GPD in success rate across all objects. One reason for this is that our method generates a wide variety of grasps, which makes it easier to find a kinematically feasible grasp. In contrast, GPD does not generate many different grasps, which sometimes leads to situations where it cannot find a kinematically feasible grasp. The mug is particularly difficult for GPD because it does not generate any edge grasps (see Figure 12). Another source of difficulty is grasps where the finger gripper is tangential to one of the object's surfaces. In this case, a slight error in executing the grasp can change the grasp from grasping the object to pushing it. Detailed experimental results are shown in Table 2 and Figure 13.

[0043] 5. Conclusion In this work, we introduce a 6DOF GraspNet to generate a diverse set of grasps for unknown objects. Our method consists of a trained VAE that samples various grasps on an object. While VAEs can capture the complex distribution of successful grasp poses, they do not provide the precision necessary for highly robust grasp generation. To overcome this limitation, we further introduce a grasp evaluator network that can evaluate grasp quality and refine grasps in an iterative process. To our knowledge, neither a learned grasp sampler nor a gradient-based refinement process has been introduced before.

[0044] Our model is trained using synthetic grasp data generated by a physical simulator. Therefore, our model can be scaled to a larger set of objects without the need to collect any real-world data. By implementing our method on a real robot platform and built-in RGB-D camera, we demonstrate the transferability of our method to the real world for objects with unknown 3D models. We conducted robotic experiments on 17 objects with unknown 3D models and achieved state-of-the-art results in 3D grasping. We also conducted a thorough analysis of the generated grasps in terms of success rate and coverage via ablation studies on a realistic physical simulator. [Table 1] [Table 2]

[0045] Table 2. Detailed results of the robot experiment. R: The experiment was successful. X: The generated grasps were not successful in grasping the object. *: None of the generated grasps were kinematically feasible.

[0046] This approach opens up many interesting directions in computer vision and robotics. In our method, all potential values ​​are uniformly sampled, and then grasps are removed based on collision checking and kinematically feasible solutions. A possible extension is to train the sampler or evaluator to consider not only symmetric objects but also surrounding objects, thus directly avoiding the creation of colliding or infeasible grasps. Another interesting direction is to use the evaluator not only to refine the sampled grasps, but also to provide real-time feedback guidance to the manipulator approaching the object. Our experiments provide evidence that our gradient-based approach can successfully bring the manipulator closer and closer to a successful grasp.

[0047] Figure 14A illustrates inference and / or training logic 1415 used to perform inference and / or training operations for one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with Figures 14A and / or 14B.

[0048] In at least one embodiment, the inference and / or training logic 1415 may include, without limitation, data storage 1401 for storing forward propagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used to infer in accordance with one or more embodiments. In at least one embodiment, data storage 1401 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments while forward propagating input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, any portion of data storage 1401 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0049] In at least one embodiment, any portion of data storage 1401 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, data storage 1401 may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether data storage 1401 is internal or external to a processor, or whether it is comprised of DRAM, SRAM, flash, or some other type of storage, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in neural network inference and / or training, or any combination of these factors.

[0050] In at least one embodiment, the inference and / or training logic 1415 may include, without limitation, data storage 1405 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, data storage 1405 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments while backpropagating input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, any portion of data storage 1405 may be included with other on-chip or off-chip data storage, including L1, L2, or L3 cache of a processor, or system memory. In at least one embodiment, any portion of data storage 1405 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, data storage 1405 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether data storage 1405 is internal or external to the processor, or whether it is comprised of DRAM, SRAM, flash, or some other type of storage, may depend on the storage available on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in the inference and / or training of the neural network, or any combination of these factors.

[0051] In at least one embodiment, data storage 1401 and data storage 1405 may be separate storage structures. In at least one embodiment, data storage 1401 and data storage 1405 may be the same storage structure. In at least one embodiment, data storage 1401 and data storage 1405 may be partially the same storage structure and partially separate storage structures. In at least one embodiment, data storage 1401 and any portion of code and / or data storage 1405 may be included with other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0052] In at least one embodiment, inference and / or training logic 1415 may include, without limitation, one or more arithmetic logic units (“ALUs”) 1410 for performing logical and / or mathematical operations based at least in part on or indicated by the training and / or inference code, which may result in activations (e.g., output values ​​from layers or neurons in a neural network) stored in activation storage 1720, which are functions of input / output and / or weight parameters stored in data storage 1401 and / or data storage 1405. In at least one embodiment, the activations stored in activation storage 1420 are generated according to linear algebra or matrix-based calculations performed by ALU 1410 in response to executing instructions or other code, where weight values ​​stored in data storage 1405 and / or data 1401 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in data storage 1405, data storage 1401, or another storage, on-chip or off-chip. In at least one embodiment, ALU 1410 is contained within one or more processors or other hardware logic devices or circuits, although in other embodiments, ALU 1410 may be external to the processors or other hardware logic devices or circuits that use them (e.g., a coprocessor). In at least one embodiment, ALU 1410 may be included within an execution unit of a processor, or may be otherwise included within an ALU bank accessible by execution units of a processor, either within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.).In at least one embodiment, data storage 1401, data storage 1405, and activation storage 1420 may be in the same processor or other hardware logic device or circuitry; in other embodiments, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same processor or other hardware logic device or circuitry with different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 1420 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry, and may be fetched and / or processed using the processor's fetch, decode, schedule, execute, retire, and / or other logic.

[0053] In at least one embodiment, activation storage 1420 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 1420 may be completely or partially internal to or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 1420 is internal or external to a processor, or whether it is comprised of DRAM, SRAM, flash, or some other type of storage, for example, may depend on available on-chip versus off-chip storage, latency requirements of the training and / or inference functions being performed, batch sizes of data used in neural network inference and / or training, or any combination of these factors. In at least one embodiment, the inference and / or training logic 1415 shown in Figure 14A may be used in conjunction with an application-specific integrated circuit ("ASIC"), such as a Tensorflow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., "Lake Crest") processor from Intel Corp. In at least one embodiment, the inference and / or training logic 1415 shown in Figure 14A may be used in conjunction with other hardware, such as central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or a field programmable gate array ("FPGA").

[0054] FIG. 14B illustrates inference and / or training logic 1415 according to at least one various embodiment. In at least one embodiment, the inference and / or training logic 1415 may include, without limitation, hardware logic in which computational resources are dedicated to, or otherwise used only in conjunction with, weight values ​​or other information corresponding to one or more layers of neurons in a neural network. In at least one embodiment, the inference and / or training logic 1415 illustrated in FIG. 14B may be used in conjunction with an application-specific integrated circuit (ASIC), such as a Tensorflow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, the inference and / or training logic 1415 illustrated in FIG. 14B may be used in conjunction with other hardware, such as central processing unit (CPU) hardware, graphics processing unit (“GPU”) hardware, or a field-programmable gate array (FPGA). In at least one embodiment, inference and / or training logic 1415 may include, without limitation, data storage 1401 and data storage 1405, which may be used to store weight values ​​and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment shown in FIG. 14B , data storage 1401 and data storage 1405 are each associated with dedicated computational resources, such as computation hardware 1402 and computation hardware 1406, respectively. In at least one embodiment, computation hardware 1402 and computation hardware 1406 each include one or more ALUs that perform mathematical functions, such as linear algebraic functions, solely on the information stored in data storage 1401 and data storage 1405, respectively, with the results stored in activation storage 1420.

[0055] In at least one embodiment, each of data storage 1401 and 1405 and corresponding computational hardware 1402 and 1406 corresponds to a different layer of a neural network, such that activations resulting from one “storage / computation pair 1401 / 1402” between data storage 1401 and computational hardware 1402 are provided as input to a next “storage / computation pair 1405 / 1406” between data storage 1405 and computational hardware 1406 to reflect the conceptual organization of the neural network. In at least one embodiment, storage / computation pairs 1401 / 1402 and 1405 / 1406 may correspond to two or more layers of the neural network. In at least one embodiment, additional storage / computation pairs (not shown) may be included in inference and / or training logic 1415 after or in parallel with storage / computation pairs 1401 / 1402 and 1405 / 1406.

[0056] FIG. 15 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an untrained neural network 91506 is trained using a training data set 1502. In at least one embodiment, the training framework 1504 is the PyTorch framework, while in other embodiments, the training framework 1504 is Tensorflow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, the training framework 1504 trains the untrained neural network 1506 and enables it to be trained using processing resources described herein to generate a trained neural network 1508. In at least one embodiment, the weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, the training may be performed in a supervised, semi-supervised, or unsupervised manner.

[0057] In at least one embodiment, the untrained neural network 1506 is trained using supervised learning, where the training data set 1502 includes inputs paired with desired outputs for those inputs, or the training data set 1502 includes inputs with known outputs, and the outputs of the neural network are manually scored. In at least one embodiment, the untrained neural network 1506 is trained in a supervised manner, processing inputs from the training data set 1502 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then back-propagated through the untrained neural network 1506. In at least one embodiment, the training framework 1504 adjusts the weights that control the untrained neural network 1506. In at least one embodiment, training framework 1504 includes tools to monitor how well untrained neural network 1506 is converging toward a model, such as trained neural network 1508, that is suitable for generating correct answers, such as results 1514, based on known input data, such as new data 1512. In at least one embodiment, training framework 1504 iteratively trains untrained neural network 1506 while adjusting weights to refine the output of untrained neural network 1506 using a loss function and a tuning algorithm, such as stochastic gradient descent. In at least one embodiment, training framework 1504 trains untrained neural network 1506 until untrained neural network 1506 reaches a desired accuracy. In at least one embodiment, trained neural network 1508 can then be deployed to implement any number of machine learning operations.

[0058] In at least one embodiment, the untrained neural network 1506 is trained using unsupervised learning, where the untrained neural network 1506 attempts to train itself using unlabeled data. In at least one embodiment, the training data set 1502 for unsupervised learning includes input data without any associated output data or “ground truth” data. In at least one embodiment, the untrained neural network 1506 can learn groupings within the training data set 1502 and determine how individual inputs relate to the untrained data set 1502. In at least one embodiment, unsupervised training can be used to generate self-organizing maps, which are a type of trained neural network 1508 that can perform operations useful for reducing the dimensionality of the new data 1512. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows for the identification of data points in the new data set 1512 that deviate from the normal patterns of the new data set 1512.

[0059] In at least one embodiment, semi-supervised learning may be used, which is a technique in which labeled and unlabeled data are mixed in the training data set 1502. In at least one embodiment, the training framework 1504 may be used to perform incremental learning, such as by transfer learning techniques. In at least one embodiment, incremental learning allows the trained neural network 1508 to adapt to new data 1512 without forgetting the knowledge instilled in the network during initial training.

[0060] Data Center 16 illustrates an exemplary data center 1600 in which at least one embodiment may be used. In at least one embodiment, data center 1600 includes a data center infrastructure layer 1610, a framework layer 1620, a software layer 1630, and an application layer 1640.

[0061] 16, data center infrastructure layer 1610 may include a resource orchestrator 1612, grouped computing resources 1614, and node computing resources (“node CRs”) 1616(1) through 1616(N), where “N” represents any positive integer. In at least one embodiment, node CRs 1616(1) through 1616(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid-state drives or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power supply modules, and cooling modules. In at least one embodiment, one or more of the nodes CR 1616(1)-1616(N) may be a server having one or more of the computing resources described above.

[0062] In at least one embodiment, grouped computing resources 1614 may include separate groups of node CRs housed within one or more racks (not shown), or multiple racks housed in a data center at various graphical locations (also not shown). Separate groups of node CRs within grouped computing resources 1614 may include grouped compute resources, network resources, memory resources, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power supply modules, cooling modules, and network switches in any combination.

[0063] In at least one embodiment, resource orchestrator 1622 may configure or otherwise control one or more nodes CR 1616(1)-1616(N) and / or grouped computing resources 1614. In at least one embodiment, resource orchestrator 1622 may include a software design infrastructure (“SDI”) management entity for data center 1600. In at least one embodiment, resource orchestrator may include hardware, software, or some combination thereof.

[0064] In at least one embodiment shown in FIG. 16 , framework layer 1620 includes job scheduler 1632, configuration manager 1634, resource manager 1636, and distributed file system 1638. In at least one embodiment, framework layer 1620 may include frameworks to support software 1632 in software layer 1630 and / or one or more applications 1642 in application layer 1640. In at least one embodiment, software 1632 or applications 1642 may each include web-based service software or applications, such as those offered by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1620 may be a type of free and open-source software web application framework, such as, but not limited to, Apache Spark® (hereinafter “Spark”), which can use distributed file system 1638 for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler 1632 may include a Spark driver to facilitate scheduling of workloads supported by various tiers of data center 1600. In at least one embodiment, configuration manager 1634 may be capable of configuring different tiers, such as software tier 1630 and framework tier 1620, which includes Spark and distributed file system 1638 to support large-scale data processing. In at least one embodiment, resource manager 1636 may be capable of managing clustered or grouped computing resources that are mapped or allocated to support distributed file system 1638 and job scheduler 1632. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1614 in data center infrastructure tier 1610.In at least one embodiment, resource manager 1636 may manage these mappings or allocated computing resources in conjunction with resource orchestrator 1612.

[0065] In at least one embodiment, software 1632 included in software layer 1630 may include software used by nodes CR 1616(1)-1616(N), grouped computing resources 1614, and / or at least a portion of distributed file system 1638 of framework layer 1620. The one or more types of software may include, but are not limited to, internet web page searching software, email virus scanning software, database software, and streaming video content software.

[0066] In at least one embodiment, applications 1642 included in application layer 1640 may include one or more types of applications used by nodes CR 1616(1)-1616(N), grouped computing resources 1614, and / or at least a portion of distributed file system 1638 of framework layer 1620. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive compute, and machine learning applications including training or inference software, machine learning framework software (e.g., PyTorch, Tensorflow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0067] In at least one embodiment, any of configuration manager 1634, resource manager 1636, and resource orchestrator 1612 may implement any number and types of self-correcting actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-correcting actions may enable data center operators of data center 1600 to avoid determining potentially faulty configurations and eliminate underutilized and / or underperforming portions of the data center.

[0068] In at least one embodiment, data center 1600 may include tools, services, software, or other resources for training one or more machine learning models or for predicting or inferring information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, machine learning models may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 1600. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 1600 by using weight parameters calculated by one or more techniques described herein.

[0069] In at least one embodiment, the data center may use a CPU, application specific integrated circuit (ASIC), GPU, FPGA, or other hardware to perform training and / or inference using the resources described above. Additionally, one or more of the software and / or hardware resources described above may be configured as a service to enable a user to train or perform inference on information, such as image recognition, speech recognition, or other artificial intelligence services.

[0070] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with Figures 14A and 14B. In at least one embodiment, inference and / or training logic 1415 may be used in the system of Figure 16 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0071] In one embodiment, the techniques described herein are applied to an autonomous vehicle or a driver assistance system for the vehicle. For example, the techniques described herein may be used to control an automated forklift or warehouse picking robot. In one embodiment, the system is used to determine a gripping pose that represents the positioning of a forklift required to lift a pallet or other object. In another embodiment, the techniques described herein are used to pick an object from a bin in an automated warehouse. In another embodiment, the system is used to determine a gripping pose for a waste collection vehicle (also called a garbage collection vehicle or refuse truck), which may be non-autonomous, autonomous, or semi-autonomous. For example, in one embodiment, the system may be used to determine the gripping pose of a gripping arm used to lift a bin (e.g., a trash can, recycling bin, or yard debris bin) and empty the contents into a separate or separate waste collection vehicle. Other vehicles or devices that use robotic arms for various purposes (e.g., moving construction materials on a job site) are also contexts in which embodiments of the present disclosure can be practiced.

[0072] 17A illustrates an example of an autonomous vehicle 1700 according to at least one embodiment. In at least one embodiment, the autonomous vehicle 1700 (alternatively referred to herein as “vehicle 1700”) may be a passenger vehicle, such as, without limitation, a car, truck, bus, and / or another type of vehicle that accommodates one or more occupants. In at least one embodiment, the vehicle 1700 may be a semi-tractor trailer truck for transporting cargo. In at least one embodiment, the vehicle 1700 may be an aircraft, a robotic vehicle, or other type of vehicle.

[0073] Autonomous vehicles may be described in terms of levels of automation as defined by the National Highway Traffic Safety Administration (“NHTSA”), a division of the U.S. Department of Transportation, and the Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, issued June 15, 2018, Standard No. J3016-201609, issued September 30, 2016, and previous and new versions of this standard). In one or more embodiments, vehicle 1700 may be capable of functionality according to one or more of Levels 1 through 5 of autonomous driving. For example, in at least one embodiment, vehicle 1700 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0074] In at least one embodiment, vehicle 1700 may include components such as, without limitation, a chassis, a vehicle body, wheels (2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 1700 may include a propulsion system 1750 such as, without limitation, an internal combustion engine, a hybrid power plant, a fully electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1750 may be coupled to a drive train of vehicle 1700, which may include, without limitation, a transmission to enable propulsion of vehicle 1700. In at least one embodiment, propulsion system 1750 may be controlled in response to receiving a signal from throttle / accelerator 1752.

[0075] In at least one embodiment, steering system 1754, which may include without limitation a steering wheel, is used to steer vehicle 1700 (e.g., along a desired path or route) when propulsion system 1750 is operating (e.g., when the vehicle is moving). In at least one embodiment, steering system 1754 may receive signals from steering actuators 1756. The steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, brake sensor system 1746 may be used to operate vehicle brakes in response to receiving signals from brake actuators 1748 and / or brake sensors.

[0076] In at least one embodiment, controller 1736, which may include, without limitation, one or more systems on a chip (“SoC”) (not shown in FIG. 17A ) and / or graphics processing units (“GPUs”), provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 1700. For example, in at least one embodiment, controller 1736 may send signals to operate vehicle brakes via brake actuators 1748, steering system 1754 via steering actuators 1756, and propulsion system 1750 via throttle / accelerator 1752. Controller 1736 may include one or more on-board (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to enable autonomous driving and / or assist a human driver in driving vehicle 1700. In at least one embodiment, the controllers 1736 may include a first controller 1736 for autonomous driving functions, a second controller 1736 for functional safety functions, a third controller 1736 for artificial intelligence functions (e.g., computer vision), a fourth controller 1736 for infotainment functions, a fifth controller 1736 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 1736 may handle two or more of the above functionalities, two or more controllers 1736 may handle a single functionality, and / or some combination thereof.

[0077] In at least one embodiment, controller 1736 provides signals to control one or more components and / or systems of vehicle 1700 in response to sensor data (e.g., sensor inputs) received from one or more sensors. In at least one embodiment, sensor data may be received from, for example, without limitation, global navigation satellite system (“GNSS”) sensors 1758 (e.g., global positioning system sensors), RADAR sensors 1760, ultrasonic sensors 1762, LIDAR sensors 1764, inertial measurement units (“IMUs”), and the like. 17A ), a speed sensor 1744 (e.g., for measuring the speed of the vehicle 1700), a vibration sensor 1742, a steering sensor 1740, a brake sensor (e.g., as part of a brake sensor system 1746), and / or other types of sensors.

[0078] In at least one embodiment, one or more controllers 1736 may receive input (e.g., represented by input data) from an instrument cluster 1732 of the vehicle 1700 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1734, an audible annunciator, a loudspeaker, and / or via other components of the vehicle 1700. In at least one embodiment, the output may include information such as vehicle speed, speeding, time, map data (e.g., a high definition map (not shown in FIG. 17A )), location data (e.g., the location of the vehicle 1700 on a map, etc.), direction, the location of other vehicles (e.g., an occupancy grid), information about objects and object conditions sensed by the controller 1736, etc. For example, in at least one embodiment, the HMI display 1734 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about a driving maneuver that the vehicle has made, is making, or will make (e.g., currently changing lanes, taking exit 34B in 2 miles, etc.).

[0079] In at least one embodiment, vehicle 1700 further includes network interface 1724, which may use a wireless antenna 1726 and / or a modem for communicating over one or more networks. For example, in at least one embodiment, network interface 1724 may be capable of communicating over Long-Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000"), etc. Additionally, in at least one embodiment, wireless antenna 1726 may enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using local area networks such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low power wide-area networks ("LPWAN") such as LoRaWAN, SigFox, etc.

[0080] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with Figures 14A and 14B. In at least one embodiment, inference and / or training logic 1415 may be used in the system of Figure 17A for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0081] In one embodiment, the camera shown in FIG. 17B may be positioned on a forklift or an automated warehouse picking robot.

[0082] 17B illustrates example camera locations and fields of view for autonomous vehicle 1700 of FIG. 17A, according to at least one embodiment. In at least one embodiment, the cameras and their respective fields of view are exemplary examples and are not limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be positioned at different locations on vehicle 1700.

[0083] In at least one embodiment, the camera type may include, but is not limited to, a digital camera that may be adapted for use with components and / or systems of vehicle 1700. The camera may operate at Automotive Safety Integrity Level (“ASIL”) B and / or another ASIL. In at least one embodiment, the camera type may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red, clear, clear, clear ("RCCC") color filter array, a red, clear, clear, blue ("RCCB") color filter array, a red, blue, green, clear ("RBGC") color filter array, a Foveon X3 color filter array, a Bayer sensor (RGGB) color filter array, a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, a clear pixel camera may be used, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, to increase light sensitivity.

[0084] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance systems ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0085] In at least one embodiment, one or more cameras may be mounted on a mounting assembly, such as a custom-designed (e.g., three-dimensionally (“3D”) printed) assembly, to eliminate stray light and reflections from the interior of the vehicle (e.g., reflections reflected from the dashboard onto the windshield) that may interfere with the camera's image data capture capabilities. With reference to door mirror mounting assemblies, in at least one embodiment, the door mirror assembly may be custom 3D printed so that the camera mounting plate conforms to the shape of the door mirror. In at least one embodiment, the camera may be integral with the door mirror. For side view cameras, in at least one embodiment, the cameras may again be integrated into the four pillars at each corner of the cabin.

[0086] In at least one embodiment, a camera (e.g., a front-facing camera) having a field of view that includes a portion of the environment ahead of vehicle 1700 may be used for a surroundings view to facilitate identification of the forward path and obstacles, and may be used in conjunction with controller 1736 and / or one or more of the control SoCs to assist in generating an occupancy grid and / or providing information essential for determining a preferred vehicle path. In at least one embodiment, the front-facing camera may be used to perform many of the same ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the front-facing camera may also be used for ADAS features and systems, including, without limitation, other features such as lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or traffic sign recognition.

[0087] In at least one embodiment, various cameras may be used in a front-facing configuration, including, for example, a monocular camera platform including a CMOS (complementary metal oxide semiconductor) color imager. In at least one embodiment, a wide-angle camera 1770 may be used to sense objects (e.g., pedestrians, cross traffic, or bicycles) coming into view from the periphery. While FIG. 17B shows only one wide-angle camera 1770, in other embodiments, there may be any number (including zero) of wide-angle cameras 1770 on the vehicle 1700. In at least one embodiment, any number of long-range cameras 1798 (e.g., a pair of long-view stereo cameras) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the long-range camera 1798 may also be used for object detection and classification, as well as basic object tracking.

[0088] In at least one embodiment, any number of stereo cameras 1768 may also be included in a front-facing configuration. In at least one embodiment, one or more stereo cameras 1768 may include an integrated control unit with a scalable processing unit, which may provide a programmable gate array ("FPGA") and a multi-core microprocessor with an integrated controller area network ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the vehicle's 1700 environment, including distance estimates for all points in the image. In at least one embodiment, one or more of the stereo cameras 1768 may include, without limitation, a compact stereo vision sensor, which may include, without limitation, two camera lenses (one on each side) and an image processing chip that can measure the distance from the vehicle 1700 to target objects and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning features. In at least one embodiment, other types of stereo cameras 1768 may be used in addition to or instead of those described herein.

[0089] In at least one embodiment, a camera having a field of view that includes a portion of the environment to the side of the vehicle 1700 (e.g., a side-view camera) may be used for the surroundings view to provide information used to create and update the occupancy grid and generate side collision warnings. For example, in at least one embodiment, surrounding cameras 1774 (e.g., four surrounding cameras 1774 as shown in FIG. 17B ) may be disposed on the vehicle 1700. The surrounding cameras 1774 may include, without limitation, any number and combination of wide-angle cameras 1770, fisheye cameras, and / or 360-degree cameras. For example, in at least one embodiment, four fisheye cameras may be disposed in front, behind, and on the sides of the vehicle 1700. In at least one embodiment, the vehicle 1700 may use three surrounding cameras 1774 (e.g., left, right, and rear) and may utilize one or more other cameras (e.g., a front camera) as a fourth surrounding camera.

[0090] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 1700 (e.g., a rear view camera) may be used for parking assistance, surrounding view, rear collision warning, and to create and update the occupancy grid. In at least one embodiment, a variety of cameras may be used, including, but not limited to, cameras also suitable as front cameras described herein (e.g., long-range camera 1798, and / or mid-range camera 1776, stereo camera 1768, infrared camera 1772, etc.).

[0091] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with Figures 14A and / or 14B. In at least one embodiment, inference and / or training logic 1415 may be used in the system of Figure 17B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0092] FIG. 17C is a block diagram illustrating an example system architecture for the autonomous vehicle 1700 of FIG. 17A according to at least one embodiment. In at least one embodiment, each of the components, features, and systems of the vehicle 1700 of FIG. 17C is shown as connected via a bus 1702. In at least one embodiment, the bus 1702 may include, without limitation, a CAN data interface (alternatively referred to herein as a (CAN bus)). In at least one embodiment, the CAN may be a network internal to the vehicle 1700 used to assist in controlling various features and functions of the vehicle 1700, such as brake application, acceleration, brake control, steering, windshield wipers, etc. In at least one embodiment, the bus 1702 may be configured to have tens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, the bus 1702 may be read to determine steering wheel angle, ground speed, engine revolutions per minute (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 1702 may be an ASIL B compliant CAN bus.

[0093] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or instead of CAN. In at least one embodiment, any number of buses 1702 may be present, including, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 1702 may be used to perform different functions and / or to provide redundancy. For example, a first bus 1702 may be used for collision avoidance functions and a second bus 1702 may be used for actuation control. In at least one embodiment, each bus 1702 may communicate with any component of the vehicle 1700, and two or more buses 1702 may communicate with the same component. In at least one embodiment, each of any number of systems-on-chip (“SoC”) 1704, each of controllers 1736, and / or each computer in the vehicle may have access to the same input data (e.g., input from sensors in vehicle 1700) and may be connected to a common bus, such as a CAN bus.

[0094] In at least one embodiment, vehicle 1700 may include one or more controllers 1736, such as those described herein with respect to FIG. 17A. Controller 1736 may be used for a variety of functions. In at least one embodiment, controller 1736 may be coupled to any of a variety of other components and systems of vehicle 1700 and may be used to control vehicle 1700, artificial intelligence of vehicle 1700, and / or infotainment of vehicle 1700, etc.

[0095] In at least one embodiment, vehicle 1700 may include any number of SoCs 1704. Each SoC 1704 may include, without limitation, a central processing unit ("CPU") 1706, a graphics processing unit ("GPU") 1708, a processor 1710, a cache 1712, an accelerator 1714, a data store 1716, and / or other components and features not shown. In at least one embodiment, SoC 1704 may be used to control vehicle 1700 in a variety of platforms and systems. For example, in at least one embodiment, SoC 1704 may be incorporated into a system (e.g., that of vehicle 1700) having a high definition ("HD") map 1722 that can obtain map refreshes and / or updates via a network interface 1724 from one or more servers (not shown in FIG. 17C ).

[0096] In at least one embodiment, CPU 1706 may include a CPU cluster, or CPU complex (also referred to herein as a "CCPLEX"). In at least one embodiment, CPU 1706 may include multiple cores and / or level 2 ("L2") caches. For example, in at least one embodiment, CPU 1706 may include eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU 1706 may include four dual-core clusters, where each cluster has a dedicated L2 cache (e.g., 2 MB of L2 cache). In at least one embodiment, CPU 1706 (e.g., a CCPLEX) may be configured to support simultaneous cluster operation, allowing any combination of clusters of CPUs 1706 to be active at any given time.

[0097] In at least one embodiment, one or more of the CPUs 1706 may implement power management functionality, including, without limitation, one or more of the following features: individual hardware blocks may be automatically clock gated when idle to save dynamic power; each core clock may be gated when the core is not actively executing instructions due to execution of a Wait for Interrupt ("WFI") / Wait for Event ("WFE") instruction; each core may be independently power gated; when all cores are clock gated or power gated, each core cluster may be independently clock gated; and / or when all cores are power gated, each core cluster may be independently power gated. In at least one embodiment, the CPU 1706 may further implement an advanced algorithm for managing power states, where, given allowed power states and expected wake-up times, hardware / microcode determines the best power state for cores, clusters, and CCPLEXes to enter. In at least one embodiment, a processing core may support in software a simple sequence of entering power states, with work offloaded to microcode.

[0098] In at least one embodiment, GPU 1708 may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU 1708 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU 1708 may use an extended tensor instruction set. In one embodiment, GPU 1708 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 (“L1”) cache (e.g., an L1 cache having at least 96 KB of storage capacity) and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having 512 KB of storage capacity). In at least one embodiment, GPU 1708 may include at least eight streaming microprocessors. In at least one embodiment, GPU 1708 may use a compute application programming interface (API). In at least one embodiment, GPU 1708 may use one or more parallel computing platforms and / or programming modules (e.g., NVIDIA's CUDA).

[0099] In at least one embodiment, one or more of the GPUs 1708 may be power-optimized for best performance in automotive and embedded use cases. For example, in one embodiment, the GPUs 1708 may be fabricated on fin field-effect transistors ("FinFETs"). In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, without limitation, 64 PF32 cores and 32 PF64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA TENSOR cores for deep learning matrix operations, a level-zero ("L0") instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor includes independent parallel integer and floating-point data paths to achieve efficient execution of workloads by mixing computational and addressing calculations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling to enable finer-grained synchronization and coordination between parallel threads. In at least one embodiment, the streaming microprocessor may include a combination of an L1 data cache and a shared memory unit to improve performance while simplifying programming.

[0100] In at least one embodiment, one or more of the GPUs 1708 may include high bandwidth memory (“HBW”) and / or a 16 GB HBM2 memory subsystem, providing, in some examples, a peak memory bandwidth of approximately 900 GB / s. In at least one embodiment, synchronous graphics random-access memory (“SGRAM”), such as graphics double data rate type five (“GDDR5”), may be used in addition to or instead of the HBM memory.

[0101] In at least one embodiment, the GPU 1708 may include unified memory technology. In at least one embodiment, address translation services (“ATS”) support may be used to allow the GPU 1708 to directly access the CPU 1706 page tables. In at least one embodiment, when the GPU 1708 memory management unit (“MMU”) encounters a miss, an address translation request may be sent to the CPU 1706. In at least one embodiment, in response, the CPU 1706 may look up the virtual-to-physical address mapping in its page table and send the translation back to the GPU 1708. In at least one embodiment, the unified memory technology allows for a single, unified virtual address space for both the CPU 1706 and the GPU 1708 memory, thereby simplifying programming the GPU 1708 and porting applications to the GPU 1708.

[0102] In at least one embodiment, GPU 1708 may include any number of access counters that can record the frequency of GPU 1708's accesses to the memory of other processors. In at least one embodiment, the access counters may help ensure that memory pages are moved to the physical memory of the processor that is accessing the pages most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0103] In at least one embodiment, one or more of the SoCs 1704 may include any number of caches 1712, including those described herein. For example, in at least one embodiment, the caches 1712 may include a level 3 (“L3”) cache available to both the CPU 1706 and the GPU 1708 (e.g., connected to both the CPU 1706 and the GPU 1708). In at least one embodiment, the caches 1712 may include a write-back cache that can record line state by using a cache coherence protocol or the like (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4 MB or more, depending on the embodiment, although smaller cache sizes may also be used.

[0104] In at least one embodiment, one or more of the SoCs 1704 may include one or more accelerators 1714 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, the SoCs 1704 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, the large on-chip memory (e.g., 4 MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to complement the GPU 1708 and offload some tasks from the GPU 1708 (e.g., freeing up more cycles for the GPU 1708 to perform other tasks). In at least one embodiment, accelerator 1714 may be used for targeted workloads that are stable enough to accommodate acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based, i.e., regional convolutional neural networks (“RCNNs”), and Fast RCNNs (e.g., used for object detection), or other types of CNNs.

[0105] In at least one embodiment, the accelerator 1714 (e.g., a hardware-accelerated cluster) may include a deep learning accelerator (“DLA”). The DLA may include, without limitation, one or more tensor processing units (“TPU”), which may be further configured to provide tens of trillion operations per second for deep learning applications and inference. In at least one embodiment, the TPU may be an accelerator configured and optimized to perform image processing functions (e.g., CNN, RCNN, etc.). The DLA may further be optimized for a specific set of neural network types and floating-point operations, as well as for inference. In at least one embodiment, the DLA's design allows for improved performance per millimeter over typical general-purpose GPUs, typically significantly exceeding the performance of a CPU. In at least one embodiment, the TPU may perform several functions, including, for example, single-instance convolution functions supporting INT8, INT16, and FP16 data types for both features and weights, as well as post-processing functions. In at least one embodiment, the DLA may quickly and efficiently run neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, without limitation, a CNN for object identification and detection using data from a camera sensor, a CNN for distance estimation using data from a camera sensor, a CNN for emergency vehicle detection and identification using data from microphone 1796, a CNN for face recognition and vehicle owner identification using data from a camera sensor, and / or a CNN for security and / or safety events.

[0106] In at least one embodiment, the DLA may perform any function of the GPU 1708, and a designer may target either the DLA or the GPU 1708 for any function, for example, by using an inference accelerator. For example, in at least one embodiment, a designer may centralize CNN and floating-point processing in the DLA and offload other functions to the GPU 1708 and / or other accelerators 1714.

[0107] In at least one embodiment, the accelerator 1714 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1738, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. The PVA may balance performance and versatility. For example, in at least one embodiment, each PVA may include, by way of example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0108] In at least one embodiment, the RISC core may interact with an image sensor (e.g., an image sensor of any of the cameras described herein), an image signal processor, and / or the like. In at least one embodiment, each of the RISC cores may include any amount of memory. In at least one embodiment, the RISC core may use any of a number of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0109] In at least one embodiment, the DMA may allow components of the PVA to access system memory independent of the CPU 1706. In at least one embodiment, the DMA may support any number of features used to provide optimizations to the PVA, including, but not limited to, multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more addressing dimensions, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and / or depth stepping.

[0110] In at least one embodiment, the vector processor may be a programmable processor that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, the vector processing subsystem may operate as the primary processing engine of the PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU may include a digital signal processor, such as a single instruction, multiple data ("SIMD"), very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0111] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on consecutive images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in a hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, a PVA may include additional error correction code ("ECC") memory to enhance the overall security of the system.

[0112] In at least one embodiment, the accelerator 1714 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the accelerator 1714. In at least one embodiment, the on-chip memory may include, for example, without limitation, at least 4 MB of SRAM consisting of eight field-configurable memory blocks, which may be accessible from both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory through a backbone that provides the PVA and DLA with high-speed access to the memory. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using the APB).

[0113] In at least one embodiment, the on-chip computer vision network may include an interface that determines whether both the PVA and DLA provide ready and enable signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as burst-based communication for continuous data transfer. In at least one embodiment, the interface may conform to International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0114] In at least one embodiment, one or more of the SoCs 1704 may include a real-time ray tracing hardware accelerator, which may be used to quickly and efficiently determine the location and range of objects (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, sound propagation synthesis and / or analysis, SONAR system simulation, general waveform propagation simulation, comparison with LIDAR data for localization and / or other functions, and / or other uses.

[0115] In at least one embodiment, accelerator 1714 (e.g., a hardware accelerator cluster) has diverse uses for autonomous driving. In at least one embodiment, the PVA may be a programmable vision accelerator that can be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the performance of the PVA is well suited to algorithm domains that require low-power, low-latency, and predictable processing. In other words, the PVA works well for semi-dense or dense regular computations that require low-latency, low-power, and predictable run times, even with small data sets. In at least one embodiment, in an autonomous vehicle such as vehicle 1700, the PVA is designed to run traditional computer vision algorithms because they are effective for object detection and integer arithmetic.

[0116] For example, according to at least one embodiment of the technology, computer stereo vision may be performed using the PVA. In at least one embodiment, algorithms based on semi-global matching may be used in some examples, but this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation / stereo matching (e.g., structure from motion, pedestrian recognition, lane detection, etc.) on the fly. In at least one embodiment, the PVA may perform computer stereo vision functions on input from two monocular cameras.

[0117] In at least one embodiment, the PVA may be used to perform dense optical flow. For example, in at least one embodiment, the PVA may process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA may be used for time-of-flight depth processing, e.g., by processing raw time-of-flight data to provide processed time-of-flight data.

[0118] In at least one embodiment, the DLA may be used to implement any type of network for enhancing control and driving safety, including, for example, without limitation, a neural network that outputs a confidence measure for each object detection. In at least one embodiment, the confidence may be expressed or interpreted as the probability of each detection compared to other detections or as providing its relative “weight.” In at least one embodiment, the confidence may further enable the system to make decisions regarding which detections should be considered positive detections rather than false detections. For example, in at least one embodiment, the system may set a threshold for confidence and consider only detections that exceed the threshold to be positive detections. In embodiments where automatic emergency braking (“AEB”) is used, a false detection may cause the vehicle to automatically apply the emergency brakes, which is clearly undesirable. In at least one embodiment, a highly confident detection may be considered to trigger AEB. In at least one embodiment, the DLA may implement a neural network to regress the confidence value. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground surface estimate obtained (e.g., from another subsystem), an output from an IMU sensor 1766 correlated with the orientation of the vehicle 1700, distance, and a 3D location estimate of the object obtained from the neural network and / or other sensors (e.g., a LIDAR sensor 1764 or a RADAR sensor 1760), among others.

[0119] In at least one embodiment, one or more of the SoCs 1704 may include a data store 1716 (e.g., memory). In at least one embodiment, the data store 1716 may be on-chip memory of the SoC 1704, which may store neural networks running on the GPU 1708 and / or DLA. In at least one embodiment, the capacity of the data store 1716 may be large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the data store 1716 may comprise an L2 or L3 cache.

[0120] In at least one embodiment, one or more of the SoCs 1704 may include any number of processors 1710 (e.g., embedded processors). The processors 1710 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions and associated security enforcement. In at least one embodiment, the boot and power management processor may be part of the boot sequence of the SoC 1704 and may provide run-time power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in transitioning the system to a low power state, manage the thermal and temperature sensors of the SoC 1704, and / or manage the power state of the SoC 1704. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and the SoC 1704 may use the ring oscillator to detect the temperature of the CPU 1706, GPU 1708, and / or accelerator 1714. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine, place the SoC 1704 in a low power state, and / or place the vehicle 1700 in a driver-safety shutdown mode (e.g., bring the vehicle 1700 to a safety shutdown).

[0121] In at least one embodiment, processor 1710 may further include a set of embedded processors capable of acting as an audio processing engine. In at least one embodiment, the audio processing engine may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide variety of flexible audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that includes a digital signal processor with dedicated RAM.

[0122] In at least one embodiment, processor 1710 may further include an always-on processor engine capable of providing the hardware features necessary to support low-power sensor management and bring-up use cases. In at least one embodiment, the always-on processor engine may include, without limitation, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0123] In at least one embodiment, the processor 1710 may further include a safety cluster engine, which may include, without limitation, a processor subsystem dedicated to handling safety management for automotive applications. In at least one embodiment, the safety cluster engine may include, without limitation, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, two or more cores may operate in lockstep mode and function as a single core with comparison logic to detect any differences between their operation. In at least one embodiment, the processor 1710 may further include a real-time camera engine, which may include, without limitation, a processor subsystem dedicated to handling real-time camera management. In at least one embodiment, the processor 1710 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0124] In at least one embodiment, processor 1710 may include a video image composer, which may be a processing block (e.g., implemented in a microprocessor) that implements video post-processing functions required by a video playback application to generate a final image in a playback device window. In at least one embodiment, the video image composer may perform lens distortion correction for wide-angle camera 1770, surrounding camera 1774, and / or in-cabin surveillance camera sensors. In at least one embodiment, the in-cabin surveillance camera sensors are preferably monitored by a neural network running on a separate instance of SoC 1704 that is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform lip reading to, without limitation, activate cellular service, make phone calls, write emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, and provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are unavailable at other times.

[0125] In at least one embodiment, the video image combiner may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, when motion occurs in the video, the noise reduction appropriately weights spatial information and downweights information provided by adjacent frames. In at least one embodiment, when an image or portion of an image does not contain motion, the temporal noise reduction performed by the video image combiner may use information from previous images to reduce noise in the current image.

[0126] In at least one embodiment, the video image composer may also be configured to perform stereo rectification on the input stereo lens frames. In at least one embodiment, the video image composer may also be used to composite a user interface when the operating system desktop is in use, eliminating the need for the GPU 1708 to continually render new surfaces. In at least one embodiment, the video image composer may be used to offload the GPU 1708 when it is powered on and actively performing 3D rendering, improving performance and responsiveness.

[0127] In at least one embodiment, one or more of the SoCs 1704 may further include a mobile industry processor interface ("MIPI") camera serial interface for receiving input from video and cameras, a high-speed interface, and / or a video input block that may be used for camera and associated pixel input functions. In at least one embodiment, one or more of the SoCs 1704 may further include an input / output controller, which may be controlled by software and may be used to receive I / O signals that are not tied to a specific role.

[0128] In at least one embodiment, one or more SoCs 1704 may further include peripherals, audio encoders / decoders (“codecs”), power management, and / or a wide range of peripheral interfaces to enable communication with other devices. SoCs 1704 may be used to process data from cameras (e.g., connected via gigabit multimedia serial links and Ethernet), data from sensors (e.g., LIDAR sensors 1764, RADAR sensors 1760, etc., which may be connected via Ethernet), data from bus 1702 (e.g., vehicle 1700 speed, steering wheel position, etc.), data from GNSS sensors 1758 (e.g., connected via Ethernet or CAN bus), etc. In at least one embodiment, one or more of SoCs 1704 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to offload routine data management tasks from CPU 1706.

[0129] In at least one embodiment, the SoC 1704 may be an end-to-end platform with a flexible architecture spanning levels 3-5 of automation, providing a comprehensive functional safety architecture that leverages and efficiently utilizes computer vision and ADAS techniques for diversity and redundancy, and a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, the SoC 1704 is faster, more reliable, and more energy- and space-efficient than conventional systems. For example, in at least one embodiment, the accelerator 1714, when combined with the CPU 1706, GPU 1708, and data store 1716, can provide a fast and efficient platform for levels 3-5 of autonomous vehicles.

[0130] In at least one embodiment, computer vision algorithms may run on a CPU, which may be configured using a high-level programming language, such as the C programming language, to perform various processing algorithms across various visual data. However, in at least one embodiment, CPUs often cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to run the complex object detection algorithms used in in-vehicle ADAS applications and realistic Level 3-5 autonomous vehicles in real time.

[0131] Embodiments described herein enable multiple neural networks to run simultaneously and / or sequentially, and the results can be combined to enable Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, the CNN running on the DLA or a separate GPU (e.g., GPU1720) may include text and word recognition, enabling the supercomputer to read and understand traffic signs, including signs for which the neural network was not specifically trained. In at least one embodiment, the DLA may further include a neural network that can identify and interpret signs and provide a semantic understanding of the signs, which can then be passed to a route planning module running on the CPU complex.

[0132] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks may be running simultaneously. For example, in at least one embodiment, a warning sign displaying "Caution: Flashing Indicates Icy Conditions" in conjunction with an electric light may be interpreted separately or collectively by several neural networks. In at least one embodiment, the sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the words "Flashing Indicates Icy Conditions" may be interpreted by a second deployed neural network, which, if the flashing light is detected, notifies the vehicle's route planning software (preferably running on the CPU complex) that an icy condition exists. In at least one embodiment, the flashing light may be identified by running a third deployed neural network over multiple frames, and the presence (or absence) of the flashing light is notified to the vehicle's route planning software. In at least one embodiment, all three neural networks may be running simultaneously, such as within the DLA and / or on the GPU 1708.

[0133] In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 1700. In at least one embodiment, an always-on sensor processing engine may be used to unlock the vehicle and turn on the lights when the owner approaches the driver's door, and to disable the vehicle in security mode when the owner leaves the vehicle. In this way, the SoC 1704 provides security against theft and / or carjacking.

[0134] In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphone 1796 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC 1704 uses a CNN to classify environmental and urban sounds as well as visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative speed at which an emergency vehicle is approaching (e.g., by using the Doppler effect). In at least one embodiment, the CNN may also be trained to identify emergency vehicles specific to the region in which the vehicle is operating, as identified by GNSS sensor 1758. In at least one embodiment, when operating in Europe, the CNN attempts to detect European sirens, and when in the United States, it attempts to identify only North American sirens. In at least one embodiment, when an emergency vehicle is detected, a control program to execute an emergency vehicle safety routine may be used to slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle in conjunction with ultrasonic sensor 1762 until the emergency vehicle has passed.

[0135] In at least one embodiment, vehicle 1700 may include a CPU 1718 (e.g., a discrete CPU or dCPU), which may be coupled to SoC 1704 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU 1718 may include, for example, an X86 processor. CPU 1718 may be used to perform any of a variety of functions, including, for example, reconciling potentially inconsistent results between ADAS sensors and SoC 1704 and / or monitoring the status and health of controller 1736 and / or infotainment system on a chip (“infotainment SoC”) 1730.

[0136] In at least one embodiment, vehicle 1700 may include GPU 1720 (e.g., a discrete GPU or dGPU), which may be coupled to SoC 1704 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, GPU 1720 may provide additional artificial intelligence functionality, such as by running redundant and / or different neural networks, and may be used to train and / or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle 1700.

[0137] In at least one embodiment, vehicle 1700 may further include a network interface 1724, which may include, without limitation, a wireless antenna 1726 (e.g., one or more wireless antennas 1726 for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1724 may be used to enable wireless connectivity over the Internet with the cloud (e.g., servers and / or other network devices), other vehicles, and / or computing devices (e.g., occupant client devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 170 and the other vehicles, and / or an indirect link (e.g., across a network and via the Internet) may be established. In at least one embodiment, the direct link may be provided using a vehicle-to-vehicle communication link. The vehicle-to-vehicle communication link may provide vehicle 1700 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 1700). In at least one embodiment, the above-described functionality may be part of a cooperative adaptive cruise control function of the vehicle 1700.

[0138] In at least one embodiment, network interface 1724 may include an SoC that provides modulation and demodulation functionality and enables controller 1736 to communicate over a wireless network. In at least one embodiment, network interface 1724 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a super-heterodyne process. In at least one embodiment, radio frequency front-end functionality may be provided by a separate chip. In at least one embodiment, network interface may include wireless functionality for communicating via LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0139] In at least one embodiment, vehicle 1700 may further include a data store 1728, which may include, without limitation, off-chip (e.g., not on SoC 1704) storage. In at least one embodiment, data store 1728 may include one or more storage elements, including, without limitation, RAM, SRAM, dynamic random access memory (“DRAM”), video random-access memory (“VRAM”), flash, a hard disk, and / or other components and / or devices capable of storing at least one bit of data.

[0140] In at least one embodiment, vehicle 1700 may further include GNSS sensors 1758 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or route planning functions. In at least one embodiment, any number of GNSS sensors 1758 may be used, including, for example, without limitation, a GPS using a USB connector with an Ethernet to serial (e.g., RS-232) bridge.

[0141] In at least one embodiment, vehicle 1700 may further include RADAR sensor 1760. RADAR sensor 1760 may be used by vehicle 1700 for long-range vehicle detection, even in darkness and / or severe weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. RADAR sensor 1760 may use CAN and / or bus 1702 for control (e.g., to transmit data generated by RADAR sensor 1760) and to access object tracking data, and in some examples, may have Ethernet access to access raw data. In at least one embodiment, various types of RADAR sensors may be used. For example, without limitation, RADAR sensor 1760 may be suitable for forward, rearward, and side RADAR use. In at least one embodiment, one or more of RADAR sensors 1760 are pulse-Doppler RADAR sensors.

[0142] In at least one embodiment, the RADAR sensor 1760 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, and short-range with side coverage. In at least one embodiment, the long-range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system may provide a wide field of view, such as within a 250-meter range, achieved by two or more independent scans. In at least one embodiment, the RADAR sensor 1760 may help distinguish between static and moving objects and may be used by the ADAS system 1738 to provide emergency braking assistance and forward collision warning. The sensors 1760 included in a long-range RADAR system may include, without limitation, multiple (e.g., six or more) fixed RADAR antennas, as well as monostatic multi-mode RADAR with high-speed CAN and FlexRay interfaces. In at least one embodiment, where there are six antennas, the four center antennas may generate a focused beam pattern designed to record the surroundings of vehicle 1700 at higher speeds with minimal interference from adjacent lanes. In at least one embodiment, the other two antennas may extend the field of view, allowing for quick detection of vehicles entering or exiting the lane of vehicle 1700.

[0143] In at least one embodiment, the medium-range RADAR system may include, by way of example, a range of up to 160 meters (forward) or 80 meters (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, the short-range RADAR system may include, without limitation, any number of RADAR sensors 1760 designed to be mounted on either end of the rear bumper. When mounted on either end of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that constantly monitor blind spots behind and adjacent to the vehicle. In at least one embodiment, the short-range RADAR system may be used in an ADAS system 1738 to provide blind spot detection and / or lane change assistance.

[0144] In at least one embodiment, vehicle 1700 may further include ultrasonic sensors 1762. Ultrasonic sensors 1762 may be positioned at the front, rear, and / or sides of vehicle 1700 and may be used for parking assistance and / or to generate and update an occupancy grid. In at least one embodiment, multiple ultrasonic sensors 1762 may be used, and different ultrasonic sensors 1762 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensors 1762 may operate at functional safety level ASIL B.

[0145] In at least one embodiment, vehicle 1700 may include a LIDAR sensor 1764. The LIDAR sensor 1764 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the LIDAR sensor 1764 may be functional safety level ASIL B. In at least one embodiment, vehicle 1700 may include multiple LIDAR sensors 1764 (e.g., two, four, six, etc.), which may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch).

[0146] In at least one embodiment, the LIDAR sensor 1764 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, a commercially available LIDAR sensor 1764 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2 cm to 3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LIDAR sensors 1764 may be used. In such an embodiment, the LIDAR sensor 1764 may be implemented as a small device that can be integrated into the front, rear, sides, and / or corners of the vehicle 1700. In at least one embodiment, the LIDAR sensor 1764 of such an embodiment may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, with a range of 200 meters, even for low-reflectivity objects. In at least one embodiment, a front-mounted LIDAR sensor 1764 may be configured to provide a horizontal field of view of 45 degrees to 135 degrees.

[0147] In at least one embodiment, LIDAR technology such as 3D flash LIDAR may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate the surroundings of the vehicle 1700 up to approximately 200 meters. In at least one embodiment, the flash LIDAR unit includes, without limitation, a receptor that records the transit time of the laser pulse and the reflected light at each pixel, which corresponds to the range from the vehicle 1700 to the object. In at least one embodiment, flash LIDAR allows a highly accurate, undistorted image of the surroundings to be generated with each laser flash. In at least one embodiment, four flash LIDARs may be deployed, one on each side of the vehicle 1700. In at least one embodiment, the 3D flash LIDAR system includes, without limitation, a solid-state 3D staring array LIDAR camera (e.g., a non-scanning LIDAR device) with no moving parts other than a fan. In at least one embodiment, the flash LIDAR device may use 5 nanosecond Class I (eye-safe) laser pulses per frame and may capture reflected laser light in the form of a 3D range point cloud and co-registered intensity data.

[0148] In at least one embodiment, the vehicle may further include an IMU sensor 1766. In at least one embodiment, the IMU sensor 1766 may be positioned at the center of the rear axle of the vehicle 1700. In at least one embodiment, the IMU sensor 1766 may include, for example, without limitation, an accelerometer, a magnetometer, a gyroscope, a magnetic compass, and / or other types of sensors. In at least one embodiment, such as in a 6-axis application, the IMU sensor 1766 may include, without limitation, an accelerometer and a gyroscope. In at least one embodiment, such as in a 9-axis application, the IMU sensor 1766 may include, without limitation, an accelerometer, a gyroscope, and a magnetometer.

[0149] In at least one embodiment, the IMU sensor 1766 may be implemented as a compact, high-performance GPS-Aided Inertial Navigation System ("GPS / INS") that combines micro-electro-mechanical systems ("MEMS") inertial sensors, a highly sensitive GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, the IMU sensor 1766 enables the vehicle 1700 to estimate its orientation by directly observing changes in velocity and correlating them from the GPS to the IMU sensor 1766 without requiring input from a magnetic sensor. In at least one embodiment, the IMU sensor 1766 and the GNSS sensor 1758 may be combined into a single integrated unit.

[0150] In at least one embodiment, vehicle 1700 may include microphones 1796 located in and / or around vehicle 1700. In at least one embodiment, microphones 1796 may be used for, among other things, detection and identification of emergency vehicles.

[0151] In at least one embodiment, vehicle 1700 may further include any number of camera types, including stereo cameras 1768, wide-angle cameras 1770, infrared cameras 1772, perimeter cameras 1774, long-range cameras 1798, mid-range cameras 1776, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire perimeter of vehicle 1700. In at least one embodiment, the types of cameras used vary depending on the characteristics of vehicle 1700. In at least one embodiment, any combination of camera types may be used to provide the required coverage around vehicle 1700. In at least one embodiment, the number of cameras may vary depending on the embodiment. For example, in at least one embodiment, vehicle 1700 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. The cameras may support, by way of example and without limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet. In at least one embodiment, each camera is described in further detail herein above with respect to Figures 17A and 17B.

[0152] In at least one embodiment, vehicle 1700 may further include a vibration sensor 1742. Vibration sensor 1742 may measure vibrations of components of vehicle 1700, such as an axle. For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, if two or more vibration sensors 1742 are used, the difference in vibration may be used to determine the amount of friction or slippage of the road surface (e.g., if there is a vibration difference between a powered axle and a free-spinning axle).

[0153] In at least one embodiment, vehicle 1700 may include an ADAS system 1738. ADAS system 1738 may include, without limitation, an SoC in some examples. In at least one embodiment, the ADAS systems 1738 may include, without limitation, any number and combination of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward crash warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keep assist ("LKA") systems, blind spot warning ("BSW") systems, rear cross-traffic warning ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions.

[0154] In at least one embodiment, the ACC system may use a RADAR sensor 1760, a LIDAR sensor 1764, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle immediately preceding the vehicle 1700 and automatically adjusts the speed of the vehicle 1700 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system enforces distance maintenance and notifies the vehicle 1700 to change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0155] In at least one embodiment, the CACC system uses information from other vehicles, which may be received by network interface 1724 and / or wireless antenna 1726 from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, a vehicle-to-vehicle ("V2V") communication link may provide a direct link, while an infrastructure-to-vehicle ("I2V") communication link may provide an indirect link. Generally, the V2V communication concept provides information about the immediate preceding vehicle (e.g., a vehicle immediately in front of vehicle 1700 and in the same lane), while the I2V communication concept provides information about traffic ahead of that. In at least one embodiment, the CACC system may include either or both I2V and V2V information sources. In at least one embodiment, information about vehicles in front of vehicle 1700 may make the CACC system more reliable, potentially allowing for smoother traffic flow and reducing congestion on the roads.

[0156] In at least one embodiment, the FCW system is designed to alert the driver to hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a front-facing camera and / or RADAR sensor 1760 coupled to a dedicated processor, DSP, FPGA, and / or ASIC that is electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings in the form of an audible, visual warning, vibration, and / or a quick brake pulse.

[0157] In at least one embodiment, the AEB system may detect an imminent frontal collision with another vehicle or other object and automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system may use a front-facing camera and / or RADAR sensor 1760 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first advises the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system may automatically apply the brakes to prevent or at least mitigate the severity of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic brake support and / or pre-collision braking.

[0158] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as vibration of the steering wheel or seat, to advise the driver when the vehicle 1700 crosses a lane marker. In at least one embodiment, the LDW system does not engage if the driver indicates an intentional lane departure by activating a turn signal. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC that can be electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variation of the LDW system. The LKA system provides steering input or brake control to correct the vehicle 1700 if the vehicle 1700 begins to drift out of its lane.

[0159] In at least one embodiment, the BSW system detects vehicles in the vehicle's blind spot and warns the driver. In at least one embodiment, the BSW system may provide visual, audible, and / or haptic alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system may provide an additional warning when the driver uses a turn signal. In at least one embodiment, the BSW system may use a rearview camera and / or RADAR sensor 1760 coupled to dedicated processors, DSPs, FPGAs, and / or ASICs, which are electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0160] In at least one embodiment, the RCTW system may provide visual, audible, and / or tactile notifications when an object is detected outside the range of the rear camera when reversing the vehicle 1700. In at least one embodiment, the RCTW system includes an AEB system to ensure vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear RADAR sensors 1760 coupled to a dedicated processor, DSP, FPGA, and / or ASIC electrically coupled to feedback to the driver, such as a display, speaker, and / or vibration components.

[0161] In at least one embodiment, conventional ADAS systems may be prone to false positive results, which can be annoying and distracting to the driver, but are typically not a major concern because conventional ADAS systems advise the driver and allow the driver to determine whether a safety condition truly exists and respond accordingly. In at least one embodiment, in the event of conflicting results, the vehicle 1700 itself determines whether to follow the results from the primary computer (e.g., first controller 1736) or the secondary computer (e.g., second controller 1736). For example, in at least one embodiment, the ADAS system 1738 may be a backup and / or secondary computer for transmitting perceptual information to a rationality module of the backup computer. In at least one embodiment, the rationality monitor of the backup computer may run redundant software on various hardware components to detect perceptual errors and dynamic driving tasks. In at least one embodiment, output from the ADAS system 1738 may be provided to a supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0162] In at least one embodiment, the primary computer may be configured to provide the monitor MCU with a reliability score indicating the reliability of the primary computer's selected result. In at least one embodiment, if the reliability score exceeds a threshold, the monitor MCU may follow the primary computer's instructions regardless of whether the secondary computers are providing conflicting or inconsistent results. In at least one embodiment, if the reliability score does not meet the threshold and the primary and secondary computers provide different (e.g., conflicting) results, the monitor MCU may arbitrate between the computers to determine the appropriate result.

[0163] In at least one embodiment, the monitoring MCU may be configured to execute a neural network trained and configured to determine conditions under which the secondary computer will provide a false alarm based at least in part on outputs from the primary and secondary computers. In at least one embodiment, the monitoring MCU's neural network may learn when the secondary computer's output may be trusted and when it may not be trusted. For example, in at least one embodiment, if the secondary computer is a RADAR-based FCW system, the monitoring MCU's neural network may learn when the FCW system identifies a metal object that is not actually a hazard, such as a drain grate or manhole cover, which triggers an alarm. In at least one embodiment, if the secondary computer is a camera-based LDW system, the monitoring MCU's neural network may learn to disable LDW when a bicyclist or pedestrian is present and lane departure is actually the safest maneuver. In at least one embodiment, the monitoring MCU may include at least one of a DLA or a GPU suitable for executing the neural network along with associated memory. In at least one embodiment, the supervisory MCU may comprise and / or be included as a component of the SoC 1704.

[0164] In at least one embodiment, the ADAS system 1738 may include a secondary computer that performs ADAS functions using traditional rules of computer vision. In at least one embodiment, the secondary computer may use traditional computer vision rules (if-then rules), and neural networks may reside in the supervisory MCU, improving reliability, safety, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity may increase the overall system's error tolerance, particularly against errors caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a bug or error in the software running on the primary computer and non-identical software code running on the secondary computer provides the same overall result, the supervisory MCU may have greater confidence that the overall result is correct and that a software or hardware bug on the primary computer did not cause a critical error.

[0165] In at least one embodiment, the output of the ADAS system 1738 may be provided to a perception block of the primary computer and / or a dynamic driving task block of the primary computer. For example, in at least one embodiment, if the ADAS system 1738 indicates a frontal collision warning due to an immediately preceding object, the perception block may use this information when identifying the object. In at least one embodiment, the secondary computer may have its own neural network that is pre-trained, as described herein, thus reducing the risk of false positives.

[0166] In at least one embodiment, vehicle 1700 may further include an infotainment SoC 1730 (e.g., an in-vehicle infotainment system (IVI)). While infotainment system 1730 is shown and described as an SoC, in at least one embodiment, it may not be an SoC and may include, without limitation, two or more separate components. In at least one embodiment, infotainment SoC 1730 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), telephony (e.g., hands-free calling), network connectivity (e.g., LTE, Wi-Fi, etc.), and / or information services (e.g., navigation system, rear park assist, wireless data system, vehicle-related information such as fuel level, total mileage, brake fuel level, oil level, door opening / closing, air filter information, etc.) to vehicle 1700. For example, infotainment SoC 1730 may include a radio, a disc player, a navigation system, a video player, USB and Bluetooth connectivity, a car computer, in-car entertainment, Wi-Fi, steering wheel audio controls, hands-free voice control, a heads-up display (“HUD”), an HMI display 1734, telematics devices, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1730 may also be used to provide information (e.g., visual and / or auditory) to a vehicle user, such as information from an ADAS system 1738, autonomous driving information such as a vehicle maneuver plan, a trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0167] In at least one embodiment, infotainment SoC 1730 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1730 may communicate with other devices, systems, and / or components of vehicle 1700 via bus 1702 (e.g., CAN bus, Ethernet, etc.). In at least one embodiment, infotainment SoC 1730 may be coupled to a supervisory MCU such that the infotainment system's GPU may perform some self-driving functions when primary controller 1736 (e.g., vehicle's 1700 primary and / or backup computer) fails. In at least one embodiment, infotainment SoC 1730 may place vehicle 1700 in a driver-safety shutdown mode, as described herein.

[0168] In at least one embodiment, vehicle 1700 may further include an instrument cluster 1732 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). The instrument cluster 1732 may include, without limitation, a controller and / or a supercomputer (e.g., a separate controller or supercomputer). In at least one embodiment, instrument cluster 1732 may include any number and combination of instrument sets, such as, without limitation, a speedometer, fuel level, oil pressure, a tachometer, an odometer, turn signals, a shift lever position indicator, a seat belt warning light, a parking brake warning light, an engine malfunction light, supplemental restraint system (e.g., airbag) information, light control, safety system control, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 1730 and instrument cluster 1732. In at least one embodiment, instrument cluster 1732 may be included as part of infotainment SoC 1730, or vice versa.

[0169] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with Figures 14A and / or 14B. In at least one embodiment, inference and / or training logic 1415 may be used in the system of Figure 17C for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0170] 17D is a diagram of a system 1776 for communicating between a cloud-based server and the autonomous vehicle 1700 of FIG. 17A , according to at least one embodiment. In at least one embodiment, the system 1776 may include any number and type of vehicle, including, without limitation, a server 1778, a network 1790, and the vehicle 1700. The server 1778 may include, without limitation, multiple GPUs 1784(A)-1784(H) (collectively referred to herein as GPUs 1784), PCIe switches 1782(A)-1782(D) (collectively referred to herein as PCIe switches 1782), and / or CPUs 1780(A)-1780(B) (collectively referred to herein as CPUs 1780). The GPUs 1784, CPUs 1780, and PCIe switches 1782 may be interconnected by a high-speed interconnect, such as, for example, without limitation, an NVLink interface 1788 developed by NVIDIA, and / or a PCIe connection 1786. In at least one embodiment, the GPUs 1784 are connected to each other via an NVLink and / or NVS switch SoC, and the GPUs 1784 and PCIe switches 1782 are connected via a PCIe interconnect. In at least one embodiment, eight GPUs 1784, two CPUs 1780, and four PCIe switches 1782 are illustrated, but this is not intended to be limiting. In at least one embodiment, each of the servers 1778 may include any number of GPUs 1784, CPUs 1780, and / or PCIe switches 1782 in any combination, without limitation. For example, in at least one embodiment, the servers 1778 may each include 8, 16, 32, and / or more GPUs 1784.

[0171] In at least one embodiment, server 1778 may receive image data from the vehicle over network 1790 representing images showing unexpected or changed road conditions, such as recently begun road construction. In at least one embodiment, server 1778 may transmit neural network 1792, updated neural network 1792, and / or map information 1794, including, without limitation, information regarding traffic and road conditions, to the vehicle over network 1790. In at least one embodiment, updates to map information 1794 may include, without limitation, updates to HD map 1722, such as information regarding construction sites, potholes, detours, flooding, and / or other obstacles. In at least one embodiment, neural network 1792, updated neural network 1792, and / or map information 1794 may be derived from new training and / or experience represented in data received from any number of vehicles in the environment and / or may be derived based at least in part on training performed at a data center (e.g., using server 1778 and / or other servers).

[0172] In at least one embodiment, server 1778 may be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. The training data may be generated by the vehicle and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data may be tagged and / or otherwise preprocessed (e.g., if the associated neural network benefits from supervised learning). In at least one embodiment, any amount of the training data may not be tagged and / or preprocessed (e.g., if the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, it may be used by the vehicle (e.g., transmitted to the vehicle via network 1790) and / or used by server 1778 to remotely monitor the vehicle.

[0173] In at least one embodiment, server 1778 may receive data from vehicles and apply the data to state-of-the-art, real-time neural networks to enable real-time intelligent inference. In at least one embodiment, server 1778 may include a deep learning supercomputer and / or dedicated AI computer powered by a GPU 1784, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server 1778 may also include a deep learning infrastructure using a CPU-powered data center.

[0174] In at least one embodiment, the deep learning infrastructure of server 1778 may be capable of rapid real-time inference and may use that capability to assess and verify the health of the processor, software, and / or associated hardware of vehicle 1700. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1700, such as a series of images and / or objects that vehicle 1700 has located in the series of images (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by vehicle 1700; if the results do not match and the deep learning infrastructure concludes that the AI ​​of vehicle 1700 has failed, server 1778 may send a signal to vehicle 1700 instructing the fail-safe computer of vehicle 1700 to take control, notify the occupants, and complete a safe stopping maneuver.

[0175] In at least one embodiment, server 1778 may include a GPU 1784 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT3). In at least one embodiment, the combination of a GPU-powered server and inference acceleration can enable real-time response. In at least one embodiment, CPU, FPGA, and other processor-powered servers may be used for inference, such as when performance is less critical. In at least one embodiment, a hardware structure 1415 is used to execute one or more embodiments. Details regarding hardware structure 1415 are provided below in conjunction with FIG. 14A and / or FIG. 14B.

[0176] Computer Systems 18 is a block diagram illustrating an exemplary computer system, which may be a system having interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof 1800 formed with a processor that may include an execution unit for executing instructions, according to at least one embodiment. In at least one embodiment, computer system 1800 may include components such as, without limitation, processor 1800 for using an execution unit that includes logic for executing algorithms for processing data in accordance with the present disclosure, such as in the embodiments described herein. In at least one embodiment, computer system 1800 may include a processor such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems may be used (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.). In at least one embodiment, computer system 1800 may run a version of the WINDOWS® operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX® and Linux®), embedded software, and / or graphical user interfaces may also be used.

[0177] Embodiments may be used in other devices, such as portable devices and embedded applications. Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable PCs. In at least one embodiment, embedded applications may include microcontrollers, digital signal processors ("DSPs"), systems-on-chips, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.

[0178] In at least one embodiment, computer system 1800 may include, without limitation, a processor 1802, which may include one or more execution units 1808 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, system 18 is a single-processor desktop or server system, while in other embodiments, system 18 may be a multiprocessor system. In at least one embodiment, processor 1802 may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 1802 may be coupled to a processor bus 1810, which may transmit digital signals between processor 1802 and other components within computer system 1800.

[0179] In at least one embodiment, processor 1802 may include, without limitation, level 1 ("L1") internal cache memory ("cache") 1804. In at least one embodiment, processor 1802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 1802. Other embodiments may include a combination of both internal and external cache, depending on the particular implementation and needs. In at least one embodiment, register file 1806 may store different types of data in various registers, including, without limitation, integer registers, floating-point registers, status registers, and an instruction pointer register.

[0180] In at least one embodiment, processor 1802 also includes an execution unit 1808, including, without limitation, logic for performing integer and floating-point operations. Processor 1802 may also include microcode (“u-code”) read-only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1808 may include logic for a packed instruction set 1809. In at least one embodiment, including the packed instruction set 1809, along with associated circuitry for executing the instructions, in the instruction set of general-purpose processor 1802 allows operations used by many multimedia applications to be performed using packed data in general-purpose processor 1802. In one or more embodiments, many multimedia applications can be accelerated and run more efficiently by performing operations on packed data using the full width of the processor's data bus, thereby eliminating the need to transfer smaller units of data between the processor's data bus to perform one or more operations on one data element at a time.

[0181] In at least one embodiment, execution unit 1808 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1800 may include, without limitation, memory 1820. In at least one embodiment, memory 1820 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. Memory 1820 may store instructions 1819 and / or data 1821 represented by data signals that may be executed by processor 1802.

[0182] In at least one embodiment, a system logic chip may be coupled to the processor bus 1810 and the memory 1820. In at least one embodiment, the system logic chip may include, without limitation, a memory controller hub (“MCH”) 1816, and the processor 1802 may communicate with the MCH via the processor bus 1810. In at least one embodiment, the MCH 1816 may provide a high-bandwidth memory path 1818 to the memory 1820 for storing instructions and data, and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 1816 may route data signals between the processor 1802, the memory 1820, and other components of the computer system 1800, and may bridge data signals between the processor bus 1810, the memory 1820, and the system I / O 1822. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1816 may be coupled to memory 1820 via a high-bandwidth memory path 1818, and the graphics / video card 1812 may be coupled to the MCH 1816 via an Accelerated Graphics Port (“AGP”) interconnect 1814.

[0183] In at least one embodiment, computer system 1800 may use system I / O 1822, a proprietary hub interface bus, to couple MCH 1816 to I / O controller hub (“ICH”) 1830. In at least one embodiment, ICH 1830 may provide direct connectivity to several I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, without limitation, a high-speed I / O bus for connecting peripherals to memory 1820, a chipset, and processor 1802. Examples may include, without limitation, an audio controller 1829, a firmware hub ("flash BIOS") 1828, a wireless transceiver 1826, data storage 1824, a legacy I / O controller 1823 including a user input and keyboard interface, a serial expansion port 1827 such as a Universal Serial Bus ("USB"), and a network controller 1834. Data storage 1824 may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0184] In at least one embodiment, Figure 18 illustrates a system including interconnected hardware devices or "chips," while in other embodiments, Figure 18 may illustrate an exemplary system-on-a-chip ("SoC"). In at least one embodiment, the devices illustrated in Figure cc may be interconnected using a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1800 may be interconnected using a compute express link (CXL) interconnect.

[0185] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with Figures 14A and / or 14B. In at least one embodiment, inference and / or training logic 1415 may be used in the system of Figure 18 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0186] In one embodiment, electronic device 1900 may be a robotic control system that controls the operation of an automated picking system or an automated forklift. In one embodiment, electronic device 1900 may include one or more servo motor controllers that actuate the grippers, claws, or hands of the robot.

[0187] 19 is a block diagram illustrating an electronic device 1900 for utilizing a processor 1910, according to at least one embodiment. In at least one embodiment, electronic device 1900 may be, for example, without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0188] In at least one embodiment, system 1900 may include, without limitation, a processor 1910 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. 2and processor 1910 coupled using a bus or interface, such as a C bus, System Management Bus (“SMBus”), Low Pin Count (“LPC”) bus, Serial Peripheral Interface (“SPI”), High Definition Audio (“HDA”) bus, Serial Advance Technology Attachment (“SATA”) bus, Universal Serial Bus (“USB”) (versions 1, 2, and 3), or Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, FIG. 19 depicts a system including interconnected hardware devices or “chips,” while in other embodiments, FIG. 19 may depict an exemplary system-on-a-chip (“SoC”). In at least one embodiment, the devices shown in Figure 19 may be interconnected with a proprietary interconnect, a standard interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of Figure 19 may be interconnected using a Compute Express Link (CXL) interconnect.

[0189] In at least one embodiment, FIG. 19 illustrates a display 1924, a touch screen 1925, a touch pad 1930, a Near Field Communications unit ("NFC") 1945, a sensor hub 1940, a thermal sensor 1946, an Express Chipset ("EC") 1935, a Trusted Platform Module ("TPM") 1938, a BIOS / firmware / flash memory ("BIOS,FW flash") 1922, a DSP 1960, a drive 1920, such as a solid state disk ("SSD") or hard disk drive ("HDD"), a wireless local area network unit ("WLAN") 1950, a Bluetooth unit 1952, a wireless wide area network unit ("WWAN") 1954, a Bluetooth module 1954, a wireless local area network unit ("WLAN") 1956, a Bluetooth module 1958, a wireless wide area network unit ("WWAN") 1960, a Bluetooth module 1962, a Bluetooth module 1964, a Bluetooth module 1966, a Bluetooth module 1968 ... The memory may include a GPS (Global Positioning System) 1956, a Global Positioning System (GPS) 1955, a camera such as a USB 3.0 camera ("USB 3.0 Camera") 1954, or a Low Power Double Data Rate ("LPDDR") memory unit ("LPDDR3") 1915, implemented, for example, to the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0190] In at least one embodiment, other components may be communicatively coupled to the processor 1910 via the components described above. In at least one embodiment, an accelerometer 1941, an ambient light sensor (“ALS”) 1942, a compass 1943, and a gyroscope 1944 may be communicatively coupled to the sensor hub 1940. In at least one embodiment, a thermal sensor 1939, a fan 1937, a keyboard 1946, and a touchpad 1930 may be communicatively coupled to the EC 1935. In at least one embodiment, a speaker 1963, headphones 1964, and a microphone (“mic”) 1965 may be communicatively coupled to an audio unit (audio codec and class D amplifier) ​​1962, which may be communicatively coupled to the DSP 1960. In at least one embodiment, the audio unit 1964 may include, for example, without limitation, an audio coder / decoder (“codec”) and a class D amplifier. In at least one embodiment, a SIM card (“SIM”) 1957 may be communicatively coupled to the WWAN unit 1956. In at least one embodiment, components such as the WLAN unit 1950 and the Bluetooth unit 1952, and the WWAN 1956 may be implemented in a Next Generation Form Factor (“NGFF”).

[0191] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with Figures 14A and / or 14B. In at least one embodiment, inference and / or training logic 1415 may be used in the system of Figure 19 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0192] 20 illustrates, according to at least one embodiment, a computer system 2000. In at least one embodiment, the computer system 2000 is configured to implement the various processes and methods described throughout this disclosure.

[0193] In at least one embodiment, computer system 2000 includes at least one central processing unit ("CPU") 2002 connected to a communication bus 2010 implemented using any suitable protocol, such as, without limitation, PCI (Peripheral Component Interconnect), Peripheral Component Interconnect Express ("PCI-Express"), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 2000 includes main memory 2004 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in main memory 2004, which may be in the form of random access memory ("RAM"). In at least one embodiment, network interface subsystem (“network interface”) 2022 provides an interface with other computing devices and networks to receive data from other systems and transmit data from computer system 2000 to other systems.

[0194] In at least one embodiment, computer system 2000 includes, without limitation, input device(s) 2008, a parallel processing system 2012, and a display device 2006, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode ("LED"), plasma display, or other suitable display technology. In at least one embodiment, user input is received from input device(s) 2008, such as a keyboard, mouse, touch pad, microphone, or the like. In at least one embodiment, each of the above modules may be located on a single semiconductor platform to form a processing system.

[0195] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with Figures 14A and / or 14B. In at least one embodiment, training logic 1415 may be used in the system of Figure 20 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0196] 21 illustrates a computer system 2100 according to at least one embodiment. In at least one embodiment, the computer system 2100 may include, without limitation, a computer 2110 and a USB stick 2120. In at least one embodiment, the computer system 2110 may include, without limitation, any number and type of processor (not shown) and memory. In at least one embodiment, the computer 2110 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.

[0197] In at least one embodiment, USB stick 2120 includes, without limitation, a processing unit 2130, a USB interface 2140, and USB interface logic 2150. In at least one embodiment, processing unit 2130 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 2130 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing core 2130 comprises an application specific integrated circuit ("ASIC") optimized to perform any amount and type of operations related to machine learning. For example, in at least one embodiment, processing core 2130 is a tensor processing unit ("TPC") optimized to perform machine vision and machine learning inference operations. In at least one embodiment, processing core 2130 is a vision processing unit ("VPU") optimized to perform machine vision and machine learning inference operations.

[0198] In at least one embodiment, USB interface 2140 may be any type of USB connector or socket. For example, in at least one embodiment, USB interface 2140 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 2140 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 2150 may include any amount and type of logic that enables processing unit 2130 to interface with a device (e.g., computer 2110) via USB connector 2140.

[0199] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with Figures 14A and / or 14B. In at least one embodiment, inference and / or training logic 1415 may be used in the system of Figure 21 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0200] 22 illustrates an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0201] 22 is a block diagram illustrating an exemplary system-on-chip integrated circuit 2200 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 2200 includes one or more application processors 2205 (e.g., CPUs), at least one graphics processor 2210, and may further include an image processor 2215 and / or a video processor 2220, any of which may be modular IP cores. In at least one embodiment, integrated circuit 2200 includes peripheral or bus logic including a USB controller 2225, a UART controller 2230, an SPI / SDIO controller 2235, and an I.sup.2S / I.sup.2C controller 2240. In at least one embodiment, integrated circuit 2200 may include a display device 2245 coupled to one or more of a high-definition multimedia interface (HDMI®) controller 2250 and a mobile industry processor interface (MIPI) display interface 2255. In at least one embodiment, storage may be provided by a flash memory subsystem 2260 including a flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via memory controller 2265 to access an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits further include an embedded security engine 2270.

[0202] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with Figures 14A and / or 14B. In at least one embodiment, inference and / or training logic 1415 may be used in integrated circuit 2200 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0203] 23A-23B illustrate an exemplary integrated circuit and associated graphics processor that can be fabricated using one or more IP cores according to various embodiments described herein. In addition to what is shown, in at least one embodiment, other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0204] 23A-23B are block diagrams illustrating exemplary graphics processors for use within an SoC according to embodiments described herein. FIG. 23A illustrates an exemplary graphics processor 2310 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. FIG. 23B illustrates a further exemplary graphics processor 2340 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the graphics processor 2310 of FIG. 23A is a low-power graphics processor core. In at least one embodiment, the graphics processor 2340 of FIG. 23B is a high-performance graphics processor core. In at least one embodiment, each of the graphics processors 2310, 2340 can be a variation of the graphics processor 2210 of FIG. 22.

[0205] In at least one embodiment, the graphics processor 2310 includes a vertex processor 2305 and one or more fragment processors 2315A-2315N (e.g., 2315A, 2315B, 2315C, 2315D-2315N-1, and 2315N). In at least one embodiment, the graphics processor 2310 can execute different shader programs through separate logic, such that the vertex processor 2305 is optimized to perform operations for vertex shader programs, while one or more fragment processors 2315A-2315N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 2305 executes the vertex processing stage of the 3D graphics pipeline, generating primitive and vertex data. In at least one embodiment, the fragment processors 2315A-2315N generate a frame buffer that is displayed on a display device using the primitive and vertex data generated by the vertex processor 2305. In at least one embodiment, the fragment processors 2315A-2315N are optimized to execute fragment shader programs provided in the OpenGL API, which may be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0206] In at least one embodiment, the graphics processor 2310 further includes one or more memory management units (MMUs) 2320A-2320B, caches 2325A-2325B, and circuit interconnects 2330A-2330B. In at least one embodiment, the one or more MMUs 2320A-2320B provide virtual-to-physical address mapping for the graphics processor 2310, including the vertex processor 2305 and / or fragment processors 2315A-2315N, which may reference vertex or image / text data stored in memory in addition to vertex or image / text data stored in one or more caches 2325A-2325B. In at least one embodiment, one or more MMUs 2320A-2320B may be synchronized with other MMUs in the system, including one or more MMUs associated with one or more application processors 2205, image processor 2215, and / or video processor 2220 of Figure 25, allowing each processor 2205-2220 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 2330A-2330B enable graphics processor 2310 to interface with other IP cores in the SoC via the SoC's internal bus or via a direct connection.

[0207] In at least one embodiment, graphics processor 2340 includes one or more MMUs 2320A-2320B, caches 2325A-2325B, and circuit interconnects 2330A-2330B of graphics processor 2310 of FIG. 23A. In at least one embodiment, graphics processor 2340 includes one or more shader cores 2355A-2355N (e.g., 2355A, 2355B, 2355C, 2355D, 2355E, 2355F-2355N-1, and 2355N), providing a unified shader core architecture in which a single core, or type, or cores can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 2340 includes an inter-core task manager 2345 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 2355A-2355N, and a tiling unit 2358 for accelerating tiling operations for tile-based rendering, where scene rendering operations are subdivided in image space, e.g., to exploit local spatial coherence within a scene or to optimize internal cache usage.

[0208] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with Figures 14A and / or 14B. In at least one embodiment, inference and / or training logic 1415 may be used in integrated circuits 23A and / or 23B for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0209] 24A-24B illustrate further exemplary graphics processor logic according to embodiments described herein. Figure 24A illustrates a graphics core 2400 that, in at least one embodiment, may be included in graphics processor 2210 of Figure 22, and in at least one embodiment, may be integrated shader cores 2355A-2355N, as in Figure 23B. Figure 24B illustrates a highly parallel, general-purpose graphics processing unit 2430 suitable for incorporation into a multi-chip module in at least one embodiment.

[0210] In one embodiment, graphics core 2400 includes a shared instruction cache 2402, a texture unit 2418, and a cache / shared memory 2420, which are common to execution resources within graphics core 2400. In at least one embodiment, graphics core 2400 may include multiple slices 2401A-2401N, or partitions, per core, and a graphics processor may include multiple instances of graphics core 2400. Slices 2401A-2401N may include supporting logic, including logical instruction caches 2404A-2404N, thread schedulers 2406A-2406N, thread dispatchers 2408A-2408N, and sets of registers 2410A-2410N. In one embodiment, slices 2401A-2401N may include a set of additional function units (AFUs) 2412A-2412N, floating-point units (FPUs) 2414A-2414N, integer arithmetic logic units (ALUs) 2416-2416N, address calculation units (ACLs) 2413A-2413N, double-precision floating-point units (DPFPUs) 2415A-2415N, and matrix processing units (MPUs) 2417A-2417N.

[0211] In one embodiment, the FPUs 2414A-2414N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, and the DPFPUs 2415A-2415N can perform double-precision (64-bit) floating-point operations. In one embodiment, the ALUs 2416A-2416N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In one embodiment, the MPUs 2417A-2417N can also be configured for mixed-precision matrix operations, including half-precision floating-point and 8-bit integer operations. In one embodiment, the MPUs 2417A-2417N can perform various matrix operations to accelerate machine learning application frameworks, including being able to support acceleration of general matrix-to-matrix multiplication (GEMM). In one embodiment, the AFUs 2412A-2412N can perform additional logical operations not supported in floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0212] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with FIG. 14A and / or FIG. 14B. In at least one embodiment, inference and / or training logic 1415 may be used in graphics core 2400 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0213] FIG. 24B illustrates a general-purpose processing unit (GPGPU) 2430, which, in at least one embodiment, can be configured to enable highly parallel compute operations to be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 2430 can be directly linked to other instances of the GPGPU 2430 to create multiple GPU clusters to improve the training speed of deep neural networks. In at least one embodiment, the GPGPU 2430 includes a host interface 2432 to enable connection to a host processor. In at least one embodiment, the host interface 2432 is a PCI Express interface. In at least one embodiment, the host interface 2432 can be a vendor-specific communications interface or fabric. In at least one embodiment, the GPGPU 2430 receives commands from the host processor and, using a global scheduler 2434, distributes execution threads associated with those commands to a set of compute clusters 2436A-2436H. In at least one embodiment, compute clusters 2436A-2436H share cache memory 2438. In at least one embodiment, cache memory 2438 can act as a higher level cache for cache memories within compute clusters 2436A-2436H.

[0214] In at least one embodiment, GPGPU 2430 includes memory 2444A-2444B coupled to compute clusters 2436A-2436H via a set of memory controllers 2442A-2442B. In at least one embodiment, memory 2444A-2444B can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0215] In at least one embodiment, compute clusters 2436A-2436H each include a set of graphics cores, such as graphics core 2400 of FIG. 24A, which may include multiple types of integer and floating-point logic units capable of performing computational operations with various precisions, including those suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of compute clusters 2436A-2436H may be configured to perform 16-bit or 32-bit floating-point operations, while another subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0216] In at least one embodiment, multiple instances of GPGPU 2430 can be configured to operate as a compute cluster. In at least one embodiment, the communications used by compute clusters 2436A-2436H for synchronization and data exchange vary across embodiments. In at least one embodiment, multiple instances of GPGPU 2430 communicate through host interface 2432. In at least one embodiment, GPGPU 2430 includes I / O hub 2439, which couples GPGPU 2430 to GPU link 2440, which enables direct connection to other instances of GPGPU 2430. In at least one embodiment, GPU link 2440 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 2430. In at least one embodiment, GPU link 2440 is coupled to a high-speed interconnect for sending and receiving data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2430 are located in separate data processing systems and communicate via a network device accessible via host interface 2432. In at least one embodiment, GPU link 2440 can be configured to allow connection to a host processor in addition to, or instead of, host interface 2432.

[0217] In at least one embodiment, the GPGPU 2430 can be configured to train a neural network. In at least one embodiment, the GPGPU 2430 can be used within an inference platform. In at least one embodiment, when the GPGPU 2430 is used for inference, the GPGPU may include fewer compute clusters 2436A-2436H than when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with memories 2444A-2444B may be different for the inference configuration and the training configuration, with higher bandwidth memory technology being devoted to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2430 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can support one or more 8-bit integer dot product instructions, which may be used during inference operations of a deployed neural network.

[0218] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1415 are provided below in conjunction with Figures 14A and / or 14B. In at least one embodiment, the inference and / or training logic 1415 may be used in the GPGPU 2430 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0219] 25 is a block diagram illustrating a computing system 2500 according to at least one embodiment. In at least one embodiment, computing system 2500 includes a processing subsystem 2501 having one or more processors 2502 and system memory 2504 that communicate via an interconnection path that may include a memory hub 2505. In at least one embodiment, memory hub 2505 may be a separate component within a chipset component or may be integrated within one or more processors 2502. In at least one embodiment, memory hub 2505 is coupled to an I / O subsystem 2511 via communication link 2506. In at least one embodiment, I / O subsystem 2511 includes an I / O hub 2507 that can enable computing system 2500 to receive input from one or more input devices 2508. In at least one embodiment, the I / O hub 2507 can enable a display controller, which may be included in one or more processors 2502 and provide output to one or more display devices 2510A. In at least one embodiment, the one or more display devices 2510A coupled to the I / O hub 2507 can include local, internal, or embedded display devices.

[0220] In at least one embodiment, processing subsystem 2501 includes one or more parallel processors 2512 coupled to memory hub 2505 via a bus or other communication link 2513. In at least one embodiment, communication link 2513 may be one of any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or fabric. In at least one embodiment, one or more parallel processors 2512 form a computationally intensive parallel or vector processing system that may include multiple processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, one or more parallel processors 2512 form a graphics processing subsystem that can output pixels to one or more display devices 2510A coupled via I / O hub 2507. In at least one embodiment, the one or more parallel processors 2512 may also include a display controller and display interface (not shown) that allows direct connection to one or more display devices 2510B.

[0221] In at least one embodiment, a system storage unit 2514 may be connected to an I / O hub 2507 to provide a storage mechanism for the computing system 2500. In at least one embodiment, an I / O switch 2516 may be used to provide an interface mechanism to enable communication between the I / O hub 2507 and other components, such as a network adapter 2518 and / or a wireless network adapter 2519, which may be integrated into the platform, as well as various other devices that may be added via one or more add-in devices 2520. In at least one embodiment, the network adapter 2518 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 2519 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more wireless radios.

[0222] In at least one embodiment, computing system 2500 may include other components not shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 2507. In at least one embodiment, the communication paths interconnecting the various components of FIG. 25 may be implemented using any suitable protocol, such as a Peripheral Component Interconnect (PCI)-based protocol (e.g., PCI-Express), or other bus or point-to-point communication interface, such as an NV-Link high-speed interconnect, or other interconnection protocol.

[0223] In at least one embodiment, one or more parallel processors 2512 incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, forming a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 2512 incorporate circuitry optimized for general-purpose processing. In at least one embodiment, components of computing system 2500 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 2512, memory hub 2505, processor 2502, and I / O hub 2507 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, components of computing system 2500 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 2500 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computing system.

[0224] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1415 are provided below in conjunction with Figures 14A and 14B. In at least one embodiment, the inference and / or training logic 1415 may be used in the system of Figure 2500 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0225] 26A illustrates a parallel processor 2600 according to at least one embodiment. In at least one embodiment, various components of parallel processor 2600 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the illustrated parallel processor 2600 is a variation of one or more parallel processors 2512 shown in FIG. 25 according to an example embodiment.

[0226] In at least one embodiment, parallel processor 2600 includes parallel processing units 2602. In at least one embodiment, parallel processing units 2602 include I / O units 2604 that enable communication with other devices, including other instances of parallel processing units 2602. In at least one embodiment, I / O units 2604 may be directly connected to other devices. In at least one embodiment, I / O units 2604 are connected to other devices through the use of a hub or switch interface, such as memory hub 2505. In at least one embodiment, the connection between memory hub 2505 and I / O units 2604 forms communication link 2513. In at least one embodiment, I / O units 2604 are connected to host interface 2606 and memory crossbar 2616, where host interface 2606 receives commands directed to the execution of processing operations and memory crossbar 2616 receives commands directed to the execution of memory operations.

[0227] In at least one embodiment, when host interface 2606 receives command buffers via I / O unit 2604, host interface 2606 can direct work operations to execute these commands to front end 2608. In at least one embodiment, front end 2608 is coupled to scheduler 2610, which is configured to distribute commands or other work items to processing cluster array 2612. In at least one embodiment, scheduler 2610 ensures that processing cluster array 2612 is properly configured and in a valid state before tasks are distributed to processing cluster array 2612 of processing cluster array 2612. In at least one embodiment, scheduler 2610 is implemented via firmware logic running on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2610 is configurable to perform complex scheduling and work distribution operations at both coarse and fine granularities, allowing rapid preemption and context switching of threads executing in the processing array 2612. In at least one embodiment, host software can signal the scheduling workload in the processing array 2612 via one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed across the processing array 2612 by scheduler 2610 logic in the microcontroller that includes the scheduler 2610.

[0228] In at least one embodiment, processing cluster array 2612 can include up to “N” processing clusters (e.g., cluster 2614A, cluster 2614B through cluster 2614N). In at least one embodiment, each cluster 2614A through 2614N of processing cluster array 2612 can execute a large number of simultaneous threads. In at least one embodiment, scheduler 2610 can allocate work to clusters 2614A through 2614N of processing cluster array 2612 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 2610 or may be partially assisted by compiler logic during compilation of program logic configured to be executed by processing cluster array 2612. In at least one embodiment, different clusters 2614A through 2614N of processing cluster array 2612 can be allocated to process different types of programs or perform different types of computations.

[0229] In at least one embodiment, processing cluster array 2612 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2612 may be configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 2612 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0230] In at least one embodiment, the processing cluster array 2612 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2612 may include additional logic to support the execution of such graphics processing operations, including, but not limited to, texture sampling logic for performing texture operations, as well as mosaic logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2612 may be configured to execute graphics processing related shader programs, such as, but not limited to, vertex shaders, mosaic shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2602 may transfer data from system memory via the I / O unit 2604 for processing. In at least one embodiment, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 2622) during processing and then written back to system memory.

[0231] In at least one embodiment, when graphics processing is performed using parallel processing unit 2602, scheduler 2610 may be configured to divide the processing workload into roughly equal-sized tasks to better distribute graphics processing operations among multiple clusters 2614A-2614N of processing cluster array 2612. In at least one embodiment, portions of processing cluster array 2612 may be configured to perform different types of processing. For example, in at least one embodiment, to generate and display a rendered image, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform mosaic and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations. In at least one embodiment, intermediate data generated by one or more of clusters 2614A-2614N may be stored in a buffer so that the intermediate data can be transmitted between clusters 2614A-2614N for further processing.

[0232] In at least one embodiment, the processing cluster array 2612 can receive processing tasks to be performed via a scheduler 2610, which receives commands defining the processing tasks from the front end 2608. In at least one embodiment, a processing task can include an index of the data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data should be processed (e.g., which program to execute). In at least one embodiment, the scheduler 2610 can be configured to fetch the index corresponding to the task or can receive the index from the front end 2608. In at least one embodiment, the front end 2608 can be configured to ensure that the processing cluster array 2612 is configured to a valid state before a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.) is initiated.

[0233] In at least one embodiment, each of one or more instances of parallel processing unit 2602 can be coupled to parallel processor memory 2622. In at least one embodiment, parallel processor memory 2622 can be accessed via memory crossbar 2616, which can receive memory requests from processing cluster array 2612 as well as I / O unit 2604. In at least one embodiment, memory crossbar 2616 can access parallel processor memory 2622 via memory interface 2618. In at least one embodiment, memory interface 2618 can include multiple partition units (e.g., partition unit 2620A, partition unit 2620B through partition unit 2620N), each of which can be coupled to a portion (e.g., a memory unit) of parallel processor memory 2622. In at least one embodiment, the number of partition units 2620A-2620N is configured to be equal to the number of memory units, such that a first partition unit 2620A has a corresponding first memory unit 2624A, a second partition unit 2620B has a corresponding memory unit 2624B, and an Nth partition unit 2620N has a corresponding Nth memory unit 2624N. In at least one embodiment, the number of partition units 2620A-2620N does not have to be equal to the number of memory devices.

[0234] In at least one embodiment, the memory units 2624A-2624N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2624A-2624N may also include 3D stacked memory, including, but not limited to, high-bandwidth memory (HBM). In at least one embodiment, to efficiently use the available bandwidth of the parallel processor memory 2622, render targets, such as frame buffers or texture maps, may be stored across the memory units 2624A-2624N, allowing the partition units 2620A-2620N to write portions of each render target in parallel. In at least one embodiment, local instances of the parallel processor memory 2622 may be omitted in favor of a unified memory design that uses a combination of system memory and local cache memory.

[0235] In at least one embodiment, any one of the clusters 2614A-2614N in the processing cluster array 2612 can process data that is to be written to any one of the memory units 2624A-2624N in the parallel processor memory 2622. In at least one embodiment, the memory crossbar 2616 can be configured to forward the output of each cluster 2614A-2614N to any partition unit 2620A-2620N or to another cluster 2614A-2614N that can perform further processing operations on the output. In at least one embodiment, each cluster 2614A-2614N can communicate with a memory interface 2618 through the memory crossbar 2616 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 2616 has connections to memory interface 2618 for communicating with I / O units 2604, as well as connections to local instances of parallel processor memory 2622, allowing processing units in different processing clusters 2614A-2614N to communicate with system memory or other memory not local to parallel processing units 2602. In at least one embodiment, memory crossbar 2616 can use virtual channels to separate traffic streams between clusters 2614A-2614N and partition units 2620A-2620N.

[0236] In at least one embodiment, multiple instances of parallel processing unit 2602 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2602 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other different configurations. For example, in at least one embodiment, some instances of parallel processing unit 2602 may include higher precision floating-point units than other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit 2602 or parallel processor 2600 may be implemented in a variety of configurations and form factors, including, but not limited to, desktop, laptop, or portable personal computers, servers, workstations, game consoles, and / or embedded systems.

[0237] FIG. 26B is a block diagram of a partition unit 2620 according to at least one embodiment. In at least one embodiment, partition unit 2620 is an instance of one of partition units 2620A-2620N of FIG. 26A. In at least one embodiment, partition unit 2620 includes an L2 cache 2621, a frame buffer interface 2625, and a raster operations unit (ROP) 2626. L2 cache 2621 is a read / write cache configured to execute load and store operations received from memory crossbar 2616 and ROP 2626. In at least one embodiment, read misses and urgent writeback requests are output by L2 cache 2621 to frame buffer interface 2625 for processing. In at least one embodiment, updates are also sent to frames via frame buffer interface 2625 for processing. In at least one embodiment, frame buffer interface 2625 interfaces with one of the memory units of a parallel processor memory, such as memory units 2624A-2624N (eg, in parallel processor memory 2622) of FIG.

[0238] In at least one embodiment, ROP2626 is a processing unit that performs raster operations such as stencil, z-test, and blending. In at least one embodiment, ROP2626 then outputs the processed graphics data stored in graphics memory. In at least one embodiment, ROP2626 includes compression logic for compressing depth or color data being written to memory and decompressing depth or color data being read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a number of compression algorithms. The type of compression performed by ROP2626 can be varied based on statistical characteristics of the data being compressed. For example, in at least one embodiment, delta color compression is performed on the depth and color data on a tile-by-tile basis.

[0239] In at least one embodiment, ROP 2626 is included within each processing cluster (e.g., clusters 2614A-2614N of FIG. 26A ) rather than within partition unit 2620. In at least one embodiment, read and write requests for pixel data, rather than pixel fragment data, are transmitted through memory crossbar 2616. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display devices 2510 of FIG. 25 , may be routed for further processing by processor 2502, or may be routed for further processing by one of the processing entities in parallel processor 2600 of FIG. 26A .

[0240] FIG. 26C is a block diagram of a processing cluster 2614 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is an instance of one of processing clusters 2614A-2614N of FIG. 26A. In at least one embodiment, processing cluster 2614 may be configured to execute multiple threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of multiple threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of multiple, generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0241] In at least one embodiment, operation of the processing clusters 2614 may be controlled via a pipeline manager 2632, which distributes processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 2632 receives instructions from the scheduler 2610 of FIG. 26 and manages the execution of those instructions via the graphics multiprocessor 2634 and / or the texture unit 2636. In at least one embodiment, the graphics multiprocessor 2634 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing clusters 2614. In at least one embodiment, one or more instances of the graphics multiprocessor 2634 may be included within the processing clusters 2614. In at least one embodiment, the graphics multiprocessor 2634 may process data, and a data crossbar 2640 may be used to distribute the processed data to one of several possible destinations, including other shader units. In at least one embodiment, pipeline manager 2632 can facilitate distribution of the processed data by specifying destinations for the processed data to be distributed through data crossbar 2640.

[0242] In at least one embodiment, each graphics multiprocessor 2634 in a processing cluster 2614 may include an identical set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, allowing new instructions to be issued before previous instructions complete. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, bit shifts, and calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0243] In at least one embodiment, instructions sent to processing cluster 2614 constitute threads. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread in a thread group can be assigned to a different processing engine in graphics multiprocessor 2634. In at least one embodiment, a thread group may include fewer threads than the number of processing engines in graphics multiprocessor 2634. In at least one embodiment, if a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is processed. In at least one embodiment, a thread group may also include more threads than the number of processing engines in graphics multiprocessor 2634. In at least one embodiment, if a thread group includes more threads than the number of processing engines in graphics multiprocessor 2634, processing may be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on graphics multiprocessor 2634.

[0244] In at least one embodiment, the graphics multiprocessor 2634 includes internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2634 can forgo the internal cache and use cache memory (e.g., L1 cache 2648) within the processing cluster 2614. In at least one embodiment, each graphics multiprocessor 2634 can also access an L2 cache within a partition unit (e.g., partition units 2620A-2620N in FIG. 26A ), which may be shared among all processing clusters 2614 and used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2634 can also access off-chip global memory, which may include one or more of the local parallel processor memories and / or system memories. In at least one embodiment, any memory external to the parallel processing unit 2602 may be used as global memory. In at least one embodiment, processing cluster 2614 includes multiple instances of graphics multiprocessor 2634 that can share common instructions and data, which may be stored in L1 cache 2648.

[0245] In at least one embodiment, each processing cluster 2614 may include an MMU 2645 (memory management unit) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2645 may reside within memory interface 2618 of FIG. 26. In at least one embodiment, MMU 2645 includes a set of page table entries (PTEs) used to map virtual addresses to physical addresses for tiles (tiling is described in more detail) and optionally cache line indices. In at least one embodiment, MMU 2645 may include an address translation lookaside buffer (TLB) or cache, which may reside within graphics multiprocessor 2634 or an L1 cache, or processing cluster 2614. In at least one embodiment, physical addresses are processed to locally distribute surface data accesses, allowing efficient interleaving of requests across partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0246] In at least one embodiment, processing cluster 2614 may be configured such that each graphics multiprocessor 2634 is coupled to a texture unit 2636 to perform texture mapping operations, such as determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2634 and fetched as needed from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2634 outputs processed tasks to data crossbar 2640 to provide the processed tasks to another processing cluster 2614 for further processing, or stores the processed tasks in an L2 cache, local parallel processor memory, or system memory via memory crossbar 2616. In at least one embodiment, a pre-ROP 2642 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2634 and direct the data to a ROP unit, which may be located within a partition unit (e.g., partition units 2620A-2620N of FIG. 26 ), as described herein. In at least one embodiment, the pre-ROP 2642 unit can perform color blending optimizations, organize pixel color data, and perform address translation.

[0247] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with FIG. 14A and / or FIG. 14B. In at least one embodiment, inference and / or training logic 1415 may be used in graphics processing cluster 2614 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0248] 26D illustrates a graphics multiprocessor 2634 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2634 couples with a pipeline manager 2632 of a processing cluster 2614. In at least one embodiment, the graphics multiprocessor 2634 has an execution pipeline including, but not limited to, an instruction cache 2652, an instruction unit 2654, an address mapping unit 2656, a register file 2658, one or more general-purpose graphics processing unit (GPGPU) cores 2662, and one or more load / store units 2666. The GPGPU cores 2662 and the load / store units 2666 are coupled to a cache memory 2672 and a shared memory 2670 via a memory and cache interconnect 2668.

[0249] In at least one embodiment, instruction cache 2652 receives a stream of instructions to execute from pipeline manager 2632. In at least one embodiment, instructions are cached in instruction cache 2652 and dispatched for execution by instruction unit 2654. In at least one embodiment, instruction unit 2654 can dispatch instructions as thread groups (e.g., warps), with each thread of a thread group being assigned to a different execution unit within GPGPU core 2662. In at least one embodiment, instructions can access either local, shared, or global address spaces by specifying addresses in the unified address space. In at least one embodiment, address mapping unit 2656 can be used to translate addresses in the unified address space into individual memory addresses accessible by load / store unit 2666.

[0250] In at least one embodiment, register file 2658 provides a set of registers to the functional units of graphics multiprocessor 2634. In at least one embodiment, register file 2658 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 2662, load / store unit 2666) of graphics multiprocessor 2634. In at least one embodiment, register file 2658 is partitioned among the respective functional units, with each functional unit allocated a dedicated portion of register file 2658. In one embodiment, register file 2658 is partitioned among the different warps being executed by graphics multiprocessor 2634.

[0251] In at least one embodiment, the GPGPU cores 2662 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) used to execute instructions for the graphics multiprocessor 2634. The GPGPU cores 2662 may have similar or different architectures. In at least one embodiment, a first portion of the GPGPU core 2662 includes a single-precision FPU and an integer ALU, and a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point operations or may enable variable-precision floating-point operations. In at least one embodiment, the graphics multiprocessor 2634 may further include one or more fixed-function or special-function units for performing specific functions, such as rectangular copy or pixel-blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0252] In at least one embodiment, GPGPU core 2662 includes SIMD logic capable of executing a single instruction on multiple data sets. In one embodiment, GPGPU core 2662 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for the GPGPU core may be generated at compile time by a shader compiler or may be generated automatically when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model can execute via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can execute in parallel via a single SIMD8 logical unit.

[0253] In at least one embodiment, memory and cache interconnect 2668 is an interconnect network connecting each functional unit of graphics multiprocessor 2634 to register file 2658 and shared memory 2670. In at least one embodiment, memory and cache interconnect 2668 is a crossbar interconnect that allows load / store unit 2666 to implement load and store operations between shared memory 2670 and register file 2658. In at least one embodiment, register file 2658 can operate at the same frequency as GPGPU cores 2662, and therefore data transfers between GPGPU cores 2662 and register file 2658 have very low latency. In at least one embodiment, shared memory 2670 can be used to enable communication between threads executing in functional units within graphics multiprocessor 2634. In at least one embodiment, cache memory 2672 can be used, for example, as a data cache to cache texture data communicated between functional units and texture unit 2636. In at least one embodiment, shared memory 2670 can also be used as a program-managed cache. In at least one embodiment, threads running on GPGPU cores 2662 can programmatically store data in the shared memory in addition to automatically caching data stored in cache memory 2672.

[0254] In at least one embodiment, a parallel processor or GPGPU described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated into the same package or chip as the core or may be communicatively coupled to the core via an internal (i.e., internal to the package or chip) processor bus / interconnect. In at least one embodiment, regardless of how the GPU is connected, the processor core may allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0255] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding inference and / or training logic 1415 are provided below in conjunction with Figures 14A and / or 14B. In at least one embodiment, inference and / or training logic 1415 may be used in graphics multiprocessor 2634 for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functionality and / or architecture, or neural network use cases described herein.

[0256] FIG. 27 is a block diagram illustrating the micro-architecture of a processor 2700 that may include logic circuits for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2700 may execute instructions, including x86 instructions, AMR instructions, special instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2700 may include registers for storing packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology by Intel Corporation of Santa Clara, California. In at least one embodiment, MMX registers, available in both integer and floating-point formats, may operate on packed data elements with Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (collectively referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processor 2700 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0257] In at least one embodiment, processor 2700 includes an in-order front end (“front end”) 2701 that fetches instructions to be executed and prepares the instructions for later use in the processor pipeline. In at least one embodiment, front end 2701 may include several units. In at least one embodiment, an instruction prefetcher 2726 fetches instructions from memory and provides the instructions to an instruction decoder 2728, which decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 2728 decodes received instructions into one or more operations, called “microinstructions” or “micro-operations” (also called “micro-ops” or “uops”), that the machine can execute. In at least one embodiment, instruction decoder 2728 parses instructions into opcodes and corresponding data and control fields that may be used by the micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, trace cache 2730 may assemble decoded uops into program-order sequences, or traces, in uop queue 2734 for execution. In at least one embodiment, when trace cache 2730 encounters a complex instruction, microcode ROM 2732 provides the uops necessary to complete the operation.

[0258] In at least one embodiment, some instructions can be converted into a single micro-op, while other instructions require several micro-ops to complete the entire operation. In at least one embodiment, if an instruction requires more than four micro-ops to complete, the instruction decoder 2728 may access the microcode ROM 2732 to execute the instruction. In at least one embodiment, the instruction may be decoded into a smaller number of micro-ops for processing in the instruction decoder 2728. In at least one embodiment, if an operation requires a large number of micro-ops to complete, the instruction may be stored in the microcode ROM 2732. In at least one embodiment, the trace cache 2730 references an entry point programmable logic array (“PLA”) to determine the correct microinstruction pointer to read the microcode sequence from to complete one or more instructions from the microcode ROM 2732, in accordance with at least one embodiment. In at least one embodiment, after the microcode ROM 2732 has finished sequencing micro-ops for an instruction, the machine front end 2701 may resume fetching micro-ops from the trace cache 2730.

[0259] In at least one embodiment, out-of-order execution engine ("out-of-order engine") 2703 may prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the flow of instructions to optimize performance as instructions are scheduled for execution down the pipeline. Out-of-order execution engine 2703 includes, without limitation, allocator / register renamer 2740, memory uop queue 2742, integer / floating point uop queue 2744, memory scheduler 2746, fast scheduler 2702, slow / general purpose floating point scheduler ("slow / general purpose FP scheduler") 2704, and simple floating point scheduler ("simple FP scheduler") 2706. In at least one embodiment, fast scheduler 2702, slow / general purpose floating point scheduler 2704, and simple floating point scheduler 2706 are also collectively referred to herein as "uop schedulers 2702, 2704, 2706." Allocator / register renamer 2740 allocates machine buffers and resources required by each uop to execute. In at least one embodiment, allocator / register renamer 2740 renames logical registers upon entry into the register file. In at least one embodiment, allocator / register renamer 2740 also allocates each uop's entry to one of two uop queues—memory uop queue 2742 for memory operations and integer / floating point uop queue 2744 for non-memory operations—before memory scheduler 2746 and uop schedulers 2702, 2704, 2706. In at least one embodiment, uop schedulers 2702, 2704, 2706 determine when uops are ready to execute based on the readiness of the sources of their dependent input register operands and the availability of the execution resources required by the uop to complete their operations.In at least one embodiment, the fast scheduler 2702 may schedule every half of the main clock cycle, and the slow / general purpose floating point scheduler 2704 and simple floating point scheduler 2706 may schedule once per main processor clock cycle. In at least one embodiment, the uop schedulers 2702, 2704, 2706 arbitrate for dispatch ports to schedule uops for execution.

[0260] In at least one embodiment, execution block b11 includes, without limitation, integer register file / bypass network 2708, floating point register file / bypass network (“FP register file / bypass network”) 2710, address generation units (“AGUs”) 2712 and 2714, fast arithmetic logic units (ALUs) (“fast ALUs”) 2716 and 2718, slower arithmetic logic unit (“slower ALU”) 2720, floating point ALU (“FP”) 2722, and floating point move unit (“FP move”) 2724. In at least one embodiment, integer register file / bypass network 2708 and floating point register file / bypass network 2710 are also referred to herein as “register files 2708, 2710.” In at least one embodiment, AGUs 2712 and 2714, fast ALUs 2716 and 2718, slow ALU 2720, floating-point ALU 2722, and floating-point move unit 2724 are also referred to herein as "execution units 2712, 2714, 2716, 2718, 2720, 2722, and 2724." In at least one embodiment, execution block b11 may include any number and type of register files (including zero), bypass networks, address generation units, and execution units, in any combination, without limitation.

[0261] In at least one embodiment, register files 2708, 2710 may be located between uop schedulers 2702, 2704, 2706 and execution units 2712, 2714, 2716, 2718, 2720, 2722, and 2724. In at least one embodiment, integer register file / bypass network 2708 performs integer operations. In at least one embodiment, floating point register file / bypass network 2710 performs floating point operations. In at least one embodiment, each of register files 2708, 2710 may include, without limitation, a bypass network that may bypass or forward recently completed results that have not yet been written to the register file to new dependent uops. In at least one embodiment, register files 2708, 2710 may communicate data with each other. In at least one embodiment, integer register file / bypass network 2708 may include, without limitation, two separate register files: one register file for the lower 32-bit data and a second register file for the higher 32-bit data. In at least one embodiment, floating-point instructions typically have operands that are 64-128 bits wide, so floating-point register file / bypass network 2710 may include, without limitation, 128-bit wide entries.

[0262] In at least one embodiment, execution units 2712, 2714, 2716, 2718, 2720, 2722, and 2724 may execute instructions. In at least one embodiment, register files 2708 and 2710 store integer and floating-point data operand values ​​required by microinstructions to execute. In at least one embodiment, processor 2700 may include any number and combination of execution units 2712, 2714, 2716, 2718, 2720, 2722, and 2724, without limitation. In at least one embodiment, floating-point ALU 2722 and floating-point move unit 2724 may execute floating-point, MMX, SIMD, AVX, and SEE, or other operations, including special machine learning instructions. In at least one embodiment, the floating-point ALU 2722 may include, without limitation, a 64-bit floating-point divider to perform division, square root, and remaining micro-ops. In at least one embodiment, instructions involving floating-point values ​​may be handled by floating-point hardware. In at least one embodiment, ALU operations may be passed to the high-speed ALUs 2716, 2718. In at least one embodiment, the high-speed ALUs 2716, 2718 may perform high-speed operations with an effective latency of half a clock cycle. In at least one embodiment, the low-speed ALU 2720 may include, without limitation, integer execution hardware for long-latency type operations such as multipliers, shifts, flag logic, and branching, with most complex integer operations proceeding to the low-speed ALU. In at least one embodiment, memory load / store operations may be performed by the ALUs 2712, 2714. In at least one embodiment, fast ALU 2716, fast ALU 2718, and slow ALU 2720 may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2716, fast ALU 2718, and slow ALU 2720 may be implemented to support various data bit sizes, including 16, 32, 128, 256, etc. In at least one embodiment, floating-point ALU 2722 and floating-point move unit 2724 may be implemented to support wide operands having various bit widths.In at least one embodiment, floating-point ALU 2722 and floating-point move unit 2724 may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0263] In at least one embodiment, the uop schedulers 2702, 2704, 2706 dispatch dependent operations before the parent load finishes execution. In at least one embodiment, because uops may be speculatively scheduled and executed in the processor 2700, the processor 2700 may also include logic to handle memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations in progress in the pipeline past the scheduler that have temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use the incorrect data. In at least one embodiment, the dependent operations may need to be replayed, and the independent operations may be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of a processor may also be designed to capture instruction sequences for text string comparison operations.

[0264] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, a register may be available externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein may be implemented by circuitry within the processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, or a combination of dedicated and dynamically allocated physical registers. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packed data.

[0265] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1415 are provided below in conjunction with FIG. 14A and / or FIG. 14B . In at least one embodiment, some or all of the inference and / or training logic 1415 may be incorporated into the EXE block 2711 and other memory or registers, shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs shown in the EXE block 2711. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the EXE block 2711 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0266] 28 illustrates a deep learning application processor 2800 according to at least one embodiment. In at least one embodiment, the deep learning application processor 2800 uses instructions that, when executed by the deep learning application processor 2800, cause the deep learning application processor 2800 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2800 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 2800 performs a matrix multiplication operation, both "hard-wired" in hardware, as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2800 includes, without limitation, processing clusters 2810(1)-2810(12), inter-chip links (“ICLs”) 2820(1)-2820(12), inter-chip controllers (“ICCs”) 2830(1)-2830(2), high-bandwidth memory second generation (“HBM2”) 2840(1)-2840(4), memory controllers (“Mem Ctrlrs”) 2842(1)-2842(4), high-bandwidth memory physical layers (“HBM 28. The peripheral component interconnect express controller and direct memory access block ("PCIe Controller and DMA") 2870 includes a 16-lane peripheral component interconnect express port ("PCI Express x16") 2880, a management-controller central processing unit ("Management-Controller CPU") 2850, a serial peripheral interface, inter-integrated circuit, and general-purpose input / output block ("SPI, I2C, GPIO") 2860, a peripheral component interconnect express controller and direct memory access block ("PCIe Controller and DMA") 2870, and a 16-lane peripheral component interconnect express port ("PCI Express x16") 2880.

[0267] In at least one embodiment, processing cluster 2810 may perform deep learning operations, including inference or prediction operations, based on weight parameters calculated using one or more training techniques, including the techniques described herein. In at least one embodiment, each processing cluster 2810 may include any number and types of processors, without limitation. In at least one embodiment, deep learning application processor 2800 may include any number and types of processing clusters 2800. In at least one embodiment, inter-chip link 2820 is bidirectional. In at least one embodiment, inter-chip link 2820 and inter-chip controller 2830 enable multiple deep learning application processors 2800 to exchange information, including activation information resulting from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2800 may include any number and types (including zero) of ICLs 2820 and ICCs 2830.

[0268] In at least one embodiment, the HBM2 2840 provides a total of 32 Gigabytes (GB) of memory. Each HBM2 2840(i) is associated with both a memory controller 2842(i) and an HBM PHY 2844(i). In at least one embodiment, any number of HBM2 2840s may provide any type and total amount of high-bandwidth memory and may be associated with any number and types of memory controllers 2842 and HBM PHYs 2844 (including zero). In at least one embodiment, the SPI, I2C, GPIO 2860, PCIe controller and DMA 2870, and / or PCIe 2880 may be replaced with any number and types of blocks enabling any number and types of communication standards in any technically feasible manner.

[0269] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1415 are provided below in conjunction with FIG. 14A and / or FIG. 14B . In at least one embodiment, deep learning application processor 2800 is used to train a machine learning model, such as a neural network, to predict or infer information provided to deep learning application processor 2800. In at least one embodiment, deep learning application processor 2800 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by deep learning application processor 2800. In at least one embodiment, processor 2800 may be used to perform one or more neural network use cases described herein.

[0270] FIG. 29 is a block diagram of a neuromorphic processor 2900, according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2900 receives one or more inputs from sources external to the neuromorphic processor 2900. In at least one embodiment, these inputs may be sent to one or more neurons 2902 within the neuromorphic processor 2900. In at least one embodiment, the neurons 2902 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2900 may include, without limitation, thousands or millions of instances of neurons 2902, although any suitable number of neurons 2902 may be used. In at least one embodiment, each instance of a neuron 2902 may include a neuron input 2904 and a neuron output 2906. In at least one embodiment, the neuron 2902 may generate an output, which may be sent to an input of another instance of a neuron. For example, in at least one embodiment, neuron input 2904 and neuron output 2906 may be interconnected via synapse 2908 .

[0271] In at least one embodiment, neurons 2902 and synapses 2908 may be interconnected such that neuromorphic processor 2900 operates to process or analyze information received by neuromorphic processor 2900. In at least one embodiment, neuron 2902 may send an output pulse (or "fire" or "spike") when input received via neuron input 2904 exceeds a threshold. In at least one embodiment, neuron 2902 may sum or integrate signals received at neuron input 2904. For example, in at least one embodiment, neuron 2902 may be implemented as a leaky integrate-and-fire neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, neuron 2902 may generate an output (or "fire") using a transfer function such as a sigmoid function or a threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron input 2904 into a membrane potential and may apply a decay factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron input 2904 quickly enough to exceed a threshold (i.e., before the membrane potential decays too little to cause firing). In at least one embodiment, neuron 2902 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. Further, in at least one embodiment, neuron 2902 may include, without limitation, comparator circuitry or logic that generates an output spike at neuron 2906 when the result of applying the transfer function to neuron 2904 exceeds a threshold. In at least one embodiment, neuron 2902 may ignore previously received input information, for example, by resetting the membrane potential to 0 or another suitable default value, once it fires.In at least one embodiment, once the membrane potential is reset to zero, neuron 2902 may resume normal operation after a suitable period (or refractory period).

[0272] In at least one embodiment, neurons 2902 may be interconnected through synapses 2908. In at least one embodiment, synapses 2908 may operate to transmit a signal from an output of a first neuron 2902 to an input of a second neuron 2902. In at least one embodiment, neurons 2902 may transmit information through two or more instances of synapses 2908. In at least one embodiment, one or more instances of neuron outputs 2906 may be connected to instances of neuron inputs 2904 of the same neuron 2902 through instances of synapses 2908. In at least one embodiment, an instance of neuron 2902 that generates an output to be transmitted through an instance of synapse 2908 may be referred to as a “pre-synaptic neuron” with respect to that instance of synapse 2908. In at least one embodiment, an instance of neuron 2902 that receives an input to be transmitted through an instance of synapse 2908 may be referred to as a “post-synaptic neuron” with respect to that instance of synapse 2908. In at least one embodiment, an instance of neuron 2902 may receive input from one or more instances of synapse 2908 and may send output through one or more instances of synapse 2908, so that a single instance of neuron 2902 may therefore be both a “pre-synaptic neuron” and a “post-synaptic neuron” with respect to various instances of synapse 2908.

[0273] In at least one embodiment, neurons 2902 may be organized into one or more layers. Each instance of a neuron 2902 may have one neuron output 2906 that can fan out to one or more neuron inputs 2904 through one or more synapses 2908. In at least one embodiment, a neuron output 2906 of a neuron 2902 in a first layer 2910 may be connected to a neuron input 2904 of a neuron 2902 in a second layer 2912. In at least one embodiment, layer 2910 may be referred to as a "feed-forward" layer. In at least one embodiment, each instance of a neuron 2902 in an instance of a first layer 2910 may fan out to each instance of a neuron 2902 in a second layer 2912. In at least one embodiment, first layer 2910 may be referred to as a "fully connected feed-forward layer." In at least one embodiment, each instance of neuron 2902 in the second layer 2912 may fan out to fewer than all instances of neuron 2902 in the third layer 2914. In at least one embodiment, the second layer 2912 may be referred to as a "sparsely connected feed-forward layer." In at least one embodiment, the neurons 2902 in the second layer 2912 may fan out to neurons 2902 in multiple other layers, including neurons 2902 in the same second layer 2912. In at least one embodiment, the second layer 2912 may be referred to as a "recurrent layer." The neuromorphic processor 2900 may include any suitable combination of recurrent and feed-forward layers, including, without limitation, both sparsely connected feed-forward layers and fully connected feed-forward layers.

[0274] In at least one embodiment, neuromorphic processor 2900 may include, without limitation, a reconfigurable interconnect architecture or dedicated hardwired interconnects for connecting synapses 2908 to neurons 2902. In at least one embodiment, neuromorphic processor 2900 may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons 2902 as needed based on the neural network topology and the fan-in / fan-out of the neurons. For example, in at least one embodiment, synapses 2908 may be connected to neurons 2902 using an interconnect fabric, such as a network-on-chip, or using dedicated connections. In at least one embodiment, synaptic interconnects and their components may be implemented using circuitry or logic.

[0275] Figure 30 is a block diagram of a graphics processor 3000, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 3000 communicates with its registers via a memory-mapped I / O interface using commands placed in memory. In at least one embodiment, the graphics processor 3000 includes a memory interface 3014 for accessing memory. In at least one embodiment, the memory interface 3014 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or system memory.

[0276] In at least one embodiment, graphics processor 3000 also includes a display controller 3002 for driving display output data to display device 3020. In at least one embodiment, display controller 3002 includes one or more overlapping planes for display device 3020 and hardware for compositing multi-layered video or user interface elements. In at least one embodiment, display device 3020 can be an internal or external display device. In at least one embodiment, display device 3020 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, graphics processor 3000 includes a video codec engine 3006 for encoding, decoding, or transcoding media to, from, or between one or more media coding formats, including, but not limited to, Motion Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264 / MPEG-4 AVC, and Joint Photographic Experts Group (JPEG) formats such as Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and JPEG, and Motion JPEG (MJPEG) formats.

[0277] In at least one embodiment, graphics processor 3000 includes a block image transfer (BLIT) engine 3004 for performing two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in at least one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 3010. In at least one embodiment, GPE 3010 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0278] In at least one embodiment, GPE 3010 includes a 3D pipeline 3012 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 3012 includes programmable and fixed function elements that perform various tasks and / or spawn execution threads for 3D / media subsystem 3015. While 3D pipeline 3012 can be used to perform media operations, in at least one embodiment, GPE 3010 also includes a media pipeline 3016 that is used to perform media operations such as video post-processing and image enhancement.

[0279] In at least one embodiment, media pipeline 3016 includes a fixed function or programmable logic unit for performing one or more specialized media operations, such as video decode acceleration, video deinterlacing, and encode acceleration, instead of or on behalf of video codec engine 3006. In at least one embodiment, media pipeline 3016 further includes a thread spawning unit for spawning threads for execution in 3D / media subsystem 3015. In at least one embodiment, the spawned threads perform computations for the media operations on one or more graphics execution units included in 3D / media subsystem 3015.

[0280] In at least one embodiment, the 3D / media subsystem 3015 includes logic for executing threads spawned by the 3D pipeline 3012 and the media pipeline 3016. In at least one embodiment, the 3D pipeline 3012 and the media pipeline 3016 send thread execution requests to the 3D / media subsystem 3015, which includes thread dispatch logic for arbitrating the various requests and dispatching them to available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing the 3D and media threads. In at least one embodiment, the 3D / media subsystem 3015 includes one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem 3015 also includes shared memory, including registers and addressable memory, for sharing data between threads and storing output data.

[0281] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1415 are provided below in conjunction with FIG. 14A and / or FIG. 14B . In at least one embodiment, some or all of the inference and / or training logic 1415 may be incorporated into graphics processor 3000. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs embodied in 3D pipeline 3012. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in FIG. 14A or FIG. 14B . In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of graphics processor 3000 for executing one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0282] Figure 31 is a block diagram of a graphics processing engine 3110 of a graphics processor according to at least one embodiment. In at least one embodiment, the graphics processing engine (GPE) 3110 is a version of the GPE 3010 shown in Figure 30. In at least one embodiment, the media pipeline 3016 is optional and may not be explicitly included within the GPE 3110. In at least one embodiment, separate media and / or image processors are coupled to the GPE 3110.

[0283] In at least one embodiment, the GPE 3110 is coupled to or includes a command streamer 3103, which provides a command stream to the 3D pipeline 3012 and / or the media pipeline 3016. In at least one embodiment, the command streamer 3103 is coupled to memory, which may be system memory or one or more of an internal cache memory and a shared cache memory. In at least one embodiment, the command streamer 3103 receives commands from memory and sends the commands to the 3D pipeline 3012 and / or the media pipeline 3016. In at least one embodiment, the commands are instructions, primitives, or micro-operations fetched from a ring buffer, which stores commands for the 3D pipeline 3012 and the media pipeline 3016. In at least one embodiment, the ring buffer further includes a batch command buffer that stores batches of commands. In at least one embodiment, commands for 3D pipeline 3012 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 3012 and / or image data and memory objects for media pipeline 3016. In at least one embodiment, 3D pipeline 3012 and media pipeline 3016 process commands and data by performing operations or dispatching one or more threads of execution to graphics core array 3114. In at least one embodiment, graphics core array 3114 includes one or more blocks of graphics cores (e.g., graphics core 3115A, graphics core 3115B), each block including one or more graphics cores.In at least one embodiment, each graphics core includes a set of graphics execution resources including general-purpose and graphics-specific execution logic for performing graphics and compute operations, as well as fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic, including inference and / or training logic 1415 of FIGS. 14A and 14B.

[0284] In at least one embodiment, 3D pipeline 3012 includes fixed-function and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to graphics core array 3114. In at least one embodiment, graphics core array 3114 provides a unified block of execution resources for use in processing shader programs. In at least one embodiment, multipurpose execution logic (e.g., execution units) within graphics cores 3115A-3115B of graphics core array 3114 includes support for various 3D API shader languages ​​and can execute multiple concurrent threads of execution associated with multiple shaders.

[0285] In at least one embodiment, the graphics core array 3114 also includes execution logic for performing media functions, such as video and / or image processing. In at least one embodiment, the execution units further include general-purpose logic that is programmable to perform parallel general-purpose computing operations in addition to graphics processing operations.

[0286] In at least one embodiment, output data generated by threads executing on graphics core array 3114 may output data to memory in unified return buffer (URB) 3118. URB 3118 may store data for multiple threads. In at least one embodiment, URB 3118 may be used to transmit data between different threads executing on graphics core array 3114. In at least one embodiment, URB 3118 may also be used for synchronization between threads on graphics core array 3114 and fixed function logic in shared function logic 3120.

[0287] In at least one embodiment, graphics core array 3114 is scalable, such that graphics core array 3114 includes a variable number of graphics cores, each having a variable number of execution units based on the desired power and performance level of GPE 3110. In at least one embodiment, execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed.

[0288] In at least one embodiment, graphics core array 3114 is coupled to shared function logic 3120, which includes multiple resources shared among the graphics cores of graphics core array 3114. In at least one embodiment, the shared functions performed by shared function logic 3120 are embodied in hardware logic units that provide dedicated complementary functions to graphics core array 3114. In at least one embodiment, shared function logic 3120 includes, but is not limited to, sampler 3121, math 3122, and inter-thread communication (ITC) 3123 logic. In at least one embodiment, one or more caches 3125 are included in or coupled to shared function logic 3120.

[0289] In at least one embodiment, shared functions are used when there is insufficient demand for dedicated functions to be included within graphics core array 3114. In at least one embodiment, a single instantiation of the dedicated functions is used in shared function logic 3120 and shared among other execution resources within graphics core array 3114. In at least one embodiment, certain shared functions within shared function logic 3120 that are used only by graphics core array 3114 may be included within shared function logic 3116 within graphics core array 3114. In at least one embodiment, shared function logic 3116 within graphics core array 3114 may include some or all of the logic within shared function logic 3120. In at least one embodiment, all logic elements within shared function logic 3120 may be duplicated within shared function logic 3116 of graphics core array 3114. In at least one embodiment, shared function logic 3120 is omitted in favor of shared function logic 3116 within graphics core array 3114.

[0290] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1415 are provided below in conjunction with FIG. 14A and / or FIG. 14B. In at least one embodiment, some or all of the inference and / or training logic 1415 may be incorporated into graphics processor 3110. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of ALUs embodied in 3D pipeline 3012, graphics core 3115A, shared function logic 3116, graphics core 3115B, shared function logic 3120, or other logic of FIG. 31. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in FIG. 14A or FIG. 14B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 3110 for executing one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0291] FIG. 32 is a block diagram of hardware logic for a graphics processor core 3200 according to at least one embodiment described herein. In at least one embodiment, graphics processor core 3200 is included within a graphics core array. In at least one embodiment, graphics processor core 3200, sometimes referred to as a core slice, may be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 3200 is an example of a single graphics core slice, and the graphics processors described herein may include multiple graphics core slices based on a target power and performance envelope. In at least one embodiment, each graphics core 3200 may include a fixed function block 3230 coupled to multiple sub-cores 3201A-3201F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed-function logic.

[0292] In at least one embodiment, fixed function block 3230 includes a geometry / fixed function pipeline 3236 that may be shared by all sub-cores within graphics processor 3200, e.g., in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry / fixed function pipeline 3236 includes a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0293] In at least one embodiment, fixed function block 3230 also includes graphics SoC interface 3237, graphics microcontroller 3238, and media pipeline 3239. Graphics SoC interface 3237 provides an interface between graphics core 3200 and other processor cores within the system-on-chip integrated circuit. In at least one embodiment, graphics microcontroller 3238 is a programmable sub-processor configurable to manage various functions of graphics processor 3200, including thread dispatch, scheduling, and preemption. In at least one embodiment, media pipeline 3239 includes logic to facilitate decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 3239 implements media operations via requests to compute logic or sampling logic within sub-cores 3201-3201F.

[0294] In at least one embodiment, SoC interface 3237 enables graphics core 3200 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as shared last-level cache memory, system RAM, and / or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface 3237 also enables communication with fixed-function devices within the SoC, such as a camera imaging pipeline, and enables and / or implements global memory atomics that can be shared between graphics core 3200 and a CPU within the SoC. In at least one embodiment, SoC interface 3237 can also implement power management controls for graphics core 3200 and enable interfacing between the graphics core 3200 clock domain and other clock domains within the SoC. In at least one embodiment, SoC interface 3237 enables receiving command buffers from a command streamer and global thread dispatcher configured to provide commands and instructions to each of one or more graphics cores in the graphics processor. In at least one embodiment, the commands and instructions may be dispatched to a media pipeline 3239 when media operations are performed, or to a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 3236, geometry and fixed function pipeline 3214) when graphics processing operations are performed.

[0295] In at least one embodiment, graphics microcontroller 3238 can be configured to perform various scheduling and management tasks for graphics core 3200. In at least one embodiment, graphics microcontroller 3238 can execute graphics and / or compute workload scheduling on various graphics parallel engines in execution unit (EU) arrays 3202A-3202F, 3204A-3204F within sub-cores 3201A-3201F. In at least one embodiment, host software running on a CPU core of an SoC including graphics core 3200 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, scheduling operations include determining which workload to run next, submitting the workload to a command streamer, preempting existing workloads running on the engines, managing the progress of the workload, and notifying host software when the workload is complete. In at least one embodiment, graphics microcontroller 3238 can also facilitate low power or idle states for graphics core 3200, providing graphics core 3200 with the ability to save and restore registers within graphics core 3200 across low power state transitions, independent of the operating system and / or graphics driver software on the system.

[0296] In at least one embodiment, graphics core 3200 may have up to N modular sub-cores, more or less than the illustrated sub-cores 3201A-3201F. For each set of N sub-cores, in at least one embodiment, graphics core 3200 may also include shared function logic 3210, shared and / or cache memory 3212, geometry / fixed function pipeline 3214, and additional fixed function logic 3216 for accelerating various graphics and compute processing operations. In at least one embodiment, shared function logic 3210 may include logic units (e.g., sampler, math, and / or inter-thread communication logic) that can be shared by each of the N sub-cores in graphics core 3200. Shared and / or cache memory 3212 may be a last-level cache for the N sub-cores 3210A-3210F in graphics core 3200 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 3214 may be included in place of geometry / fixed function pipeline 3236 in fixed function block 3230 and may include the same or similar logical units.

[0297] In at least one embodiment, graphics core 3200 includes additional fixed-function logic 3216, which can include various fixed-function acceleration logic for use by graphics core 3200. In at least one embodiment, additional fixed-function logic 3216 includes an additional geometry pipeline for use with position-only shading. For position-only shading, there are at least two geometry pipelines: a full geometry pipeline in geometry / fixed-function pipeline 3216, 3236, and a cull pipeline, which is an additional geometry pipeline that may be included in additional fixed-function logic 3216. In at least one embodiment, the cull pipeline is a scaled-down version of the full geometry pipeline. In at least one embodiment, the full pipeline and the cull pipeline can run different instances of an application, each with a separate context. In at least one embodiment, position-only shading can hide long cull runs of truncated triangles, allowing shading to complete earlier in some instances. For example, in at least one embodiment, because the cull pipeline fetches and shades vertex position attributes without rasterizing and rendering pixels to the frame buffer, the cull pipeline logic in the additional fixed-function logic 3216 can execute position shaders in parallel with the main application, producing critical results overall faster than the full pipeline. In at least one embodiment, the cull pipeline can use the produced critical results to compute visibility information for all triangles, regardless of whether they are culled. In at least one embodiment, the full pipeline (which may be referred to in this instance as the replay pipeline) can consume the visibility information and shade only the visible triangles, skipping over the culled triangles, which are ultimately passed to the rasterization phase.

[0298] In at least one embodiment, the additional fixed function logic 3216 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementations involving machine learning training or inference optimization.

[0299] In at least one embodiment, each graphics sub-core 3201A-3201F includes a set of execution resources that may be used to perform graphics operations, media operations, and compute operations in response to requests from a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-cores 3201A-3201F include a plurality of EU arrays 3202A-3202F, 3204A-3204F, thread dispatch and inter-thread communication (TD / IC) logic 3203A-3203F, 3D (e.g., texture) samplers 3205A-3205F, media samplers 3206A-3206F, shader processors 3207A-3207F, and shared local memory (SLM) 3208A-3208F. EU arrays 3202A-3202F, 3204A-3204F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logical operations in service of graphics, media, or compute operations, including graphics, media, or compute shader programs. In at least one embodiment, TD / IC logic 3203A-3203F performs local thread dispatch and thread control operations for the execution units within a sub-core and facilitates communication between threads running on the sub-core's execution units. In at least one embodiment, 3D samplers 3205A-3205F can read textures or other 3D graphics-related data into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sample state and texture format associated with a given texture. In at least one embodiment, media samplers 3206A-3206F can perform similar read operations based on the type and format associated with the media data.In at least one embodiment, each graphics sub-core 3201A-3201F can alternatively include an integrated 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 3201A-3201F can utilize shared local memory 3208A-3208F within each sub-core to allow threads executing within a thread group to execute using a common pool of on-chip memory.

[0300] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1415 are provided below in conjunction with FIG. 14A and / or FIG. 14B. In at least one embodiment, some or all of the inference and / or training logic 1415 may be incorporated into the graphics processor 3210. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more of the ALUs embodied in the 3D pipeline 3210, the graphics microcontroller 3238, the geometry and fixed function pipelines 3214 and 3236, or other logic of FIG. 31. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in FIG. 14A or FIG. 14B. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of graphics processor 3200 for executing one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0301] 33A-33B illustrate thread execution logic 3300 including an array of processing elements of a graphics processor core, according to at least one embodiment. Figure 33A illustrates at least one embodiment in which thread execution logic 3300 is used. Figure 33B illustrates example internal details of an execution unit, according to at least one embodiment.

[0302] 33A , in at least one embodiment, thread execution logic 3300 includes a shader processor 3302, a thread dispatcher 3304, an instruction cache 3306, a scalable execution unit array including multiple execution units 3308A-3308N, a sampler 3310, a data cache 3312, and a data port 3314. In at least one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any of execution units 3308A, 3308B, 3308C, 3308D-3308N-1, and 3308N) based on, for example, the computational requirements of a workload. In at least one embodiment, the scalable execution units are interconnected via an interconnect fabric that links to each of the execution units. In at least one embodiment, thread execution logic 3300 includes one or more connections to memory, such as system memory or cache memory, via one or more of instruction cache 3306, data port 3314, sampler 3310, and execution units 3308A-3308N. In at least one embodiment, each execution unit (e.g., 3308A) is a standalone, programmable, general-purpose computational unit capable of executing multiple simultaneous hardware threads, processing multiple data elements in parallel per thread. In at least one embodiment, the array of execution units 3308A-3308N is scalable to include any number of individual execution units.

[0303] In at least one embodiment, the execution units 3308A-3308N are primarily used to execute shader programs. In at least one embodiment, the shader processor 3302 processes various shader programs and can dispatch execution threads associated with the shader programs via the thread dispatcher 3304. In at least one embodiment, the thread dispatcher 3304 includes logic for arbitrating thread initiation requests from the graphics and media pipelines and instantiating the requested threads on one or more of the execution units 3308A-3308N. For example, in at least one embodiment, the geometry pipeline can dispatch a vertex shader, mosaic shader, or geometry shader to thread execution logic for processing. In at least one embodiment, the thread dispatcher 3304 can also handle run-time thread spawning requests from executing shader programs.

[0304] In at least one embodiment, the execution units 3308A-3308N support an instruction set that includes native support for many standard 3D graphics shader instructions, allowing shader programs from graphics libraries (e.g., Direct3D and OpenGL) to execute with minimal translation. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders). In at least one embodiment, each execution unit 3308A-3308N, including one or more arithmetic logic units (ALUs), can issue multiple single instruction, multiple data (SIMD) executions, allowing for multithreaded operation and an efficient execution environment despite high memory access latency. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. In at least one embodiment, execution is issued multiple times per clock to a pipeline capable of performing integer operations, single- and double-precision floating-point operations, SIMD branch performance, logical operations, transcendental operations, and various other operations. In at least one embodiment, while waiting for data from memory or one of the shared functions, subordinate logic within the execution units 3308A-3308N puts the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is asleep, hardware resources may be dedicated to processing other threads. For example, in at least one embodiment, during a delay associated with a vertex shader operation, the execution unit may execute another type of shader program, including a pixel shader, a fragment shader, or a different vertex shader.

[0305] In at least one embodiment, each of execution units 3308A-3308N operates on an array of data elements. In at least one embodiment, the number of data elements is the "execution size," or the number of channels for an instruction. In at least one embodiment, an execution channel is a logical unit of execution related to data element access, masking, and flow control within an instruction. In at least one embodiment, the number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In at least one embodiment, execution units 3308A-3308N may support integer and floating-point data types.

[0306] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements may be stored in registers as packed data types, and the execution unit processes the various elements based on the data size of the elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit packed data elements (quad-word (QW) sized data elements), eight separate 32-bit packed data elements (double-word (DW) sized data elements), sixteen separate 16-bit packed data elements (word (W) sized data elements), or thirty-two separate 8-bit data elements (byte (B) sized data elements). However, in at least one embodiment, different vector widths and register sizes are contemplated.

[0307] In at least one embodiment, one or more execution units can be combined into fused execution units 3309A-3309N with thread control logic (3307A-3307N) common to the fused EUs. In at least one embodiment, multiple EUs can be fused into EU groups. In at least one embodiment, each EU in a fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary depending on the embodiment. In at least one embodiment, various SIMD widths can be executed per EU, including, but not limited to, SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 3309A-3309N includes at least two execution units. For example, in at least one embodiment, the fused execution unit 3309A includes a first EU 3308A, a second EU 3308B, and thread control logic 3307A common to the first EU 3308A and the second EU 3308B. In at least one embodiment, thread control logic 3307A controls threads executing in fused graphics execution unit 3309A, allowing each EU in fused execution units 3309A-3309N to execute using a common instruction pointer register.

[0308] In at least one embodiment, one or more internal instruction caches (e.g., 3306) are included in the thread execution logic 3300 for caching thread instructions for the execution units. In at least one embodiment, one or more data caches (e.g., 3312) are included for caching thread data during thread execution. In at least one embodiment, a sampler 3310 is included for performing texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, the sampler 3310 includes special texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

[0309] During execution, in at least one embodiment, the graphics and media pipeline sends thread start requests to the thread execution logic 3300 via thread spawning and dispatch logic. In at least one embodiment, once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 3302 is invoked to further compute output information and write the results to an output surface (e.g., a color buffer, a depth buffer, a stencil buffer, etc.). In at least one embodiment, the pixel shader or fragment shader calculates values ​​for various vertex attributes that are to be interpolated between the rasterized objects. In at least one embodiment, the pixel processor logic within the shader processor 3302 then executes a pixel shader program or fragment shader program with an application programming interface (API). In at least one embodiment, to execute a shader program, shader processor 3302 dispatches threads to execution units (e.g., 3308A) via thread dispatcher 3304. In at least one embodiment, shader processor 3302 accesses texture data from texture maps stored in memory using texture sampling logic in sampler 3310. In at least one embodiment, pixel color data for each geometry fragment is computed by arithmetic operations on the texture data and input geometry data, or one or more pixels are truncated so that they are not further processed.

[0310] In at least one embodiment, data port 3314 provides a memory access mechanism for thread execution logic 3300 to output processed data to memory for further processing in the graphics processor output pipeline. In at least one embodiment, data port 3314 includes or is coupled to one or more cache memories (e.g., data cache 3312) to cache data for memory access via the data port.

[0311] As shown in FIG. 33B , in at least one embodiment, graphics execution unit 3308 may include an instruction fetch unit 3337, a general register file array (GRF) 3324, an architectural register file array (ARF) 3326, a thread arbiter 3322, a send unit 3330, a branch unit 3332, a set of SIMD floating-point units (FPUs) 3334, and, in at least one embodiment, a set of dedicated integer SIMD ALUs 3335. In at least one embodiment, GRF 3324 and ARF 3326 include a general register file and a set of architectural register files associated with each concurrent hardware thread that may be active in graphics execution unit 3308. In at least one embodiment, per-thread architectural state is maintained in ARF 3326, and data used during thread execution is stored in GRF 3324. In at least one embodiment, the execution state of each thread, including the instruction pointer for each thread, may be kept in thread-specific registers in ARF 3326.

[0312] In at least one embodiment, the graphics execution unit 3308 has an architecture that is a combination of simultaneous multi-threading (SMT) and fine-grained interleaved multi-threading (IMT). In at least one embodiment, the architecture has a modular organization that can be tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, where the resources of the execution unit are divided across the logic used to execute multiple simultaneous threads.

[0313] In at least one embodiment, the graphics execution unit 3308 can jointly issue multiple instructions, which may each be a different instruction. In at least one embodiment, the thread arbiter 3322 of a graphics execution unit thread 3308 can dispatch an instruction to one of the send unit 3330, the branch unit 3342, or the SIMD FPU 3334 for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers in the GRF 3324, where each register can store 32 bytes accessible as a vector of SIMD8 elements of 32-bit data elements. In at least one embodiment, each execution unit thread can access 4 Kbytes in the GRF 3324, although embodiments are not limited in this manner and more or less resources may be provided in other embodiments. In at least one embodiment, up to seven threads can execute simultaneously, although the number of threads per execution unit can also vary depending on the embodiment. In at least one embodiment, where seven threads can access 4 Kbytes, the GRF 3324 can store a total of 28 Kbytes. In at least one embodiment, flexible addressing modes allow multiple registers to be addressed together to build wider registers or to represent strided rectangular block data structures.

[0314] In at least one embodiment, memory operations, sampler operations, and other long latency system communications are dispatched via "send" instructions executed by message passing send unit 3330. In at least one embodiment, branch instructions are dispatched to a dedicated branch unit 3332 to facilitate SIMD divergence and eventual convergence.

[0315] In at least one embodiment, the graphics execution unit 3308 includes one or more SIMD floating-point units (FPUs) 3334 for performing floating-point operations. In at least one embodiment, the FPUs 3334 also support integer calculations. In at least one embodiment, the FPUs 3334 can SIMD up to M 32-bit floating-point (or integer) operations or up to 2M 16-bit integer or 16-bit floating-point operations. In at least one embodiment, at least one of the FPUs provides extended mathematical functionality to support high-throughput transcendental functions and double-precision 64-bit floating-point. In at least one embodiment, a set of 8-bit integer SIMD ALUs 3335 are also present and may be specifically optimized to perform operations related to machine learning calculations.

[0316] In at least one embodiment, an array of multiple instances of graphics execution unit 3308 may be instantiated in a graphics sub-core group (e.g., a sub-slice). In at least one embodiment, execution unit 3308 can execute instructions across multiple execution channels. In at least one embodiment, each thread executing in a graphics execution unit 3308 executes on a different channel.

[0317] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1415 are provided below in conjunction with FIG. 14A and / or FIG. 14B . In at least one embodiment, some or all of the inference and / or training logic 1415 may be incorporated into the execution logic 3300. Furthermore, in at least one embodiment, the inference and / or training operations described herein may be performed using logic other than that shown in FIG. 14A or FIG. 14B . In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of the execution logic 3300 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0318] FIG. 34 illustrates a parallel processing unit (“PPU”) 3400 according to at least one embodiment. In at least one embodiment, the PPU 3400 comprises machine-readable code that, when executed by the PPU 3400, causes the PPU 3400 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the PPU 3400 is a multi-threaded processor that is implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) in parallel on multiple threads. In at least one embodiment, a thread refers to a thread of execution, which is an instantiation of a set of instructions configured to be executed by the PPU 3400. In at least one embodiment, PPU 3400 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as a liquid crystal display ("LCD") device. In at least one embodiment, PPU 3400 is utilized to perform computations, such as linear algebra and machine learning operations. FIG. 34 depicts an example parallel processor for illustrative purposes only and should be construed as a non-limiting example of a processor architecture contemplated within the scope of the present disclosure, and it should be understood that any suitable processor may be utilized in addition to and / or to replace the same.

[0319] In at least one embodiment, one or more PPUs 3400 are configured to accelerate any High Performance Computing ("HPC"), data center, and machine learning application. In at least one embodiment, the PPUs 3400 are configured to accelerate deep learning systems and applications, including, but not limited to, the following examples: autonomous vehicle platforms, deep learning, high-precision speech, image, and text recognition systems, intelligent video analytics, molecular simulation, drug discovery, disease diagnostics, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimization, and personalized user recommendations.

[0320] In at least one embodiment, PPU 3400 includes, without limitation, an input / output ("I / O") unit 3406, a front-end unit 3410, a scheduler unit 3412, a work distribution unit 3414, a hub 3416, a crossbar ("Xbar") 3420, one or more general processing clusters ("GPCs") 3418, and one or more partition units ("memory partition units") 3422. In at least one embodiment, PPU 3400 is connected to a host processor or other PPUs 3400 via one or more high-speed GPU interconnects ("GPU interconnects") 3408. In at least one embodiment, PPU 3400 is connected to a host processor or other peripheral devices via interconnect 3402. In at least one embodiment, PPU 3400 is connected to local memory comprising one or more memory devices ("memory") 3404. In at least one embodiment, memory device 3404 includes, without limitation, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices may be configured and / or configurable as a high bandwidth memory ("HBM") subsystem with multiple DRAM dies stacked within each device.

[0321] In at least one embodiment, high-speed GPU interconnect 3408 may refer to a wire-based, multi-lane communication link used by a system to scale, including one or more PPUs 3400 in combination with one or more central processing units (“CPUs”), supporting cache coherence between the PPUs 3400 and the CPUs, and CPU mastering. In at least one embodiment, data and / or commands are transmitted by high-speed GPU interconnect 3408 through hub 3416 to and from other units of PPU 3400, such as one or more copy engines, video encoders, video decoders, power management units, and other components that may not be explicitly shown in FIG. 34 .

[0322] In at least one embodiment, I / O unit 3406 is configured to receive and send communications (e.g., commands, data) from a host processor (not shown in FIG. 34 ) via system bus 3402. In at least one embodiment, I / O unit 3406 communicates with the host processor directly via system bus 3402 or through one or more intermediate devices, such as memory bridges. In at least one embodiment, I / O unit 3406 may communicate with one or more other processors, such as one or more of PPUs 3400, via system bus 3402. In at least one embodiment, I / O unit 3406 implements a Peripheral Component Interconnect Express (“PCIe”) interface to enable communication over a PCIe bus. In at least one embodiment, I / O unit 3406 implements an interface for communicating with external devices.

[0323] In at least one embodiment, I / O unit 3406 decodes packets received via system bus 3402. In at least one embodiment, at least some of the packets represent commands configured to cause PPU 3400 to perform various operations. In at least one embodiment, I / O unit 3406 transmits the decoded commands to various other units of PPU 3400 specified by the commands. In at least one embodiment, the commands are transmitted to front end unit 3410 and / or to hub 3416 or other units of PPU 3400, such as one or more copy engines, video encoders, video decoders, or power management units (not explicitly shown in FIG. 34 ). In at least one embodiment, I / O unit 3406 is configured to route communications between various logical units of PPU 3400.

[0324] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 3400 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory accessible (e.g., writeable / readable) by both the host processor and the PPU 3400, and the post interface unit may be configured to access the buffer in system memory connected to the system bus 3402 via memory requests sent by the I / O unit 3406 over the system bus 3402. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer to the start of the command stream to the PPU 3400, whereupon the front end unit 3410 receives the pointer to one or more command streams and manages the one or more command streams, reading commands from the command streams and forwarding the commands to various units of the PPU 3400.

[0325] In at least one embodiment, front end unit 3410 is coupled to scheduler unit 3412, which configures various GPCs 3418 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 3412 is configured to track state information related to the various tasks managed by scheduler unit 3412, where the state information may indicate which GPC 3418 a task is assigned to, whether the task is active or inactive, the priority level associated with the task, etc. In at least one embodiment, scheduler unit 3412 manages the execution of multiple tasks on one or more of GPCs 3418.

[0326] In at least one embodiment, scheduler unit 3412 is coupled to work distribution unit 3414, which is configured to dispatch tasks for execution on GPCs 3418. In at least one embodiment, work distribution unit 3414 tracks the number of scheduled tasks received from scheduler unit 3412, and work distribution unit 3414 manages a pending task pool and an active task pool for each of GPCs 3418. In at least one embodiment, the pending task pool comprises a number of slots (e.g., 32 slots) containing tasks assigned to be processed by a particular GPC 3418, and the active task pool comprises a number of slots (e.g., 4 slots) for tasks being actively processed by the GPC 3418, such that when one of the GPCs 3418 completes execution of a task, the task is removed from the active task pool of the GPC 3418, and one of the other tasks from the pending task pool is selected and scheduled to run on the GPC 3418. In at least one embodiment, when an active task is idle on GPC3418, such as while waiting for a data dependency to be resolved, the active task is removed from GPC3418 and returned to the pending task pool, while another task from the pending task pool is selected and scheduled to run on GPC3418.

[0327] In at least one embodiment, work distribution unit 3414 communicates with one or more GPCs 3418 via X-bar 3420. In at least one embodiment, X-bar 3420 is an interconnection network that couples many of the units of PPU 3400 to other units of PPU 3400 and can be configured to couple work distribution unit 3414 to a particular GPC 3418. In at least one embodiment, one or more other units of PPU 3400 may also be connected to X-bar 3420 via hub 3416.

[0328] In at least one embodiment, tasks are managed by scheduler unit 3412 and dispatched by work distribution unit 3414 to one of GPCs 3418. GPC 3418 is configured to process the task and produce a result. In at least one embodiment, the result may be consumed by other tasks within GPC 3418, routed to a different GPC 3418 via Xbar 3420, or stored in memory 3404. In at least one embodiment, the result may be written to memory 3404 via partition unit 3422, which implements a memory interface for reading and writing data to / from memory 3404. In at least one embodiment, the result may be sent to another PPU 3404 or a CPU via high-speed GPU interconnect 3408. In at least one embodiment, PPU 3400 includes U partition units 3422, equal to, but not limited to, the number of separate individual memory devices 3404 coupled to PPU 3400. In at least one embodiment, partition unit 3422 is described in further detail below in conjunction with FIG.

[0329] In at least one embodiment, the host processor executes a driver kernel that implements an application programming interface (API) that enables one or more applications running on the host processor to schedule operations for execution on the PPU 3400. In at least one embodiment, multiple compute applications are executed simultaneously by the PPU 3400, which provides isolation, quality of service (QoS), and independent address spaces for the multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause the driver kernel to generate one or more tasks for execution by the PPU 3400, and the driver kernel outputs the tasks to one or more streams that are processed by the PPU 3400. In at least one embodiment, each task comprises one or more groups of related threads, which may be referred to as warps. In at least one embodiment, a warp comprises multiple related threads (e.g., 32 threads) that can execute in parallel. In at least one embodiment, cooperating threads may refer to multiple threads that contain instructions for performing tasks and exchange data via shared memory. In at least one embodiment, threads and cooperating threads are described in further detail in accordance with at least one embodiment in conjunction with FIG. 36.

[0330] Inference and / or training logic 1415 is used to perform inference and / or training operations associated with one or more embodiments. More details regarding the inference and / or training logic 1415 are provided below in conjunction with FIG. 14A and / or FIG. 14B. In at least one embodiment, the deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to the PPU 3400. In at least one embodiment, the deep learning application processor 3400 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the PPU 3400. In at least one embodiment, the PPU 3400 may be used to perform one or more neural network use cases described herein.

[0331] FIG. 35 illustrates a general purpose processing cluster (“GPC”) 3500 according to at least one embodiment. In at least one embodiment, GPC 3500 is GPC 3418 of FIG. 34. In at least one embodiment, each GPC 3500 includes several hardware units for processing tasks, including, without limitation, a pipeline manager 3502, a pre-raster operations unit (“PROP”) 3504, a raster engine 3508, a work distribution crossbar (“WDX”) 3516, a memory management unit (“MMU”) 3518, one or more data processing clusters (“DPC”) 3506, and any suitable combination of parts.

[0332] In at least one embodiment, operation of the GPC 3500 is controlled by a pipeline manager 3502. In at least one embodiment, the pipeline manager 3502 manages the configuration of one or more DPCs 3506 to process tasks allocated to the GPC 3500. In at least one embodiment, the pipeline manager 3502 configures at least one of the one or more DPCs 3506 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 3506 is configured to execute vertex shader programs on a programmable streaming multi-processor (“SM”) 3514. In at least one embodiment, pipeline manager 3502 is configured to route packets received from the work distribution unit to the appropriate logical unit within GPC 3500, where some packets may be routed to a fixed function hardware unit of PROP 3504 and / or Raster Engine 3508, and other packets may be routed to DPC 3506 for processing by Primitive Engine 3512 or SM 3514. In at least one embodiment, pipeline manager 3502 configures at least one of DPC 3506 to implement a neural network model and / or computing pipeline.

[0333] In at least one embodiment, the PROP unit 3504 is configured to route data generated by the raster engine 3508 and the DPC 3506 to a raster operation (ROP) unit of the partition unit 3922, which is described in more detail above in conjunction with FIG. 39. In at least one embodiment, the PROP unit 3504 is configured to perform color blending optimization, organize pixel data, perform address translation, and perform other operations. In at least one embodiment, the raster engine 3508 includes several fixed-function hardware units configured to perform various raster operations, which in at least one embodiment include, without limitation, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices, which are sent to a coarse raster engine to generate coverage information for the primitives (e.g., x,y coverage masks for tiles), and the output of the coarse raster engine is sent to a culling engine, which culls fragments associated with primitives that fail a z-test, and to a clipping engine, which clips fragments that are outside the view frustum. In at least one embodiment, fragments that pass clipping and culling are passed to a fine raster engine, which generates attributes for the pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of the raster engine 3508 includes fragments that may be processed by any suitable entity, such as by a fragment shader implemented in the DPC 3506.

[0334] In at least one embodiment, each DPC 3506 included in GPC 3500 includes, without limitation, an M-Pipe Controller (“MPC”) 3510, a Primitive Engine 3512, one or more SMs 3514, and any suitable combination thereof. In at least one embodiment, MPC 3510 controls the operation of DPC 3506, routing packets received from Pipeline Manager 3502 to appropriate units within DPC 3506. In at least one embodiment, packets associated with vertices are routed to Primitive Engine 3512, which is configured to fetch vertex attributes associated with the vertices from memory; in contrast, packets associated with shader programs may be sent to SM 3514.

[0335] In at least one embodiment, the SM3514 includes, without limitation, a programmable streaming processor configured to process tasks represented by several threads. In at least one embodiment, the SM3514 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular group of threads and implements a single instruction, multiple data (SIMD) architecture, where each thread within a group of threads (warp) is configured to process different data sets based on the same instruction set. In at least one embodiment, all threads within a thread group execute the same instructions. In at least one embodiment, the SM3514 implements a single instruction, multiple thread (SIMT) architecture, where each thread within a thread group is configured to process different data sets based on the same instruction set, but individual threads within a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained per warp to enable concur...

Claims

1. 1. A computer system comprising: one or more processors; a computer-readable memory storing executable instructions that cause the computer system to at least: Equipped with The computer system, when executed by the one or more processors, generating, from the three-dimensional point cloud of the object, a set of grasping poses that enable the robot to grasp the object, using a first neural network; determining an evaluation of each grasp pose in the set of grasp poses using a second neural network; and refining the individual grip poses in the set of grip poses based at least in part on gradients of the evaluations determined by the second neural network to generate the refined set of grip poses.

2. 2. The computer system of claim 1, The executable instructions, when executed by the one or more processors, cause the computer system to: selecting a particular gripping posture from the refined set of gripping postures based at least in part on an evaluation of the individual gripping postures in the set of gripping postures; causing the robot to grasp the object by executing a particular grasping pose with the robot.

3. 2. The computer system of claim 1, The executable instructions, when executed by the one or more processors, cause the computer system to: acquiring three-dimensional image information from a depth camera; generating a three-dimensional point cloud of the object from the three-dimensional image information; The computer system further comprises:

4. 2. The computer system of claim 1, wherein the executable instructions, when executed by the one or more processors, cause the computer system to refine a previously refined grasp pose based at least in part on a gradient of the previously refined grasp pose determined by the second neural network.

5. 2. The computer system of claim 1, wherein the first neural network is a variational autoencoder trained to map a partial point cloud of the object to a set of grasp poses of the object.

6. The computer system of claim 1 , wherein refining each grasping pose is achieved at least in part by applying rigid body constraints to the robot's gripper.

7. The computer system of claim 1 , wherein the second neural network evaluates each grasp pose in the set of grasp poses using a three-dimensional point cloud of the object.

8. The computer system of claim 1 , wherein the three-dimensional point cloud of the object is a point cloud of a portion of the object.

9. A computer-implemented method generating a three-dimensional point cloud of the object using the image data generated by the depth camera; providing the three-dimensional point cloud to a first neural network, the first neural network being trained to generate from the three-dimensional point cloud a first set of grasping poses that enable a robot to grasp an object; providing the first set of grasp poses and the three-dimensional point cloud to a second neural network, the second neural network being trained to determine an assessment of each grasp pose; and modifying the individual grip poses of the first set of grip poses using gradients of the evaluations produced by the second neural network to generate the second set of grip poses.

10. identifying a third set of gripping postures from the second set of gripping postures, each of which has an associated rating greater than a threshold; selecting a particular gripping posture from the third set of gripping postures based at least in part on the evaluation of each gripping posture in the third set of gripping postures; grasping the object by performing a specific grasping pose with the robot; 10. The method of claim 9, further comprising:

11. acquiring image information of the object, the image information including depth information for at least a portion of the object; determining a three-dimensional point cloud of at least a portion of the object from the image information; 10. The method of claim 9, further comprising:

12. 10. The method of claim 9, further comprising generating the third set of grip poses by modifying the second set of grip poses based at least in part on gradients generated by the second neural network for the second set of grip poses.

13. the first neural network is trained to map a partial point cloud of the object to the first set of grasp poses of the object; The method of claim 9 , wherein the second neural network is trained to generate an estimate of the probability of success of the grasp pose of the object.

14. The method of claim 9 , wherein individual grasp pose modifications are limited to less than the translation update amount.

15. The method of claim 9 , wherein the second neural network represents a derivative of grasp success based at least in part on the point cloud of the object and the grasp pose of the object.

16. The method of claim 9 , wherein the second neural network evaluates the grasp pose by extrapolating the positions of at least portions of the object not represented by the 3D point cloud.

17. A recordable medium having stored thereon a set of instructions, the set of instructions being executable by one or more processors to: generating, from the three-dimensional point cloud of the object, a set of grasping poses for grasping the object with a gripper of the robot using a first neural network; using a second neural network to determine an assessment of each grip pose in the set of grip poses; improving the success probability of the individual gripping postures in the set of gripping postures based at least in part on the gradient of the evaluation to generate the improved set of gripping postures; A recordable medium that causes the execution of the above.

18. The set of instructions is executed by the one or more processors: removing from the improved set of grasping poses poses that are predicted to be unsuccessful based at least in part on the evaluation; causing the robot to grasp the object by executing a particular grasping pose selected from the set of improved grasping poses; The recordable medium of claim 17 , further comprising:

19. 20. The recordable medium of claim 17, wherein the set of instructions causes the one or more processors to refine individual grip poses in the set of refined grip poses using gradients of the individual grip poses generated by the second neural network.

20. 20. The recordable medium of claim 17, wherein the first neural network is a variational autoencoder trained to map a partial point cloud of the object to a set of grasp poses for the object.

21. 20. The recordable medium of claim 17, wherein the second neural network is trained using both successful and unsuccessful grasping poses.

22. 20. The recordable medium of claim 17, wherein the second neural network uses the three-dimensional point cloud of the object and the individual grip poses in the set of grip poses to evaluate the likelihood of success of the individual grip poses.

23. one or more processors; memory storing executable instructions; a first neural network trained to generate a set of grasp poses for an object from a point cloud of the object; a second neural network trained to evaluate the success of each grasp posture within the set of grasp postures; a robot manipulator executing refined grip poses generated from the set of grip poses by refining each of the grip poses in the set of grip poses using gradients generated by a second neural network; A robot equipped with

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