Semiconductor device manufacturing method and semiconductor device

Abstract

To reduce manufacturing cost and improve characteristics.SOLUTION: A manufacturing method includes: disposing first and second semiconductor chips 21a, 21b on a front surface of a die pad part 41a1 of a main current lead frame 41a and performing wiring; encapsulating the main current lead frame 41a and first and second semiconductor chips 21a, 21b with an encapsulation raw material in a semi-cured state thereby forming a semi-cured unit, such that a terminal part 41a3 of the main current lead frame 41a protrudes and such that a rear surface of the die pad part 41a1 is exposed; and pressure-bonding a front surface of an insulating sheet 70 to the rear surface of the semi-cured unit to cover the rear surface of the die pad part 41a1 of the main current lead frame 41a. Such a manufacturing method allows attachment of the insulating sheet 70 without turning up the insulating sheet 70 and regardless of specifications of a molding die.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] The semiconductor device includes a power semiconductor chip, a control IC (Integrated Circuit), a die pad on which the semiconductor chip and the control IC are arranged, and an insulating sheet provided on the back surface of the die pad, and is sealed with a sealing member. The power semiconductor chip uses a switching element of a power device. The switching element is, for example, an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The control IC controls the drive of the power semiconductor chip. In this semiconductor device, heat generated from the power semiconductor chip and the control IC is dissipated from the insulating sheet via the die pad.

[0003] Such a semiconductor device is manufactured through the following process. First, a power semiconductor chip and electronic components are placed on a die pad, and the die pad is then placed on an insulating sheet that has been set in a mold beforehand. While pressing the die pad against the insulating sheet with a pressure pin, the mold is filled with encapsulating resin, the pressure pin is removed, and the encapsulating resin is allowed to solidify within the mold. The semiconductor device is obtained by removing the mold (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-123495 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the above-described manufacturing method of a semiconductor device, With a presser pin To press the die pad onto the insulating sheet, Presser pin As the distance from the die pad increases, curling occurs between the die pad and the insulating sheet. A semiconductor device sealed in this state may have poor heat dissipation performance, resulting in reduced reliability. Furthermore, the shape and size of the insulating sheet set in the mold must be changed according to the mold specifications. Therefore, the specifications of the insulating sheet must be reviewed for each mold. Furthermore, the transport mechanism for setting the insulating sheet in the mold is complex and expensive. This increases the manufacturing cost of the semiconductor device.

[0006] The present invention has been made in consideration of these points, and aims to provide a semiconductor device and a method for manufacturing the same that prevent a decrease in heat dissipation performance while suppressing an increase in manufacturing costs. [Means for solving the problem]

[0007] According to one aspect of the present invention, there are provided a preparation step of preparing a power semiconductor chip, a lead frame including a die pad portion and a terminal portion integrally connected to the die pad portion, and a semi-cured insulating sheet; a mounting step of arranging the power semiconductor chip on the front surface of the die pad portion and wiring it; a sealing step of forming a semi-cured unit by sealing the lead frame and the power semiconductor chip with a semi-cured sealing material, causing the terminal portion to protrude and exposing the back surface of the die pad portion; and a sealing step of forming a semi-cured unit by pressing the front surface of the insulating sheet against the back surface of the semi-cured unit and covering the back surface of the die pad portion. The semi-curing unit is pressed against the insulating sheet in a heated state. There is provided a method for manufacturing a semiconductor device, which includes a compression bonding step and a curing step of heating and curing the semi-curing unit and the insulating sheet.

[0008] According to one aspect of the present invention, there is provided a lead frame including a die pad portion and a terminal portion integrally connected to the die pad portion; a power semiconductor chip arranged on an upper surface of the die pad portion; a sealing member that protrudes the terminal portion and exposes a first back surface of the die pad portion to seal the lead frame and the power semiconductor chip, and has a second back surface that protrudes outward beyond the first back surface of the die pad portion; and a third back surface that is provided to cover the first back surface of the die pad portion exposed from the second back surface of the sealing member, and forms a step with respect to the second back surface of the sealing member, and the second back surface of the sealing member is connected to the third back surface. protrudes further outwards than A semiconductor device is provided, which comprises an insulating sheet, a heat sink provided on the second rear surface of the sealing member, and a thermal compound provided between the third rear surface of the insulating sheet and the heat sink, and is configured so that each of the two side portions of the insulating sheet is sandwiched between the sealing member via the thermal compound. [Effects of the Invention]

[0009] According to the disclosed technology, a decrease in heat dissipation performance is prevented while suppressing an increase in manufacturing costs, and a decrease in reliability of the semiconductor device is suppressed. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is an external view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment. [Figure 4] 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. [Figure 5] 3A to 3C are diagrams illustrating a mounting step of a semiconductor chip and an electronic component included in the manufacturing method of the semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are diagrams illustrating a sealing step included in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 7]4 is a vertical cross-sectional view of a semi-cured unit produced after sealing in the manufacturing method of the semiconductor device according to the first embodiment. FIG. [Figure 8] 10A and 10B are diagrams illustrating pressure bonding of a semi-cured unit to an insulating sheet, which is included in the method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] 1 is a plan view of a semiconductor device to which a heat sink according to a first embodiment is attached; [Figure 10] 1 is a longitudinal sectional view (part 1) of a semiconductor device to which a heat sink according to a first embodiment is attached; [Figure 11] 1 is a longitudinal sectional view (part 2) of the semiconductor device to which the heat sink of the first embodiment is attached; FIG. [Figure 12] FIG. 10 is a longitudinal sectional view of a semiconductor device according to a second embodiment. [Figure 13] FIG. 10 is a longitudinal sectional view of a semiconductor device and a heat sink according to a second embodiment. [Figure 14] FIG. 10 is a longitudinal sectional view of a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "upper surface" refer to the surface facing upward in the semiconductor device 10 of FIGS. 1 and 3. Similarly, "up" refers to the upward direction in the semiconductor device 10 of FIGS. 1 and 3. The terms "back surface" and "lower surface" refer to the surface facing downward in the semiconductor device 10 of FIGS. 1 and 3. Similarly, "lower" refers to the downward direction in the semiconductor device 10 of FIGS. 1 and 3. Similar orientations will be used in other drawings as necessary. The terms "front surface," "upper surface," "upper," "back surface," "lower surface," "lower," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "upper" and "lower" do not necessarily refer to the vertical direction relative to the ground. In other words, the "upper" and "lower" directions are not limited to the direction of gravity. In the following description, the term "main component" refers to a component containing 80 vol% or more of a component.

[0012] [First embodiment] A semiconductor device 10 according to the first embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is an external view of the semiconductor device according to the first embodiment. FIG. 1(A) is a side view of the semiconductor device 10 (seen from above or below FIG. 1(B)), and FIG. 1(B) is a plan view of the semiconductor device 10. FIG. 2 is a horizontal cross-sectional view of the semiconductor device according to the first embodiment, and FIG. 3 is a vertical cross-sectional view of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along dashed line YY in FIG. 1(A). FIG. 3 is a cross-sectional view taken along dashed line XX in FIG. 2.

[0013] First, as shown in FIG. 1 , the semiconductor device 10 has a three-dimensional shape in which all components are encapsulated by an encapsulating member 60. The encapsulating member 60 of the semiconductor device 10 may have a cubic shape with curvature at the corners. The front surface of the semiconductor device 10 is covered with the encapsulating member 60, and the back surface is covered with the encapsulating member 60 and an insulating sheet 70. In FIG. 2 , the position of the insulating sheet 70 on the back surface of the encapsulating member 60 is indicated by a dashed line. Furthermore, the semiconductor device 10 has a plurality of control lead frames 30 and a plurality of main current lead frames 40 extending from both long side surfaces of the encapsulating member 60. In this embodiment, when the control lead frames and the main current lead frames are not particularly distinguished, they will be referred to as the control lead frames 30 and the main current lead frames 40. Furthermore, the semiconductor device 10 has mounting holes 60a formed at both longitudinal ends of the encapsulating member 60. The mounting holes 60a may be located at two ends on a centerline parallel to the longitudinal direction of the encapsulating member 60 and passing through the center. The mounting holes 60a have a diameter such that bolts, which will be described later, are inserted therethrough. The mounting holes 60a penetrate between the front and back surfaces of the sealing member 60. The mounting holes 60a are formed on the outside of the insulating sheet 70 in plan view. By inserting bolts through the mounting holes 60a, the semiconductor device 10 can be attached to a cooling unit such as a heat sink.

[0014] In this semiconductor device 10, components such as those shown in FIGS. 2 and 3 are encapsulated in an encapsulating member 60. Specifically, the semiconductor device 10 includes six pairs of first and second semiconductor chips 21a and 21b, a control lead frame 30 (including control lead frames 31 to 34), a main current lead frame 40 (including main current lead frames 41a to 41d), and a control IC 50. In the semiconductor device 10, the control lead frame 30, the control IC 50, the first semiconductor chip 21a, the second semiconductor chip 21b, and the main current lead frame 40 are electrically connected via bonding wires 22 as appropriate. Note that the bonding wires 22 connected to the control IC 50 are not shown in FIG. 2. These components are encapsulated in the semiconductor device 10. However, the back surface of a die pad portion (die pad portion 41a1 in FIG. 2) of the main current lead frame 40, which will be described later, is exposed from the encapsulating member 60 and is flush with the back surface of the encapsulating member 60. In the semiconductor device 10, an insulating sheet 70 is attached to the back surface of the sealing member 60 so as to cover the exposed die pad portion.

[0015] The first and second semiconductor chips 21a and 21b are power semiconductor chips made of silicon, silicon carbide, or gallium nitride. The first semiconductor chip 21a includes a switching element. The switching element is a power MOSFET, an IGBT, or the like. The first semiconductor chip 21a includes, for example, a drain electrode (positive electrode, or collector electrode in an IGBT) as a main electrode on the back surface, and a gate electrode (control electrode) as a control electrode and a source electrode (negative electrode, or emitter electrode in an IGBT) as main electrodes on the front surface. The second semiconductor chip 21b includes a diode element. The diode element is a free-wheeling diode (FWD) such as a Schottky barrier diode (SBD) or a P-intrinsic-N (PiN) diode. The second semiconductor chip 21b includes a cathode electrode as a main electrode on the back surface, and an anode electrode as a main electrode on the front surface. The thickness of the first and second semiconductor chips 21a, 21b is, for example, 180 μm or more and 220 μm or less, with an average thickness of approximately 200 μm. Also, FIG. 2 merely shows a case where six pairs of first and second semiconductor chips 21a, 21b are provided. The number of pairs is not limited to six, and may be determined according to the specifications of the semiconductor device 10. Also, instead of the first and second semiconductor chips 21a, 21b, a semiconductor chip including a switching element of RC (Reverse-Conducting)-IGBT in which an IGBT and an FWD are configured on one chip may be provided.

[0016] The backsides of the first and second semiconductor chips 21a and 21b are joined to a predetermined main current lead frame 40 by solder (not shown). The solder is made of lead-free solder containing a predetermined alloy as its main component. The predetermined alloy is, for example, at least one of an alloy made of tin-silver, an alloy made of tin-zinc, and an alloy made of tin-antimony. The solder may contain additives such as copper, bismuth, indium, nickel, germanium, cobalt, or silicon. Instead of solder, joining may be performed by sintering using a sintering material. In this case, the sintering material is, for example, powder of silver, gold, or copper.

[0017] The first and second semiconductor chips 21a and 21b have their main electrodes on their front surfaces electrically connected to terminal portions (described later) of the main current lead frame 40 via bonding wires 22. The first and second semiconductor chips 21a and 21b also have their control electrodes on their front surfaces electrically connected to the control IC 50 via bonding wires (not shown). The bonding wires 22 are made of a material with excellent conductivity, such as gold, silver, copper, aluminum, or an alloy containing at least one of these metals. The diameter of the bonding wires 22 is, for example, 100 μm or more and 1.0 mm or less.

[0018] The multiple main current lead frames 40 are provided on the right side of the semiconductor device 10 in FIG. 2, and the other ends of the multiple main current lead frames 40 extend outward from the side surface of the semiconductor device 10 on the right side in FIG. 2. Of the multiple main current lead frames 40, main current lead frames 41b, 41a, 41c, and 41d are sealed in the sealing member 60 with the back surfaces of their die pad portions exposed. The main current lead frame 41a has a die pad portion 41a1, a linking portion 41a2, and a terminal portion 41a3. The back surface of the die pad portion 41a1 is exposed from the back surface of the sealing member 60, and is in contact with the back surface of the sealing member 60. same planeFurthermore, the back surface of the die pad portion 41a1 and the back surface of the sealing member 60 may be flush with each other. As described above, the first and second semiconductor chips 21a and 21b are disposed on the front surface of the die pad portion 41a1. The linking portion 41a2 is inclined to integrally connect the die pad portion 41a1 and the terminal portion 41a3. The periphery of the linking portion 41a2 is sealed by the sealing member 60. The terminal portion 41a3 is spaced upward and laterally from the front surface of the die pad portion 41a1 in accordance with the inclination of the linking portion 41a2. One end of the terminal portion 41a3 is integrally connected to the die pad portion 41a1 via the linking portion 41a2. Bonding wires 22 connected to the first and second semiconductor chips 21a and 21b are connected to the portion of the terminal portion 41a3 whose periphery is sealed by the sealing member 60. The other end of the terminal portion 41a3 extends outward from the sealing member 60. The terminal portion 41a3 may extend from the side surface of the sealing member 60 in parallel with the front surface of the die pad portion 41a1. Although not shown, the main current lead frames 41b, 41c, and 41d also include a die pad portion, a linking portion, and a terminal portion, similar to the main current lead frame 41a.

[0019] The multiple control lead frames 30 (including control lead frames 31, 32, 33, and 34) are provided on the left side of the sealing member 60 in FIG. 2. The multiple control lead frames 30 are located higher than the die pad portion of the main current lead frame 40 and at the same height as the terminal portion of the main current lead frame 40. The control lead frames 30 extend outward from the left side surface of the semiconductor device 10 in FIG. 2. Of the multiple control lead frames 30, the control lead frame 34 includes a control die pad portion 34a1, a control wiring portion 34a2, and a control terminal portion 34a3. The control die pad portion 34a1 extends along the longitudinal direction of the semiconductor device 10, and the control IC 50 is disposed on the control die pad portion 34a1 via solder (not shown). The control wiring portion 34a2 integrally connects the control die pad portion 34a1 and the control terminal portion 34a3. The control die pad portion 34a1 and the control wiring portion 34a2 are sealed by a sealing member 60. One end of the control terminal portion 34a3 is integrally connected to the control wiring portion 34a2, and is sealed by the sealing member 60. A bonding wire (not shown) connected to the control IC 50 or the like is connected to the sealed portion of the control wiring portion 34a2. The other end of the control terminal portion 34a3 extends from the sealing member 60 to the outside. The control terminal portion 34a3 may extend from a side surface of the sealing member 60 in parallel with the front surface of the die pad portion 41a1.

[0020] The main current lead frames 40 and the control lead frames 30 are made of a material with excellent conductivity. Examples of such materials include copper, aluminum, or an alloy containing at least one of these. The thickness of the main current lead frames 40 and the control lead frames 30 is preferably 0.10 mm or more and 1.00 mm or less, and more preferably 0.20 mm or more and 0.50 mm or less. The main current lead frames 40 and the control lead frames 30 can also be plated with a material with excellent corrosion resistance. Examples of such materials include nickel, gold, or an alloy containing at least one of these.

[0021] The control IC 50 is electrically connected to the gate electrode of the first semiconductor chip 21a by a bonding wire (not shown). The control IC 50 applies a control voltage to the first semiconductor chip 21a at a predetermined timing. Note that in the semiconductor device 10, electronic components such as a thermistor, a capacitor, a resistor, a current sensor, and a temperature sensor may be disposed in place of or together with the control IC 50 in order to achieve a desired function.

[0022] The sealing member 60 contains a thermosetting resin and an inorganic filler contained in the thermosetting resin. The thermosetting resin is mainly composed of at least one selected from the group including, for example, epoxy resin, phenolic resin, and melamine resin. Preferably, the thermosetting resin is mainly composed of epoxy resin. The inorganic filler is made of an inorganic material mainly composed of silicon oxide. The use of silicon oxide also functions as a mold release agent. Furthermore, high flame retardancy can be maintained without blending halogen-based, antimony-based, metal hydroxide-based, or other flame retardants. The inorganic filler accounts for 70 vol% or more and 90 vol% or less of the entire sealing raw material.

[0023] The insulating sheet 70 also contains a thermosetting resin and an inorganic filler contained in the resin. The thermosetting resin is primarily composed of at least one selected from the group including, for example, epoxy resin, phenolic resin, melamine resin, and polyimide resin. Preferably, the thermosetting resin is primarily composed of epoxy resin. The inorganic filler is an inorganic material primarily composed of at least one selected from the group including aluminum oxide, aluminum nitride, silicon nitride, and boron nitride, which have high insulation and thermal conductivity. Furthermore, it is preferable that the sealing member 60 and the insulating sheet 70 contain the same thermosetting resin as the primary component. More preferably, the thermosetting resins of both the sealing member 60 and the insulating sheet 70 contain epoxy resin as the primary component.

[0024] The insulating sheet 70 has, for example, a rectangular shape in a plan view. The thickness of the insulating sheet 70 is 50 μm or more and 1.0 mm or less. The insulating sheet 70 is formed to cover the back surface of the die pad portion of the main current lead frame 40 exposed on the back surface of the sealing member 60. The insulating sheet 70 covers the back surface of the die pad portion (die pad portion 41 a 1 in FIG. 3 ) of the main current lead frame 40 and may also cover the back surface of the sealing member 60 around the die pad portion. In other words, the back surface of the insulating sheet 70 forms a step with respect to the back surface of the sealing member 60. Covering the back surface of the die pad portion (die pad portion 41 a 1 in FIG. 3 ) ensures insulation between the die pad portion and the outside. Furthermore, covering the back surface of the sealing member 60 around the die pad portion also ensures insulation even if the semiconductor device 10 is deformed.

[0025] Next, a manufacturing method of such a semiconductor device 10 will be described with reference to FIGS. 4 to 8. FIG. 4 is a flowchart showing a manufacturing method of a semiconductor device according to the first embodiment. FIG. 5 is a diagram showing a mounting process of a semiconductor chip and electronic components included in the manufacturing method of a semiconductor device according to the first embodiment. FIG. 6 is a diagram showing a sealing process included in the manufacturing method of a semiconductor device according to the first embodiment. FIG. 7 is a vertical cross-sectional view of a semi-cured unit generated after sealing in the manufacturing method of a semiconductor device according to the first embodiment. FIG. 8 is a diagram showing pressure bonding of the semi-cured unit to an insulating sheet included in the manufacturing method of a semiconductor device according to the first embodiment. Note that FIGS. 5 to 8 are cross-sectional views corresponding to the cross-sectional position of the dashed dotted line XX in FIG. 2.

[0026] First, a preparation step is performed (step S1 in FIG. 4) to prepare components of the semiconductor device 10. The components of the semiconductor device 10 include a first semiconductor chip 21a, a second semiconductor chip 21b, a main current lead frame 40, a control lead frame 30, a semi-cured insulating sheet, a sealing material, etc.

[0027] The main current lead frame 40 and the control lead frame 30 are metal plates having wiring patterns integrated with tie bars or the like. The main current lead frame 40 and the control lead frame 30 are formed from a single metal plate by, for example, etching or punching. Then, a step is formed by pressing using a mold. In this way, a metal plate having a wiring pattern in which the main current lead frame 40 and the control lead frame 30 are integrated with tie bars or the like is obtained.

[0028] The insulating sheet is a sheet containing a semi-cured (B-stage) thermosetting resin and an inorganic filler. For example, it can be manufactured as follows. First, a liquid resin (A-stage) that is a thermosetting resin and an inorganic filler to be mixed with the liquid resin are prepared. The resin used here is mainly composed of at least one selected from the group including epoxy resin, phenolic resin, melamine resin, and polyimide resin. Preferably, the resin is mainly composed of epoxy resin. The inorganic filler is an inorganic material mainly composed of at least one selected from the group including aluminum oxide, aluminum nitride, silicon nitride, and boron nitride. Next, the liquid (A-stage) thermosetting resin and the inorganic filler are mixed, coated into a sheet, and heated to semi-cure (B-stage). Alternatively, the insulating sheet may be manufactured by heating the liquid (A-stage) thermosetting resin mixed with the inorganic filler to semi-cure (B-stage) and then molding it into a sheet. The heating time is set appropriately depending on the takt time and depends on the type of catalyst in the resin. For example, the heating temperature is 100°C or higher and 200°C or lower.

[0029] The encapsulating raw material is a powder or tablet containing a semi-cured (B-stage) thermosetting resin and an inorganic filler. For example, it can be manufactured as follows: First, a liquid resin (A-stage) that is a thermosetting resin and an inorganic filler to be mixed with the liquid resin are prepared. The resin used here is mainly composed of at least one selected from the group including epoxy resin, phenolic resin, and melamine resin. Preferably, epoxy resin is the main component. The inorganic filler is an inorganic material mainly composed of silicon oxide. Next, the inorganic filler is mixed with the liquid resin. The liquid resin (A-stage) mixed with the inorganic filler is heated to produce a semi-cured semi-cured raw material (B-stage). The heating and warming time is appropriately set based on the takt time and depends on the catalyst type of the resin. For example, the heating temperature is 100°C or higher and 200°C or lower. The semi-cured semi-cured raw material is powdered and molded into, for example, a tablet to produce the encapsulating raw material.

[0030] Next, a mounting process is performed in which the semiconductor chips 21a, 21b and the control IC 50 are arranged and wired on the main current lead frame 40 and the control lead frame 30, respectively, included in the metal plate (step S2 in FIG. 4). Here, as shown in FIG. 5, first, the first and second semiconductor chips 21a, 21b are soldered to the die pad portion of the main current lead frame 40, and the control IC 50 is soldered to the control die pad portion of the control lead frame 30. For example, the first and second semiconductor chips 21a, 21b are soldered to the front surface of the die pad portion 41a1 of the main current lead frame 41a. The control IC 50 is also soldered to the control die pad portion 34a1 of the control lead frame 34. Next, these components are transported to a predetermined bonding device for wire bonding, where they are wired. For example, the main current lead frame 40 on which the first and second semiconductor chips 21a and 21b are arranged and the control lead frame 30 on which the control IC 50 is arranged are electrically connected and wired by bonding wires 22 as appropriate.

[0031] Next, an encapsulation step is performed to form the semi-cured unit 11 (step S3 in FIG. 4). The semi-cured unit 11 is formed by encapsulating the control die pad and control wiring of the control lead frame 30, the linking portion of the main current lead frame 40, and the first and second semiconductor chips 21a and 21b with a semi-cured encapsulating material, with the terminal portions of the main current lead frame 40 and the control terminal portions of the control lead frame 30 protruding and the back surface of the die pad portion of the main current lead frame 40 exposed.

[0032] In the sealing step (step S3 in FIG. 4), first, as shown in FIG. 6, the main current lead frame 40 and the control lead frame 30 on which the first and second semiconductor chips 21a, 21b and the control IC 50 are mounted are set in a molding die 80. Here, the main current lead frame 40 and the control lead frame 30 are first transported to a sealing device that performs sealing and placed in a lower mold 82 of the sealing device. Next, the sealing device sandwiches the main current lead frame 40 and the control lead frame 30 between an upper mold 81 and a lower mold 82 of the molding die 80. At this time, a flow path 83 and a cavity 84 are formed in the molding die 80. In this way, a plurality of main current lead frames 40 (main current lead frames 41a in FIG. 6) and a plurality of control lead frames 30 (control lead frames 34 in FIG. 6) are set in the cavity 84 formed by the upper mold 81 and the lower mold 82.

[0033] 6 and 7, the cavity 84 formed in the molding die 80 is filled with an encapsulating material to form the semi-cured unit 11. First, as shown in FIG. 6, the front surface of the die pad portion 41a1 of the main current lead frame 40 (the die pad portion 41a1 in FIG. 6) is pressed toward the lower mold 82 by the presser pins 85a and 85b so that the back surface of the die pad portion 41a1 contacts the surface of the lower mold 82, and this state is maintained. The presser pins 85a and 85b may be provided on the upper mold 81 of the molding die 80 and press perpendicularly against the surface of the lower mold 82. The presser pins 85a and 85b may press an area of ​​the die pad portion (the die pad portion 41a1 in FIG. 6) of the main current lead frame 40 set in the molding die 80 where the first and second semiconductor chips 21a and 21b are not arranged.

[0034] Next, the tablet-shaped semi-cured (B stage) sealing material is placed in the pot of the sealing device and heated to soften it. The softened semi-cured sealing material is pressed into the cavity 84 through the flow path 83 under pressure. The upper mold 81 and the lower mold 82 are preheated, and the softened semi-cured sealing material is filled into the cavity 84. Then, when the cavity 84 is filled with the semi-cured sealing material, the presser pins 85a and 85b are moved above the molding die 80 to release the pressure on the die pad portion (die pad portion 41a1 in FIG. 6). At this time, the semi-cured sealing material is still pressed into the cavity 84 under pressure from the flow path 83, and the portions where the presser pins 85a and 85b were located are filled with the semi-cured sealing material.

[0035] Then, the filling of the semi-cured sealing material from the flow path 83 is stopped, the molding die 80 is separated, and the semi-cured unit 11 is removed from the molding die 80. As a result, as shown in FIG. 7, the semi-cured unit 11 is molded, in which the first and second semiconductor chips 21a and 21b, the main current lead frame 40, the control lead frame 30, etc. are sealed with the semi-cured sealing material (semi-cured resin 61). At this time, although not shown in FIG. 7, the back surface of the semi-cured unit 11 is exposed so that the back surface of the die pad portion (die pad portion 41a1 in FIG. 7) of the main current lead frame 40 is flush with the back surface of the semi-cured unit 11. Furthermore, by pulling the pressure pins 85a and 85b upward, recesses are formed in the front surface of the semi-cured resin 61 at the locations where the pressure pins 85a and 85b were located. Note that the locations on the front surface of the semi-cured resin 61 where the pressure pins 85a and 85b were located may be protrusions.

[0036] Next, a crimping step is performed in which the semi-cured insulating sheet 70 is crimped to the semi-cured unit 11 (step S4 in FIG. 4). First, as shown in FIG. 8, the semi-cured insulating sheet 70 and the semi-cured unit 11 are transported to a crimping device. Next, the front surface of the semi-cured insulating sheet 70 is placed so as to cover the exposed die pad portion on the back surface of the semi-cured unit 11, and the semi-cured unit 11 is crimped using the crimping device. A press machine can be used as the crimping device. Note that heat may be applied during crimping. Such a crimping device can be a heating press machine. The semi-cured insulating sheet 70 is heated and crimped in a softened state, allowing it to be installed in close contact. The semi-cured unit 11 is then removed from the crimping device, and the semi-cured unit 11 to which the semi-cured insulating sheet 70 is crimped is formed.

[0037] Next, a curing process is performed (step S5 in FIG. 4). First, the semi-cured unit 11 to which the semi-cured insulating sheet 70 is attached is transported to a heating device. Then, the semi-cured unit 11 to which the semi-cured insulating sheet 70 is attached is heated at a predetermined temperature. The heating temperature is 120°C or higher and 180°C or lower. During heating, the semi-cured unit 11 to which the semi-cured insulating sheet 70 is attached is in an unpressurized state, i.e., no pressure is applied. In this manner, the semi-cured insulating sheet 70 and the semi-cured unit 11 are cured, thereby producing the semiconductor device 10 including the cured sealing member 60 and insulating sheet 70 shown in FIG. 3. Note that unnecessary members such as tie bars may be removed from the metal plate before or after the curing process (step S5 in FIG. 4). Furthermore, bending may be performed on the terminal portions of the main current lead frame 40 and the control terminal portions of the control lead frame 30.

[0038] By pressing the semi-cured insulating sheet 70 against the back surface of the semi-curing unit 11 and curing it in this way, the sealing member 60 and the semi-cured insulating sheet 70 simultaneously cure from a semi-cured state. This allows them to be firmly bonded to each other. Furthermore, by using resins with the same main component for the sealing member 60 and the semi-cured insulating sheet 70, they can be bonded even more firmly. Preferably, the thermosetting resins of the sealing member 60 and the insulating sheet 70 both contain epoxy resin as a main component. Furthermore, by pressing the semi-cured insulating sheet 70 against the back surface of the semi-curing unit 11 in this way and then performing a curing process on them together in a separate device, the semiconductor device 10 including the insulating sheet 70 can be easily manufactured without increasing manufacturing costs.

[0039] Next, a case where a heat sink is attached to the semiconductor device 10 as an example of a cooling unit will be described with reference to FIGS. 9 to 11. FIG. 9 is a plan view of the semiconductor device to which the heat sink of the first embodiment is attached, and FIGS. 10 and 11 are vertical cross-sectional views of the semiconductor device to which the heat sink of the first embodiment is attached. Note that FIG. 10 is a cross-sectional view taken along dashed line XX in FIG. 9, and FIG. 11 is a cross-sectional view taken along dashed line YY in FIG. 9. The dashed line XX in FIG. 9 corresponds to the dashed line XX in FIG. 2. Note that the reference numerals of some components are omitted in FIGS. 10 and 11.

[0040] A heat sink 90 is attached to the back surface of the semiconductor device 10 with bolts 93. The heat sink 90 is an example of a cooling unit and is made of a metal with excellent thermal conductivity. Examples of such metals include aluminum, iron, silver, copper, or an alloy containing at least one of these. The heat sink 90 includes a heat sink 91 and a fin portion 92 including one or more fins formed on the back surface of the heat sink 91. The heat sink 91 has a rectangular shape that is larger than the area of ​​the semiconductor device 10 in a plan view, and a bolt hole 91a is formed on the front surface into which a bolt 93 is threaded. The bolt hole 91a corresponds to the mounting hole 60a of the semiconductor device 10 when the heat sink 90 is attached to the back surface of the semiconductor device 10. To improve corrosion resistance, the surface of the heat sink 90 may be plated with a material such as nickel. Examples of materials other than nickel include nickel-phosphorus alloys and nickel-boron alloys. A water-cooled cooling device may also be used as a cooling unit. The cooling device in this case also has bolt holes corresponding to the mounting holes 60a of the semiconductor device 10.

[0041] The back surface of the semiconductor device 10 is placed on the front surface of this heat sink 90 (heat sink 91), and bolts 93 are inserted through the mounting holes 60a and screwed into the bolt holes 91a of the heat sink 90's heat sink 91. This allows the heat sink 90 to be attached to the semiconductor device 10. In the semiconductor device 10, the insulating sheet 70 is attached to the sealing member 60 with a step. Therefore, only the insulating sheet 70 is in contact with the front surface of the heat sink 90's heat sink 91. Therefore, the force generated by tightening the bolts 93 acts as an adhesive force between the heat sink 90 and the insulating sheet 70, thereby improving the heat dissipation performance of the semiconductor device 10. At this time, a thermal compound is applied between the insulating sheet 70 and the heat sink 90. ​​As the adhesive force between the heat sink 90 and the insulating sheet 70 increases, the thermal compound spreads thinly and evenly across the entire area between the insulating sheet 70 and the heat sink 90.

[0042] In the semiconductor device 10 described above, the first and second semiconductor chips 21a, 21b are arranged and wired on the front surface of the die pad portion 41a1 of the main current lead frame 41a. Next, the terminal portion 41a3 of the main current lead frame 41a is protruded, the back surface of the die pad portion 41a1 is exposed, and the main current lead frame 41a and the first and second semiconductor chips 21a, 21b are encapsulated with a semi-cured encapsulating material to form a semi-cured unit 11. The front surface of the insulating sheet 70 is then pressure-bonded to the back surface of the semi-cured unit 11, covering the back surface of the die pad portion 41a1 of the main current lead frame 41a. This manufacturing method prevents the insulating sheet 70 from peeling and allows the insulating sheet 70 to be attached regardless of the specifications of the molding die 80. A transport mechanism for transporting the insulating sheet 70 to the molding die 80 is not required, and the semiconductor device 10 including the insulating sheet 70 can be easily and reliably manufactured while reducing manufacturing costs.

[0043] The sealing member 60 and insulating sheet 70 of the semiconductor device 10 manufactured in this manner contain a thermosetting resin and an inorganic filler. Preferably, the thermosetting resins of the sealing member 60 and the insulating sheet 70 contain the same thermosetting resin as a main component. More preferably, the thermosetting resins of the sealing member 60 and the insulating sheet 70 both contain an epoxy resin as a main component.

[0044] Furthermore, in the semiconductor device 10 manufactured in this manner, the insulating sheet 70 is attached with a step on the back surface of the sealing member 60. Therefore, when the heat sink 90 is attached to the back surface of the semiconductor device 10, the heat sink 90 comes into contact only with the insulating sheet 70. Therefore, the force generated by tightening the bolts 93 acts as an adhesive force between the heat sink 90 and the insulating sheet 70, and the thermal compound between the heat sink 90 and the insulating sheet 70 also spreads thinly over the entire surface, thereby improving the heat dissipation performance of the semiconductor device 10.

[0045] [Second embodiment] A semiconductor device according to a second embodiment will be described with reference to FIG. 12. FIG. 12 is a longitudinal cross-sectional view of the semiconductor device according to the second embodiment. Components of the semiconductor device 10a that are the same as those of the semiconductor device 10 are designated by the same reference numerals, and their description will be omitted or simplified. In the semiconductor device 10a, a recess 60b is provided on the back surface of the sealing member 60. The back surface of the die pad portion (die pad portion 41a1 in FIG. 12) of the main current lead frame 40 is exposed within the recess 60b. Thus, the back surface of the sealing member 60 around the recess 60b is positioned lower than the back surface of the die pad portion 41a1. To manufacture such a semiconductor device 10a, a molding die is used that has a protrusion in the sealing member 60 that forms the recess 60b. Other manufacturing processes are the same as those of the first embodiment.

[0046] Next, the attachment of a heat sink 90 to such a semiconductor device 10a will be described with reference to FIG. 13 . FIG. 13 is a longitudinal cross-sectional view of a semiconductor device and heat sink according to the second embodiment. Note that FIG. 13 corresponds to the cross-section of FIG. 11 . When attaching the heat sink 90 to the semiconductor device 10a, a thermal compound is first applied to the recess 60b of the semiconductor device 10a. Then, as in the first embodiment, the heat sink 90 is attached to the back surface of the semiconductor device 10a and bolts 93 are fastened. When the back surface of the semiconductor device 10a and the front surface of the heat sink 90 are tightly attached by fastening the bolts 93, the thickness of the thermal compound between the back surface of the insulating sheet 70 and the front surface of the heat sink 90 can be made uniform. This improves the thermal conductivity from the insulating sheet 70 to the heat sink 90. ​​To improve this thermal conductivity, it is desirable for the thermal compound to be uniform and thin. Therefore, it is preferable that the depth of the recess 60b is the same as the height of the rear surface of the insulating sheet 70 and the rear surface around the recess 60b of the semiconductor device 10a, or is 10 μm or more and 100 μm or less.

[0047] [Third embodiment] A semiconductor device according to a third embodiment will be described with reference to FIG. 14 . FIG. 14 is a longitudinal cross-sectional view of the semiconductor device according to the third embodiment. Components of the semiconductor device 10b that are the same as those of the semiconductor device 10 are designated by the same reference numerals, and their description will be omitted or simplified. The semiconductor device 10b has a thicker die pad portion (die pad portion 41a1 in FIG. 14 ) of the main current lead frame 40 than the first embodiment. Therefore, the thickness of the die pad portion 41a1 is thicker than the thicknesses of the linking portion 41a2 and the terminal portion 41a3. This increases the heat capacity of the main current lead frame 40, thereby suppressing transient increases in thermal resistance. Furthermore, the thicker die pad portion (die pad portion 41a1 in FIG. 14 ) causes thermal diffusion, thereby reducing thermal resistance compared to the first embodiment. Therefore, the semiconductor device 10b can achieve improved heat dissipation compared to the semiconductor device 10. The third embodiment is not limited to the example shown in FIG. 14 . For example, in the die pad portion of the main current lead frame 40 of the second embodiment, the thickness of the die pad portion may be made thicker than that in the second embodiment. [Explanation of symbols]

[0048] 10, 10a, 10b Semiconductor device 11 Semi-hardening unit 21a First semiconductor chip 21b Second semiconductor chip 22 Bonding wire 30, 31, 32, 33, 34 Control lead frame 34a1 Control die pad section 34a2 Control wiring section 34a3 Control terminal section 40, 41a, 41b, 41c, 41d Main current lead frame 41a1 Die pad part 41a2 Liaison Section 41a3 Terminal part 50 Control IC 60 Sealing member 60a mounting hole 60b recess 61 Semi-cured resin 70 Insulation sheet 80 molding die 81 Upper mold 82 Lower mold 83 Flow path 84 Cavity 85a, 85b Presser pin 90 Heatsink 91 Heat sink 91a Bolt hole 92 Fin section 93 volts

Claims

1. a preparation step of preparing a power semiconductor chip, a lead frame including a die pad portion and a terminal portion integrally connected to the die pad portion, and a semi-cured insulating sheet; a mounting step of placing the power semiconductor chip on the front surface of the die pad portion and wiring the power semiconductor chip; a sealing process of sealing the lead frame and the power semiconductor chip with a semi-cured sealing material, causing the terminal portion to protrude and exposing a back surface of the die pad portion, to form a semi-cured unit; a pressure-bonding step of pressing the front surface of the insulating sheet against the back surface of the semi-cured unit to cover the back surface of the die pad portion, and pressing the semi-cured unit against the insulating sheet in a heated state; a curing step of heating and curing the semi-curing unit and the insulating sheet; A method for manufacturing a semiconductor device comprising:

2. After performing the crimping step, The semi-curing unit to which the insulating sheet is pressed is transported to a heating device, and the curing step is carried out in the heating device. The method for manufacturing a semiconductor device according to claim 1 .

3. The curing step heats the semi-cured unit to which the insulating sheet is pressed in a non-pressurized state.

3. The method for manufacturing a semiconductor device according to claim 1.

4. the sealing material and the insulating sheet contain a semi-cured thermosetting resin and an inorganic filler; 4. The method for manufacturing a semiconductor device according to claim 1.

5. the thermosetting resin of the sealing material and the thermosetting resin of the insulating sheet both contain epoxy resin as a main component; The method for manufacturing a semiconductor device according to claim 4 .

6. the inorganic filler of the sealing material contains silicon oxide as a main component, and the inorganic filler of the insulating sheet contains at least one selected from the group consisting of aluminum oxide, aluminum nitride, silicon nitride, and boron nitride as a main component; The method for manufacturing a semiconductor device according to claim 4 .

7. a lead frame including a die pad portion and a terminal portion integrally connected to the die pad portion; a power semiconductor chip disposed on a front surface of the die pad portion; a sealing member that seals the lead frame and the power semiconductor chip by protruding the terminal portion and exposing a first back surface of the die pad portion, and whose second back surface protrudes outward beyond the first back surface of the die pad portion; an insulating sheet provided so as to cover the first back surface of the die pad portion exposed from the second back surface of the sealing member, forming a step with respect to the second back surface of the sealing member, and having a third back surface, the second back surface of the sealing member protruding outward beyond the third back surface; a heat sink provided on the second rear surface of the sealing member; a thermal compound provided between the third rear surface of the insulating sheet and the heat sink; and The insulating sheet is configured so that both side portions thereof are sandwiched between the sealing members via the thermal compound. Semiconductor device.

8. the sealing member and the insulating sheet contain a thermosetting resin and an inorganic filler; The semiconductor device according to claim 7 .

9. the thermosetting resin of the sealing member and the thermosetting resin of the insulating sheet both contain epoxy resin as a main component; The semiconductor device according to claim 8 .

10. the inorganic filler of the sealing member is mainly composed of silicon oxide, and the inorganic filler of the insulating sheet is mainly composed of at least one selected from the group consisting of aluminum oxide, aluminum nitride, silicon nitride, and boron nitride; The semiconductor device according to claim 8 .

11. The thickness of the die pad portion is greater than the thickness of the terminal portion.

11. The semiconductor device according to claim 7.

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