Semiconductor device and method for manufacturing the same

Abstract

To preferably improve positioning accuracy in manufacture of a semiconductor device.SOLUTION: There is provided a semiconductor device comprising a semiconductor substrate, a gate electrode provided in the semiconductor substrate, and a poly gate runner provided above the semiconductor substrate and connected to the gate electrode. The semiconductor device may comprise an oxide film provided on the semiconductor substrate. The through hole may expose the oxide film. The semiconductor device may comprise an inter-layer insulation film provided above the semiconductor substrate. The inter-layer insulation film may be filled in the through hole.SELECTED DRAWING: Figure 22

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, in the manufacture of semiconductor devices such as IGBTs (Insulated Gate Bipolar Transistors), alignment (position correction function) is performed by providing markers on a semiconductor substrate (see, for example, Patent Documents 1 and 2). Patent Document 1: JP 2021-032672 A Patent Document 2: Japanese Patent Application Laid-Open No. 2010-219233 Summary of the Invention [Problem to be solved by the invention]

[0003] In the manufacture of semiconductor devices, it is preferable to improve positioning accuracy. [Means for solving the problem]

[0004] In order to solve the above problems, a first aspect of the present invention provides a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate electrode. The gate electrode may be provided on the semiconductor substrate. The semiconductor device may include a poly gate runner. The poly gate runner may be provided above the semiconductor substrate. The poly gate runner may be connected to the gate electrode. The poly gate runner may have a through-hole.

[0005] The semiconductor device may include an oxide film. The oxide film may be provided on a semiconductor substrate. The through-hole may expose the oxide film. The semiconductor device may include an interlayer insulating film. The interlayer insulating film may be provided above the semiconductor substrate. The through-hole may be filled with the interlayer insulating film. The interlayer insulating film may be in contact with the oxide film via the through-hole.

[0006] The poly gate runner may have multiple through holes.

[0007] The semiconductor substrate may have an active portion. The poly gate runner may have a transverse poly gate runner. The transverse poly gate runner may be provided so as to cross the active portion in a top view. The transverse poly gate runner may have a through-hole.

[0008] The poly gate runner may include an outer periphery poly gate runner. The outer periphery poly gate runner may be provided so as to surround the active portion in a top view. The outer periphery poly gate runner may have a through-hole. The outer periphery poly gate runner may have a plurality of edge edges. Two or more through-holes may be discretely arranged on each edge of the plurality of edge edges.

[0009] The semiconductor device may include a metal gate runner. The metal gate runner may be provided above the poly gate runner. The metal gate runner may be recessed above the through hole.

[0010] The interlayer insulating film may have a contact hole. The contact hole may connect the poly gate runner and the metal gate runner. The contact hole may overlap the through hole in a top view. The contact hole may not overlap the through hole in a top view.

[0011] A second aspect of the present invention provides a method for manufacturing a semiconductor device. The semiconductor device includes a semiconductor substrate. The semiconductor device includes a gate electrode. The gate electrode may be provided on the semiconductor substrate. The semiconductor device may include a poly gate runner. The poly gate runner may be provided above the semiconductor substrate. The poly gate runner may be connected to the gate electrode. In the method for manufacturing the semiconductor device, a through hole may be formed in the poly gate runner.

[0012] The method for manufacturing a semiconductor device may include a patterning step, in which the polysilicon is patterned to form a poly gate runner, and in which a through hole is formed in the poly gate runner.

[0013] The method for manufacturing a semiconductor device may include an inspection step, in which the semiconductor device may be inspected for defects, and the inspection may be performed by positioning the semiconductor device using the through-holes.

[0014] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a top view showing an example of a semiconductor device 100. FIG. [Figure 2] 1 is a diagram showing an example of the layout of poly gate runners 46 of the semiconductor device 100. FIG. [Figure 3] 10 is a flowchart showing a method for forming a gate electrode of the semiconductor device 100 according to the comparative example. [Figure 4] FIG. 10 is a diagram illustrating a gate trench formation step S101. [Figure 5] FIG. 5 is a cross-sectional view of FIG. 4 taken along line aa. [Figure 6] FIG. 10 is a diagram illustrating the gate insulating film forming step S102. [Figure 7] FIG. 10 is a diagram illustrating a polysilicon film forming step S103. [Figure 8] FIG. 10 is a diagram illustrating a resist formation step S104. [Figure 9] FIG. 9 is a view showing a cross section bb of FIG. 8. [Figure 10] FIG. 10 is a diagram illustrating the patterning step S105. [Figure 11] FIG. 11 is a view showing a cross section cc of FIG. [Figure 12] FIG. 10 is a diagram illustrating the resist removal step S106. [Figure 13] FIG. 13 is a view showing a cross section dd of FIG. [Figure 14] FIG. 10 is a diagram illustrating an inspection step S107. [Figure 15] 1 is a flowchart showing a method for forming a gate electrode of the semiconductor device 100 according to the embodiment. [Figure 16] FIG. 10 is a diagram illustrating a resist formation step S204. [Figure 17] FIG. 17 is a view showing the ee cross section of FIG. [Figure 18] FIG. 10 is a diagram illustrating the patterning step S205. [Figure 19] FIG. 19 is a cross-sectional view of FIG. 18 taken along line ff. [Figure 20] FIG. 10 is a diagram illustrating the resist removal step S206. [Figure 21] FIG. 21 is a diagram showing the gg cross section of FIG. 20. [Figure 22] FIG. 10 is a diagram illustrating an inspection step S207. [Figure 23] 1 shows an example of the arrangement of the interlayer insulating film 38 and the metal gate runner 130 in a top view. [Figure 24] FIG. 24 is a diagram showing a cross section hh of FIG. 23. [Figure 25] 10 shows another example of the arrangement of the interlayer insulating film 38 and the metal gate runner 130 in a top view. [Figure 26] 1 shows an example of the arrangement of through holes 184 in the poly gate runner 46 as viewed from above. [Figure 27] 10 is a diagram for explaining the shape of a through-hole 184 in detail. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0016] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0017] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper" and the other side as "lower." Of the two main surfaces of a substrate, layer, or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the directions when the semiconductor module is mounted.

[0018] In this specification, technical matters may be described using orthogonal coordinate axes, i.e., the X-axis, Y-axis, and Z-axis. The orthogonal coordinate axes merely identify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit the height direction relative to the ground. The +Z-axis direction and the -Z-axis direction are opposite directions. When the Z-axis direction is referred to without specifying positive or negative, it means a direction parallel to the +Z-axis and the -Z-axis. In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the top and bottom surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X-axis and Y-axis, may be referred to as the horizontal direction.

[0019] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0020] Fig. 1 is a top view showing an example of a semiconductor device 100. Fig. 1 shows the positions of each component projected onto the top surface of a semiconductor substrate 10. Fig. 1 shows only some of the components of the semiconductor device 100, and some components are omitted.

[0021] The semiconductor device 100 is provided on a semiconductor substrate 10. The semiconductor substrate 10 is a substrate made of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate, but the material of the semiconductor substrate 10 is not limited to silicon. The semiconductor substrate 10 may also be a silicon carbide substrate.

[0022] The semiconductor substrate 10 has a first end edge 161 and a second end edge 162 in a top view. In this specification, the term "top view" simply refers to a view from the top surface side of the semiconductor substrate 10. The semiconductor substrate 10 of this example has two pairs of first end edges 161 that face each other in a top view. The semiconductor substrate 10 of this example also has two pairs of second end edges 162 that face each other in a top view. In FIG. 1, the first end edges 161 are parallel to the X-axis direction. The second end edges 162 are parallel to the Y-axis direction. The Z-axis is perpendicular to the top surface of the semiconductor substrate 10. The first end edges 161 are perpendicular to the extension direction of a gate trench, which will be described later. The second end edges 162 are parallel to the extension direction of a gate trench, which will be described later.

[0023] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region through which a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160, but is not shown in FIG.

[0024] In this example, the active section 160 is provided with a transistor section 70 including a transistor element such as a field effect transistor (MOSFET). In another example, the transistor section 70 and a diode section including a diode element such as a FWD (Free Wheel Diode) may be alternately arranged along a predetermined arrangement direction on the upper surface of the semiconductor substrate 10. The transistor section 70 may be provided with an IGBT. The transistor section 70 may be provided with a reverse-blocking IGBT. In this example, two transistor sections 70 (transistor section 70-1 and transistor section 70-2) are provided along the Y-axis direction. A P+ type well region or a poly gate runner, which will be described later, may be provided between the transistor sections 70.

[0025] The transistor section 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. The transistor section 70 also has an N+ type emitter region, a P- type base region, a gate conductive portion, and a gate electrode having a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10.

[0026] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 164. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is disposed near a first edge 161. The vicinity of the first edge 161 refers to the region between the first edge 161 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as a wire.

[0027] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate electrode of the active portion 160. The semiconductor device 100 includes a metal gate runner 130 that connects the gate pad 164 and the gate electrode. In FIG. 1, the metal gate runner 130 is indicated by diagonal hatching.

[0028] The metal gate runner 130 is disposed between the active portion 160 and the first end edge 161 or the second end edge 162 in a top view. The metal gate runner 130 of this example surrounds the active portion 160 in a top view. The area surrounded by the metal gate runner 130 in a top view may be the active portion 160. The metal gate runner 130 is also connected to a gate pad 164. The metal gate runner 130 is disposed above the semiconductor substrate 10. The metal gate runner 130 may be a metal wiring containing aluminum or the like.

[0029] The peripheral well region 11 is provided so as to overlap with the metal gate runner 130. In other words, similar to the metal gate runner 130, the peripheral well region 11 surrounds the active portion 160 in a top view. The peripheral well region 11 is also provided so as to extend by a predetermined width in an area that does not overlap with the metal gate runner 130. The peripheral well region 11 is a region of the second conductivity type. In this example, the peripheral well region 11 is of P+ type (not shown). The impurity concentration of the peripheral well region 11 is 5.0×10 17 atoms / cm 3 or more and 5.0 x 10 19 atoms / cm 3 The impurity concentration of the peripheral well region 11 may be 2.0×10 18 atoms / cm 3 or more and 2.0 x 10 19 atoms / cm 3 It may be the following:

[0030] The semiconductor device 100 may also include a temperature sensor (not shown) that is a PN junction diode formed of polysilicon or the like, and a current detector (not shown) that simulates the operation of the transistor section 70 provided in the active section 160. The temperature sensor may be connected to the anode pad and the cathode pad via wiring. When a temperature sensor is provided, it is preferably provided in the center of the semiconductor substrate 10 in the X-axis direction and the Y-axis direction.

[0031] In a top view, the semiconductor device 100 of this example includes an edge termination structure 90 between the active section 160 and the first edge 161 or the second edge 162. The edge termination structure 90 of this example is disposed between the metal gate runner 130 and the first edge 161 or the second edge 162. The edge termination structure 90 reduces electric field concentration on the top surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a guard ring, a field plate, and a resurf, which are arranged in an annular shape surrounding the active section 160.

[0032] FIG. 2 is a diagram showing an example of the arrangement of poly gate runners 46 in the semiconductor device 100. The poly gate runners 46 connect to gate electrodes provided on the semiconductor substrate 10. In FIG. 2, the poly gate runners 46 are shown as discrete dashed lines, but the poly gate runners 46 are provided continuously along the dashed lines. The poly gate runners 46 connect to the gate conductive portion of the gate electrode. By connecting the poly gate runners 46 to the gate electrode, a gate potential can be applied to the gate electrode via the poly gate runners 46.

[0033] The poly gate runner 46 is provided above the semiconductor substrate 10. At least a portion of the poly gate runner 46 overlaps with the metal gate runner 130 in a top view. At least a portion of the poly gate runner 46 may be provided below the metal gate runner 130. Therefore, the poly gate runner 46 and the metal gate runner 130 can be connected to each other. Furthermore, at least a portion of the poly gate runner 46 is provided in the active section 160. Therefore, the poly gate runner 46 and the gate electrode of the active section 160 can be connected to each other.

[0034] In this example, the poly gate runner 46 has a transverse poly gate runner 47 and an outer periphery poly gate runner 48. The transverse poly gate runner 47 is provided so as to cross the active section 160 in a top view. In this example, the transverse poly gate runner 47 extends in the X-axis direction. The transverse poly gate runner 47 is disposed between the transistor section 70-1 and the transistor section 70-2 in a top view. By providing the transverse poly gate runner 47, the gate potential can be applied evenly to each gate electrode. Two or more transverse poly gate runners 47 may be provided.

[0035] The outer periphery poly gate runner 48 is provided so as to surround the active portion 160 in top view. The outer periphery poly gate runner 48 is disposed between the active portion 160 and the first end edge 161 or the second end edge 162 in top view. The outer periphery poly gate runner 48 may be provided so as to surround the gate pad 164.

[0036] 3 is a flowchart showing a method for forming a gate electrode of a semiconductor device 100 according to a comparative example. The method for forming a gate electrode includes a gate trench forming step S101, a gate insulating film forming step S102, a polysilicon film forming step S103, a resist forming step S104, a patterning step S105, a resist removing step S106, and an inspection step S107. Each step will be described below.

[0037] 4 is a diagram illustrating the gate trench forming step S101, showing the gate trench 45 in a top view.

[0038] The gate trench 45 in this example may have two straight portions 39 (portions of the trench that are straight along the extension direction) extending along the extension direction (Y-axis direction) and a tip portion 41 connecting the two straight portions 39.

[0039] At least a portion of the tip portion 41 is preferably curved in a top view. The tip portion 41 connects the ends of the two straight portions 39 in the Y-axis direction, thereby alleviating electric field concentration at the ends of the straight portions 39. As shown in Fig. 4, the gate trenches 45 may be arranged along an arrangement direction (X-axis direction) perpendicular to the extension direction.

[0040] Fig. 5 is a diagram showing the aa cross section of Fig. 4. Fig. 5 is an XZ cross section passing through the gate trench 45. Note that Fig. 5 shows only the vicinity of the upper surface 21 of the semiconductor substrate 10, and omits the vicinity of the lower surface of the semiconductor substrate 10.

[0041] In the gate trench formation step S101, a gate trench 45 is formed in the upper surface 21 of the semiconductor substrate 10. The gate trench 45 may be formed by anisotropic dry etching. Since the gate trench 45 is formed by anisotropic dry etching, the sidewalls of the gate trench 45 are approximately perpendicular to the upper surface 21 of the semiconductor substrate 10, as shown in FIG.

[0042] FIG. 6 is a diagram illustrating the gate insulating film forming step S102. FIG. 6 shows the same cross section as FIG. 5. In the gate insulating film forming step S102, a gate insulating film 42 is formed. The gate insulating film 42 is provided on the upper surface 21 of the semiconductor substrate 10. The gate insulating film 42 is also provided inside the gate trench 45. The gate insulating film 42 may be formed by thermal oxidation. The gate insulating film 42 may also be formed by chemical vapor deposition (CVD). In this example, the gate insulating film 42 is an oxide film.

[0043] 7 is a diagram illustrating the polysilicon deposition step S103. FIG. 7 shows the same cross section as FIG. 5. In the polysilicon deposition step S103, polysilicon 50 is deposited. The polysilicon 50 may be deposited to a predetermined thickness above the gate insulating film 42. The inside of the gate trench 45 may be filled with the polysilicon 50. The polysilicon 50 may be formed by chemical vapor deposition (CVD).

[0044] 8 is a diagram illustrating the resist formation step S104. In Fig. 8, the arrangement of the resist 180 is shown in a top view. In Fig. 8, the arrangement of the gate trench 45 on the top surface 21 is shown by dotted lines.

[0045] Fig. 9 is a diagram showing the bb cross section of Fig. 8. Fig. 9 is an XZ cross section passing through the gate trench 45. Note that Fig. 9 shows only the vicinity of the upper surface 21 of the semiconductor substrate 10, and omits the vicinity of the lower surface of the semiconductor substrate 10.

[0046] In the resist formation step S104, a resist 180 is formed above the polysilicon 50. The resist 180 may be formed by a known photo process. By providing the resist 180, the polysilicon 50 can be patterned.

[0047] 10 is a diagram illustrating the patterning step S105. In Fig. 10, the arrangement of the resist 180 is shown in a top view. In Fig. 10, the arrangement of the gate trench 45 on the top surface 21 is shown by a dotted line.

[0048] Fig. 11 is a view showing the cc cross section of Fig. 10. Fig. 11 is an XZ cross section passing through the gate trench 45. Note that Fig. 11 shows only the vicinity of the upper surface 21 of the semiconductor substrate 10, and omits the vicinity of the lower surface of the semiconductor substrate 10.

[0049] In the patterning step S105, the polysilicon 50 is patterned. The polysilicon 50 is patterned by isotropic dry etching. By patterning the polysilicon 50, a gate conductive portion 44 is formed inside the gate trench 45. Furthermore, by patterning the polysilicon 50, a poly gate runner 46 is formed above the semiconductor substrate 10. By performing the patterning step S105, the gate electrode 40 is formed.

[0050] 12 is a diagram illustrating the resist removal step S106. In FIG. 12, the arrangement of the poly gate runners 46 is shown in a top view. In FIG. 12, the arrangement of the gate trenches 45 on the top surface 21 is shown by dotted lines.

[0051] Fig. 13 is a diagram showing the dd cross section of Fig. 12. Fig. 13 is an XZ cross section passing through the gate trench 45. Note that Fig. 13 shows only the vicinity of the upper surface 21 of the semiconductor substrate 10, and omits the vicinity of the lower surface of the semiconductor substrate 10.

[0052] In the resist removal step S106, the resist 180 is removed. The resist 180 may be removed by ashing and cleaning.

[0053] 14 is a diagram illustrating the inspection step S107. FIG. 14 shows a region including the poly gate runner 46 (outer peripheral poly gate runner 48) near the gate pad 164 after the resist removal step S106. The poly gate runner 46 is the region surrounded by a thick line. In FIG. 14, the semiconductor device 100 includes a gate electrode 40, a poly gate runner 46, and a gate pad 164.

[0054] In the inspection stage S107, the semiconductor device 100 is inspected. In this example, the semiconductor device 100 is inspected for defects. The defect inspection is performed, for example, using an image matching defect inspection device. In the image matching defect inspection device, image data of an area without defects is registered in advance as a reference image, and a location with a characteristic shape is used as a reference for alignment. Therefore, accurate matching with a corresponding area on the semiconductor device 100 can be performed to determine the presence or absence of a defect. The image matching defect inspection device may be a known device. By performing defect inspection during the manufacturing process (inline), the cause of the defect can be identified and yield can be improved. Furthermore, defective products can be prevented from being distributed on the market.

[0055] In the case of image matching, inspection is performed after positioning. In this example (comparative example), the tip 41 of the gate trench 45 is used as a reference for positioning, and inspection is performed to determine whether the end position of the poly gate runner 46 is located at a predetermined position. The tip 41 of the gate trench 45 is located below the poly gate runner 46. Therefore, positioning is performed using the tip 41 of the gate trench 45, which is visible in a top view. Because the poly gate runner 46 is patterned by isotropic dry etching in the patterning step S105, the side surface of the poly gate runner 46 is not vertical. Therefore, the end position of the poly gate runner 46 may vary depending on the inclination of the side surface. Similarly, the position of the tip 41 of the gate trench 45 may also vary. Therefore, the relative position of the end of the poly gate runner 46 with respect to the tip 41 of the gate trench 45 varies. As a result, during defect inspection, portions that do not match the reference image are detected as pseudo defects 190. Therefore, it is preferable to improve positioning accuracy for accurate inspection.

[0056] 15 is a flowchart showing a method for forming a gate electrode of a semiconductor device 100 according to an embodiment. The method for forming a gate electrode includes a gate trench forming step S201, a gate insulating film forming step S202, a polysilicon film forming step S203, a resist forming step S204, a patterning step S205, a resist removing step S206, and an inspection step S207. Each step will be described below. Note that the gate trench forming step S201, the gate insulating film forming step S202, and the polysilicon film forming step S203 may be the same as the gate trench forming step S101, the gate insulating film forming step S102, and the polysilicon film forming step S103, respectively. Therefore, descriptions of the gate trench forming step S201, the gate insulating film forming step S202, and the polysilicon film forming step S203 will be omitted.

[0057] 16 is a diagram illustrating the resist formation step S204. In Fig. 16, the arrangement of the resist 180 is shown in a top view. In Fig. 16, the arrangement of the gate trench 45 on the top surface 21 is shown by a dotted line.

[0058] Fig. 17 is a diagram showing the ee cross section of Fig. 16. Fig. 17 is an XZ cross section passing through the gate trench 45. Note that Fig. 17 shows only the vicinity of the upper surface 21 of the semiconductor substrate 10, and omits the vicinity of the lower surface of the semiconductor substrate 10.

[0059] In resist formation step S204, resist 180 is formed above polysilicon 50. In this example, resist 180 has pattern 182. In FIGS. 16 and 17, pattern 182 exposes polysilicon 50. Because resist 180 has pattern 182, through-holes can be formed in poly gate runner 46 in patterning step S205. Therefore, to form through-holes in patterning step S205, it is sufficient to change the photomask used to pattern the resist, preventing an increase in the number of steps.

[0060] 18 is a diagram illustrating the patterning step S205. In FIG. 18, the arrangement of the resist 180 is shown in a top view. In FIG. 18, the arrangement of the gate trench 45 on the top surface 21 is shown by a dotted line.

[0061] Fig. 19 is a diagram showing the ff cross section of Fig. 18. Fig. 19 is an XZ cross section passing through the gate trench 45. Note that Fig. 19 shows only the vicinity of the upper surface 21 of the semiconductor substrate 10, and omits the vicinity of the lower surface of the semiconductor substrate 10.

[0062] In patterning step S205, polysilicon 50 is patterned in the same manner as in patterning step S105 of FIG. 3. In patterning step S205, poly gate runner 46 has through-hole 184. In this example, resist 180 has pattern 182, so that through-hole 184 can be formed in poly gate runner 46. In FIG. 19, through-hole 184 exposes gate insulating film 42. Through-hole 184 may have the same shape as pattern 182 in top view. Through-hole 184 is surrounded by poly gate runner 46. In other words, through-hole 184 is not provided at the end of poly gate runner 46. The detailed shape of through-hole 184 will be described with reference to FIG. 27.

[0063] 20 is a diagram illustrating the resist removal step S206. The arrangement of the poly gate runners 46 is shown in a top view in FIG. 20. The arrangement of the gate trenches 45 on the top surface 21 is shown by dotted lines in FIG.

[0064] Fig. 21 is a diagram showing the gg cross section of Fig. 20. Fig. 21 is an XZ cross section passing through the gate trench 45. Note that Fig. 21 shows only the vicinity of the upper surface 21 of the semiconductor substrate 10, and omits the vicinity of the lower surface of the semiconductor substrate 10.

[0065] In resist removal step S206, resist 180 is removed in the same manner as in resist removal step S106 of Fig. 3. After resist 180 is removed, through-hole 184 exposes gate insulating film 42 (oxide film in this example). Therefore, through-hole 184 of poly gate runner 46 can be seen.

[0066] Fig. 22 is a diagram illustrating inspection step S207. Fig. 22 shows a region including the poly gate runner 46 (outer peripheral poly gate runner 48) near the gate pad 164 after resist removal step S206. The poly gate runner 46 is the region surrounded by a thick line. In Fig. 22, the semiconductor device 100 includes a gate electrode 40, a poly gate runner 46, and a gate pad 164.

[0067] In inspection step S207, the semiconductor device 100 is inspected for defects. In this example (embodiment), the through hole 184 is used as a reference for positioning. That is, in inspection step S207, inspection is performed by positioning using the through hole 184. Because the through hole 184 is formed in the same process as the patterning of the poly gate runner 46, the inclination of the side surface of the through hole 184 and the inclination of the side surface of the poly gate runner 46 are approximately the same. This makes it possible to reduce variations in the relative position of the end of the poly gate runner 46 with respect to the through hole 184. This makes it possible to improve positioning accuracy and prevent the occurrence of false defects.

[0068] FIG. 23 shows an example of the arrangement of the interlayer insulating film 38 and the metal gate runner 130 in a top view. FIG. 23 shows the arrangement of the interlayer insulating film 38 and the metal gate runner 130 in a top view when they are formed after the inspection step S207. In FIG. 23, the arrangement of the gate trench 45 on the top surface 21 is indicated by dotted lines. In FIG. 23, the through hole 184 of the poly gate runner 46 is also indicated by dotted lines. Also in FIG. 23, the contact hole 54 in the interlayer insulating film 38 is indicated by a dashed line.

[0069] Fig. 24 is a diagram showing the hh cross section of Fig. 23. Fig. 24 is an XZ cross section passing through the gate trench 45. Note that Fig. 24 does not show the contact hole 54. Note that Fig. 24 shows only the vicinity of the upper surface 21 of the semiconductor substrate 10, and omits the vicinity of the lower surface of the semiconductor substrate 10.

[0070] The interlayer insulating film 38 is provided above the semiconductor substrate 10. The interlayer insulating film 38 may be provided between the poly gate runner 46 and the metal gate runner 130. The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one layer of an insulating film such as silicate glass doped with impurities such as boron or phosphorus, a thermal oxide film, and other insulating films. A contact hole 54 is provided in the interlayer insulating film 38. The poly gate runner 46 may be connected to the metal gate runner 130 through the contact hole 54. In FIG. 23 , the contact hole 54 does not overlap with the through hole 184 in a top view.

[0071] 24, the through hole 184 is filled with the interlayer insulating film 38. That is, the interlayer insulating film 38 is provided inside the through hole 184 of the poly gate runner 46. The interlayer insulating film 38 is also in contact with the gate insulating film 42 via the through hole 184. Since the poly gate runner 46 has the through hole 184, the through hole 184 is filled with the interlayer insulating film 38.

[0072] 24, the metal gate runner 130 is recessed above the through-hole 184. That is, the metal gate runner 130 has a recessed portion above the through-hole 184. Because the poly gate runner 46 has the through-hole 184, the metal gate runner 130 is recessed.

[0073] 25 shows another example of the arrangement of the interlayer insulating film 38 and the metal gate runner 130 in a top view. FIG. 25 differs from FIG. 23 in that the contact hole 54 overlaps the through hole 184 in a top view. Other configurations in FIG. 25 may be the same as those in FIG. 23. The contact hole 54 may overlap the through hole 184 in a top view.

[0074] Fig. 26 shows an example of the arrangement of through holes 184 in a top view of the poly gate runner 46. Fig. 26 shows only the arrangement of the through holes 184 in the poly gate runner 46, and the dimensions do not match those of other examples.

[0075] In this example, the poly gate runner 46 has a plurality of through holes 184. It is preferable to provide at least one through hole 184 per field of view for defect inspection. In other words, more through holes 184 may be provided in the poly gate runner 46 than in the example of FIG. 26 .

[0076] 26, the traverse poly gate runner 47 has a through hole 184. Also, in FIG.

[0077] The edge of the outer periphery poly gate runner 48 parallel to the X-axis direction is referred to as edge 49-1. Furthermore, the edge of the outer periphery poly gate runner 48 parallel to the Y-axis direction is referred to as edge 49-2. The outer periphery poly gate runner 48 has two edge sides 49-1 and two edge sides 49-2. In this example, two or more through holes 184 are discretely arranged on each edge of the multiple edge sides 49. In this way, multiple through holes 184 may be arranged on each edge.

[0078] FIG. 27 is a diagram illustrating the shape of the through-hole 184 in detail. FIG. 27 shows a poly gate runner 46 extending in the Y-axis direction. In this example, the through-hole 184 has a cross shape. Because the through-hole 184 has a cross shape, it has many ends, making it easy to use as a reference for alignment. Although the through-hole 184 is represented in a cross shape in this specification, the shape of the through-hole 184 is not limited to a cross shape.

[0079] Through hole 184 has an extending portion 186 and a protruding portion 188. Extending portion 186 is the portion of through hole 184 that extends in the X-axis direction. Protruding portion 188 is the portion of through hole 184 that protrudes in the Y-axis direction. Through hole 184 has two protruding portions 188 (protruding portion 188-1 and protruding portion 188-2). In FIG. 27, the boundary between extending portion 186 and protruding portion 188 is indicated by a dashed dotted line.

[0080] The width d2 of the extension portion 186 in the X-axis direction may be 1 / 3 or less of the width d1 of the poly gate runner 46 in the X-axis direction. The width d2 of the extension portion 186 in the X-axis direction may be the maximum width of the through-hole 184 in the X-axis direction. The width d1 of the poly gate runner 46 in the X-axis direction may be the minimum width of the poly gate runner 46 in the X-axis and Y-axis directions. If the width of the through-hole 184 is too large, the resistance value of the poly gate runner 46 increases, so it is preferable that the width d2 of the extension portion 186 in the X-axis direction be 1 / 3 or less of the width d1 of the poly gate runner 46 in the X-axis direction. Furthermore, if the width of the through-hole 184 is too small, it cannot be used as a reference for alignment, so the width d2 of the extension portion 186 in the X-axis direction may be 1 / 10 or more of the width d1 of the poly gate runner 46 in the X-axis direction. The width d2 of the extension portion 186 in the X-axis direction is, for example, approximately 1.2 μm. The width d2 of the extension 186 in the X-axis direction may be 1.2 μm or less.

[0081] The width d3 of the extension 186 in the Y-axis direction may be 0.1 μm or more. The width d3 of the extension 186 in the Y-axis direction may be 0.5 μm or less. The width d4 of the protrusion 188-1 in the X-axis direction may be 0.1 μm or more. The width d4 of the protrusion 188-1 in the X-axis direction may be 0.5 μm or less. The width d5 ​​of the protrusion 188-1 in the Y-axis direction may be 0.1 μm or more. The width d5 ​​of the protrusion 188-1 in the Y-axis direction may be 0.5 μm or less. The width of the protrusion 188-2 may also be the same as that of the protrusion 188-1.

[0082] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0083] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0084] 10 semiconductor substrate, 11 peripheral well region, 21 upper surface, 38 interlayer insulating film, 39 straight portion, 40 gate electrode, 41 tip portion, 42 gate insulating film, 44 gate conductive portion, 45 gate trench, 46 poly gate runner, 47 crossing poly gate runner, 48 peripheral poly gate runner, 49 edge, 50 polysilicon, 70 transistor portion, 90 edge termination structure portion, 54 contact hole, 100 semiconductor device, 130 metal gate runner, 160 active portion, 161 first edge, 162 second edge, 164 gate pad, 180 resist, 182 pattern, 184 through hole, 186 extension portion, 188 protrusion portion, 190 pseudo defect

Claims

1. a semiconductor substrate; a gate pad provided above the semiconductor substrate and to which a gate potential is applied; a gate electrode provided on the semiconductor substrate; a poly gate runner provided above the semiconductor substrate, connected to the gate electrode, and applying the gate potential to the gate electrode; Equipped with the poly gate runner has a portion surrounding the gate pad; The poly gate runner has a through hole in the portion surrounding the gate pad. Semiconductor device.

2. a semiconductor substrate; a gate electrode provided on the semiconductor substrate; a poly gate runner provided above the semiconductor substrate and connected to the gate electrode; Equipped with the poly gate runner has a through hole; When viewed from above, the through hole is an extension portion extending in a first direction; a protruding portion protruding from the extending portion at a portion other than both ends in the first direction of the extending portion; A semiconductor device having:

3. a semiconductor substrate; a gate electrode provided on the semiconductor substrate; a poly gate runner provided above the semiconductor substrate and connected to the gate electrode; Equipped with the poly gate runner has a through hole; an active portion is provided in the semiconductor substrate; the poly gate runner has a traversing poly gate runner provided so as to traverse the active portion in a top view, The transverse poly gate runner has the through hole. Semiconductor device.

4. a semiconductor substrate; a gate electrode provided on the semiconductor substrate; a poly gate runner provided above the semiconductor substrate and connected to the gate electrode; a metal gate runner disposed above the poly gate runner; an interlayer insulating film provided above the semiconductor substrate; Equipped with the poly gate runner has a through hole; The metal gate runner is recessed above the through hole, the interlayer insulating film has a contact hole connecting the poly gate runner and the metal gate runner; The contact hole overlaps with the through hole in a top view. Semiconductor device.

5. Further comprising an oxide film provided on the semiconductor substrate, The through-hole exposes the oxide film. The semiconductor device according to claim 1 .

6. further comprising an interlayer insulating film provided above the semiconductor substrate; The through-hole is filled with the interlayer insulating film. The semiconductor device according to claim 5 .

7. The interlayer insulating film is in contact with the oxide film through the through hole. The semiconductor device according to claim 6.

8. The poly gate runner has a plurality of the through holes. The semiconductor device according to claim 1 .

9. an active portion is provided in the semiconductor substrate; the poly gate runner has an outer periphery poly gate runner provided so as to surround the active portion in a top view, The outer periphery side poly gate runner has the through hole. The semiconductor device according to claim 2 .

10. the outer periphery side poly gate runner has a plurality of edge sides, Two or more of the through holes are discretely arranged on each of the plurality of end sides. The semiconductor device according to claim 9 .

11. a metal gate runner disposed above the poly gate runner; The metal gate runner is recessed above the through hole. The semiconductor device according to claim 1 .

12. further comprising an interlayer insulating film provided above the semiconductor substrate; the interlayer insulating film has a contact hole connecting the poly gate runner and the metal gate runner; The contact hole does not overlap the through hole in top view. The semiconductor device according to claim 11.

13. a semiconductor substrate; a gate electrode provided on the semiconductor substrate; a poly gate runner provided above the semiconductor substrate and connected to the gate electrode; A method for manufacturing a semiconductor device comprising: forming a through hole in the poly gate runner; an inspection step of inspecting the semiconductor device for defects; Equipped with In the inspection step, the inspection is performed by positioning using the through-hole. A method for manufacturing a semiconductor device.

14. a patterning step of patterning polysilicon to form the poly gate runner; In the patterning step, the through holes are formed in the poly gate runner. The method for manufacturing a semiconductor device according to claim 13.

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