Semiconductor device manufacturing method, slurry, and resin material

Abstract

An example of a manufacturing method using hybrid bonding for semiconductor packages is disclosed. In this method, a semiconductor substrate 100 having an electrode 102 and an insulating layer 103 on its surface side and a semiconductor substrate 200 having an electrode 202 and an insulating layer 203 on its surface side are prepared. The semiconductor substrate 100 is singulated to obtain multiple semiconductor chips 110. An insulating portion 103A of the semiconductor chip 110 is bonded to the insulating layer 203 of the semiconductor substrate 200. Then, the electrode 102 of the semiconductor chip 110 is bonded to the electrode 202 of the semiconductor substrate 200. In this manufacturing method, the insulating portion 103A is an inorganic insulating layer, and the insulating layer 203 is an organic insulating layer. When the insulating portion 103A is bonded to the insulating layer 203, the electrode 102 is spaced apart from the electrode 202. This prevents misalignment caused by the electrodes 102 and 202 contacting each other first.

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a semiconductor device, a slurry, and a resin material. [Background technology]

[0002] In recent years, with the rapid advancement in functionality of electronic devices, such as AI and HPC, semiconductor packages have become larger and denser. These package structures are not limited to surface mounting, but are becoming more complex and diverse, with inorganic (silicon) or organic interposer (Bridge die / RDL) technology, 2.xD mounting using these, and 3D mounting (HBM / Chiplet) technology utilizing TSV. For example, Resonac Inc., based at its "Packaging Solutions Center," is developing next-generation semiconductor packaging process technology from the perspective of its customers (semiconductor manufacturers), combining mounting processes and materials.

[0003] As such a technology in the field of semiconductor packaging, Patent Documents 1 to 4 disclose examples of hybrid bonding technology used in a wafer-to-wafer (W2W) bonding process or a chip-on-wafer (CoW) bonding process in 3D mounting of semiconductor devices. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-197430 [Patent Document 2] Patent Publication No. 2021-197431 [Patent Document 3] Special Publication No. 2018-528622 [Patent Document 4] International Publication No. 2024 / 172044 Summary of the Invention [Problem to be solved by the invention]

[0005] When three-dimensionally mounting semiconductor chips (e.g., die-to-wafer (D2W) or wafer-to-wafer (W2W) bonding) is performed, the use of hybrid bonding technology is being considered to enable miniaturization of connection terminals. In this case, to prevent bonding failure due to debris (cutting fragments) adhering to the bonding interface, it is considered to use organic insulating materials for both insulating layers to be bonded, and the organic insulating layer can absorb the debris. The method of bonding organic insulating layers requires heating, and each electrode is made to protrude from the organic insulating layer to take into account thermal expansion during heating. However, this method can cause the electrodes to come into contact with each other prematurely when bonding the organic insulating layers, resulting in misalignment. Therefore, a method of manufacturing a semiconductor device that can reduce misalignment is desired.

[0006] An object of the present disclosure is to provide a method for manufacturing a semiconductor device that can reduce misalignment between electrodes to be bonded in a hybrid bonding method. [Means for solving the problem]

[0007] (1) A method for manufacturing a semiconductor device according to one aspect of the present disclosure includes the steps of: preparing a first substrate having a first insulating layer and a first electrode on its surface; preparing a second substrate having a second insulating layer and a second electrode on its surface; bonding the first insulating layer to the second insulating layer; and bonding the first electrode to the second electrode. At least one of the first substrate and the second substrate includes a semiconductor substrate. The first insulating layer is an inorganic insulating layer, and the second insulating layer is an organic insulating layer. When the first insulating layer is bonded to the second insulating layer, the first surface of the first electrode is spaced apart from the second surface of the second electrode.

[0008] In the semiconductor device manufacturing method (1) above, the first insulating layer is an inorganic insulating layer, and the second insulating layer is an organic insulating layer. In this case, the heating temperature when bonding the insulating layers together can be lower than the heating temperature when bonding the organic insulating layers together. This is because, when bonding organic insulating layers together, the organic material (resin) needs to be thermally expanded to form both electrodes in a convex shape due to thermal expansion. However, when bonding an organic insulating layer and an inorganic insulating layer, one electrode can be formed in a concave shape due to thermal expansion, making it possible to bond the insulating layers together without thermal expansion. This increases the design freedom for the step between the electrodes and the insulating layers, and when bonding the first insulating layer to the second insulating layer, the amount of unevenness of the electrodes can be set so that the first surface of the first electrode is separated from the second surface of the second electrode. Therefore, when bonding the insulating layers together, the electrodes can be bonded without contacting each other first, thereby reducing misalignment between the electrodes during the subsequent electrode bonding. Furthermore, since one of the insulating layers to be bonded (the second insulating layer) is an organic insulating layer, debris at the bonding interface can be absorbed by the organic insulating layer, and therefore, this manufacturing method can prevent bonding defects.

[0009] (2) In the method for manufacturing a semiconductor device described in (1) above, when joining the first insulating layer to the second insulating layer, it is preferable that the protruding portion of the first electrode, including the first surface, protrudes from the third surface of the first insulating layer, and the second surface of the second electrode is located in a region recessed inward from the fourth surface of the second insulating layer.

[0010] (3) In the method for manufacturing a semiconductor device according to (2), the width or diameter of the first electrode is preferably smaller than the width or diameter of the second electrode. When the first insulating layer is bonded to the second insulating layer, the protruding portion of the first electrode is preferably located in a region recessed inward from the fourth surface of the second insulating layer, and the first electrode faces the second electrode at a distance.

[0011] (4) In the method for manufacturing a semiconductor device according to (2) or (3), when the first insulating layer is bonded to the second insulating layer, the amount by which the first electrode protrudes from the third surface of the first insulating layer is preferably smaller than the amount by which the second electrode recesses from the fourth surface of the second insulating layer. In this case, contact between the electrodes can be reliably prevented when bonding the insulating layers together.

[0012] (5) In the method for manufacturing a semiconductor device according to any one of (2) to (4), the bottom and side surfaces of the first electrode are preferably covered with a first barrier layer, and when the first electrode is bonded to the second electrode, the first surface of the first electrode is preferably bonded to the second electrode, thereby preventing migration of the first electrode.

[0013] (6) In the method for manufacturing a semiconductor device according to any one of (2) to (5), the bottom and side surfaces of the second electrode are preferably covered with a second barrier layer, and the first insulating layer preferably includes a third barrier layer on its surface side. When the first electrode is bonded to the second electrode, the second surface of the second electrode is preferably covered with the third barrier layer except for the area bonded to the first electrode. In this case, migration of the second electrode can be prevented.

[0014] (7) In the method for manufacturing a semiconductor device according to (6) above, the third barrier layer preferably contains SiCN, SiN, or SiCH or SiO2. In this case, the third barrier layer can be easily formed. Furthermore, migration of the second electrode can be reliably prevented.

[0015] (8) In the method for manufacturing a semiconductor device described in (1) above, when the first insulating layer is bonded to the second insulating layer, the first surface of the first electrode may be located in a region recessed inward from the third surface of the first insulating layer, and the protruding portion of the second electrode, including the second surface, may protrude from the fourth surface of the second insulating layer.

[0016] (9) In the method for manufacturing a semiconductor device according to (8), the width or diameter of the second electrode may be smaller than the width or diameter of the first electrode. When the first insulating layer is bonded to the second insulating layer, the protruding portion of the second electrode may be located in a region recessed inward from the third surface of the first insulating layer, and the second electrode may face the first electrode at a distance.

[0017] (10) In the method for manufacturing a semiconductor device according to (8) or (9), when the first insulating layer is bonded to the second insulating layer, the amount by which the second electrode protrudes from the fourth surface of the second insulating layer may be smaller than the amount by which the first electrode recesses from the third surface of the first insulating layer. In this case, contact between the electrodes can be reliably prevented when bonding the insulating layers together.

[0018] (11) The method for manufacturing a semiconductor device according to any one of (1) to (10) above may further include a step of polishing the first substrate and the second substrate. In the polishing step, the first electrode may be protruded and the second electrode may be recessed, or the first electrode may be recessed and the second electrode may be protruded. In this case, the amount of unevenness of the electrodes can be set while polishing the electrodes and the insulating layer.

[0019] (12) The method for manufacturing a semiconductor device according to any one of (1) to (11) above may further include a step of polishing the second substrate. In the step of polishing the second substrate, the second insulating layer is preferably polished by a CMP method using a slurry containing abrasive grains of at least one of alumina particles and silica particles. In this case, the organic insulating layer can be polished at high speed, thereby improving the manufacturing efficiency of the semiconductor device.

[0020] (13) In the method for manufacturing a semiconductor device according to any one of (1) to (12) above, the heating temperature when bonding the first insulating layer to the second insulating layer is preferably 150° C. or less. In this case, the insulating layers are bonded together while suppressing thermal expansion of the organic insulating layer, and positional displacement of the electrodes can be prevented.

[0021] (14) In the method for manufacturing a semiconductor device according to (13), the heating temperature when joining the first electrode to the second electrode may be 200° C. or higher. In this case, the joining of the first electrode and the second electrode can be ensured.

[0022] (15) In the method for manufacturing a semiconductor device according to any one of (1) to (14), at least one of the first substrate and the second substrate is preferably manufactured by dividing a semiconductor wafer or a semiconductor panel having an insulating layer and a plurality of electrodes on its surface side. In this case, a semiconductor device having a Chip-on-Wafer (CoW) structure or a Chip-to-Chip (C2C) structure can be manufactured.

[0023] (16) In the method for manufacturing a semiconductor device according to (15), the first substrate is preferably produced by dividing a semiconductor wafer or a semiconductor panel having an insulating layer and a plurality of electrodes on its surface. When the insulating layer is made of an inorganic material, it is easier to miniaturize the electrodes in the insulating layer than when the insulating layer is made of an organic material. Therefore, this manufacturing method allows the electrodes of the divided semiconductor chips to be further miniaturized.

[0024] (17) In any of the above methods for manufacturing a semiconductor device (1) to (16), the resin material forming the second insulating layer preferably has a linear expansion coefficient of 40 ppm / K or less. In this case, thermal expansion of the second insulating layer due to heating when bonding electrodes can be suppressed, thereby reducing residual stress formed on the bonding surfaces.

[0025] (18) In the method for manufacturing a semiconductor device according to (17) above, it is further preferable that the resin material forming the second insulating layer has a linear expansion coefficient of 30 ppm / K or less. In this case, thermal expansion of the second insulating layer due to heating when bonding electrodes can be further suppressed, and residual stress formed on the bonding surfaces can be further reduced.

[0026] (19) In the method for manufacturing a semiconductor device according to any one of (1) to (18), the resin material forming the second insulating layer may be a curable composition containing a maleimide compound having a maleimide group and a reactive component other than the maleimide compound, and the reactive component may be at least one of a styrene compound and an allyl compound. In this case, by bonding the insulating layer at a lower temperature, the thermal effects on the semiconductor device to be manufactured can be reduced.

[0027] (20) In any of the methods for manufacturing a semiconductor device described above in (1) to (18), the resin material forming the second insulating layer may be a curable composition containing a block maleimide compound having a maleimide group blocked with a blocking agent that dissociates upon heating, and a reactive component, which is a compound having a reactive group that reacts with the maleimide group or a compound that generates the reactive group upon heating. The reactive component may be at least one of a styrene-based compound and an allyl compound. In this case, the viscosity stability of the curable composition containing the maleimide compound at room temperature is improved, and excellent storage stability can be achieved.

[0028] (21) In the method for manufacturing a semiconductor device according to any one of (1) to (20) above, it is preferable that the first substrate and the second substrate each include a semiconductor substrate.

[0029] (22) In another aspect, the present disclosure relates to a slurry. This slurry is used to polish a second substrate by a CMP method in the semiconductor device manufacturing method described above in (12). This slurry contains abrasive particles of at least one of alumina particles and silica particles. This allows for high-speed polishing of an organic insulating layer.

[0030] (23) In yet another aspect, the present disclosure relates to a resin material. This resin material is used to form a second insulating layer in the semiconductor device manufacturing method according to any one of (1) to (21) above. This resin material is a curable composition containing a maleimide compound having a maleimide group and at least one of a styrene compound and an allyl compound as a reactive component. This allows the insulating layer to be bonded at a low temperature. [Effects of the Invention]

[0031] According to the present disclosure, in a hybrid bonding method, it is possible to reduce misalignment between electrodes to be bonded. [Brief explanation of the drawings]

[0032] [Figure 1] FIG. 1 is a cross-sectional view schematically illustrating an example of a semiconductor device (CoW) manufactured by a method according to an embodiment of the present disclosure. [Figure 2] 2(a) to 2(d) are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. [Figure 3] 3(a) to 3(c) are cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment, showing steps subsequent to those shown in FIG. [Figure 4] 4(a) and 4(b) are enlarged cross-sectional views of the regions S1 and S2 shown in FIG. 2(c) and 2(d). [Figure 5] 5(a) to 5(c) are cross-sectional views illustrating the bonding step in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 6(a) to 6(c) are cross-sectional views illustrating the bonding step in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 7] FIG. 7 is a cross-sectional view for explaining a method for calculating the protrusion amount and the recess amount in the method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a table showing an example for calculating the thickness of the organic insulating layer in the manufacturing method according to the first embodiment. [Figure 9] FIG. 9 is a table showing an example for calculating the coefficient of linear expansion (CTE) of the organic insulating layer in the manufacturing method according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view for explaining a method for calculating the protrusion amount and the recess amount in the method for manufacturing a semiconductor device according to the second embodiment. [Figure 11] FIG. 11 is a table showing an example for calculating the thickness of the organic insulating layer in the manufacturing method according to the second embodiment. [Figure 12] FIG. 12 is a table showing an example for calculating the coefficient of linear expansion (CTE) of the organic insulating layer in the manufacturing method according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0033] Hereinafter, several embodiments of the present disclosure will be described in detail, with reference to the drawings as necessary. In the following description, the same or equivalent parts will be denoted by the same reference numerals, and duplicate explanations will be omitted. Positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings unless otherwise specified. When terms such as "left," "right," "front," "back," "top," "bottom," "upper," and "lower" are used in the description and claims of this specification, these are intended for explanatory purposes and do not necessarily mean that these relative positions will always be the same. The dimensional ratios of the drawings are not limited to those shown in the drawings.

[0034] In this specification, the term "layer" encompasses not only a structure with a shape formed over the entire surface when observed in a plan view, but also a structure with a shape formed on a portion of the surface. In this specification, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes, as long as the intended effect of the process is achieved. Numerical ranges indicated using "to" indicate ranges that include the numerical values ​​before and after "to" as the minimum and maximum values, respectively.

[0035] (Configuration of semiconductor device) FIG. 1 is a cross-sectional view schematically illustrating an example of a semiconductor device manufactured by a method according to an embodiment. As shown in FIG. 1, the semiconductor device 1 is, for example, an example of a semiconductor package, and includes multiple semiconductor chips 10 and a semiconductor substrate 20. The semiconductor chips 10 are fabricated by dicing a semiconductor substrate 100 (described later) into individual chips. The multiple semiconductor chips 10 are mounted on the semiconductor substrate 20 to form a three-dimensional mounting structure. The semiconductor substrate 20 may be a substrate on which multiple semiconductor chips, such as LSI (Large Scale Integrated Circuit) chips or CMOS (Complementary Metal Oxide Semiconductor) sensors, are formed at locations corresponding to the semiconductor chips 10. Each semiconductor chip 10 may be a semiconductor chip such as an LSI or memory. The multiple semiconductor chips 10 and the semiconductor substrate 20 are finely bonded to each other by hybrid bonding (described later) to firmly and without misalignment, with their respective terminal electrodes and surrounding insulating layers. 1 , and a substrate portion that is a part of the semiconductor substrate 20 corresponding to the semiconductor chip 10. The manufacturing method according to this embodiment may also be applied to a C2C bonding process, in which case semiconductor chips are bonded to each other.

[0036] (Method for manufacturing a semiconductor device according to the first embodiment) Next, a method for manufacturing a semiconductor device according to the first embodiment will be described with reference to Fig. 2 to Fig. 5. Fig. 2 and Fig. 3 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the first embodiment. Fig. 4 is a cross-sectional view showing an enlargement of regions S1 and S2 shown in Fig. 2(c) and (d). Fig. 5 is a cross-sectional view for explaining a bonding step in the method for manufacturing a semiconductor device according to the first embodiment.

[0037] The semiconductor device 1 shown in FIG. 1 can be manufactured, for example, through the following steps (a) to (h). (a) preparing a first substrate having a first insulating layer and a plurality of first electrodes on a surface side thereof; (b) preparing a second substrate having a second insulating layer and a plurality of second electrodes on a surface side thereof; (c) polishing the surface of the first insulating layer and the surfaces of the first electrodes disposed on the surface side of the first substrate; (d) polishing the surface of the second insulating layer and the surfaces of the second electrodes disposed on the surface side of the second substrate; (e) A step of dividing the polished first substrate into individual semiconductor chips, each of which has an insulating portion corresponding to the first insulating layer and at least one first electrode. (f) A step of aligning the first electrodes of at least one semiconductor chip of the plurality of semiconductor chips with the second electrodes of the second substrate. (g) A step of bonding the insulating portion (first insulating layer) of the semiconductor chip to the second insulating layer of the second substrate. (h) A step of bonding the first electrode of the semiconductor chip to the second electrode of the second substrate.

[0038] [Process (a)] Step (a) is a step of preparing a semiconductor substrate 100 (first substrate) including a silicon substrate on which integrated circuits each including semiconductor elements and interconnections connecting them are formed, corresponding to a plurality of semiconductor chips 10. In step (a), as shown in FIG. 2(a), a plurality of electrodes 102 (a plurality of first electrodes) made of copper, aluminum, or the like are provided at predetermined intervals on a surface 101a of a substrate body 101 made of a semiconductor such as silicon, and an insulating layer 103 (a first insulating layer) made of an inorganic material such as silicon dioxide (SiO2) is also provided. Each electrode 102 is a terminal electrode for exposing the integrated circuits formed on the substrate body 101 to the outside through the insulating layer 103. The width or diameter of each electrode 102 may be 0.1 μm to 5 μm. The thickness of the insulating layer 103 may be 1 μm to 20 μm, or may be 1 μm or less. By making the insulating layer 103 sufficiently thin, the wiring formed from the electrodes 102 can be made finer. The insulating layer 103 may be provided on the surface 101a of the substrate body 101, and then the plurality of electrodes 102 may be provided, or the insulating layer 103 may be provided on the surface 101a of the substrate body 101. The plurality of electrodes 102 may be produced by, for example, electrolytic plating, or may be produced by other known methods.

[0039] When forming the multiple electrodes 102, a barrier layer 104 (first barrier layer) covering the bottom surface 102b and side surface 102c (outer peripheral surface) of each electrode 102 may be formed between each electrode 102 and the insulating layer 103 (see (a) of FIG. 4). The barrier layer 104 is a metal layer for preventing diffusion of the material (e.g., copper) constituting the electrode 102, and contains at least one metal material selected from the group consisting of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold. The barrier layer 104 can be formed by, for example, sputtering. The thickness of the barrier layer 104 is, for example, 0.001 μm to 0.5 μm.

[0040] When forming the insulating layer 103, a barrier layer 105 (third barrier layer) may be further formed on the surface side of the insulating layer 103 (see (a) of FIG. 4). The barrier layer 105 is formed on the surface side of the insulating layer 103 excluding the region where the plurality of electrodes 102 are formed. The barrier layer 105 is an inorganic layer for preventing diffusion of a material (e.g., copper) constituting the electrodes 202 described below, and contains, for example, SiCN, SiN, SiCH, or SiO2. The barrier layer 105 can be formed by, for example, CVD or ALD. The thickness of the barrier layer 105 is, for example, 0.01 μm to 1 μm.

[0041] [Step (b)] Step (b) corresponds to the semiconductor substrate 20 and is a step of preparing a semiconductor substrate 200 (second substrate) including a silicon substrate on which an integrated circuit composed of semiconductor elements and wiring connecting the elements is formed. In step (b), as shown in FIG. 2(b), a plurality of electrodes 202 (a plurality of second electrodes) made of copper, aluminum, or the like are provided at predetermined intervals on a surface 201a of a substrate body 201 made of silicon or the like, and an insulating layer 203 (second insulating layer) made of an organic material is also provided. Each electrode 202 is a terminal electrode for exposing the integrated circuit or the like formed on the substrate body 201 to the outside through the insulating layer 203. The width or diameter of each electrode 202 may be 0.1 μm to 5 μm. In this embodiment, the width or diameter of the electrodes 202 of the semiconductor substrate 200 is equal to or larger than the width or diameter of the electrodes 102 of the semiconductor substrate 100. The insulating layer 203 may be provided on the surface 201a of the substrate body 201, and then the plurality of electrodes 202 may be provided, or the insulating layer 203 may be provided on the surface 201a of the substrate body 201. The plurality of electrodes 202 may be fabricated using, for example, a semi-additive method, or may be fabricated using other known methods.

[0042] The insulating layer 203 used in step (b) is formed to contain an organic material. Examples of the organic material used for these insulating layers include polyimide, polyimide precursors (e.g., polyimide esters or polyamic acids), polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and PBO precursors. These organic materials have a lower elastic modulus and are softer than inorganic materials such as silicon dioxide (SiO2). By using such organic materials, when bonding insulating layers together in step (g) described below, even if debris (cut pieces) is present on the insulating layers, it is absorbed into the insulating layer 203, preventing bonding defects due to debris and ensuring reliable bonding of the insulating layers. The elastic modulus of the organic material constituting the insulating layer 203 may be, for example, 7.0 GPa or less, 5.0 GPa or less, 3.5 GPa or less, 3.0 GPa or less, or 2.5 GPa or less. The elastic modulus here refers to Young's modulus. The organic material constituting the insulating layer 203 may be a material having a coefficient of linear expansion (CTE) calculated by a method described below, and may be, for example, an organic material having a CTE of 40 ppm / K or less, or an organic material having a CTE of 30 ppm / K or less. The coefficient of linear expansion (CTE) here is the value at a so-called CTE (α1) below the glass transition temperature Tg.

[0043] The organic materials used for the insulating layer are liquid or soluble in a solvent, and therefore the insulating layer 203 can be easily formed as a thin film by spin coating or the like. Furthermore, these organic materials are heat-resistant and can withstand the temperatures (e.g., high temperatures of 300°C or higher) used when bonding the electrodes 102 and 202 in step (h) described below, and the bonding between the insulating layers does not deteriorate due to high temperatures. The organic material constituting the insulating layer 203 may include a photosensitive resin or a thermosetting resin. The organic material constituting the insulating layer 203 may also be a thermosetting non-conductive film (NCF), an underfill material, a polyimide-based material, or an epoxy-based material.

[0044] The thickness of the insulating layer 203 may be 0.5 μm to 5 μm, or may be thinner than 0.5 μm. By making the insulating layer 203 sufficiently thin, the wiring formed from the electrodes 202 can be made finer. For example, the minimum size (electrode width) of each electrode 202 formed in the insulating layer 203 is determined by the thickness of the insulating layer 203 and the aspect ratio of the photosensitive material used. When the aspect ratio of the photosensitive material is, for example, 1:1 (opening width:depth), the thickness of the insulating layer 203 is 5 μm or less, so that the electrode width of the electrode 202 can be 5 μm or less. The thickness of the insulating layer 203 may be thicker than 5 μm. In this case, when the insulating layers are bonded together in step (g) described below, more debris can be embedded in the resin insulating layer 203, allowing the insulating layers to be bonded more reliably. Furthermore, the resin insulating layer can alleviate stress when bonding the insulating layers together, thereby improving the adhesion between the insulating layers.

[0045] The thickness of insulating layer 203 may be 0.5 μm or more. In this case, by embedding minute debris in the resin insulating layer, the connection between insulating layer 103 and insulating layer 203 can be improved. For example, the size of debris that can be embedded in insulating layer 203 is determined by the thickness of resin insulating layer 203. If the thickness of insulating layer 203 is, for example, 1 μm, debris with a diameter or width of 1 μm can be embedded in insulating layer 203. In other words, according to this manufacturing method, even if debris smaller than the thickness of insulating layer 203 exists, embedding the debris in the resin insulating layer can improve the connection between insulating layer 103 and insulating layer 203.

[0046] The organic material used for the insulating layer 203 may be the following resin material so that low-temperature bonding can be performed during the bonding in step (g) described below. As such an organic material, a curable composition containing a maleimide compound having one or more maleimide groups and a reactive component other than the maleimide compound can be used. From the viewpoints of heat resistance and a reduced thermal expansion coefficient of the insulating layer 203, the curable composition may contain a maleimide compound having two or more maleimide groups. Examples of commercially available maleimide compounds include NE-X-9470S (trade name, DIC), MIR-3000-70MT (trade name, Nippon Kayaku), BMI-1000 (trade name, Yamato Chemical Industries, Ltd.), BMI-2300 (trade name, Yamato Chemical Industries, Ltd.), BMI-5100 (trade name, Yamato Chemical Industries, Ltd.), BMI-80 (trade name, Yamato Chemical Industries, Ltd.), BMI (trade name, Yamato Chemical Industries, Ltd.), and SFR-2300MR-T (trade name, Resonac).

[0047] The reactive component other than the maleimide compound is a compound that participates in the curing reaction of the curable composition and may include a styrene-based compound, an allyl compound, or both. A curable composition containing a combination of a maleimide compound and a specific reactive component can be cured or semi-cured at a relatively low temperature to form an insulating layer through the progress of a curing reaction involving the maleimide compound and the reactive component. Being able to cure at a low temperature is also advantageous in terms of reducing thermal damage to the substrate body 201, etc. Furthermore, since the curing reaction is primarily an addition reaction such as radical polymerization or Diels-Alder reaction, it is less likely to generate volatile components due to elimination components.

[0048] As the styrene-based compound, a styrene-based compound having a reactive group, which is a group obtained by removing one or more hydrogen atoms bonded to the benzene ring from a compound represented by the following formula (I), can be used. In formula (I), R 1 and R 2 are each independently a hydrogen atom or an alkyl group having 1 to 3 carbon atoms (for example, a methyl group). 1 is a hydrogen atom, and R 2 may be a hydrogen atom or an alkyl group having 1 to 3 carbon atoms (for example, a methyl group). [ka]

[0049] The styrene-based compound may have a plurality of reactive groups. The reactive group of the styrene-based compound is represented by, for example, the following formula (Ia) or (Ib). R in formula (Ia) and (Ib) 1 and R 2 is R in formula (I). 1 and R 2 It is defined similarly to R 11 and R 12 is an alkyl group having 1 to 3 carbon atoms, p is an integer of 0 to 3, and q is an integer of 0 to 4. 11 and R 12 may be the same or different. [ka]

[0050] The styrene-based compound may be a polymer containing a structural unit represented by the following formula (11) or (12): 1 and R 2 is R in formula (I) 1 and R 2 In equation (11), L 1 is a single bond or a divalent organic group, and R 11 is an alkyl group having 1 to 3 carbon atoms (for example, a methyl group), and p is an integer of 0 to 3. 2 is a single bond or a divalent organic group, and R 12 is an alkyl group having 1 to 3 carbon atoms (for example, a methyl group), and q is an integer of 0 to 4. [ka] [ka]

[0051] L 1 or L 2Examples of divalent organic groups as the alkyl group include an oxy group (-O-), a -C(R 13 )(R 14 )-, carbonyl group (-C(=O)-), carbonyloxy group (-C(=O)O-), amide group (-C(=O)NH-), carbonate group (-OC(=O)O-), sulfonyl group (-S(=O)2-), and thio group (-S-). 13 and R 14 are each independently a hydrogen atom or an alkyl group having 1 to 3 carbon atoms.

[0052] The allyl compound may include an allyl compound having a reactive group represented by the following formula (II) (hereinafter, sometimes referred to as an "allylamino compound"): The allylamino compound may have a plurality of reactive groups represented by formula (II). [ka]

[0053] The content of the reactive component may be 10% by mass or more and 80% by mass or less, based on the total amount of the maleimide compound and the reactive component. The content of the reactive component may be 15% by mass or more, 20% by mass or more, 25% by mass or more, or 30% by mass or more, based on the total amount of the maleimide compound and the reactive component, and may be 75% by mass or less, 70% by mass or less, 65% by mass or less, or 60% by mass or less. The total content of the styrene compound and the allylamino compound may be within these numerical ranges.

[0054] Another example of a curable composition containing a maleimide compound may be used as the organic material for the insulating layer 203. This curable composition contains a block maleimide compound having a maleimide group blocked by a blocking agent that dissociates upon heating, and a reactive component. The maleimide compound may be a commercially available product similar to the above. The reactive component is a compound having a reactive group that reacts with a maleimide group, or a compound that generates a reactive group upon heating. The reactive component may contain at least one compound selected from the group consisting of a styrene-based compound, an allyl compound, a thiol compound, a phenolic compound, and a benzoxazine compound. The reactive component may contain a styrene-based compound and an allyl compound.

[0055] By blocking the maleimide group with a blocking agent, the progress of curing, including the reaction between the maleimide compound and the reactive component, is suppressed at room temperature (e.g., 20 to 35°C). Therefore, even if the reactive component has high reactivity, the curable composition can have high viscosity stability at room temperature. Various cured resin products, such as resin films, can be formed using the curable composition.

[0056] The blocking agent may be a compound that dissociates from the maleimide group upon heating at 40°C or higher and 230°C or lower. If the blocking agent is a compound with a low boiling point, the blocking agent dissociated from the maleimide group can be easily volatilized from the resin film containing the curable composition. A small amount of blocking agent remaining in the resin film after curing can be advantageous for suppressing defects in the resin film, such as voids. From this perspective, the blocking agent may be a compound with a boiling point of 250°C or lower, or 230°C or lower. The boiling point of the compound used as the blocking agent may be 40°C or higher. Here, the boiling point means the boiling point under 1 atmosphere.

[0057] The blocking agent may contain a diene compound having a diene group. The diene compound as a blocking agent may be any compound capable of reacting with a maleimide group via a Diels-Alder reaction, and examples thereof include compounds represented by the following formula:1 , R 2 , R 3 , R 4 , R 5 and R 6 are each independently a hydrogen atom or a monovalent organic group. 1 , R 2 , R 3 , R 4 , R 5 and R 6 Two groups selected from the following may be bonded to form a cyclic group. Maleimide group 1 and diene compound 2 react rapidly via a Diels-Alder reaction to produce blocked maleimide group 1A. Diene compound 2 is easily dissociated from blocked maleimide group 1A by heating. [ka]

[0058] R 1 , R 2 , R 3 , R 4 , R 5 and R 6 may each independently be an alkyl group (-R) which may have a substituent, an alkoxycarbonyl group (-C(=O)OR) which may have a substituent, or an alkanoyl group (-C(=O)R) which may have a substituent. Examples of substituents that the alkyl group, alkoxycarbonyl group, and alkanoyl group may have include a hydroxy group, an alkanoyloxy group (-O(C=O)R), an alkoxycarbonyl group, an alkanoyl group, an aryl group, and a furyl group. R 1 , R 2 , R 3 , R 4 , R 5 or R 6 The organic group may have 1 to 10 carbon atoms. 2 and R 6 may be bonded to form a cyclic group which may contain a hetero atom. The diene compound may be a compound having a furyl group.

[0059] When forming the plurality of electrodes 202, a barrier layer 204 (second barrier layer) covering the bottom surface 202b and the side surface 202c (outer peripheral surface) of each electrode 202 may be formed between each electrode 202 and the insulating layer 203 (see (b) of FIG. 4). The barrier layer 204 is a metal layer for preventing the diffusion of the material (e.g., copper) constituting the electrode 202, and similar to the barrier layer 104, contains at least one metal material selected from the group consisting of titanium, nickel, palladium, chromium, tantalum, tungsten, and gold. The barrier layer 204 can be formed by, for example, sputtering. The thickness of the barrier layer 204 is, for example, 0.001 μm to 0.5 μm.

[0060] [Process (c)] Step (c) is a step of polishing the surface 100a side of the semiconductor substrate 100. In step (c), as shown in FIG. 2(c), the multiple electrodes 102 and insulating layer 103 provided on the surface 100a side of the semiconductor substrate 100 are polished using a polishing pad and slurry by using a chemical mechanical polishing (CMP) method. This polishing results in an arithmetic mean roughness Ra of each surface 102a (first surface) of the multiple electrodes 102 and the surface 103a (third surface) of the insulating layer 103 being 2.0 nm or less, preferably 1.2 nm or less, and more preferably 1.0 nm or less, enabling hybrid bonding, as described below. The arithmetic mean roughness Ra used here is the arithmetic mean roughness (Ra) specified in JIS B 0601-2001.

[0061] In step (c), the polishing material, polishing conditions, and the like are set during polishing, and the surface of the semiconductor substrate 100 is polished so that the protruding portions 102d of the electrodes 102 protrude from the surface 103a of the insulating layer 103, as shown in FIG. 4(a). This forms a step between each electrode 102 and the insulating layer 103. The protruding amount (step amount) of the protruding portions 102d may be set to a value calculated by a method described below, and may be 3 μm or less, for example. Note that this polishing may also remove debris on the surface of the semiconductor substrate 100.

[0062] [Step (d)] Step (d) is a step of polishing the front surface 200a side of the semiconductor substrate 200. In step (d), as shown in (d) of Fig. 2, the CMP method is used to polish the plurality of electrodes 202 and the insulating layer 203 provided on the front surface 200a side of the semiconductor substrate 200 with a polishing pad and slurry. This polishing makes the arithmetic mean roughness Ra of each surface 202a (second surface) of the plurality of electrodes 202 and the surface 203a (fourth surface) of the insulating layer 203 equal to or less than 2.0 nm, preferably equal to or less than 1.2 nm, and more preferably equal to or less than 1.0 nm, thereby enabling hybrid bonding, which will be described later.

[0063] In step (d), the semiconductor substrate 200 is polished by setting the polishing material, polishing conditions, and the like during polishing so that the surface 202a of the electrode 202 is located at the bottom of a region 205 recessed inward from the surface 203a of the insulating layer 203, as shown in FIG. 4(b). This forms a step between each electrode 202 and the insulating layer 203. The recess amount (step amount) of the electrode 202 may be set to a value calculated by a method described below, and is, for example, 3 μm or less and larger than the protrusion amount of the protrusion 102d. In other words, since the protrusion amount of the protrusion 102d of the electrode 102 is smaller than the recess amount of the electrode 202, the electrodes will not come into contact with each other when the insulating layers are bonded to each other in step (g) described below. Note that this polishing may remove debris on the surface of the semiconductor substrate 200.

[0064] The CMP method of step (d) can use various slurries containing abrasive particles of at least one of alumina particles and silica particles. As an example, a slurry (CMP polishing liquid) containing abrasive particles having silicon oxide particles and aluminum components present on the surfaces of the silicon oxide particles can be used. Polishing using this slurry can polish the organic insulating layer at high speed, for example, at a polishing rate of 160 nm / min or more (preferably 170 nm / min or more, 180 nm / min or more). It is presumed that the high speed polishing of the organic insulating layer is achieved by increasing the frequency of contact between the abrasive particles and the organic insulating layer (resin portion) due to the interaction between the aluminum components present on the surfaces of the silicon oxide particles and the resin material (e.g., electrostatic attraction between the positively charged aluminum components and the negatively charged resin material).

[0065] The silicon oxide particles contained in the slurry may be silica particles (particles containing silica). As the silica particles, colloidal silica may be used, or particles other than colloidal silica may be used. The silicon oxide particles may contain colloidal silica, which facilitates reducing the surface roughness of the polished surface after polishing.

[0066] The aluminum component can be present on at least a portion of the surface of the silicon oxide particles. Examples of the aluminum component include aluminum compounds, aluminum ions (Al 3+) and the like. Examples of aluminum compounds include aluminum acetate (including aluminum monohydroxide diacetate, aluminum dihydroxide monoacetate, etc.), aluminum lactate, aluminum laurate, aluminum stearate, aluminum oxalate, aluminum oxide, aluminum hydroxide, aluminum sulfide, aluminum nitride, aluminum fluoride, aluminum chloride, aluminum bromide, aluminum iodide, aluminum sulfate, sodium aluminum sulfate, potassium aluminum sulfate, ammonium aluminum sulfate, aluminum nitrate, aluminum perchlorate, aluminum aluminate, aluminum silicate, aluminum phosphate, alkoxyaluminum, aluminum compounds containing one or more of these conjugate acids, and hydrates thereof. One aluminum compound can be used alone, or two or more aluminum compounds can be used in combination. From the viewpoint of polishing the organic insulating layer at high speed, the aluminum compound may contain a compound other than aluminum oxide.

[0067] In the above slurry, the mass ratio of aluminum to silicon oxide (SiO2 / Al2O3) in the abrasive grains containing silicon oxide particles and an aluminum component may be within the following ranges from the viewpoint of high-speed polishing of the organic insulating layer. The mass ratio (SiO2 / Al2O3) may be 1.0 or more, more than 1.0, 2.0 or more, 3.0 or more, 4.0 or more, 5.0 or more, 6.0 or more, 6.5 or more, 7.0 or more, 7.5 or more, or 7.6 or more. The mass ratio (SiO2 / Al2O3) may be 30.0 or less, 25.0 or less, 20.0 or less, 15.0 or less, 12.0 or less, 10.0 or less, 9.0 or less, 8.5 or less, 8.0 or less, or 7.6 or less. From these viewpoints, the mass ratio (SiO2 / Al2O3) may be 1.0 to 30.0, 1.0 to 15.0, 1.0 to 10.0, 3.0 to 30.0, 3.0 to 15.0, 3.0 to 10.0, 5.0 to 30.0, 5.0 to 15.0, or 5.0 to 10.0.

[0068] The slurry used as a CMP polishing liquid may contain, in addition to the silicon oxide particles and aluminum components present on the surface, silicon oxide particles not present on the surface of aluminum components, cerium oxide particles, aluminum oxide particles, silicon nitride particles, zirconium oxide particles, titanium oxide particles, yttrium oxide particles, etc. The slurry may also contain water, an additive, and an acid component.

[0069] In steps (c) and (d), the insulating layer 103 may be polished so that the thickness of the insulating layer 203 is the same as that of the insulating layer 103, or the insulating layer 203 may be polished so that the thickness of the insulating layer 203 is thicker than that of the insulating layer 103. Alternatively, the insulating layer 203 may be polished so that the thickness of the insulating layer 203 is thinner than that of the insulating layer 103. When the insulating layer 203 is formed so that the thickness of the insulating layer 203 is thicker than that of the insulating layer 103, the insulating layer 203, which is made of an organic material, can contain most of the debris that adheres to the bonding interface during singulation into semiconductor chips 10 or during chip mounting, thereby reducing bonding defects. On the other hand, when the thickness of the insulating layer 103 is thinner than that of the insulating layer 203, the height of the mounted semiconductor chip 10, i.e., the semiconductor device 1, can be reduced.

[0070] [Step (e)] In step (e), the semiconductor substrate 100 is diced to obtain a plurality of semiconductor chips 110. The semiconductor chips 110 here correspond to the semiconductor chips 10 in FIG. 1. After polishing the semiconductor substrate 100, in step (e), as shown in FIG. 3(a), the polished semiconductor substrate 100 is diced to obtain a plurality of semiconductor chips 110, each of which includes a substrate portion 101A corresponding to the substrate main body 101, one or more electrodes 102, and an insulating portion 103A (first insulating layer) corresponding to the insulating layer 103. The semiconductor substrate 100 to be diced may be either a semiconductor wafer or a semiconductor panel. In step (e), the semiconductor substrate 100 is placed on a dicing tape 107 and diced into a plurality of semiconductor chips 110 from the insulating layer 103 toward the substrate main body 101 using a cutting means such as a dicer 150. In step (e), the insulating layer 103 of the semiconductor substrate 100 is divided into insulating portions 103A corresponding to each semiconductor chip 110. The substrate body 101 is similarly divided into corresponding substrate portions 101A. As a dicing method for dividing the semiconductor substrate 100, other than blade dicing, for example, plasma dicing, stealth dicing, or laser dicing can be used.

[0071] [Process (f)] 3(b), step (f) is a step of aligning the electrodes 102 of each of the multiple semiconductor chips 110 with the electrodes 202 of the semiconductor substrate 200. In step (f), the semiconductor chips 110 are aligned so that the electrodes 102 of each semiconductor chip 110 face the corresponding electrodes 202 of the semiconductor substrate 200.

[0072] [Process (g)] Step (g) is a step of bonding each insulating portion 103A (insulating layer) of the multiple semiconductor chips 110 to the insulating layer 203 of the semiconductor substrate 200. In step (g), debris such as organic matter or metal oxide adhering to the surfaces of each semiconductor chip 110 and the semiconductor substrate 200 is removed by cleaning or the like, and then the semiconductor chip 110 is aligned with the semiconductor substrate 200. Once this is complete, as shown in FIG. 3(c), the insulating portion 103A of each of the multiple semiconductor chips 110 is bonded to the insulating layer 203 of the semiconductor substrate 200 by hybrid bonding. As shown in FIGS. 5(a) and 5(b), when the surface 103a of the insulating portion 103A and the surface 203a of the insulating layer 203 are bonded, the surface 102a of the electrode 102 and the surface 202a of the electrode 202 face each other at a distance. That is, a gap S is formed between the surface 102a of the electrode 102 and the surface 202a of the electrode 202. In the step (g) of bonding the insulating layer, the semiconductor chip 110 and the semiconductor substrate 200 may be heated before bonding, but the heating temperature is not high, and it is preferable to bond the insulating layer in an atmosphere of, for example, 150° C. or less, and more preferably, to bond the insulating layer in an atmosphere of 100° C. or less. Heating at a low temperature reduces the thermal expansion of the insulating layer 203.

[0073] [Process (h)] Step (h) is a step of bonding the electrodes 102 of each of the semiconductor chips 110 to the corresponding electrodes 202 of the semiconductor substrate 200. In step (h), as shown in FIG. 3(c) and FIGS. 5(b) and 5(c), after the insulating layers have been bonded together in step (g), a predetermined amount of heat and / or pressure is applied to bond the electrodes 102 of each of the semiconductor chips 110 to the corresponding electrodes 202 of the semiconductor substrate 200 by hybrid bonding. When the electrodes 102 and 202 are made of copper, the annealing temperature (heating temperature) in step (h) is preferably 150°C to 400°C, more preferably 200°C to 300°C, and preferably 200°C or higher and 250°C or lower. This thermal bonding process forms an electrode bonded portion where the electrode 102 and the corresponding electrode 202 are bonded, and the electrodes 102 and 202 are firmly bonded mechanically and electrically. 5(c), when the electrode 102 and the electrode 202 are bonded, the electrode 102 is entirely covered by the barrier layer 104 and the surface 202a of the electrode 202, thereby preventing migration. The electrode 202 is entirely covered by the barrier layer 204, the barrier layer 105, and the electrode 102, thereby preventing migration. All the semiconductor chips 110 are bonded to the semiconductor substrate 200, thereby obtaining the semiconductor device 1 shown in FIG.

[0074] As a result, it is possible to obtain a semiconductor device 1 in which a plurality of semiconductor chips 110 are electrically and mechanically mounted with high precision at predetermined positions on the semiconductor substrate 200. Thereafter, the semiconductor device (CoW) having the configuration shown in Fig. 1 may be further divided into individual pieces by dicing, to form individual semiconductor devices each composed of at least one semiconductor chip 10 (110) and a portion of the semiconductor substrate 200 corresponding to the divided semiconductor chip 10.

[0075] As described above, according to the semiconductor device manufacturing method of the first embodiment, insulating layer 103 is an inorganic insulating layer, and insulating layer 203 is an organic insulating layer. In this case, the heating temperature when bonding insulating layers together can be lower than the heating temperature when bonding organic insulating layers together. This is because, when bonding organic insulating layers together, the organic material (resin) needs to be thermally expanded to make both electrodes convex due to thermal expansion. However, when bonding an organic insulating layer and an inorganic insulating layer together, one electrode can be made concave due to thermal expansion, making it possible to bond the insulating layers together without thermal expansion. This increases the design freedom for the step (amount of unevenness) between electrodes 102, 202 and insulating layers 103, 203. Therefore, when bonding insulating layer 103 (insulating portion 103A) to insulating layer 203, surface 102a of electrode 102 can be set away from surface 202a of electrode 202. Therefore, when bonding insulating layers together, the insulating layers can be bonded without the electrodes first coming into contact with each other, and in the subsequent electrode bonding, misalignment between the electrodes to be bonded can be reduced. Furthermore, since one of the insulating layers to be bonded (insulating layer 203) is an organic insulating layer, debris at the bonding interface can be absorbed by the organic insulating layer. Therefore, this manufacturing method can prevent bonding defects.

[0076] [Method for manufacturing a semiconductor device according to the second embodiment] Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to Fig. 6. In the following description, differences from the manufacturing method according to the first embodiment will be mainly described, and overlapping descriptions may be omitted.

[0077] In the manufacturing method according to the second embodiment, first, semiconductor substrates 100 and 200 are prepared, similarly to steps (a) and (b) of the first embodiment. However, in the second embodiment, the width or diameter of the electrode 102 of the semiconductor substrate 100 is equal to or larger than the width or diameter of the electrode 202 of the semiconductor substrate 200 (see (a) of FIG. 6). After the semiconductor substrates 100 and 200 are prepared, in steps (c) and (d), the surfaces of the semiconductor substrates 100 and 200 are polished by a CMP method or the like. Unlike the first embodiment, in the second embodiment, the semiconductor substrate 100 is polished so that the surface 102a of the electrode 102 of the semiconductor substrate 100 is located at the bottom of a region recessed inward from the surface 103a of the insulating layer 103. Meanwhile, the semiconductor substrate 200 is polished so that the protruding portion 202d of the electrode 202 protrudes from the surface 203a of the insulating layer 203. 6(a), the electrode 102 of the semiconductor substrate 100 is recessed inward, and the electrode 202 of the semiconductor substrate 200 is protruded. That is, in the manufacturing method according to the second embodiment, the concave-convex relationship of the electrodes 102, 202 is reversed from that in the first embodiment.

[0078] After the surface polishing of each semiconductor substrate 100, 200 is completed, in step (e), the semiconductor substrate 100 is divided into individual pieces to obtain multiple semiconductor chips 110, as in the first embodiment. Then, in step (f), the electrodes 102 of each of the multiple semiconductor chips 110 are aligned with the electrodes 202 of the semiconductor substrate 200. Then, in step (g), as in the first embodiment, the insulating portions 103A (insulating layers) of the multiple semiconductor chips 110 are bonded to the insulating layer 203 of the semiconductor substrate 200 under low-temperature heating. The bonding temperature is the same as in the first embodiment. As shown in FIG. 6(b), when the surface 103a of the insulating portion 103A and the surface 203a of the insulating layer 203 are bonded, the electrodes 102 and 202 face each other and are spaced apart. That is, a gap S is formed between the surface 102a of the electrode 102 and the surface 202a of the electrode 202.

[0079] After the insulating layer is bonded in step (g), the electrodes 102 of each of the semiconductor chips 110 are bonded to the electrodes 202 of the semiconductor substrate 200 in step (h), as in the first embodiment. This completes the fabrication of the semiconductor device 1 shown in Fig. 1. Thereafter, the semiconductor device 1 may be further divided into individual pieces, as in the first embodiment.

[0080] As described above, according to the manufacturing method of the semiconductor device of the second embodiment, similar to the manufacturing method of the first embodiment, when bonding insulating layers together, the insulating layers can be bonded together without the electrodes first coming into contact with each other. This reduces misalignment between the electrodes to be bonded in the subsequent electrode bonding. Furthermore, since one of the insulating layers to be bonded (insulating layer 203) is an organic insulating layer, debris at the bonding interface can be absorbed by the organic insulating layer. Therefore, this manufacturing method can prevent bonding defects.

[0081] [Calculation method for unevenness amount] Here, with reference to FIG. 7, a method for calculating the protrusion amount of the electrode 102 on the semiconductor substrate 100 and the recess amount of the electrode 202 on the semiconductor substrate 200 in the manufacturing method according to the first embodiment will be described.

[0082] 7, "a" is the thickness of insulating layer 203 of semiconductor substrate 200, and corresponds to the distance from the position of bottom surface 202b of electrode 202 to surface 203a of insulating layer 203. "b" is the thickness of electrode 202 of semiconductor substrate 200, and corresponds to the distance from bottom surface 202b to surface 202a. "c" is the distance from surface 202a of electrode 202 of semiconductor substrate 200 to surface 203a of insulating layer 203 (the amount of recession of electrode 202).

[0083] 7, "d" is the thickness of electrode 102 of semiconductor substrate 100 (semiconductor chip 110), and corresponds to the distance from bottom surface 102b to surface 102a. "e" is the amount of protrusion of electrode 102 of semiconductor substrate 100 from surface 103a of insulating layer 103. "f" is the thickness of insulating portion 103A (insulating layer) of semiconductor substrate 100, and corresponds to the distance from the position of bottom surface 102b of electrode 102 to surface 103a of insulating layer 103.

[0084] The magnitudes of the above-mentioned distances or thicknesses "a" to "f" have the relationship of the following formulas (1) and (2), where T is the temperature. Here, "T0" means room temperature (20°C), and "ΔT" means the temperature difference. Plm " means the coefficient of linear expansion (CTE) of the resin material (polymer) that forms the insulating layer 203, and "α Cu " denotes the coefficient of linear expansion (CTE) of the copper material forming the electrodes 102, 202, and "α Si " means the coefficient of linear expansion (CTE) of the inorganic material (silicon oxide) that forms the insulating layer 103.

[0085]

number

number

[0086] In the manufacturing method according to the first embodiment, the temperature is set at room temperature T o In this case, the following formulas (3) and (4) are satisfied: In other words, the recessed amount of the electrode 202 is larger than the protruding amount of the electrode 102.

number

number

[0087] Furthermore, in the manufacturing method according to the first embodiment, when the insulating layers are bonded to each other in step (g) (heating temperature is T1), the following formulas (5) and (6) are satisfied. In other words, the recessed amount of electrode 202 remains larger than the protruding amount of electrode 102.

number

number

[0088] Furthermore, in the method for manufacturing the semiconductor device according to the first embodiment, when the electrodes are joined together in step (h) (heating temperature is T2), the following formulas (7) and (8) are satisfied.

number

number

[0089] The above equations (6) and (8) can be summarized as the following equations (9) and (10).

number

number

[0090] Therefore, in the manufacturing method according to the first embodiment, it is necessary to set the amount of unevenness of each electrode 102, 202 and select the coefficient of linear expansion (CTE) of the organic material (polymer) of the insulating layer 203 so as to satisfy the following formulas (4) and (10).

number

number

[0091] Using such an equation, for example, the thickness "a" of the insulating layer 203 can be calculated. As conditions, the thickness "b" of the electrode 202 is (a-3) nm, the thickness "d" of the electrode 102 is 1002 nm, the thickness "f" of the insulating layer 103 is 1000 nm, and the linear expansion coefficient "α" of the insulating layer 203 is Plm ” is 30 ppm / K, and the linear expansion coefficient “α Si " is 0.5 ppm / K, and the linear expansion coefficient "α CuConsider the case where "a" is 17 ppm / K. In this case, if (ce) nm is calculated for each of the cases where "a" is 0.5 μm, 1 μm, 2 μm, and 3 μm, the table shown in FIG. 8 is obtained. From the table in FIG. 8, it can be seen that the thickness "a" of the insulating layer 203 needs to be 1 μm or less.

[0092] On the other hand, using such an equation, for example, the linear expansion coefficient α Plm As conditions, the thickness "a" of the insulating layer 203 is 3000 nm, the thickness "b" of the electrode 202 is 2997 nm, the thickness "d" of the electrode 102 is 1002 nm, the thickness "f" of the insulating layer 103 is 1000 nm, and the linear expansion coefficient "α Si " is 0.5 ppm / K, and the linear expansion coefficient "α Cu " is 17 ppm / K. In this case, (ce)nm is "α Plm When the linear expansion coefficient "α" of the insulating layer 203 is calculated for each of 30 ppm / K, 25 ppm / K, 22 ppm / K, and 20 ppm / K, the table shown in FIG. 9 is obtained. Plm It can be seen that " must be 21 ppm / K or less.

[0093] In the manufacturing method according to the first embodiment, the amount of unevenness of the electrode and the linear expansion coefficient of the organic insulating layer can be set using such a calculation method.

[0094] Next, with reference to FIG. 10, a method for calculating the protrusion amount of the electrode 202 on the semiconductor substrate 200 and the recess amount of the electrode 102 on the semiconductor substrate 100 in the manufacturing method according to the second embodiment will be described.

[0095] 10, "a" is the thickness of insulating layer 103 of semiconductor substrate 100, and corresponds to the distance from the position of bottom surface 102b of electrode 102 to surface 103a of insulating layer 103. "b" is the thickness of electrode 102 of semiconductor substrate 100, and corresponds to the distance from bottom surface 102b to surface 102a. "c" is the distance from surface 102a of electrode 102 of semiconductor substrate 100 to surface 103a of insulating portion 103A (insulating layer 103) (depression amount of electrode 102).

[0096] 10, "d" is the thickness of electrode 202 of semiconductor substrate 200, and corresponds to the distance from bottom surface 202b to surface 202a. "e" is the amount of protrusion of electrode 202 of semiconductor substrate 200 from surface 203a of insulating layer 203. "f" is the thickness of insulating layer 203 of semiconductor substrate 200, and corresponds to the distance from the position of bottom surface 202b of electrode 202 to surface 203a of insulating layer 203.

[0097] The magnitudes of the above-mentioned distances or thicknesses "a" to "f" have the relationships shown in the following formulas (11) and (12), where T is the temperature. Here, "T0" means room temperature (20°C), and "ΔT" means the temperature difference. Plm " means the coefficient of linear expansion (CTE) of the resin material (polymer) that forms the insulating layer 203, and "α Cu " denotes the coefficient of linear expansion (CTE) of the copper material forming the electrodes 102, 202, and "α Si " means the coefficient of linear expansion (CTE) of the inorganic material (silicon) that forms the insulating layer 103.

[0098]

number

number

[0099] In the manufacturing method according to the second embodiment, the temperature is set at room temperature T o In this case, the following formulas (13) and (14) are satisfied: In other words, the recessed amount of the electrode 102 is greater than the protruding amount of the electrode 202.

number

number

[0100] Furthermore, in the manufacturing method according to the second embodiment, when the insulating layers are aligned with each other in step (g) (heating temperature is T1), the following formulas (15) and (16) are satisfied. That is, the recessed amount of electrode 202 remains larger than the protruding amount of electrode 102.

number

number

[0101] Furthermore, in the method for manufacturing a semiconductor device according to the second embodiment, when the electrodes are joined together in step (h) (heating temperature is T2), the following formulas (17) and (18) are satisfied.

number

number

[0102] The above equations (16) and (18) can be summarized as the following equations (19) and (20).

number

number

[0103] Therefore, in the manufacturing method according to the second embodiment, it is necessary to set the amount of unevenness of each electrode 102, 202 and select the coefficient of linear expansion (CTE) of the organic material (polymer) of the insulating layer 203 so as to satisfy the following equations (14) and (20).

number

number

[0104] Using such an equation, for example, the thickness "f" of the insulating layer 203 can be calculated. As conditions, the thickness "a" of the insulating layer 103 is 1000 nm, the thickness "b" of the electrode 102 is 997 nm, the thickness "d" of the electrode 202 is (f+2) nm, and the linear expansion coefficient "α" of the insulating layer 203 is Plm ” is 30 ppm / K, and the linear expansion coefficient “α Si " is 0.5 ppm / K, and the linear expansion coefficient "α Cu Consider the case where "f" is 17 ppm / K. In this case, if (ce) nm is calculated for each of the cases where "f" is 0.5 μm, 1 μm, 2 μm, and 3 μm, the table shown in FIG. 11 is obtained. From the table shown in FIG. 11, it can be seen that the thickness "f" of the insulating layer 203 needs to be 1 μm or less.

[0105] On the other hand, using such an equation, for example, the linear expansion coefficient α Plm As conditions, the thickness "a" of the insulating layer 103 is 1000 nm, the thickness "b" of the electrode 102 is 997 nm, the thickness "d" of the electrode 202 is 3002 nm, the thickness "f" of the insulating layer 203 is 3000 nm, and the linear expansion coefficient "α Si " is 0.5 ppm / K, and the linear expansion coefficient "α Cu " is 17 ppm / K. In this case, (ce)nm is "α Plm When the linear expansion coefficient "α" of the insulating layer 203 is calculated for each of 30 ppm / K, 25 ppm / K, 22 ppm / K, and 20 ppm / K, the table shown in FIG. 12 is obtained. Plm It can be seen that " must be 21 ppm / K or less.

[0106] In the manufacturing method according to the second embodiment, the amount of unevenness of the electrode and the linear expansion coefficient of the organic insulating layer can also be set using such a calculation method.

[0107] The method for manufacturing a semiconductor device according to this embodiment has been described in detail above, but the present invention is not limited to the above embodiment and can be applied to various embodiments or modifications.

[0108] For example, in the above embodiment, an example was described in which hybrid bonding was used to bond semiconductor substrates together or to bond a semiconductor substrate to a semiconductor chip. However, this also includes bonding a semiconductor interposer formed from a semiconductor material to a semiconductor chip. The hybrid bonding method according to this embodiment may also be used to bond a semiconductor substrate or a semiconductor chip to a substrate including a redistribution layer (RDL layer). In this case, the semiconductor chip 110 may be bonded to a redistribution layer (redistribution substrate) corresponding to the semiconductor substrate 200 using the above-described hybrid bonding method. It may also be used to bond other members together.

[0109] Furthermore, in the above embodiment, a method has been described in which the semiconductor substrate 100 having the insulating layer 103 formed from an inorganic material is diced to form individual semiconductor chips 110, and these semiconductor chips 110 are then bonded to the semiconductor substrate 200. However, the present invention is not limited to this. That is, the present invention may also be applied to a method in which the semiconductor substrate 200 having the insulating layer 203 formed from an organic material (polymer) is diced to form multiple semiconductor chips, and these semiconductor chips are then bonded to the semiconductor substrate 100.

[0110] In the above embodiment, the plurality of semiconductor chips 110 (see (a) of FIG. 3 ) singulated in step (e) are aligned with the semiconductor substrate 200 in step (f), and then the plurality of semiconductor chips 110 are attached to the semiconductor substrate 200. At this time, the plurality of singulated semiconductor chips 110 may be fixed to a carrier substrate or the like to form a pseudo-wafer or panel shape, and the plurality of semiconductor chips 110 in the pseudo-wafer or panel shape may be aligned with the semiconductor substrate in step (f). Then, in steps (g) and (h), the plurality of semiconductor chips 110 in the pseudo-wafer or panel shape may be bonded to the semiconductor substrate 200. Note that the carrier substrate may be removed by separation after step (g) or step (h). This allows the present disclosure to be applied to pseudo W2W bonding as well. [Explanation of symbols]

[0111] 1...semiconductor device, 10...semiconductor chip, 20...semiconductor substrate, 100...semiconductor substrate (first substrate), 100a...surface, 101...substrate body, 101a...surface, 102...electrode (first electrode), 102a...surface (first surface), 102b...bottom surface, 102c...side surface, 102d...protruding portion, 103...insulating layer (first insulating layer), 103A...insulating portion (first insulating layer), 103a...surface (third surface), 104...burrs a layer (first barrier layer), 105...barrier layer (third barrier layer), 200...semiconductor substrate (second substrate), 200a...surface, 201...substrate body, 201a...surface, 202...electrode (second electrode), 202a...surface (second surface), 202b...bottom surface, 202c...side surface, 202d...protrusion, 203...insulating layer (second insulating layer), 203a...surface (fourth surface), 204...barrier layer (second barrier layer), S...gap.

Claims

1. preparing a first substrate having a first insulating layer and a first electrode on a surface side; preparing a second substrate having a second insulating layer and a second electrode on a surface side thereof; bonding the first insulating layer to the second insulating layer; and joining the first electrode to the second electrode; at least one of the first substrate and the second substrate includes a semiconductor substrate; the first insulating layer is an inorganic insulating layer, the second insulating layer is an organic insulating layer, a first surface of the first electrode spaced apart from a second surface of the second electrode when the first insulating layer is bonded to the second insulating layer;

2. When bonding the first insulating layer to the second insulating layer, a protrusion of the first electrode, including the first surface, protruding from a third surface of the first insulating layer; the second surface of the second electrode is located in a region recessed inward from a fourth surface of the second insulating layer; The method for manufacturing a semiconductor device according to claim 1 .

3. the width or diameter of the first electrode is smaller than the width or diameter of the second electrode; when the first insulating layer is bonded to the second insulating layer, the protruding portion of the first electrode is located in a region recessed inward from the fourth surface of the second insulating layer, and the first electrode faces the second electrode at a distance. The method for manufacturing a semiconductor device according to claim 2 .

4. when bonding the first insulating layer to the second insulating layer, a protrusion amount of the first electrode from the third surface of the first insulating layer is smaller than a recess amount of the second electrode from the fourth surface of the second insulating layer. The method for manufacturing a semiconductor device according to claim 2 .

5. a bottom surface and a side surface of the first electrode are covered with a first barrier layer; When bonding the first electrode to the second electrode, the first surface of the first electrode is bonded to the second electrode. The method for manufacturing a semiconductor device according to claim 2 .

6. a bottom surface and a side surface of the second electrode are covered with a second barrier layer; the first insulating layer includes a third barrier layer on a surface side; When the first electrode is bonded to the second electrode, the second surface of the second electrode is covered with the third barrier layer except for a region bonded to the first electrode. The method for manufacturing a semiconductor device according to claim 2.

7. The third barrier layer is made of SiCN, SiN, SiCH, or SiO ２ Including, The method for manufacturing a semiconductor device according to claim 6 .

8. When bonding the first insulating layer to the second insulating layer, the first surface of the first electrode is located in a region recessed inward from a third surface of the first insulating layer; a protrusion of the second electrode, including the second surface, protruding from a fourth surface of the second insulating layer; The method for manufacturing a semiconductor device according to claim 1 .

9. the width or diameter of the second electrode is smaller than the width or diameter of the first electrode; when the first insulating layer is bonded to the second insulating layer, the protruding portion of the second electrode is located in a region recessed inward from the third surface of the first insulating layer, and the second electrode faces the first electrode at a distance. The method for manufacturing a semiconductor device according to claim 8 .

10. when bonding the first insulating layer to the second insulating layer, a protrusion amount of the second electrode from the fourth surface of the second insulating layer is smaller than a recess amount of the first electrode from the third surface of the first insulating layer. The method for manufacturing a semiconductor device according to claim 8 .

11. further comprising polishing the first substrate and the second substrate; In the polishing step, the first electrode is made to protrude and the second electrode is made to be recessed, or the first electrode is made to be recessed and the second electrode is made to protrude. The method for manufacturing a semiconductor device according to claim 1 .

12. further comprising polishing the second substrate; In the step of polishing the second substrate, the second insulating layer is polished by a CMP method using a slurry containing abrasive grains of at least one of alumina particles and silica particles. The method for manufacturing a semiconductor device according to claim 1 .

13. The heating temperature when bonding the first insulating layer to the second insulating layer is 150°C or less. The method for manufacturing a semiconductor device according to claim 1 .

14. The heating temperature when joining the first electrode to the second electrode is 200° C. or higher. The method for manufacturing a semiconductor device according to claim 13.

15. At least one of the first substrate and the second substrate is produced by dividing a semiconductor wafer or a semiconductor panel having an insulating layer and a plurality of electrodes provided on a surface side thereof. The method for manufacturing a semiconductor device according to claim 1 .

16. The first substrate is produced by dicing a semiconductor wafer or a semiconductor panel having an insulating layer and a plurality of electrodes on a surface side thereof into individual pieces. The method for manufacturing a semiconductor device according to claim 15.

17. The linear expansion coefficient of the resin material forming the second insulating layer is 40 ppm / K or less. The method for manufacturing a semiconductor device according to claim 1 .

18. The linear expansion coefficient of the resin material forming the second insulating layer is 30 ppm / K or less. The method for manufacturing a semiconductor device according to claim 17.

19. the resin material forming the second insulating layer is a curable composition containing a maleimide compound having a maleimide group and a reactive component other than the maleimide compound, and the reactive component is at least one of a styrene-based compound and an allyl compound; The method for manufacturing a semiconductor device according to claim 1 .

20. the resin material forming the second insulating layer is a curable composition including a block maleimide compound having a maleimide group blocked with a blocking agent that dissociates upon heating, and a reactive component that is a compound having a reactive group that reacts with the maleimide group or a compound that generates the reactive group upon heating, and the reactive component is at least one of a styrene-based compound and an allyl compound; The method for manufacturing a semiconductor device according to claim 1 .

21. each of the first substrate and the second substrate includes the semiconductor substrate; The method for manufacturing a semiconductor device according to claim 1 .

22. 13. The method for manufacturing a semiconductor device according to claim 12, wherein the slurry for polishing the second substrate by CMP comprises: A slurry containing abrasive particles of at least one of alumina particles and silica particles.

23. 22. The method for manufacturing a semiconductor device according to claim 1, wherein the resin material forming the second insulating layer is A resin material is a curable composition containing a maleimide compound having a maleimide group and at least one of a styrene-based compound and an allyl compound as a reactive component.

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