Ferroelectric memory readout circuit, ferroelectric memory, and ferroelectric memory readout method

Abstract

To provide a ferroelectric memory reading circuit, a ferroelectric memory, and a ferroelectric reading method for reducing influence of noise when reading the ferroelectric memory.SOLUTION: A control circuit 11 of a reading circuit 10 controls an input voltage so that an input voltage of a memory cell 13, which is a voltage between a plate line (PL) electrically connected to the other terminal of a ferroelectric capacitor 13a and a bit line (BL), is fixed, based on the result of comparing a bit line potential, which is a potential of bit line electrically connected to one terminal of a ferroelectric capacitor 13a and a first reference potential (VREF1), when reading data from a memory cell 13, and a sense amplifier 12 determines a data value based on the comparison result between the bit line potential and a second reference potential (VREF2) when the input voltage is fixed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a read circuit for a ferroelectric memory, a ferroelectric memory, and a read method for a ferroelectric memory. [Background technology]

[0002] In a ferroelectric memory, a memory cell including a ferroelectric capacitor stores data "0" or "1" depending on the polarization state of the ferroelectric. During read operation, for example, the potential of the plate line (hereinafter referred to as the plate line potential) connected to one terminal of the ferroelectric capacitor is raised. At this time, the potential of the bit line (hereinafter referred to as the bit line potential) electrically connected to the other terminal of the ferroelectric capacitor differs depending on whether a "0" or a "1" is stored in the memory cell. This difference in the bit line potential occurs depending on whether the polarization of the ferroelectric material is reversed or not.

[0003] For example, if the plate line potential is raised as described above, and a "1" is stored in the memory cell, the ferroelectric material undergoes polarization reversal, causing a large current to flow through the bit line. In contrast, if a "0" is stored in the memory cell, raising the plate line potential does not cause polarization reversal, and little current flows through the bit line. The sense amplifier connected to the bit line determines the data based on the results of comparing the bit line potential with the reference potential.

[0004] The above-described readout that involves reversal of the polarization of the ferroelectric material is called destructive readout. Furthermore, in a ferroelectric memory, rewriting is performed to store the same data in the same memory cell after reading.

[0005] Incidentally, there has been a conventional technology in which, depending on the result of comparing the bit line potential with a reference potential when the plate line potential is increased, charge is supplied to the bit line so that the bit line potential does not change, and data is determined based on the amount of charge supplied (see, for example, Patent Document 1).

[0006] Furthermore, in the past, in order to prevent the reference potential from becoming unstable due to deterioration of the memory cell that generates the reference potential, there was a technology in which the reference potential was obtained by increasing the read potential from a memory cell that stores "0", which does not undergo polarization inversion (see, for example, Patent Document 2).

[0007] Furthermore, there has been a conventional technology in which the bit line is charged via a resistor, the rate at which the bit line potential rises varies significantly depending on whether or not there is polarization reversal in the memory cell, and data is determined at a timing that provides a sufficient read margin (see, for example, Patent Document 3). [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-351374 [Patent Document 2] Japanese Patent Application Laid-Open No. 2001-57071 [Patent Document 3] Japanese Patent Application Laid-Open No. 2006-31800 Summary of the Invention [Problem to be solved by the invention]

[0009] In ferroelectric memories, if the read margin between "0" and "1" becomes smaller due to fatigue degradation of memory cells or other reasons, the memory becomes more susceptible to noise, which can lead to malfunctions.

[0010] In one aspect, the present invention aims to provide a readout circuit that is less susceptible to noise, a ferroelectric memory having such a readout circuit, and a method for reading from a ferroelectric memory. [Means for solving the problem]

[0011] In one embodiment, a read circuit for a ferroelectric memory having a memory cell including a ferroelectric capacitor is provided, the read circuit having: a control circuit that controls an input voltage to fix an input voltage of the memory cell, which is a voltage between a plate line electrically connected to the other terminal of the ferroelectric capacitor, based on a comparison result between a bit line potential, which is the potential of a bit line electrically connected to one terminal of the ferroelectric capacitor, and a first reference potential when reading data from the memory cell; and a sense amplifier that determines a value of the data based on a comparison result between a plate line potential, which is the potential of the bit line or the plate line when the input voltage is fixed, and a second reference potential.

[0012] Also, in one embodiment, a ferroelectric memory is provided. Also, in one embodiment, a method for reading a ferroelectric memory is provided. [Effects of the Invention]

[0013] According to one aspect of the present invention, when data is read from a memory cell of a ferroelectric memory, the memory cell is less susceptible to noise. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 2 is a diagram illustrating an example of a read circuit of the ferroelectric memory according to the first embodiment. [Figure 2] This figure shows the hysteresis loop characteristics of a ferroelectric capacitor. [Figure 3] 4 is a timing chart showing an example of the operation of the read circuit of the ferroelectric memory according to the first embodiment. [Figure 4] FIG. 10 is a diagram showing the relationship between VPL and the amount of charge supplied to BL. [Figure 5] FIG. 1 is a diagram showing a part of a ferroelectric memory of a comparative example. [Figure 6] 10 is a timing chart showing an example of a read operation of the ferroelectric memory of the comparative example. [Figure 7] FIG. 1 is a diagram illustrating an example of a ferroelectric memory. [Figure 8] FIG. 2 is a diagram illustrating an example of a part of a memory cell array and a part of a column-related circuit unit. [Figure 9] FIG. 10 is a diagram illustrating an example of a read circuit of a ferroelectric memory according to a second embodiment. [Figure 10] 10 is a timing chart showing an example of the operation of the read circuit of the ferroelectric memory according to the second embodiment. [Figure 11] FIG. 10 is a diagram showing the relationship between VPL and the amount of charge supplied to BL. [Figure 12] FIG. 10 is a diagram illustrating an example of a read circuit of a ferroelectric memory according to a third embodiment. [Figure 13] 10 is a timing chart showing an example of the operation of the read circuit of the ferroelectric memory according to the third embodiment. [Figure 14] FIG. 10 is a diagram showing the relationship between VBL and VRBL and the amount of charge supplied to a ferroelectric capacitor. [Figure 15] FIG. 10 is a diagram showing the relationship between the magnitude of the bit line capacitance and the magnitude of the read margin in a ferroelectric memory of a comparative example. [Figure 16] FIG. 4 is a diagram showing the relationship between the magnitude of the bit line capacitance and the magnitude of the read margin in the ferroelectric memory according to the first embodiment. [Figure 17] FIG. 10 is a diagram showing the relationship between the magnitude of the bit line capacitance and the magnitude of the read margin in the ferroelectric memory according to the second embodiment. [Figure 18] FIG. 11 is a diagram showing the relationship between the magnitude of the bit line capacitance and the magnitude of the read margin in the ferroelectric memory according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the invention will be described with reference to the drawings. (First embodiment) 1 is a diagram showing an example of a read circuit of a ferroelectric memory according to the first embodiment, in which WL represents a word line, BL represents a bit line, and PL represents a plate line.

[0016] The read circuit 10 of the ferroelectric memory of the first embodiment is a circuit that reads out data stored in memory cells 13 connected to WL, PL, and BL. The memory cell 13 has a ferroelectric capacitor 13a and an n-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) (hereinafter abbreviated as nMOS) 13b. One end of the ferroelectric capacitor 13a is connected to PL, and the other end is connected to the drain of nMOS 13b. The source of nMOS 13b is connected to BL, and the gate of nMOS 13b is connected to WL.

[0017] In such a memory cell 13, when the potential of WL is raised during reading or writing, the nMOS 13b is turned on, and the other end of the ferroelectric capacitor 13a is electrically connected to BL. Note that the nMOS 13b may also be called an access transistor or an access gate.

[0018] The read circuit 10 includes a control circuit 11 and a sense amplifier (denoted as “SA” in FIG. 1) 12. The control circuit 11 controls the bit line potential, which is the potential of BL, and the reference potential (V REF1 ), the input voltage of the memory cell 13, which is the voltage between PL and BL, is controlled so that the input voltage is fixed.

[0019] In the read circuit 10 of the ferroelectric memory according to the first embodiment, the control circuit 11 includes a differential amplifier 11a. The differential amplifier 11a has an inverting input terminal (denoted as "-" in FIG. 1) and a non-inverting input terminal (denoted as "+" in FIG. 1). The inverting input terminal is connected to BL, and the potential of the non-inverting input terminal is V REF1The output terminal of the differential amplifier 11a is connected to PL. REF1 is a constant potential, and is applied to the non-inverting input terminal of the differential amplifier 11a by a reference potential generating circuit 24 (see FIG. 7), which will be described later. REF1 is set appropriately so that the read margin is of an appropriate size.

[0020] The differential amplifier 11a is enabled when reading data from the memory cell 13, and compares the bit line potential with V REF1 The difference between the two is amplified and output as a signal to raise the plate line potential. The amplification factor is, for example, 100 times or 1000 times.

[0021] Such a differential amplifier 11a is configured such that the bit line potential is V REF1 When the voltage reaches the threshold voltage, the input voltage of the memory cell 13 is fixed by stopping the increase in the plate line potential. The sense amplifier 12 is connected to PL. The sense amplifier 12 detects the plate line potential and the reference potential (V REF2 ), the value of the data stored in the memory cell 13 is determined based on the comparison result, and the determination result DATA is output. REF2 is a constant potential, and is applied to the sense amplifier 12 by a reference potential generating circuit 24 (see FIG. 7), which will be described later. REF2 is set to be an intermediate potential between the plate line potential when "0" is read from the memory cell 13 and the plate line potential when "1" is read from the memory cell 13, for example.

[0022] 1 also shows an nMOS 14. The drain of the nMOS 14 is connected to the BL, and the source is grounded. A precharge signal PRECHG is input to the gate of the nMOS 14. The PRECHG is supplied by a controller 23 (see FIG. 7), which will be described later. FIG. 1 also shows a bit line capacitance (parasitic capacitance of the BL) 15.

[0023] In such a read circuit 10, charges are supplied from PL to the ferroelectric capacitor 13a as indicated by the arrow. Figure 2 shows the hysteresis loop characteristics of a ferroelectric capacitor. The horizontal axis represents the potential difference (V PL -V BL ) (corresponding to the input voltage of the memory cell 13), and the vertical axis represents the polarization Q.

[0024] As shown in FIG. 2, the ferroelectric capacitor 13a is PL -V BL When is 0V, there are two stable points with different polarization Q, the positive stable point corresponds to "0" and the negative stable point corresponds to "1". Note that the positive stable point may be "1" and the negative stable point may be "0".

[0025] V PL -V BL When the temperature rises, the polarization Q changes in the direction of the arrow along the hysteresis loop characteristic. The change in polarization Q, ΔQ, is larger when the temperature rises from the negative stable point than when the temperature rises from the positive stable point. This is because the polarization reversal of the ferroelectric occurs when the temperature rises from the negative stable point.

[0026] Therefore, for example, if "1" is stored in memory cell 13, a large current flows through BL, and if "0" is stored in memory cell 13, no polarization reversal occurs and little current flows through BL.

[0027] 3 is a timing chart showing an example of the operation of the read circuit of the ferroelectric memory according to the first embodiment. Time variations in the potentials (V) of PRECHG, OAEN, which is the enable signal of the differential amplifier 11a, and SAEN, which is the enable signal of the sense amplifier 12, are shown in FIG. 3. Furthermore, V, which is the potential of WL, is shown in FIG. WL , V is the potential of the PL PL , V is the potential of BL BL The time variation of the potential (V) of DATA, which is the output of the sense amplifier 12, is also shown.

[0028] When the potential of PRECHG falls from the power supply potential to the ground potential (for example, 0 V) ​​(timing t1), the nMOS 14 is turned off and BL is put into a floating state.

[0029] V WL rises (timing t2), and when the potential of OAEN rises, the differential amplifier 11a starts operating, and V PL and V BL starts to rise. This turns on the nMOS 13b, and data starts to be read from the memory cell 13. At this time, depending on whether or not the polarization inversion described above occurs, the rise in voltage per unit time is smaller (i.e., the rise speed is slower) when "0" is stored in the memory cell 13 than when "1" is stored.

[0030] For this reason, V BL When a "1" is stored in the memory cell 13, V becomes V faster than when a "0" is stored in the memory cell 13. REF1 (timing t3), the differential amplifier 11a PL This stops the rise of V BL The rise in the input voltage (V PL -V BL ) is fixed.

[0031] On the other hand, V BL When a "0" is stored in memory cell 13, V REF1 (timing t4), the differential amplifier 11a PL This stops the rise of V BL The rise in the input voltage (V PL -V BL ) is fixed.

[0032] Thereafter, the potential of OAEN falls, causing the differential amplifier 11a to stop operating (timing t5), and when the potential of SAEN rises, the sense amplifier 12 PL And, V REF2Based on the comparison result with V, the value of the data stored in the memory cell 13 is determined, and the determination result DATA is output. PL ≧V REF2 In this case, DATA = "0" (for example, ground potential) and V PL <V REF2 In this case, DATA="1" (for example, power supply potential).

[0033] Then, based on the results of the judgment, V PL and V BL is set (timing t6), and V WL is further increased, and the memory cell 13 is rewritten. When "0" is rewritten, V PL is further increased, and V BL When a "1" is rewritten, V PL is pulled down to ground potential, and V BL will be further raised.

[0034] When a plurality of memory cells 13 are connected to the same WL (see FIG. 8), according to the above read method, V PL is controlled for each memory cell. Therefore, when rewriting to multiple memory cells connected to the same WL, it is not necessary to write "0" and "1" at different times as in the comparative example described later (see Figure 6).

[0035] When the potential of PRECHG rises to the power supply potential (timing t7), nMOS14 turns on, and V BL is fixed at ground potential. Figure 4 shows the V PL The horizontal axis shows the relationship between V and the amount of charge supplied to BL. PL The vertical axis represents the amount of charge (Q) supplied to BL.

[0036] FIG. 4 shows V when "0" is stored in the memory cell 13 and when "1" is stored in the memory cell 13. PL The relationship between the amount of charge supplied to the BL and Q VREF1is V BL =V REF1 It represents the amount of charge supplied to BL when V PL1 When "1" is stored in the memory cell 13, Q=Q VREF1 When V PL V PL0 When "0" is stored in the memory cell 13, Q=Q VREF1 When V PL is.

[0037] Therefore, in the read circuit 10 of the ferroelectric memory according to the first embodiment, the read margin is V PL0 -V PL1 The read margin is Q VREF1 Since it is determined by the value of , it is affected by the bit line capacitance 15. The relationship between the magnitude of the bit line capacitance 15 and the magnitude of the read margin will be described later (see FIG. 16).

[0038] In the read circuit 10 of the ferroelectric memory according to the first embodiment, the control circuit 11 controls V BL and V REF1 Based on the comparison result, the input voltage is controlled so that the input voltage of the memory cell 13 is fixed.

[0039] For example, V PL When V rises, noise BL is temporarily V REF1 Beyond V PL Even if the increase in V stops, BL When it returns to normal, V PL continues to rise, and V BL V REF1 When V PL The rise in voltage stops and the input voltage of the memory cell 13 is fixed.

[0040] Then, the sense amplifier 12 calculates V PL and V REF2 The value of the data stored in the memory cell 13 is determined based on the result of the comparison with the value of the data stored in the memory cell 13, and therefore is less susceptible to the influence of noise.

[0041] In addition, the read circuit 10 includes a control circuit 11 including a differential amplifier 11a, which converts V BL and V REF1 The gain of the differential amplifier 11a can be easily increased, and if the gain is large, the input offset and V REF1 It is possible to operate correctly even if there is variation in the

[0042] (Comparative Example) 5 is a diagram showing a part of a ferroelectric memory of a comparative example, in which the same elements as those shown in FIG.

[0043] In FIG. 5, the sense amplifier 12 is connected to BL and V BL and V REF Based on the comparison result, the value of the data stored in the memory cell 13 is determined, and DATA, which is the determination result, is output.

[0044] 6 is a timing chart showing an example of a read operation of the ferroelectric memory of the comparative example. FIG. 6 shows the time change of the potential (V) of PRECHG and SAEN, which is the enable signal of the sense amplifier 12. Furthermore, FIG. 6 shows the time change of V, which is the potential of WL. WL , V is the potential of the PL PL , V is the potential of BL BL The time variation of the potential (V) of DATA, which is the output of the sense amplifier 12, is also shown.

[0045] When the potential of PRECHG falls from the power supply potential to the ground potential (for example, 0 V) ​​(timing t10), the nMOS 14 is turned off and BL is put into a floating state.

[0046] V WL rises (timing t11), and the specified V PL When is applied, V BLThis causes the data to be read from the memory cell 13. At this time, depending on whether or not the polarization inversion has occurred, the voltage V BL The increase per unit time is small (i.e., the increase rate is slow).

[0047] When the potential of SAEN rises (timing t12), the sense amplifier 12 BL And, V REF Based on the comparison result with V, the value of the data stored in the memory cell 13 is determined, and the determination result DATA is output. BL ≧V REF In this case, DATA = "1" (for example, power supply potential) and V BL <V REF In this case, DATA=“0” (for example, ground potential).

[0048] After that, to rewrite "0", V PL is maintained as it is, V BL is pulled down to the ground potential (timing t13). Next, to rewrite "1", V BL is maintained as it is, V PL is pulled down to the ground potential (timing t14).

[0049] When the potential of PRECHG rises to the power supply potential (timing t15), nMOS14 turns on, and V BL is fixed at ground potential. In such a ferroelectric memory of the comparative example, when the read margin becomes small due to degradation of the ferroelectric capacitor 13a or the like, the memory becomes susceptible to the influence of noise.

[0050] In contrast to this, the ferroelectric memory of the first embodiment has the read circuit 10, and is therefore less susceptible to the effects of noise for the reasons described above. (Example of a ferroelectric memory to which the read circuit 10 is applied) FIG. 7 is a diagram showing an example of a ferroelectric memory.

[0051] The ferroelectric memory 20 includes a memory cell array 21, an address buffer 22, a controller 23, a reference potential generating circuit 24, a row-related circuit section 25, and a column-related circuit section 26. The memory cell array 21 has a plurality of memory cells arranged in a matrix, a plurality of bit lines, a plurality of word lines, and a plurality of plate lines (see FIG. 8, which will be described later).

[0052] The address buffer 22 receives an address from outside the ferroelectric memory 20 and supplies the received address to a row-related circuit section 25 and a column-related circuit section 26 . The controller 23 receives commands (such as a chip select signal, a write enable signal, and an output enable signal) from outside the ferroelectric memory 20. Then, based on the received commands, the controller 23 supplies various control signals (such as the aforementioned PRECHG and SAEN) to the row-related circuit unit 25 and the column-related circuit unit 26.

[0053] The reference potential generating circuit 24 generates the reference potential (V REF1 and V REF2 ) Although not shown, the row-related circuit unit 25 includes, for example, a row decoder and a driver circuit. The row decoder generates a row decode signal by decoding a row address included in the address (for example, the most significant bits of the address signal), and supplies the generated row decode signal to the driver circuit. The driver circuit applies a predetermined voltage to a word line designated by the row decode signal among the plurality of word lines for a predetermined period in response to a control signal supplied from the controller 23.

[0054] Although not shown, the column-related circuit section 26 includes a column decoder, a write amplifier, an input / output circuit, and the read circuit 10 as shown in FIG. FIG. 8 is a diagram showing an example of a part of a memory cell array and a part of a column-related circuit unit.

[0055] 8, the memory cell array 21 includes the memory cells 13 shown in FIG. 1. When the read circuit 10 is used, the multiple memory cells connected to the same WL are each V PL Since the values ​​are different, the PL is arranged perpendicular to the WL.

[0056] 1 and the read circuit 10. The column-related circuit 26 further includes a column decoder / write amplifier section 26a and an input / output circuit 26b. A configuration similar to the nMOS 14 and the read circuit 10 is provided for each pair of BL and PL.

[0057] The column decoder / write amplifier unit 26a includes, for example, a column decoder, a write amplifier, and a column switch. The column decoder generates a column decode signal by decoding a column address (for example, the lower bits of the address signal) included in the address. The generated column decode signal is supplied to a column switch, which selects one of the multiple BLs or multiple PLs to connect to the write amplifier or input / output circuit 26b based on the column decode signal.

[0058] The input / output circuit 26b includes, for example, a write buffer that holds write data supplied from outside the ferroelectric memory 20. The write buffer may have a function of holding data read by the sense amplifier 12 for writing back.

[0059] Furthermore, the input / output circuit 26b holds the value of the data determined by the sense amplifier 12 and outputs it. The read circuit 10 is applicable to the ferroelectric memory 20 described above.

[0060] (Second embodiment) Fig. 9 is a diagram showing an example of a read circuit of a ferroelectric memory according to the second embodiment. In Fig. 9, the same elements as those shown in Fig. 1 are given the same reference numerals. In Fig. 1, WL represents a word line, BL represents a bit line, PL represents a plate line, RWL represents a reference word line, and RBL represents a reference bit line.

[0061] The read circuit 30 of the ferroelectric memory of the second embodiment has a sense amplifier 12 and a control circuit 31, similar to the read circuit 10 of the ferroelectric memory of the first embodiment. The read circuit 30 further has a capacitor 32 and an nMOS 33.

[0062] One end of the capacitor 32 is electrically connected to PL, and the other end is connected to the drain of the nMOS 33. The source of the nMOS 33 is connected to RBL, and the gate of the nMOS 33 is connected to RWL. The capacitor 32 is not a ferroelectric capacitor, but a linear capacitor whose stored charge increases in proportion to an increase in applied voltage. When reading the memory cell 13, the potential of RWL is raised, the nMOS 33 is turned on, and the other end of the capacitor 32 is electrically connected to BL.

[0063] The control circuit 31 of the read circuit 30 controls the potential of BL, V BL and V is the potential of RBL RBL Based on the comparison result, the input voltage is controlled so that the input voltage of the memory cell 13, which is the voltage between PL and BL, is fixed.

[0064] The control circuit 31, like the control circuit 11 of the readout circuit 10, has a differential amplifier 31a, the inverting input terminal of which is connected to BL, the non-inverting input terminal of which is connected to RBL, and the output terminal of which is connected to PL.

[0065] The differential amplifier 31a is enabled when reading data from the memory cell 13, and V BL and V RBLThe difference between the two is amplified and output as a signal to the PL potential, V PL The differential amplifier 31a increases V BL V RBL When it reaches V PL By stopping the rise of the voltage, the input voltage of the memory cell 13 is fixed.

[0066] The sense amplifier 12 is connected to PL. The sense amplifier 12 detects the voltage V PL And, V REF Based on the comparison result with V, the value of the data stored in the memory cell 13 is determined, and the determination result DATA is output. REF is a constant potential, and is applied to the sense amplifier 12 by the reference potential generating circuit 24 shown in FIG. REF For example, V in Figure 1 REF2 is set in the same way.

[0067] 9 also shows an nMOS 34. The drain of the nMOS 34 is connected to the RBL, and the source is grounded. PRECHG is input to the gate of the nMOS 34. Furthermore, FIG. 9 shows a bit line capacitance 35 of the RBL.

[0068] In such a read circuit 30, charges are supplied from PL to the ferroelectric capacitor 13a and the capacitor 32, as indicated by the two arrows. 10 is a timing chart showing an example of the operation of the read circuit of the ferroelectric memory according to the second embodiment. Time variations in the potentials (V) of PRECHG, OAEN, which is the enable signal of the differential amplifier 31a, and SAEN, which is the enable signal of the sense amplifier 12, are shown in FIG. 10. Furthermore, V, which is the potential of WL, is shown in FIG. WL , V is the potential of the PL PL , V is the potential of BL BL , V is the potential of RBL RBL The time variation of the potential (V) of DATA, which is the output of the sense amplifier 12, is also shown.

[0069] When the potential of PRECHG falls from the power supply potential to the ground potential (for example, 0 V) ​​(timing t20), the nMOSs 14 and 34 are turned off, and BL and RBL are brought into a floating state.

[0070] V WL rises (timing t21), and when the potential of OAEN rises, the differential amplifier 31a starts operating, and V PL and V BL As a result, the nMOS 13b is turned on, and data reading from the memory cell 13 begins. At this time, depending on whether or not the polarization inversion occurs, when "0" is stored in the memory cell 13, V BL The rise in the voltage V per unit time is small (i.e., the rise rate is slow). On the other hand, although not shown in the figure, at timing t21, the potential of RWL also rises, and the nMOS 33 is turned on. RBL increases in proportion to time.

[0071] In Figure 10, V BL and V RBL 1. The enlarged view of the rising portion of V is shown. The V is the voltage when "0" is stored in the memory cell 13 and when "1" is stored in the memory cell 13. BL is shown by a solid line. RBL is shown by a dashed line in the enlarged view, but after timing t22, the case where "0" is stored in the memory cell 13 is shown. RBL changes in the same way up to timing t22 whether "0" is stored in the memory cell 13 or "1" is stored in the memory cell 13.

[0072] As shown in the enlarged view of FIG. 10, when a "1" is stored in memory cell 13, V BL At timing t22, V RBL Therefore, the differential amplifier 31a reaches V PL This stops the rise of V BL and V RBLThe input voltage (V PL -V BL ) is fixed.

[0073] On the other hand, if "0" is stored in the memory cell 13, V BL is V RBL Therefore, V PL V continues to rise until it reaches a maximum value (for example, the power supply potential). PL When reaches its maximum value (timing t23), V BL and V RBL The input voltage (V PL -V BL ) is fixed.

[0074] Thereafter, the potential of OAEN falls, causing the differential amplifier 31a to stop operating (timing t24), and when the potential of SAEN rises, the sense amplifier 12 PL And, V REF Based on the comparison result with V, the value of the data stored in the memory cell 13 is determined, and the determination result DATA is output. PL ≧V REF In this case, DATA = "0" (for example, ground potential) and V PL <V REF In this case, DATA="1" (for example, power supply potential).

[0075] Then, based on the results of the judgment, V PL and V BL is set (timing t25), and V WL is further increased, and the memory cell 13 is rewritten. When "0" is rewritten, V PL is maintained, V BL When a "1" is rewritten, V PL is pulled down to ground potential, and V BL will be further raised.

[0076] When a plurality of memory cells 13 are connected to the same WL (see FIG. 8), according to the above read method, VPL is controlled for each memory cell. Therefore, when rewriting to multiple memory cells connected to the same WL, it is not necessary to write "0" and "1" at different times as in the comparative example described above (see Figure 6).

[0077] When the potential of PRECHG rises to the power supply potential (timing t26), nMOSs 14 and 34 are turned on, and V BL and V RBL is fixed at ground potential. Figure 11 shows the V PL The horizontal axis shows the relationship between V and the amount of charge supplied to BL. PL The vertical axis represents the amount of charge (Q) supplied to BL.

[0078] FIG. 11 shows the V when "0" is stored in the memory cell 13 and when "1" is stored in the memory cell 13. PL The relationship between V and the amount of charge supplied to BL is shown in Figure 11. PL The relationship between the capacitance and the amount of charge supplied to RBL is shown by the dashed line. The slope of the dashed line varies depending on the size of the capacitor 32 (C REF ) is determined by

[0079] V PL0 is obtained when "0" is stored in the memory cell 13, V PL is the maximum value of V PL1 When "1" is stored in the memory cell 13, V BL =V RBL When V PL is.

[0080] Therefore, in the read circuit 30 of the ferroelectric memory according to the second embodiment, the read margin is V PL0 -V PL1 is. In the read circuit 30 of the ferroelectric memory according to the second embodiment, the control circuit 31 controls V BL and V RBLBased on the comparison result, the input voltage is controlled so that the input voltage of the memory cell 13 is fixed.

[0081] For example, V PL When V rises, noise BL is temporarily V RBL Beyond V PL Even if the increase in V stops, BL When it returns to normal, V PL continues to rise, and V BL V RBL When V PL The rise in voltage stops and the input voltage of the memory cell 13 is fixed.

[0082] Then, the sense amplifier 12 calculates V PL and V REF The value of the data stored in the memory cell 13 is determined based on the result of the comparison with the value of the data stored in the memory cell 13, and therefore is less susceptible to the influence of noise.

[0083] In addition, the read circuit 30 includes a control circuit 31 including a differential amplifier 31a, which is used to convert V BL and V RBL The gain of the differential amplifier 31a can be easily increased, and if the gain is large, the input offset and V RBL It is possible to operate correctly even if there is variation in the

[0084] Furthermore, when "0" is stored in the memory cell 13, the read circuit 30 reads V PL rises until it reaches a maximum value, at which point V BL This allows a relatively large read margin and makes it less susceptible to noise.

[0085] The read circuit 30 as described above can also be applied to the ferroelectric memory 20 as shown in FIG. 7. The configuration of the column-related circuit section 26 as shown in FIG. 8 can be changed to match the circuit configuration of the read circuit 30. When the read circuit 30 is used, multiple memory cells connected to the same WL are each V PL Since the values ​​are different, the PL is placed perpendicular to the WL.

[0086] (Third embodiment) Fig. 12 is a diagram showing an example of a read circuit of a ferroelectric memory according to the third embodiment. In Fig. 12, the same elements as those shown in Fig. 1 are assigned the same reference numerals. In Fig. 12, WL represents a word line, BL represents a bit line, PL represents a plate line, RWL represents a reference word line, and RBL represents a reference bit line.

[0087] The read circuit 40 of the ferroelectric memory of the third embodiment has a sense amplifier 12 and a control circuit 41, similar to the read circuit 10 of the ferroelectric memory of the first embodiment. The read circuit 40 further has a capacitor 42 and an nMOS 43.

[0088] One end of the capacitor 42 is grounded, and the other end is connected to the source of the nMOS 43. The drain of the nMOS 43 is connected to the RBL, and the gate of the nMOS 43 is connected to the RWL. The capacitor 42 is not a ferroelectric capacitor, but a linear capacitor whose stored charge increases in proportion to an increase in applied voltage. When reading the memory cell 13, the potential of the RWL is raised, the nMOS 43 is turned on, and the other end of the capacitor 42 is electrically connected to the BL.

[0089] The control circuit 41 of the read circuit 40 controls the potential of BL, V BL and V is the potential of RBL RBL Based on the comparison result, the input voltage is controlled so that the input voltage of the memory cell 13, which is the voltage between PL and BL, is fixed.

[0090] The control circuit 41 has a differential amplifier 41a, similar to the control circuit 11 of the read circuit 10. Furthermore, the control circuit 41 includes p-channel MOSFETs (hereinafter abbreviated as pMOS) 41b and 41c.

[0091] In the differential amplifier 41a, the inverting input terminal is connected to BL, and the non-inverting input terminal is connected to RBL. The output terminal of the differential amplifier 41a is connected to the gates of pMOSs 41b and 41c. The drain of pMOS 41b is connected to RBL, and the drain of pMOS 41c is connected to BL. A power supply voltage (VDD) is applied to the sources of pMOSs 41b and 41c.

[0092] The differential amplifier 41a is effective when reading data from the memory cell 13, and has a function of controlling the amount of current in BL and RBL by an output signal. BL V RBL When the voltage V falls below V , an output signal is output to turn off the pMOSs 41b and 41c. BL The increase in V BL is fixed.

[0093] In the ferroelectric memory of the third embodiment, when reading the memory cell 13, V PL is fixed at ground potential (for example, 0V). BL The increase in V BL When is fixed, the input voltage of memory cell 13 is also fixed.

[0094] In the read circuit 40, the sense amplifier 12 is connected to BL. The sense amplifier 12 detects the voltage V BL And, V REF Based on the comparison result with V, the value of the data stored in the memory cell 13 is determined, and the determination result DATA is output. REF is a constant potential, and is applied to the sense amplifier 12 by the reference potential generating circuit 24 shown in FIG. REF For example, V in Figure 1REF2 is set in the same way.

[0095] 12 also shows an nMOS 44. The drain of the nMOS 44 is connected to the RBL, and the source is grounded. PRECHG is input to the gate of the nMOS 34. Furthermore, FIG. 12 shows a bit line capacitance 45 of the RBL.

[0096] In such a read circuit 40, as indicated by the two arrows, charge is supplied from RBL to the capacitor 42, and charge is supplied from BL to the ferroelectric capacitor 13a. FIG. 13 is a timing chart showing an example of the operation of the read circuit of the ferroelectric memory according to the third embodiment.

[0097] 13 shows the time variations of the potentials (V) of PRECHG, OAEN which is the enable signal of the differential amplifier 41a, SAEN which is the enable signal of the sense amplifier 12, and AMPOUT which is the output signal of the differential amplifier 41a. WL , V is the potential of the PL PL , V is the potential of BL BL , V is the potential of RBL RBL The time variation of the potential (V) of DATA, which is the output of the sense amplifier 12, is shown. RBL The time variation of is shown by the dashed line.

[0098] When the potential of OAEN is the ground potential, the differential amplifier 41a does not operate, and the output signal AMPOUT of the differential amplifier 41a is at the power supply potential. In other words, the initial potential of AMPOUT is the power supply potential. Therefore, the pMOSs 41b and 41c are in the off state.

[0099] When the potential of PRECHG falls from the power supply potential to the ground potential (for example, 0 V) ​​(timing t30), the nMOSs 14 and 44 are turned off, and BL and RBL are brought into a floating state.

[0100] V WL rises (timing t31), and when the potential of OAEN rises, nMOS 13b turns on, the differential amplifier 41a starts operating, and V BL As a result, the potential of AMPOUT also starts to drop, pMOS41b and 41c turn on, and BL and RBL are charged by VDD. PL remains at ground potential.

[0101] This starts the reading of data from the memory cell 13. When the read circuit 40 of the ferroelectric memory of the third embodiment is used, unlike the case shown in FIG. 2, polarization reversal occurs when "0" is stored in the memory cell 13. Therefore, the amount of charge drawn from BL to the ferroelectric capacitor 13a of FIG. 12 increases compared to when "1" is stored in the memory cell 13, and V BL The increase per unit time is small (i.e., the increase rate is slow).

[0102] On the other hand, although not shown in the drawing, at timing t31, the potential of RWL also rises, and the nMOS 43 is turned on. RBL increases in proportion to time.

[0103] Figure 13 shows the V BL and V RBL 1. The enlarged view of the rising portion of V is shown. The V is the voltage when "0" is stored in the memory cell 13 and when "1" is stored in the memory cell 13. BL is shown by a solid line. RBL is shown as a dashed line in the enlarged view. RBL changes in the same way up to timing t32 whether "0" is stored in the memory cell 13 or "1" is stored in the memory cell 13.

[0104] As shown in the enlarged view of Figure 13, V BL Whether "0" is stored in the memory cell 13 or "1" is stored in the memory cell 13, V RBLHowever, if "0" is stored in the memory cell 13, the rate of increase gradually slows down, and at timing t32, V BL is V RBL At this time, the potential of AMPOUT starts to rise, pMOS 41b and 41c are turned off, and V BL and V RBL is fixed.

[0105] On the other hand, if "1" is stored in the memory cell 13, V BL reaches the power supply potential (e.g., VDD) and is fixed, and then V RBL also reaches the power supply potential and is fixed. V PL is fixed at ground potential, so as shown above, V BL By fixing the input voltage (V PL -V BL ) is fixed.

[0106] Thereafter, the potential of the signal OAEN falls, causing the differential amplifier 41a to stop operating (timing t33), and the potential of the signal SAEN rises (timing t34). BL And, V REF Based on the comparison result with V, the value of the data stored in the memory cell 13 is determined, and the determination result DATA is output. BL ≧V REF In this case, DATA = "1" (for example, power supply potential) and V BL <V REF In this case, DATA=“0” (for example, ground potential).

[0107] Then V WL is further increased, and rewriting to the memory cell 13 is performed (timing t35). BL and V PL is maintained as it is, a "1" is rewritten, and then V BL is maintained as it is, V PL is raised to a predetermined potential (timing t36).

[0108] When the potential of the signal PRECHG rises to the power supply potential (timing t37), the nMOSs 14 and 44 are turned on, and V BL and V RBL is fixed at ground potential. Figure 14 shows the V BL and V RBL The horizontal axis shows the relationship between the voltage V and the amount of charge supplied to the ferroelectric capacitor. PL The vertical axis represents the amount of charge (Q) supplied to the ferroelectric capacitor 13a.

[0109] FIG. 14 shows V when "0" is stored in the memory cell 13 and when "1" is stored in the memory cell 13. BL and V RBL The relationship between V and the amount of charge supplied to BL is shown in FIG. BL The relationship between the charge and the V RBL The relationship between the capacitance and the amount of charge is shown by the dashed line. The slope of the dashed line varies depending on the size (C REF ) is determined by

[0110] V BL0 When "0" is stored in the memory cell 13, V BL =V RBL When V BL V BL1 is obtained when a "1" is stored in the memory cell 13, V BL is the maximum value of

[0111] Therefore, in the read circuit 40 of the ferroelectric memory according to the third embodiment, the read margin is V BL1 -V BL0 is. In the read circuit 40 of the ferroelectric memory according to the third embodiment, the control circuit 41 controls V BL and V RBL Based on the comparison result, the input voltage of the memory cell 13 is controlled so that the input voltage is fixed.

[0112] Then, the sense amplifier 12 calculates V BL and V REF The value of the data stored in the memory cell 13 is determined based on the result of the comparison with the value of the data stored in the memory cell 13, and therefore is less susceptible to the influence of noise.

[0113] In addition, the read circuit 40 includes a control circuit 41 that includes a differential amplifier 41a. BL and V RBL The gain of the differential amplifier 41a can be easily increased, and if the gain is large, the input offset and V RBL It is possible to operate correctly even if there is variation in the

[0114] The read circuit 40 described above can also be applied to the ferroelectric memory 20 shown in Fig. 7. The configuration of the column-related circuit section 26 shown in Fig. 8 may be changed to match the circuit configuration of the read circuit 40.

[0115] When the read circuit 40 is used, a plurality of memory cells connected to the same WL are each V PL Since the distance between the PL and the WL may be the same, the PL may be arranged parallel to the WL or perpendicular to the WL.

[0116] (Relationship between bit line capacitance and read margin) The relationship between the size of the bit line capacitance 15 and the read margin when using the read circuits 10, 30, and 40 of the ferroelectric memories of the above embodiments will be described below. First, the relationship between the size of the bit line capacitance 15 and the read margin in the ferroelectric memory of the comparative example shown in FIG. 5 will be described.

[0117] 15 is a diagram showing the relationship between the magnitude of the bit line capacitance and the magnitude of the read margin in the ferroelectric memory of the comparative example. PL , the vertical axis represents ΔQ (the change in the charge supplied to BL) V PL-ΔQ characteristic graph, and the horizontal axis is the size of the bit line capacitance 15 (C BL ) and the vertical axis is V BL C stands for BL -V BL A graph showing the characteristics is shown.

[0118] V PL In the graph showing the -ΔQ characteristics, the slope is C BL and ΔQ=C BL ×V BL The line expressed by the formula V is shown. BL is determined by the capacitance division between the ferroelectric capacitor 13 a and the bit line capacitance 15 .

[0119] The straight line expressed by the above formula and the V PL The potential difference between the intersections with the -ΔQ characteristic line is the read margin (ΔV BL ) is equivalent to

[0120] In the comparative ferroelectric memory, C BL -V BL As shown in the characteristic graph, ΔV BL is C BL =C BL1 So, small, C BL =C BL2 increases, but C BL =C BL3 If it is further increased, it becomes smaller.

[0121] 16 is a diagram showing the relationship between the magnitude of the bit line capacitance and the magnitude of the read margin in the ferroelectric memory according to the first embodiment. PL , the vertical axis represents ΔQ (the change in the charge supplied to BL) V PL -ΔQ characteristic graph, and the horizontal axis is the size of the bit line capacitance 15 (C BL ) and the vertical axis is V PL C stands for BL -V PL A graph showing the characteristics is shown.

[0122] V PL In the graph showing the -ΔQ characteristics, V BL =ΔQ / C BL =V REF1 When V becomes PL is determined for each of the cases where "0" and "1" are stored in the memory cell 13.

[0123] In FIG. 16, when "0" is stored in the memory cell 13, V BL0 =ΔQ / C BL2 =V REF1 When V becomes PL0 When "1" is stored in the memory cell 13, V BL1 =ΔQ / C BL2 =V REF1 When V becomes PL1 It is shown that V PL0 and V PL1 The difference (ΔV PL ) but C BL =C BL2 This corresponds to the read margin when

[0124] In the ferroelectric memory of the first embodiment, C BL -V PL As shown in the characteristic graph, ΔV PL is C BL =C BL1 So, small, C BL =C BL2 increases, but C BL =C BL3 If it is further increased, it becomes smaller.

[0125] As described above, in the ferroelectric memories of the comparative example and the first embodiment, in order to increase the read margin, the C BL It is desirable to set it to an appropriate value. 17 is a diagram showing the relationship between the magnitude of the bit line capacitance and the magnitude of the read margin in the ferroelectric memory according to the second embodiment. PL , the vertical axis represents ΔQ (the change in the charge supplied to BL) V PL-ΔQ characteristic graph, and the horizontal axis is the size of the bit line capacitance 15 (C BL ) and the vertical axis is V PL C stands for BL -V PL A graph showing the characteristics is shown.

[0126] In addition, V PL In the -ΔQ characteristic graph, V PL The relationship between the change in the charge supplied to RBL and the capacitance of the capacitor 32 (C REF ) is determined by

[0127] In the ferroelectric memory of the second embodiment, as described above, when reading out a data "0" stored in the memory cell 13, V PL is the maximum value (V PL0 On the other hand, when "1" is stored in the memory cell 13, ΔQ at the time of reading is fixed to the dashed line in FIG. PL -ΔQ characteristic line and the intersection point, C BL It is constant regardless of

[0128] In FIG. 17, when "1" is stored in the memory cell 13, C BL =C BL2 V at the time PL1 This V PL0 and V PL1 The difference (ΔV PL ) but C BL =C BL2 This corresponds to the read margin when

[0129] In the ferroelectric memory of the second embodiment, C BL -V PL As shown in the characteristic graph, ΔV PL is C BL increases as In this way, in the ferroelectric memory of the second embodiment, C BL If you increase C, you can increase the read margin. BLWhen C becomes larger, the input signal to the differential amplifier 31a becomes smaller. BL Whether it can be increased depends on the capability of the differential amplifier 31a.

[0130] 18 is a diagram showing the relationship between the magnitude of the bit line capacitance and the magnitude of the read margin in the ferroelectric memory according to the third embodiment. BL , and the vertical axis represents ΔQ (the amount of change in the charge supplied to the ferroelectric capacitor 13a) V BL -ΔQ characteristic graph, and the horizontal axis is the size of the bit line capacitance 15 (C BL ) and the vertical axis is V BL C stands for BL -V BL A graph showing the characteristics is shown.

[0131] In addition, V BL In the -ΔQ characteristic graph, V RBL The relationship between the change in the charge supplied to RBL and the capacitance of the capacitor 42 (C REF ) is determined by

[0132] In the ferroelectric memory of the third embodiment, as described above, when reading out a data "1" stored in the memory cell 13, V BL is the maximum value (V BL1 On the other hand, when "1" is stored in the memory cell 13, ΔQ at the time of reading is fixed to the dashed line in FIG. BL -ΔQ characteristic line and the intersection point, C BL It is constant regardless of V at this intersection. BL1 And, V BL0 The difference between V and V BL0 -V BL1 corresponds to the read margin.

[0133] In the ferroelectric memory of the third embodiment, C BL -V BL As shown in the characteristic graph, ΔV BL is C BL is constant regardless of In this way, in the ferroelectric memory of the third embodiment, C BL However, regardless of C BL When C becomes large, the input signal to the differential amplifier 41a becomes small. BL Whether it can be increased depends on the capabilities of the differential amplifier 41a.

[0134] The above has described one aspect of the ferroelectric memory readout circuit, ferroelectric memory, and ferroelectric memory readout method of the present invention based on the embodiments, but these are merely examples and are not limited to the above description.

[0135] For example, the circuit configuration can be changed as appropriate, such as by using pMOS instead of nMOS. [Explanation of symbols]

[0136] 10 Readout circuit 11 Control circuit 11a Differential Amplifier 12 Sense Amplifier 13 memory cells 13a Ferroelectric capacitor 13b,14 nMOS 15 Bit line capacitance

Claims

1. In a read circuit for a ferroelectric memory having memory cells each including a ferroelectric capacitor, a control circuit that controls an input voltage of the memory cell, which is a voltage between a plate line electrically connected to the other terminal of the ferroelectric capacitor and the bit line, based on a result of comparison between a bit line potential, which is a potential of a bit line electrically connected to one terminal of the ferroelectric capacitor, and a first reference potential, so that the input voltage is fixed when reading data from the memory cell; a sense amplifier that determines the value of the data based on a comparison result between a plate line potential, which is the bit line potential or the plate line potential when the input voltage is fixed, and a second reference potential; A read circuit for a ferroelectric memory having:

2. 2. The ferroelectric memory read circuit according to claim 1, wherein said control circuit includes a differential amplifier having a first input terminal receiving said bit line potential and a second input terminal receiving said first reference potential.

3. the first reference potential is a constant potential, 3. The ferroelectric memory read circuit according to claim 1, wherein the control circuit fixes the input voltage by stopping the increase in the plate line potential when the bit line potential reaches the first reference potential.

4. a capacitor having one end electrically connected to the plate line and the other end electrically connected to a reference bit line; the first reference potential is the potential of the reference bit line; 3. A read circuit for a ferroelectric memory according to claim 1.

5. the control circuit fixes the plate line potential when the bit line potential reaches the reference bit line potential if a first value is stored in the memory cell; If the memory cell stores a second value different from the first value, the plate line potential increases until it reaches a maximum value, at which point the bit line potential is fixed.

5. A read circuit for a ferroelectric memory according to claim 4.

6. a capacitor having one end grounded and the other end electrically connected to the reference bit line; the first reference potential is the potential of the reference bit line; 3. A read circuit for a ferroelectric memory according to claim 1.

7. 7. The read circuit for a ferroelectric memory according to claim 6, wherein said control circuit fixes said bit line potential when said bit line potential falls below the potential of said reference bit line.

8. a memory cell including a ferroelectric capacitor; a read circuit including: a control circuit that controls an input voltage of the memory cell, which is a voltage between a plate line electrically connected to the other terminal of the ferroelectric capacitor and the bit line, based on a comparison result between a bit line potential, which is a potential of a bit line electrically connected to one terminal of the ferroelectric capacitor, and a first reference potential, when reading data from the memory cell; and a sense amplifier that determines a value of the data based on a comparison result between a plate line potential, which is a potential of the bit line or the plate line when the input voltage is fixed, and a second reference potential; A ferroelectric memory having:

9. A method for reading a ferroelectric memory having a memory cell including a ferroelectric capacitor, comprising: a control circuit, when reading data from the memory cell, controls an input voltage, which is a voltage between a plate line electrically connected to the other terminal of the ferroelectric capacitor and the bit line, based on a result of comparison between a bit line potential, which is a potential of a bit line electrically connected to one terminal of the ferroelectric capacitor, and a first reference potential, so that an input voltage of the memory cell, which is a voltage between the bit line and the plate line electrically connected to the other terminal of the ferroelectric capacitor, is fixed; a sense amplifier determines a value of the data based on a result of comparison between a plate line potential, which is a potential of the bit line or a potential of the plate line when the input voltage is fixed, and a second reference potential; A method for reading ferroelectric memory.

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